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he steady reduction in the minimum 10 nm (1). We discuss below the challenges gate voltage is removed or set at zero volt-
feature size in integrated circuits has in device scaling and possible solutions in age, the surface region under the gate is
helped the microelectronic industry to maintaining the performance trend. depleted with electric carriers and there is no
produce products with spectacular increase in current flow between the source and the
computational capability and integration den- MOSFETs: The Building Blocks drain. We can therefore see that the current
sity at lower cost. Smaller transistors operate The MOSFET, or metal oxide semiconductor flowing through the structure can be regulat-
faster than larger ones, and for a given chip field-effect transistor, is a fundamental ed by applying voltage to the gate electrode.
technology, the cost
of a chip decreases
with area rather than B C
A Scaled Device
with the number of
transistors. Voltage, V/α
The exponential ed
tox/α pe
ctive
s
Gate delay
Pa
will eventually hit Voltage: V/α re
GATE Vt In
c
uce
fundamental limits, Oxide: tox/α
Red
but the many predic- n+ source n+ drain
Gate Length: L/α
tions of a near-term Diffusion: xd/α e P standby
end of device scaling Substrate: α*NA Reduc
have proven too pes- L/α
xd/α Vt Vdd Vdd
simistic. With the
introduction of the p substrate, doping α*NA
production of 90-nm
node technology in
2004, the semicon- Fig. 1. (A) Schematic of MOSFET indicating various relevant device scaling parameters. (B) Complementary metal-oxide
ductor industry is en- semiconductor (CMOS) inverter gate delay as a function of power-supply voltage (Vdd). Gate delay rapidly increases as Vdd
tering the Bnano[ era approaches the threshold voltage (Vt). (C) Design space for supply and threshold voltages for optimum performance and
power dissipation. Technology scaling diminishes this design space.
(1). (The B90-nm
node[ refers to the
smallest half-pitch metal lines available in the switching device in very-large-scale integrat- A MOSFET can be used either as an elec-
technology. The actual gate lengths of the de- ed (VLSI) circuits. A MOSFET (Fig. 1A) trical switch or as an amplifier. The majority
vices are about 50 nm.) In the next decade, has at least three terminals, which are des- of MOSFETs on an integrated circuit today
device gate lengths will be scaled to below ignated as gate, source, and drain. The gate are used as electrical switches. How fast a
electrode is separated electrically from the MOSFET can be switched on and off is
1
IBM Semiconductor Research and Development source and the drain by a thin dielectric film, therefore a critical figure of merit to deter-
Center, T. J. Watson Research Center, Yorktown
2
Heights, NY 10598, USA. IBM Semiconductor Re-
usually silicon dioxide. The source and the mine the competitiveness of the technology.
search and Development Center, Microelectronic drain are doped with impurities that are op- The two major factors that control the speed
Division, Hopewell Junction, NY 12533, USA. posite in polarity to the substrate, which is of MOSFETs are the channel length from
*To whom correspondence should be addressed. doped with boron for N-channel transistors the source to the drain and the speed at which
E-mail: mkieong@us.ibm.com and with arsenic or phosphorous for P- channel charge carriers travel from the source
Gate
now become the number one issue in Z FET reduces the depletion width by 50%
any high-performance and low-power compared with that of a single-gate
application. Currently, there is a con- structure. In addition, there is no drain-
Source Drain
sensus that maintaining the device to-body fringing field through the buried
performance trend with conventional STI
oxide (BOX) (Fig. 2A) in a double-gate
device scaling technique is extremely Desired Stress: structure. Numerical simulations indicate
Transverse
challenging, if possible at all. New Tran. Long. Z that scalability for double-gate FETs
Gate