2010 Basic Training

Quartus II Basic Training
© 2010 Altera Corporation—Confidential

Agenda
Introduction to Altera Devices

Quartus II Development system overview
Timing Analysis
Quartus II Quick Start using Galaxy Demo Kit
ALTERA Development Kit
Galaxy Development Kit

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
Introduction to Altera Devices

Programmable Logic Families
Structured ASIC
− HardCopy® IV HardCopy III HardCopy® II
High & medium density FPGAs
− Stratix IV E ,Stratix III L&E, Stratix II
Low-cost FPGAs
− Cyclone IV E ,Cyclone III, Cyclone II
FPGAs w/ clock data recovery
− Stratix IV GT&GX, Stratix IIGX, StratixGX
− Arria II GX, Arria GX, Cyclone IV GX
CPLDs
- MAX II , MAX II Z
- MAX 3000 & MAX7000S
Configuration devices
− AS Mode Serial (EPCS) & PS Mode enhanced (EPC)
Design Security Feature
− Cyclone III LS

ALTERA CPLDs

MAX 3000A & MAX 7000S Family Overview
Parameter MAX 3000A MAX 7000S
EPM7064S
EPM7160S
EPM7192S
EPM7256S
EPM3032A
EPM3064A
EPM3512A
EPM3256A
EPM3128A
EPM7128S
Useable Gates 600 1,250 2,500 5,000 10,000 1,250 2,500 3200 3750 5000
Macrocells 32 64 128 256 512 64 128 160 192 256
Maximum User 34 66 96 158 208 68 100 104 124 164
I/O Pins
tPD (ns) 4.5 4.5 5.0 7.5 7.5 5 6 6 7.5 7.5
fCNT (MHz) 227 222 192 127 116 175.4 147.1 149.3 125.0 128.2
tSU (ns) 2.9 2.8 3.3 5.2 5.6 2.9 3.4 3.4 4.1 3.9
tCO1 (ns) 3.0 3.1 3.4 4.8 4.7 3.2 4 3.9 4.7 4.7
EPM7032S End Of Life

Complete Voltage Portfolio
5.0 V 3.3 V MultiVolt Core and I/O Operation
MAX 7000S MAX II MAX II

Performance
Leader Price Leader ■ 3.3-V LVTTL/LVCMOS
Feature Leader ■ 2.5-V LVTTL/LVCMOS
Wide Range of ■ 1.8-V LVTTL/LVCMOS
■ 1.5-V LVCMOS
Package Offerings Base on each I/O Bank
Industrial-Grade
Offerings
MAX 3000A
Price Leader

MAX 3000A Device Block Diagram

MAX Macrocell Global Global
Clear Clock
Parallel Logic 7000 has two Global Clock

Expanders
(from other MCs) Programmable
Register
Register
Bypass
PRn
Product- D Q to I/O
Term Control
Select Block
ENA
Matrix CLRn
VCC
Clear
Select
Clock/
Shared Logic Enable to PIA
36 Programmable Expanders Select
Interconnect
Signals
16 Expander
and Altera marks in and outside the U.S. Product Terms
9
MAX II Device Family Overview
Device characteristics
− Non-volatile, instant-on programmable logic
− TSMC 0.18-μm, 6-lm flash process
− 240 to 2,210 logic elements (LEs)
− 80 to 272 user I/O pins
Key benefits
− Lowest cost per I/O pin
− Low power consumption
− Fast performance
− High-density

MAX II: The Lowest-Cost CPLD Ever
New Logic Architecture

− 1/2 the Cost
− 1/10 the Power Consumption
− 2X the Performance
− 4X the Density
Non-Volatile, Instant-On
Supports 3.3-, 2.5- & 1.8-V Supply
Voltages
Breakthrough Technology
to Expand the Market
Flexible Supply Voltage
On-Chip Voltage Regulator

Accepts 3.3-, 2.5- &
1.8-V Supply Inputs
Internally Converted to 1.8-
V Core Voltage
2.5 V
1.8 V
3.3 V
Convenience of 3.3 V with

the Power & Performance of 1.8 V
MAX II Device Family

MAX II Packaging and User I/O Pins

MAX II Family Package Size
F256
1.0mm FBGA
17x17mm
T100
0.5mm TQFP
16x16mm Partial
M100 Partial
0.5mm MBGA M256
6x6mm 0.5mm MBGA
© 2010 Altera Corporation—Confidential 11x11mm
MAX II Architecture
Logic
Elements
(LEs)
Staggered
I/O Pads
Configuration
Flash Memory
JTAG &
Control
Circuitry
User Flash
Memory
MAX II Performance
Delay for Best-Case

I/O Placement
tPD2
Delay for Worst-

tPD1 Case I/O
Placement: (Full
Diagonal Path
Across Device)

LE Normal Mode
sload sclear aload
Register
addnsub Chain
Row,
Reg
Reg Column
data1 & Direct
Link
data2 Routing
4-Input
4-Input clock
data3 LUT
LUT ena Local
cin aclr Routing
DEV_CLRn
data4 LUT
Chain
Register
Chain

User Flash Memory
Feature
− Flash memory
storage bank
Industry
− 8,192 bits per device
First!
− Interface to SPI, parallel, I2C
or proprietary buses
Applications
− Store revision & serial
number data
− Store boot-up & configuration data

MAX & MAX II Comparison
Parameter/Feature MAX MAX II

Process Technology 0.3-um EEPROM 0.18-um Flash
Logic Architecture Product Term Look-Up Table (LUT)
Density Range 32 to 512 Macrocells 128 to 2210 Macrocells
(240 to 2,210 LEs)
Routing Architecture Global Row & Column
On-Chip Flash Memory None 8 Kbits
Maximum User I/O Pins 212 272
Supply Voltage 5.0 V, 3.3 V, 2.5 V 3.3 V/2.5 V, 1.8 V
I/O Voltages 5.0 V, 3.3 V, 2.5 V, 1.8 V 3.3 V, 2.5 V, 1.8 V, 1.5 V
Global Clock Networks 2 per Device 4 per Device
Output Enables (OEs) 6 to 10 per Device 1 per I/O Pin
Schmitt Triggers None 1 per I/O Pin
ALTERA FPGA Cyclone series

Cyclone IV GX: Lowest Cost, Lowest Power
FPGAs with Transceivers Lowest Cost
Low Power
High functionality
− Up to 150K Logic Elements Functionality
− Up to 6.5 Mb RAM, 360 Multipliers
− Up to 8 integrated 3.125Gbps transceivers
Lowest system cost

− Smallest density FPGA with transceivers
− Integrated Hard IP
z PCIe x1, x2, x4 endpoint and rootport
z Transceivers built from ground up for low cost
− Requires only two power supplies
− Wirebond packages
Low power
− 60nm Low power process
− PCI to GbE bridge for <1.5W
− <150 mW per channel
15K LEs + two transceivers in 11 x 11mm package

Cyclone IV GX Family Plan
Total Hard
18 X 18
Device KLEs memory Transceivers MPLLs PLLs PCIe IP
multipliers cores
(Mbits)
EP4CGX15 14.4 0.5 0 2 2 1 1
EP4CGX22 21.3 0.8 40 4 2 2 1
EP4CGX30 29.4 1.1 80 4 2 2 1
EP4CGX50 49.9 2.5 140 8 4 4 1
EP4CGX75 73.9 4.2 198 8 4 4 1
EP4CGX110 109.4 5.5 280 8 4 4 1
EP4CGX150 149.8 6.5 360 8 4 4 1

Cyclone IV GX Package Plan
QN148 F169 F324 F484 F672 F896
0.5 mm 1.0 mm 1.0 mm 1.0 mm 1.0 mm 1.0 mm

11 x 11 14 x 14 19 x 19 23 x 23 27 x 27 31 x 31
XCV XVC XCV XCV XCV XCV

Device I/O I/O I/O I/O I/O I/O
Rs Rs Rs Rs Rs Rs
EP4CGX15 72 2 72 2
I/O intensive
EP4CGX22 72 2 150 4 applications
EP4CGX30 72 2 150 4
EP4CGX50 290 4 310 8

Low I/O count for
EP4CGX75 290 4 310 8
cost and form factor
EP4CGX110 optimization 270 4 393 8 475 8
EP4CGX150 270 4 393 8 475 8
All packages are wire bond and come in both leaded and RoHS-compliant options

Cyclone IV GX Device Packaging Ordering Information

Protocol Support
EP4CGX50, 75,
Bandwidth EP4CGX15, 22,
Protocol 110, and 150 IP support
(Gbps) and 30 support
support
PCIe Gen1.1 2.5 Yes Yes Altera

GbE 1.25 Yes Yes Altera
Basic (proprietary) Up to 2.5 Up to 3.125 N/A
CPRI 3.072 (1) (2) Yes Altera
XAUI 3.125 (1) Yes Altera
3G Triple Rate SDI 2.97 Yes Altera

V-by-one 3.0 Yes 3rd Party
DisplayPort 2.7 Yes 3rd Party
SRIO 3.125 (1) Yes Altera
SATA 3.0 Yes 3rd Party
(1) These protocols may be added opportunistically pending characterization at 3.125G data rates
(2) If implemented, CPRI support for EP4C30 and smaller will support single hop topology only
Protocol Support Roadmap
Protocol QII 9.1 QII 9.1 SP1 QII 9.1 SP2 QII 10.0
PCIe x1, x4
GIGE
PCIe x2
Basic
SRIO
XAUI
CPRI
SDI
Vx1
DisplayPort
SATA
Cyclone IV E: Lowest Cost, Lowest Power
Lower your costs Lowest Cost

− Lowest cost FPGAs Lowest Power
− Only 2 power supplies Unprecedented
− Cost optimized packaging Combination
Lower your power

− 25% lower power consumption
− 1.0V core voltage
− Low Power process
Unprecedented Combination
− Up to 115K LE of logic
− Up to 3.8 Mbits of Embedded RAM
− Up to 266 18x18 Embedded Multipliers
− Up to 535 user IO
The Lowest Cost, Lowest Power FPGAs

28
Cyclone IV E Family Plan
Equivalent Total memory 18 X 18

Device PLLs
KLEs (Mbits) multipliers
EP4C6E 6.2 0.27 15 2
EP4C10E 10.3 0.42 23 2
EP4C15E 15.4 0.51 56 4
EP4C30E 28.8 0.6 66 4
EP4C40E 39.6 1.16 116 4
EP4C55E 55.8 2.39 154 4
EP4C75E 75.4 2.8 200 4
EP4C115E 114.4 3.98 266 4

Cyclone IV E Package Plan
E144 F256 F484 F672

Device 14 x 14 mm 14 x 14 mm 23 x 23 mm 27 x 27 mm
EP4C6E 94 182
EP4C10E 94 182
EP4C15E 168 346
EP4C30E 331 535

EP4C40E 331 535
EP4C55E 327 377
EP4C75E 295 429
EP4C115E 283 531
All packages are wire bond and come in both leaded and RoHS-compliant options

Cyclone III FPGA Family
Low power
− TSMC 65-nm low-power (LP) process Low Power
− Quartus® II software power-aware design flow High Functionality
− 120K logic elements (LEs) under ½ W static Low Cost
High functionality
− Densities ranging from 5K to 120K LEs
− Up to 4 Mbits of embedded memory
− Up to 288 embedded multipliers for digital signal processing
(DSP)
Low cost
− First low-cost 65-nm FPGA Shipping
− Free Quartus II Web Edition software Now!
Turn your ideas into revenue faster

Cyclone III Family
M9K Total
18 X 18
Device LEs memory memory PLLs Global clocks
Multipliers
blocks (Mbits)
EP3C5 5,136 46 0.4 23 2 10
EP3C10 10,320 46 0.4 23 2 10
EP3C16 15,408 56 0.5 56 4 20
EP3C25 24,624 66 0.6 66 4 20
EP3C40 39,600 126 1.1 126 4 20
EP3C55 55,856 260 2.3 156 4 20
EP3C80 81,264 305 2.7 244 4 20
EP3C120 119,088 432 3.9 288 4 20
Available in commercial, industrial,

extended temperature, -6,7,8 speed grades
Cyclone III Package Offerings
E144 Q240 F256 U256 F324 F484 U484 F780
Device
0.5 mm 0.5 mm 1.0 mm 0.8 mm 1.0 mm 1.0 mm 0.8 mm 1.0 mm
22 x 22 35 x 35 17 x 17 14 x14 19 x 19 23 x 23 19 x19 29 x 29
EP3C5 94 182 182
EP3C10 94 182 182
EP3C16 84 160 168 168 346 346
EP3C25 82 148 156 156 215
EP3C40 128 195 331 331 535
EP3C55 327 327 377
EP3C80 295 295 429
EP3C120 283 531
Denotes vertical migration support

Optimized to offer the highest logic, memory,
multiplier, and I/O resources
Cyclone II FPGA Family
Low-Cost Leadership
− Industry’s Smallest Die Size
− Low-Cost Packages
− 30% Lower Cost than Cyclone FPGAs
New Advanced Capabilities
− Over 3.5X the Logic Density of Cyclone FPGAs
− High-Performance DSP
− Low-Cost Embedded Processing
Performance Leadership
− 60% Faster Than Competing Low-Cost FPGAs
Proven 90-nm Process Technology
− Second Altera Product on TSMC 90-nm Process
The Lowest-Cost FPGAs Ever

Cyclone II Family Overview
Logic M4K Total 18x18 Maximum

Device Element Memory Memory Embedded PLLs User
s Blocks Bits Multipliers I/O Pins
EP2C5 4,608 26 119,808 13 2 158
EP2C8 8,256 36 165,888 18 2 182

EP2C15A 14,448 52 239616 26 4 315
EP2C20 18,752 52 239,616 26 4 315
EP2C35 33,216 105 483,840 35 4 475
EP2C50 50,528 129 594,432 86 4 450
EP2C70 68,416 250 1,152,000 150 4 622
Note: All Densities Will be Offered in All Speed Grades (-6, -7, -8). -6 is the Fastest Speed Grade.

Cyclone IV & III Logic Element

Cyclone II Logic Element
LUT Carry Carry Register

Chain In0 In1 Chain
Local
Routing
In1
In2 General
LUT REG
In3 Routing
In4
Clock General
Routing
Carry Carry Register

Out0 Out1 Chain

Cyclone III Embedded Multiplier Functionality
Up to 260-MHz performance
Supports full-precision 18-bit or 9-bit mode
− One 18-bit or two 9-bit multipliers per block
Sign_X
Output Registers
18
Input Registers
X
36 36
18
Y
Sign_Y
Clock
Clear
■ Cyclone IV Up to 360 18 × 18 multipliers for DSP processing

Cyclone II Embedded Multiplier Details
Sign_X
Output Registers
18
Input Registers
X
36 36
18
Y
Sign_Y
Clock
Clear
250-MHz Performance
Note: Fastest
© 2010 Altera Speed Grade with Registers Activated in 18x18 or 9x9 Mode
Corporation—Confidential
Cyclone III Clock Networks & PLLs Overview
Up to 20 Global Clocks Per Device
Dual purpose as high fan out control signals
4
GCLK
PLL 3 Mux PLL 2
GCLK [14:10]
4
GCLK GCLK
4 Mux GCLK [9:5] Mux
GCLK [0:4]
GCLK [15:19]
GCLK
PLL 1 PLL 4
Mux
4
Cascading PLLs Supply a
clk to other
devices
Cyclone III
PLL Output Pin
5 55Clock
Clock
GCLK Networks
MUX Networks
per
perPLL
PLL
Supply a
Cascade through global clock network clk to other
devices
Cyclone III
PLL 5 Up to 10 internal & 2 external clocks
GCLK from 1 clock source
MUX
Finer resolution multiplication/division &
phase shifting
Clean up noisy external clock sources

New in Cyclone III
Cyclone III: PLLs
Output
Clock Pins
Switchover
Clock Pin C0
[3..0]
N Global
PFD CP LF VCO C1 Clock
Network
Clock C2 [4..0]
Network M
C3
Feedback
C4
Two Additional
Output Counters
Dynamically reconfigurable in user mode

Cyclone III: Clocking and PLLs
Cyclone II Cyclone III Cyclone III Advantages
Number of PLLs 2–4 2–4 Same

Up to 8 additional global clocks
Outputs per PLL 3 5
driven by PLLs
Number of Global Combine required clock
8 – 16 10 – 20
Clocks signals into fewer PLLs
Min, Max Broader range improves
10 – 400 5 – 440
Frequency (MHz) system flexibility
Dynamically Frequency Improve system performance

No
Configurable and Phase by removing device downtime
Increase PCB routing flexibility

Cascadable No Yes
and reduce jitter

I/O Pin Features
Variety of I/O Standards LVDS
− HSTL, SSTL Class I and II up to 875
Mbps
− LVDS, RSDS, Mini-LVDS, PPDS Bank
Bank 33 Bank
Bank 44
− LVCMOS
Bank 22
Bank
Bank 55
− LVTTL
Bank
− LVPECL
− PCI, PCI-X
Bank 11
Bank
Bank 66
Bank
3.3-V compatible
On-chip termination
Bank
Bank 88 Bank
Bank 77
Adjustable slew rates
Eight banks of every device in the family
− Each can implement any supported I/O standard
DDR2
Dedicated memory interfaces up to 400 Mbps
− QDR II, DDR, and DDR2
Complete flexibility to implement a

wide variety of I/O standards
Cyclone III: Supported I/O Standards
Single-Ended I/O Standards Max Usage

2.5V SSTL Class I and II 167 MHz DDR SDRAM
1.8-V SSTL Class I and II 200 MHz DDR/DDR2 SDRAM
1.8-V/1.5V/1.2-V HSTL I and II 167 MHz QDR I/II SRAM
3.3-V PCI Compatible 66 MHz Embedded
3.3-V PCI-X 1.0 Compatible 100 MHz Embedded
3.3-V LVTTL, LVCMOS 100 MHz System Interface
3.0V/2.5-V/1.8-V LVTTL 167 MHz System Interface
3.0-V/2.5-V/1.8-V/1.5-V/1.2-V LVCMOS 167 MHz System Interface
Differential I/O Standards Max Comment

LVDS 875 Mbps High-Speed Serial
RSDS/Mini-LVDS Transmission 440 Mbps High-Speed Serial
LVPECL 500 MHz High-Speed Clocks
PCI Express* 2.5 Gbps Per Channel
Read and Follow AN 447 If Using 2.5/3.0/3.3-V

LVTTL or LVCMOS I/O Standards
*IP cores available, requires external PHY devices
External Memory Interface Summary
Memory Bus Maximum Maximum

I/O Standard
Technology Width Clock Speed Data Rate
SDR SDRAM LVTTL 72 bits 167 MHz 167 Mbps
SSTL-2 Class I 72 bits 167 MHz 333 Mbps

DDR SDRAM
SSTL-2 Class II 72 bits 133 MHz 267 Mbps
SSTL-18 Class I 72 bits 167 MHz 333 Mbps

DDR2 SDRAM
SSTL-18 Class II 72 bits 125 MHz 250 Mbps
HSTL 1.8V Class I 36 bits 167 MHz 668 Mbps

QDRII SRAM
HSTL 1.8V Class II 36 bits 100 MHz 400 Mbps
Note: New Standards Highlighted in Italics
Optimized in Dedicated Circuitry

Key Memory Interfaces Supported
Cyclone II Cyclone III

Memory Performance Performance % Increase
SDR 167 MHz 167 MHz -
DDR 167 MHz 167 MHz -
DDR2 167 MHz 200 MHz 20%
QDR II 167 MHz 167 MHz -
*External memory interface support on all I/O banks
Improved Memory Performance

and Flexibility

Configuration Mode Overview
Programming Mode Cyclone III Cyclone I & II Stratix III Stratix II Stratix
Active Serial 9 9 9 9
Active Parallel 9
Passive Serial 9 9 9 9 9
Fast Passive Parallel 9 9 9 9
JTAG 9 9 9 9 9
Remote Update 9 9 9 9
First time for Cyclone Family FPGAs
Active: Controller in FPGA & Clock is from FPGA
Passive: Controller outside of FPGA & clock is supplied from outside controller
New Configuration Options
Configuration Option Cyclone II Cyclone III
Active Serial (2-Chip) Yes Yes

Passive Serial (3-Chip) Yes Yes
Active Parallel (2-Chip) No Yes
Passive Parallel (3-Chip) No Yes
Altera, Intel, and
Flash Source Altera
Spansion
SEU Protection CRC CRC
With External
Remote Update No Host Required
Host
< 50 ms Wake-Up Select Densities All Densities

Programming Flash in System
Program or examine Flash device from Quartus II programmer
window
− Cyclone III works as a Flash programmer with Flash loader SOF
− Quartus II downloads SOF automatically & programs Flash
Eliminates additional hardware and software for on board Flash
programming
− Unique tool for Altera
USB Flash Programmer*
JTAG Parallel Flash Or

Serial Configuration
Cyclone III Device
Flash Loader
SOF
USB
User board
* ByteBlaster & EthernetBlaster works identically

Configuration Mode Comparison
Additional # # of Data
Configuration Ease of Config Remote
Chips Cyclone III Compre-
Mode Usea Speedb Upgrade
Required Pinsc ssion
Active Serial 1 257ms 1 4 9 9

Active Parallel 2 29ms 1 47 9
Passive Serial 3 103ms 2 2 9
Fast Passive
Parallel
4 23ms 2 9
JTAGd 5 185ms 2 4
a. Ease of Use: Subjective rating based on number of chips, number of I/Os
required, and additional knowledge requirement (1 being the easiest solution)
b. Benchmark based on 3C80 at maximum frequency for each mode
c. Pin count excluding MSEL3..0, nStatus, CONF_Done, nCE, and nCEO
d. JTAG using an external controller and a Flash device
Configuration File Size & Time
File Size* Compressed AS**
Device AP (ms) FPP (ms)
(Mbits) Size (Mbits) (ms)
EP3C10 2.2 1.2 33 4 3
EP3C16 3.4 1.9 49 5 4
EP3C25 5.4 3.0 78 9 7
EP3C40 8.6 4.8 125 14 11
EP3C55 12.1 6.7 177 20 16
EP3C80 17.7 9.8 257 29 23
Clock Frequency for Active Serial (AS): 40Mhz, Active Parallel (AP):
40Mhz, Fast Passive Parallel (FPP): 100Mhz
* Preliminary information
** Configuration Time using compressed data for AS mode
ALTERA FPGA Stratix series

Stratix IV FPGAs: A Closer Look
Highest density (these numbers need to be updated)
− Up to 820K LEs
− Up to 23.1 Mbits internal RAM Shipping
− Up to 1,288 18 x 18 multipliers now!
Highest bandwidth and performance
− Up to 48 transceivers operating up to 8.5 Gbps
− Up to 4 x8 hard intellectual property (IP) blocks for
PCI Express Gen1 and Gen2
− Up to 773 giga multiply-accumulate operations per second (GMACS)
digital signal processing (DSP) performance
− 2 speed grade performance advantage
Lowest power
− Programmable Power Technology
− Quartus II PowerPlay technology
Highest density,
− 40-nm process benefits including 0.9V core voltage
Seamless FPGA prototyping to HardCopy

ASIC production highest performance,
Quartus II software: #1 in performance and productivity AND lowest power

Stratix IV Device Family Plan
Transceivers LVDS(1) Memory Multipliers
Device LEs I/Os
(11.3,8.5, 6.5 Gbps) (1.6, 1.1 Gbps) (Mbits) (18x18)
EP4SGX70 70K 24 (0, 16, 8) 120 (56, 64) 480 6.3 384
EP4SGX110 110K 24 (0, 16, 8) 120 (56, 64) 480 8.1 512
EP4SGX180 180K 36 (0, 24,12) 184 (88, 96) 736 11.1 920
Stratix IV GX
EP4SGX230 230K 36 (0, 24,12) 184 (88, 96) 736 13.9 1,288
FPGA
EP4SGX290 290K 48 (0, 32,16) 226 (98, 128) 904 13.3 832
EP4SGX360 360K 48 (0, 32,16) 226 (98, 128) 904 17.7 1,040
EP4SGX530 530K 48 (0, 32,16) 226 (98, 128) 904 20.3 1,024
EP4S40G2 230K 36 (12,12,12) 140 (44, 96) 636 13.9 1,288
EP4S40G5 530K 36 (12,12,12) 140 (44, 96) 636 20.3 1,024
Stratix IV GT EP4S100G2 230K 36 (24, 0,12) 140 (44, 96) 636 13.9 1,288
FPGA EP4S100G3 290K 48 (24, 8,16) 172 (44, 128) 754 13.3 832
EP4S100G4 360K 48 (24, 8,16) 172 (44, 128) 754 17.7 1,024
EP4S100G5 530K 48 (32, 0,16) 172 (44, 128) 754 20.3 1,024
EP4SE230 230K - 120 (56, 64) 480 13.9 1,288
Stratix IV E EP4SE360 360K - 216 (88, 128) 864 17.7 1,040
FPGA
EP4SE530 530K - 240 (112, 128) 960 20.3 1,024
EP4SE820 820K - 276 (132, 144) 1,104 23.1 960
(1) LVDS channel count represents number of full duplex channels, included in the total I/O count. (True LVDS, Emulated LVDS)
© 2010 All LVDS
Altera Rx can be used as
True LVDS Rx or emulated LVDS Tx, effectively doubling the number of LVDS Tx available per device.
Corporation—Confidential
TheCYCLONE,
ALTERA, ARRIA, maximum data rateMAX,
HARDCOPY, for the EP4SE820
MEGACORE, LVDS
NIOS, I/Os &isSTRATIX
QUARTUS 1.25 Gbps (notU.S.
are Reg. 1.6Pat.
Gbps).
& Tm. Off.
55
Stratix IV E Device Package Plan
F780 F1152 F1517 F1760
Device
(29 mm) (35 mm) (40 mm) (43 mm)
EP3SL50 480, 56
(Total I/O count, true LVDS count)
EP3SL70 480, 56
EP3SL110 480, 56 736, 88
EP3SL150 480, 56 736, 88
Stratix III EP3SL200 480, 56 (2) 736, 88 960, 112

family EP3SL340 736, 88 (2) 960, 112 1,104, 132
EP3SE50 480, 56
EP3SE80 480, 56 736, 88
EP3SE110 480, 56 736, 88
EP3SE260 480, 56 (2) 736, 88 960, 112
EP4SE230 480, 56
EP4SE360 480, 56 (2) 736, 88

Stratix IV E
family EP4SE530 736, 88 (2) 960, 112 (2) 960, 112
EP4SE820 736, 88 (2) 960, 112(2) 1,104, 132
(1) All devices are offered in flip-chip ball-grid array (BGA) with 1.0-mm pitch
(2) These devices are in hybrid flip-chip ball-grid array, identical ball pattern but larger body overhang Pin
(3) LVDS I/O count represents number of full duplex channels, these are included in the total I/O count migration
(4) AN557: Stratix III to Stratix IV E Cross-Family Migration Guidelines
Stratix IV GX Device Package Plan
F780(4) F1152(4) F1152 F1517 F1760 F1932
Device
(29 mm) (35 mm) (35 mm) (40 mm) (43 mm) (45 mm)
EP4SGX70 368, 28, 8 480, 56, 24
EP4SGX110 368, 28, 8 368, 28, 16 480, 56, 24
EP4SGX180 368, 28, 8 560, 44, 16 560, 44, 24 736, 88, 36
EP4SGX230 368, 28, 8 560, 44, 16 560, 44, 24 736, 88, 36
EP4SGX290 288, 0, 16 560, 44, 16 560, 44, 24 736, 88, 36 864, 88, 36 904, 98, 48
(2)
EP4SGX360 288, 0, 16 560, 44, 16 560, 44, 24 736, 88, 36 864, 88, 36 904, 98, 48
(2)
EP4SGX530 560, 44, 24 736, 88, 36 864, 88, 36 904, 98, 48

(2) (2)
Total I/O, LVDS, transceiver count Pin migration

(2) These devices are in hybrid flip-chip ball-grid array, identical ball pattern but larger body overhang
(3) LVDS I/O count represents number of full duplex channels, these are included in the total I/O count
(4) Devices in these columns have 6.5 Gbps transceivers only.
57
Stratix IV GT Device Family
Transceivers Memory
Device LEs 11.3 Gbps (Total) LVDS I/Os (Mbits) Package1
40G Devices
EP4S40G2 230K 12 (36) 44 636 13.9 F1517
EP4S40G5 530K 12 (36) 44 636 20.3 H1517 (2)
100G Devices
EP4S100G2 230K 24 (36) 44 636 13.9 F1517
EP4S100G5 530K 24 (36) 44 636 20.3 H1517 (2)
EP4S100G3 290K 24 (48) 44 754 13.3 F1932
EP4S100G4 360K 24 (48) 44 754 17.7 F1932
EP4S100G5 530K 32 (48) 44 754 20.3 F1932
Total I/O, LVDS, transceiver count Pin migration

(2) Some devices are in hybrid flip-chip ball-grid array, identical ball pattern but larger body overhang
(3) LVDS I/O count represents number of full duplex channels, these are included in the total I/O count

Stratix IV GX Transceiver Block Topology
F780 F1152 F1152 F1517 F1760 F1932
Device
(29 mm) (35 mm) (35 mm) (40 mm) (42.5 mm) (45 mm)
EP4SGX70 DF29 HF35
EP4SGX110 DF29 FF35 HF35
EP4SGX180 DF29 FF35 HF35 KF40
EP4SGX230 DF29 FF35 HF35 KF40
EP4SGX290 FH291 FF35 HF35 KF40 KF43 NF45
EP4SGX360 FH291 FF35 HF351 KF40 KF43 NF45
EP4SGX530 HH351 KH401 KF43 NF45
TCVR (8.5G, 6.5G) DF29 FH29 HF35, HH35 KF40, KH40 NF45
8 (0,8) 16 (0,16)2 24 (16, 8)2 36 (24,12)2 48 (32,16)2
8.5G Full XCVR
6.5G Full XCVR
6.5G CMU XCVR
CMU
6G LC2
PCIe hard IP
1. Hybrid packages have larger molding dimensions - FH29 (33mm), HH35 (42.5mm), KH40 (42.5mm)
2. TheCorporation—Confidential
© 2010 Altera 4SGX230/180/110 and 70 have only 1 LC tank per side
Stratix IV GT Transceiver Block Topology
F1517 F1932
Device
(40 mm) (45 mm)
EP4S40G2 F40
EP4S40G5 H40
EP4S100G2 F40
EP4S100G3 x F45
EP4S100G4 x F45
EP4S100G5 H401 F45
TCVR (11.3G, 8.5G, 6.5G) 4S40G2 4S100G2 4S40G5 4S100G5 4S100G3/4/5

F40 F40 H40 H40 F45
11.3G Full XCVR 36 (12,12,12) 36 (24,0,12) 36 (12,12,12) 36 (24,0,12) 48 (24,8,16)
.600 - 8.5G Full XCVR

.600 - 6.5G CMU XCVR
10G LC
6G LC
PCIe hard IP
1) Hybrid package molding dimension H40 (42.5mm)

2) 4S100G2 and 4S40G2 have only 1 6G LC per side
Stratix III Device Family Plan
Embedded
Equiv. M9K M144K MLAB Max 18X18
FPGA Variant Device ALMs Regs Memory
LEs Blocks Blocks (Kbits) Multipliers
(Kbits)
EP3SL50 19K 48K 38K 108 6 1,836 594 216
EP3SL70 27K 68K 54K 150 6 2214 844 288
EP3SL110 43K 107K 86K 275 12 4203 1,331 288
Stratix III L EP3SL150 57K 142K 114K 355 16 5,499 1,775 384
EP3SL200 80K 199K 160K 468 24 7,668 2,486 576
EP3SE260* 102K 254K 204K 864 48 14,688 3,180 768
EP3SL340 135K 338K 270K 1,040 48 16,272 4,225 576
EP3SE50 19K 48K 38K 400 12 5,328 594 384
Stratix III EP3SE80 32K 80K 64K 495 12 6,183 1,000 672
E EP3SE110 43K 107K 86K 639 16 8,055 1,331 896
EP3SE260 102K 254K 204K 864 48 14,688 1,331 768
*EP3SE260 shown in both logic & enhanced groupings

Stratix III Device Family Plan
484-Pin 780-Pin 1152-Pin 1517-Pin 1760-Pin

FPGA FBGA FBGA FBGA FBGA FBGA
Device
Variant
1.0 mm 1.0 mm 1.0 mm 1.0 mm 1.0 mm
23 x 23 29 x 29 35 x 35 40 x 40 43 x 43
EP3SL50 288 480

EP3SL70 288 480
EP3SL110 480 736
Stratix III L EP3SL150 480 736
EP3SL200 480 736 864
EP3SE260 480 736 960
EP3SL340 736 960 1,104
EP3SE50 288 480
EP3SE80 480 736

Stratix III E
EP3SE110 480 736
EP3SE260 480 736 960
Denotes vertical migration support

Introducing Stratix II FPGAs
50% Faster Performance

2.25X Logic Capacity Increase
40% Lower Price per Density
4X DSP Bandwidth Increase
1-Gbps LVDS
New, Faster External Memory
Interfaces
Non-Volatile Design Security
All New Logic Architecture

Enables Breakthrough Capabilities
Stratix II Device Family
Equivalent Total 18-Bit x Maximum

M512 M4K M-
Device ALMs (1)
Logic Memory 18-Bit PLLs(3) user I/O
RAM RAM RAM pins
Elements Bits Multipliers(2)
EP2S15 6,240 15,600 104 78 0 419,328 48 6 366
EP2S30 13,552 33,880 202 144 1 1,369,728 64 6 500
EP2S60 24,176 60,440 329 255 2 2,544,192 144 12 718
EP2S90 36,384 90,960 488 408 4 4,520,448 192 12 902
EP2S130 53,016 132,540 699 609 6 6,747,840 252 12 1126
EP2S180 71,760 179,400 930 768 9 9,383,040 384 12 1170
(1) Adaptive Logic Modules

(2) Does Not Include Soft Multipliers Implemented in Memory Blocks
(3) Includes Enhanced & Fast PLLs

Stratix IV & III Adaptive Logic Module (ALM)

Stratix series Adaptive Logic Module (ALM)
ALM
1 Comb.
2 Logic
Reg
Reg
Adder
Adder
ALM Inputs
3
4
5
6
Adder
Adder
7 Reg
Reg
8
Adaptive Logic Usage

Flexible Input Sharing
ALM Normal Mode Configurations
ALM ALM
5-LUT
5-LUT 5-LUT
5-LUT
3-LUT
3-LUT 4-LUT
4-LUT ALM
ALM ALM
4-LUT 6-
6-
4-LUT
7- LUT(1)
LUT (1)
7-
LUT(1)
LUT (1)
4-LUT
4-LUT 6-
6-
ALM ALM
LUT(1)
LUT (1)
5-LUT
5-LUT
6-LUT
6-LUT
5-LUT
5-LUT

Stratix IV DSP Block Details

DSP Block Details
Configurable 52-Bit
Multiplier Accumulator 50%
50% Faster
Faster
than
than
Stratix FPGAs(1)
Stratix FPGAs (1)
36
37
+-Σ
Output Register Unit

Input Register Unit
Optional Pipelining
Output Multiplexer
36
144 38 144
+
36
37
+-Σ
36
Includes Rounding &

Saturation Support
(1) 420-MHz Performance Target for Registered 18-Bit x 18-Bit & 9-Bit x 9-Bit Modes
Stratix III/IV I/O Performance
Stratix III/IV Stratix III/IV

FPGAs I/O feature Benefit
FPGAs
Interconnect Performance
Dynamic
Saves
533 MHz/1,067 on-chip 9
DDR3 power
Mbps termination
DDR2 400 MHz/800 Mbps DDR3

DIMM
Read/Write 9
QDR II 350 MHz support
leveling
QDR II+ 400 MHz
Allows
RLDRAM II 400 MHz Variable
9 signal
I/O delay
LVDS 1.6 Gbps de-skew
Up to 24 I/O banks distributed on

all sides offer more flexibility
Stratix III External Memory Interfaces

Stratix II External Memory Interfaces(2006.11.28)

ALTERA FPGA Arria II GX series

Comprehensive, Robust Protocol Support
Protocol Data rate (Gbps)
Mainstream Wireline
PCI Express Fibre Channel ASI 0.27
3G basic SerialLite II Basic (proprietary) 0.6 - 3.75

Gigabit Ethernet SGMII, SONET 0.6144, 1.2288, 2.4576,
CPRI
SATA GPON, XAUI 3.072
SAS 10G Ethernet (XAUI) 3.125

Gigabit Ethernet 1.25
1.244 uplink, 2.488
GPON
downlink
HiGig+ 3.75
OBSAI 0.768, 1.536, 3.072
PCI Express Gen1 2.5
PCI Express Cable 2.5
SAS 1.5, 3
SATA 1.5, 3
SDI SD/HD 0.27 / 1.485
3G-SDI 2.97
SerialLite II 0.6 - 3.75
Wireless Broadcast Serial RapidIO®
CPRI SD
1.25, 2.5, 3.125
OBSAI HD SONET OC-3/OC-12/OC-48 0.155, 0.622, 2.488

SRIO 3G-SDI
Arria II GX Family Plan
RAM Total
Equiv MLAB 18 X 18 Transceivers Tx
Device Mbits/ M9K PLLs Clks
LEs memory multipliers @ 3.75 Gbps PLLs
blocks (Mbits)
EP2AGX45 45K 2.9 / 319 0.6 228 8 4 4 32
EP2AGX65 63K 4.4 / 495 0.8 312 8 4 4 32
EP2AGX95 94K 5.5 / 612 1.2 448 12 6 6 40
EP2AGX125 124K 6.6 / 730 1.6 576 12 6 6 40
EP2AGX190 190K 7.6 / 840 2.4 656 16 6 8 40
EP2AGX260 256K 8.5 / 950 3.2 736 16 6 8 40

75
Arria II GX Package Offerings
U358 F572 F780 F1152

Device
0.8 mm 1.0 mm 1.0 mm 1.0 mm
17 x 17 25 x 25 29 x 29 35 x 35
EP2AGX45 156 (32,4) 252 (56,8) 364 (84,8)
EP2AGX65 156 (32,4) 252 (56,8) 364 (84,8)
EP2AGX95 260 (56,8) 372 (84,12) 452 (104,12)
EP2AGX125 260 (56,8) 372 (84,12) 452 (104,12)
EP2AGX190 372 (84,12) 612 (144,16)
EP2AGX260 372 (84,12) 612 (144,16)
Number of I/Os (LVDS, number of transceivers)

76
HardCopy Structured ASICs
Cost-Competitive with
Structured ASICs
More Robust
Back-End Flow
Faster Performance at
Lower Cost than FPGA

What is Nios II?
Altera’s Second Generation Soft-Core 32 Bit RISC Microprocessor
− Developed
- Nios Internally
II Plus By Altera Written In HDL
All Peripherals
− Harvard Architecture
- Can Be Targeted For All Altera FPGAs
− Royalty-Free
- Synthesis Using Quartus II Integrated Synthesis
Nios II
Avalon Switch Fabric

Cache
UART
CPU
Debug GPIO
On-Chip Timer
ROM
SPI
On-Chip SDRAM
RAM Controller
FPGA
Nios II Processor Architecture
Classic Pipelined RISC Machine
− 32 General Purpose Registers
− 3 Instruction Formats
− 32-Bit Instructions
− 32-Bit Data Path
− Flat Register File
− Separate Instruction and Data Cache (configurable sizes)
− Tightly-Coupled Memory Options
− Branch Prediction
− 32 Prioritized Interrupts
− On-Chip Hardware (Multiply, Shift, Rotate)
− Custom Instructions
− JTAG-Based Hardware Debug Unit

Problem: Reduce Cost, Complexity & Power
I/O Flash
CPU
SDRAM
I/O
I/O I/O I/O
DSP
I/O FPGA
CPU DSP
Solution: Replace External Devices

with Programmable Logic
Problem: Reduce
System Cost, Complexity & Power
On A Programmable Chip (SOPC)
Flash
FPGA
SDRAM
CPU is a Critical
Solution: ReplaceControl Function
External Devices
Required forProgrammable
with System-Level Logic
Integration
Quartus II Development system overview

Software & Development Tools
Quartus II Subscription Edition
software
− MAX series devices : All
− Cyclone series devices : All
− Arria GX FPGAs : All
− Arria II GX FPGAs : All
− Stratix IV/ IV GX/IV GT FPGAs: All
− Stratix III FPGAs: All
− Stratix II / II GX FPGAs: All
− Stratix / GX FPGAs: All
Quartus II Web Edition software
− Free version
− Not all features & devices included
z See
http://www.altera.com/literature/po/ss_quartussevswe.pdf

Quartus II Development System
Fully-Integrated Design Tool

− Multiple Design Entry Methods
− Logic Synthesis
− Place & Route
− Simulation
− Timing & Power Analysis
− Device Programming

Typical PLD Design Flow
Design Specification Design entry/RTL coding
- Behavioral or structural description of design
RTL simulation
- Functional simulation
- Verify logic model & data flow
(no timing delays)
M512
LE Synthesis
- Translate design into device specific primitives
M4K I/O - Optimization to meet required area & performance constraints
Place & route

- Map primitives to specific locations inside
Target technology with reference to area &
performance constraints
- Specify routing resources to be used
Typical PLD Design Flow
tclk Timing analysis
- Verify performance specifications were met
- Static timing analysis
Gate level simulation

- Timing simulation
- Verify design will work in target technology
PC board simulation & test

- Simulate board design
- Program & test device on board

Design Entry Methods
Quartus II software Top-level design files can be
schematic, HDL or 3rd-Party
− Text Editor Top-
Level File
netlist file
z AHDL
z VHDL
z Verilog HDL
z System Verilog HDL
− Schematic Editor .bdf .v, vlg,
.bsf .tdf .vhd .v .edf
z Block diagram files .gdf
.edif .vhd, .VHDL,
z Graphic design files vqm
z State Machine files Block Symbol Text Text Text Text Text
− Memory Editor file file file file file file file
z HEX
z MIF Imported from 3rd-Party
3rd-party EDA tools

Generated within Quartus II software EDA tools

− EDIF files
− Verilog/VHDL
− Verilog Quartus Mapping (.VQM)
Mixing & matching design files allowed

What’s New in Quartus II v9.1 Technical.
Avalon® verification IP
Further expands leadership in − Bus functional models
compile time and timing closure − Bus monitors
cycle
− Rapid Recompile Nios II embedded processors
− Faster push-button compilation − Nios II Software Build Tools for
Eclipse®
Initial synthesis support for
VHDL-2008 Operating system support for
SUSE Enterprise 10
I/O system design enhancements
− SSN Analyzer support for Stratix IV External memory interface
and Arria II GX FPGAs enhancements
− New High-Performance Memory
Controller II (DDR/DDR2/DDR3
support)
− New low-latency UniPHY
architecture

Agenda
Timing Analysis

Principles of Static Timing Analysis
Every path has a start point and an end point:

ONLY FOUR POSSIBLE Start Points: End Points:
TIMING PATHS • Input ports • Output ports
• Clock pins • Data input pins
of sequential devices
IN * D Q * D Q * OUT
CLK clk clk
combinational
delays*

Running Timing Analysis
Automatically
− Use Full Compilation
Manually
− Processing Menu ⇒ Start ⇒ Start Timing Analysis
− Tcl Scripts
− Uses
z Changing Speed Grade
z Annotating Netlist with Delay Information

Reporting Timing Results
Timing Analyzer Section of

Compilation Report
− Summary
Timing Analyses
− Clock Setup (fmax)
− Clock Hold
− tsu (Input Setup Times)
− th (Input Hold Times)
− tco (Clock to Out Delays)
− tpd (Pin to Pin Combinatorial Delays)

Clock Setup (fmax)
Worst-Case (Maximum) Clock Frequency

− Without Violating Internal Setup Times
tco B tsu
C
Clock Period
Clock Period = Clock-to-Out + Data Delay + Setup Time - Clock Skew

= tco + B + tsu - (E - C)
fmax = 1/Clock Period

Clock Setup (fmax) Tables
Fmax Values Are Listed in Ascending Order;
Worst fmax Worst Fmax Is Listed on the Top
Source, Destination
Registers & Associated
Fmax Values
Select
Clock Setup

fmax Analysis
To Analyze the Path More Closely
Highlight,
Right-Click
& Select
List Paths
Similar Steps for All Timing Path Analysis in Quartus II

fmax Analysis Details
Data Delay (B) Messages Window (System Tab) in Quartus II
Destination Register
Clock Delay (E)
Source Register
Clock Delay (C)
Setup Time (tsu)
Clock to
Output (tco)
tco B tsu
C
E 1 = 327.65 MHz
0.250 ns + 2.837 ns + (-0.036) ns – (-0.001) ns
Clock Period
Locate Delay Path in Floorplan
Right-click &
select locate
Compilation Report
Notes:
1) May also locate to floorplan from
message window
2) Use similar procedure for all
timing path analysis
Locate Delay Path in Floorplan
4.512 ns is the
total path delay
between source
& destination

I/O Setup (tsu) & Hold (th) Analyses
Data delay intrinsic tsu & hold
tsu
th
Clock delay
tsu = data delay - clock delay + intrinsic tsu

th = clock delay - data delay + intrinsic th

I/O Clock-to-Output Analysis (tco)
intrinsic tco Data delay
tco
Clock delay
clock delay + intrinsic tco + data delay = tco

I/O Timing Analyzer
tsu, tco, th Will All Show up in the Timing Analyzer Report
Register Name
Clock Name
Select Value
Parameter
Pin Name

Note:
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS Timing
& STRATIX Analysis
are Reg. of Off.
U.S. Pat. & Tm. tpd is similar
Single Clock Assignment
Assignments ⇒ Settings ⇒ Timing Requirements & Options
Global Clock Assignment

for a Single Clock Design
For Designs with Multiple

Asynchronous Clocks, Enter
Required Fmax for Each
Individual Clock

Quartus II Quick Start using Galaxy Demo Kit

GALAXY MAX II Starter Kit
The MAX II Starter Kit includes the following :
1.Quartus II Web Edition Design Software

2.User Manual.
3.MAX II board
－MAX II (EPM1270T144C5)
－8 User-defined LED
－Four user-defined push-buttons switches
－7-segment LED display
－Serial connectors (RS-232 DB9 port)
－8-bis DIP Switch
－Four user-defined push-button switches
4.Accessories
－ByteBlaster II Download Cable
－6-V power supply or USB to DC Cable

4 Digitals seven segment LED Displayer (DS1)
LED Displayer是由4組7段顯示器所組成，七段顯示器的每一段LED相互連接在
一起，另外還各有一支common pin連接至其中一組七段顯示器。當其中一支
common pin為高準位時而且7段顯示器中的其中一段LED為低準位時，此七段
顯示器之其中一段LED將亮起。雖然4組7段顯示器中的每一段LED是連接在一
起的，但我們可以利用common pin 來決定到底啟動哪一組7段顯示器。一般來
說我們都是利用掃描common pin的方式來呈現4個不同的數字。

4 Digitals seven segment LED Displayer (DS1)
裝置 4 Digitals seven segment LED Displayer
Segment pin代號 a b c d e f g DP
MAX II腳位 37 38 39 40 41 42 43 44
裝置 4 Digitals seven segment LED Displayer
Common pin代號 Digital 1 Digital 2 Digital 3 Digital 4
MAX II腳位 29 30 31 32

8 Bits DIP Switch (SW6)
本實驗板提供 8 bits DIP Switch，當Switch切至

”ON”時，MAX II Device I/O將為Low，其中
8 bits DIP Switch的信號接腳和MAX II Device 的
I/O關係可參
考下表。
裝置 8 Bits DIP Switch
Switch代號 DIP1 DIP2 DIP3 DIP 4 DIP 5 DIP 6 DIP 7 DIP 8
MAX II腳位 22 21 16 15 14 13 12 11
備註：ON為低準位，OFF為高準位

4 Push Button (SW1 – SW4)
本實驗板提供4個 Push button 當按下此按鍵時，

將提供Low的信號給MAX II，不按時，此接腳將
Pull-High，其中Push Button的信號接腳和
MAX II Device 的I/O關係可參考下表。
裝置 4 Push Button
Push Button代號 SW1 SW2 SW3 SW 4
MAX II腳位 23 24 27 28
備註：按下時為低準位，不按時為高準位

8 LEDs (D1 – D8)
當MAX II I/O送出Low的信號時，LED將亮起
，其中8個LED的信號接腳和
MAX II Device 的I/O關係可參考下表。
裝置 8 LEDs
LED代號 D1 D2 D3 D4 D5 D6 D7 D8
MAX II腳位 1 2 3 4 5 6 7 8
備註：低準位LED亮，高準位LED不亮

16M Hz Oscillator
本實驗板提供1個16M Hz 全長型的振盪器，
此震盪器可經由JP1並利用Jumper將clock送至
MAX II Device，其中16M Hz 的全長型的振盪
器及JP1的信號接腳和MAX II Device 的I/O關
係可參考下表
Pin_18 / GCLK0P Pin_89 / GCLK2P
Pin_20 / GCLK1P Pin_91 / GCLK3P

Quartus II Quick Start LAB1

Objectives
Create a project using the New Project Wizard

Name the project
Add design files
Pick a device

Step 1 (Setup Project for QII 9.1)
Under File, Select New Project Wizard….
A new window appears. If an Introduction
screen appears, click Next.

Page 1 of the wizard should be completed with the following
working directory for this project <lab_install_directory> \galaxy_counter\
name of project galaxy_counter
top-level design entity galaxy_counter
Copy “seven_segment.vhd” and

“updowncounter.vhd” in galaxy_counter
Click Next to advance to the

Project Wizard: Add Files [page 2 of 5].

Using the browse button, select seven_segment.vhd and updowncounter.vhd
Add to the project. Click Next.

On page 3, select MAX II as the Family. Also, in the Filters section,
set Package to TQFP, Pin count to 144, and Speed grade to 5.
Select the EPM1270T144C5(or EPM1270T144C5ES) device from
the Available devices: window. Click Next.

On page 4 , you can specify any third party EDA tools you may be using
along with Quartus II. Since these exercises will be done entirely within
Quartus II, click Next.

The summary screen appears as shown. Click Finish.
The project is now created.


Objectives
Create a counter using the MegaWizard Plug-in

Manager
Build a design using the schematic editor
Analyze and elaborate the design to check for
errors

Step 1 Open the project and create schematic file
Select File ⇒ New and select Block Diagram/Schematic File. Click OK.
Select File ⇒ Save As and save the file as
C:\altera\galaxy_training\galaxy_counter.bdf

Step 2 Build an 23 bits counter using the MegaWizard Plug-in Manager
1.Choose Tools ⇒ MegaWizard Plug-In Manager. In the window that appears,
select Create a new custom megafunction variation. Click on Next.
2.On page 2a of the MegaWizard expand the arithmetic folder and select
LPM_COUNTER.
3.Choose Verilog HDL output For the name of the output file, type cnt23.
Click on Next

Step 3
Set the output bus to 23 bits. For the remaining settings in this window,
use the defaults that appear . Select Finish.

Step 4
In the Graphic Editor, double-click in the screen so that the Symbol Window
appears. Inside the symbol window, click on to expand the symbols defined
in the Project folder. Double-click on cnt23. Click the left mouse button to
put down the symbol inside the schematic file.
The symbol for “cnt23” now appears in the schematic.

Step 5
1. From the File menu, open the file seven_segment.vhd
2. From the File menu, go the Create/Update menu option and select
Create Symbol Files for Current File. Click Yes to save changes
to galaxy_counter.bdf.
3. Once Quartus II is finished creating the symbol, click OK. Close the
seven_segment.vhd file
4. In the Graphic Editor, double-click in the screen so that the Symbol
Window appears again. Double-click on seven_segment in the
Project folder. Click OK.. The symbol for “seven_segment”
now appears in the schematic.
5. Repeat 1~4 to Create a updowncounter symbol

Step 6 Add Pins to the Design
Input Output
For each of the pins listed in left Table , you must insert
clk seg[7..0]
rst Dig1
a pin and change its name
dig2
dig3
Dig4
1. To place pins in the schematic file, go to Edit ⇒ Insert ⇒ Symbol OR

double-click in any empty location of the Graphic Editor.
2. Browse to libraries ⇒ primitives ⇒ pin folder. Double-click on input
or output Hint: To insert multiple pins select Repeat Insert Mode.
3. To rename the pins double-click on the pin name after it has been
inserted.
4. Type the name in the Pin name(s) field and Click OK
.
Step 7 Connect the Pins and Blocks in the Schematic
1. In the left hand tool bar click on button to draw a wire and button to draw a bus.
Another way to draw wires and busses is to place the cursor next to the port of any
symbol. When you do this, the wire or bus tool will automatically appear.
2. Connect all of the pins and blocks as shown in the figure below

Step 8 Save and check the schematic
1. Click on the Save button in the toolbar to save the schematic.
2. From the Project menu, select Add/Remove Files in Project.
Click on the browse button to make sure the galaxy_counter.bdf,
cnt23.v ,seven_segment.vhd and updowncounter.vhd are added
to the project.
3. From the Processing menu, select Start ⇒ Start Analysis & Elaboration.
Analysis and elaboration checks that all the design files are present and
connections have been made correctly.
4. Click OK when analysis and elaboration is completed


Objectives
Pin assignment
Perform full compilation Build a design using the
schematic editor
How to Download programming file

Step 1
1. Choose Assignments ⇒ Assignment editor.
2. From the View menu, select Show All Know Pin Names.
3. Please click Pin in Category

Step 2
1. See “How to use MAX II Starter Kit”
2. Key in your pin number in location
3. Click on the Save button in the toolbar
4. From Assignments, select Device. Click Device & Pin options. Click
Unused pins .Select As input tri-stated from Reserve all unused pins
5. From the Processing menu, select Start Compilation

Step 3
1. From the Tools menu, select programmer
2. Click on Add File. Select galaxy_counter.pof.
3. Check Hardware Setup. Select your download cable on
Currently selected hardware
4. Select JTAG from Mode

Step 4
1. Turn on Program/configure and Verify. Or see figure below
2. Click Start
3. See 7-segment status

ALTERA Development Kit

Audio Video Dev Kit, Stratix IV GX Edition

Stratix IV E Development Board

Stratix III Development Board

Arria II GX development kit

Arria GX development kit
Low-cost board: $995
PCI Express x1, x4 compliance
Gigabit Ethernet (with
daughtercard)
Serial RapidIO 1.25 & 2.5 Gbps
(with daughtercard)
DDR2
1 HSMC connector
JTAG header
Complete documentation
and support
Arria GX development kit
DK-DEV-1AGX60N
Available in September

Cyclone III LS FPGA Development Kit

EP3C120 Development Kit
Specifications
− 256-Mbyte dual-channel DDR2
SDRAM
− 8-Mbyte SRAM
− 64-Mbyte Flash
− 10/100/1000 Ethernet and USB 2.0
− 2 line Character LCD
− 128 x 64 Graphics LCD
DSP version with A/D and D/A
Daughter card options from Altera
and partners
− DVI input/output
− Prototyping
− Connector conversion
Price
− Standard $1,495
− DSP $1695
Available in October
DSP using Data conversion HSMC board

Cyclone III FPGA Starter Kit
The Cyclone III FPGA Starter Development Kit is RoHS compliant and features:
Cyclone III Starter Board ,Cyclone III EP3C25F324 FPGA
Configuration
Embedded USB-Blaster™ circuitry (includes an Altera EPM3128A CPLD) allowing download of FPGA configurati
via the users USB port ,Power and analog devices from Linear Technology ,Switching power supply LTM4603EV
Switching and step-down regulators LTC3413, LT1959
Memory:
256-Mbit DDR SDRAM ,1-Mbyte Synchronous SRAM ,16-Mbytes Intel P30/P33 flash
Clocking
50-MHz on-board oscillator
Switches and indicators ,Six push buttons total, 4 user controlled ,Seven LEDs total, 4 user controlled
Connectors
High-Speed Mezzanine Connector (HSMC)
Supporting 13 user-controlled LVDS I/O channels and associated control signals
USB type B
Cables and power
USB cable
External power supply (U.S. compatible plug with EU and UK adaptors)
Cyclone III FPGA Starter Kit CD-ROM
Example designs targeting the Cyclone III FPGA Starter Board
Create an FPGA design in one hour ,Power measurements of a Cyclone III FPGA
A 32-bit soft processor system inside an FPGA
User guide ,Reference manual ,Board schematic and layout
Bill of Materials
Product and partner information
Download instructions to receive the latest version of the following software (at no charge):
Quartus® II Web Edition (FPGA design software) ,ModelSim®-Altera Web Edition (FPGA simulation software from Mode
Nios II Embedded Design Suite, Evaluation Edition (32-bit microprocessor software)
NEEK

Cyclone II FPGA Starter Development Kit
The Cyclone II FPGA Starter Development Kit is RoHS compliant and features:
Cyclone II Starter Development Board
Cyclone II EP2C20F484C7N device
Configuration
USB-BlasterTM download cable (embedded)
EPCS4 serial configuration device
Memory
8-Mbyte SDRAM ,512-Kbit SRAM ,1- to 4-Mbyte Flash
Clocking
SMA connector (external clock input)
Audio
24-bit coder/decoder (CODEC)
Switches and indicators
Ten switches and four push buttons
Four 7-segment displays
Ten red and eight green LEDs
Connectors
VGA, RS-232, and PS/2 ports
Two 40-pin expansion ports
SD/MMC socket
Cables/power
USB cable
External power supply with U.S. adaptor (optional, but recommended when using the kit with additional accessory
daughtercards)
Cyclone II FPGA Starter Development Kit CD-ROM
Reference designs and demonstrations targeted for the Cyclone II FPGA Starter Development Board
User manual ,Reference guide ,Quartus II Web Edition CD-ROM ,Nios II EDS CD-ROM

DSP Development Kit, Stratix II Professional Edition
The DSP Development Kit, Stratix II Edition features:
Stratix II EP2S180 DSP development board ,Stratix II EP2S180F1020C3 device
Analog I/O
Two-channel, 12-bit, 125-million samples per second (MSPS) analog-to-digital (A/D)
Two-channel, 14-bit, 165-MSPS digital-to-analog (D/A)
VGA digital-to-analog converter (DAC) ,Stereo audio coder/decoder (CODEC), 96 KHz
Digital I/O
Connector for the Texas Instruments (TI) C6000 DSP Starter Kit (DSK) to enable peripheral expansion and FPGA
coprocessing Two 40-pin connectors for Analog Devices' A/D converter evaluation boards
Mictor connector for Agilent and Tektronix logic analyzers
RS-232 serial port
10/100 Ethernet physical layer/media access control (PHY/MAC) and RJ-45 jack
Memory :32-Mbyte SDR SDRAM ,16-Mbyte flash ,1-Mbyte SRAM ,16-Mbyte compact flash
The MathWorks' MATLAB/Simulink evaluation software ,DSP Builder development tool
Quartus II DKE ,Evaluation IP cores ,System reference designs and labs
DSP Builder filtering design
DSP Builder/SOPC Builder image processing reference design
Fast Fourier transform (FFT) coprocessor reference design for TI's TMS320C6416 DSK
Nios® II reference designs
Cables and accessories
USB-Blaster download cable
Serial cable (RS-232)
Power supply
International power cords
Video Input Daughtercard features:
2 Composite Video Input Channels using the TI TVP5146 ADC
Support for NTSC/PAL
10-bit BT.656 Output
Compatibility with expansion connector, standard on most Altera® Development Kits
Included with Video Development Kit, Cyclone II Edition

MAX II Development Kit
• MAX II Development Board
• MAX II EPM1270F256C5ES CPLD
Universal serial bus (USB) media access control (MAC) with physical
layer (PHY) and Type B connector
PCI Edge connector (3.3 and 5 volt tolerant)
LCD module
SRAM (128k x 8-bit)
Temperature gauge with serial peripheral interface (SPI)
Onboard power meter
Active I/O sense circuitry
One 3.3-V-tolerant expansion/prototype header (41 available user I/O pins)
Joint Test Action Group (JTAG) connectors
Four user-defined, push-button switches
Four user-defined LEDs
•Quartus® II Web Edition design software (Free License)
•Cables and accessories
ByteBlaster™ II parallel download cable
Type A-B USB cable (3 feet)
•Reference designs and demos for MAX II including:
USB reference design
PCI reference design
Low power demo
Real-time in-system programmability (ISP) demo

PCI Development Kit, Cyclone II Edition
The PCI Development Kit, Cyclone II Edition features:
Cyclone II PCI Development Board (see Figure 1) ,Cyclone II EP2C35F672 FPGA
Short-form universal PCI (3.3 or 5.0 V) card ,32-bit or 64-bit PCI per the PCI Local Bus
Specification Revision 2.3 at 33 or 66 MHz ,100 MHz PCI-X Revision 2.0 mode 1
Memory:Two 64 Mbyte DDR2 SDRAM devices ,FPGA device configuration
Switch-selectable on power-up, choose one of two serial,configuration devices (EPCS64 devices).
One device contains,the pre-loaded factory default design, and the other device is for
user-programming. Configuration data is downloaded via the
USB-Blaster™ download cable.
Flexible clocking options ,Socketed 100-MHz high-speed clock oscillator ,SMA connector clock input
PCI edge connector clock input ,Switches and indicators ,Four user-definable push-button switches
Eight-position user-definable dual in-line package (DIP) switch ,Eight user-definable LEDs
Flexible power options
PCI connector
External power supply
PCI Development Kit, Cyclone II Edition CD-ROM
PCI-to-DDR2 Reference Design
Cyclone II PCI Development Kit Application & Drivers
PLD Applications PCI-X CORE CD-ROM
PLD Applications PCI-X function for OpenCore® evaluation
Reference designs & applications targeted to the Cyclone II PCI development board
Quartus® II design software, including the SOPC Builder system development tool
One-year license ,Windows platform only ,
Jungo WinDriver Development Toolkit
Cables & accessories
USB Blaster download cable
Power cable

Transceiver Signal Integrity Development Kit, Stratix IV GT Edition

Transceiver Signal Integrity Development Kit, Stratix II GX Edition
The Transceiver Signal Integrity Development Kit, Stratix II GX Edition includes:
Stratix II GX development board ,Stratix II GX EP2SGX90EF1152C3 FPGA ,Six full-duplex transceiver channels,
brought out to SMA connectors ,One microstrip channel ,Four stripline channels from the same transceiver quad
-- all the trace lengths are matched across channels ,One channel with 40-inch board trace length on transmit and
5-inch board trace length on receive to simulate the degradation associated with backplanes or long traces
FPGA device configuration options
Passive serial configuration via an on-board EPCS64 device which contains pre-loaded factory reference desig
JTAG configuration via USB-Blaster™ download cable ,Flexible clocking options
On-board 25-Mhz and 156.25-MHz clock oscillators ,SMA connector clock input ,Switches and indicators
Six user-definable push-button switches ,Eight-position user-definable dual in-line package (DIP) switch
Eight user-definable LEDs ,Two 7-segment displays ,USB port to interface with PC for easy plug and play
Flexible power options
AC adapter shipped with the kit
Banana jack for using bench power supply
RoHS Compliance
Transceiver Signal Integrity Development Kit, Stratix II GX Edition CD-ROM
Software application to interface to the board
Simple to use GUI that allows user to control Stratix II GX transceiver settings and run bit-error ratio (BER) test
Reference Design
Quartus® II design software
One-year license
Windows platform only
Cables and accessories
AC adapter power supply
USB-Blaster download cable
Development kit user guide
Board reference manual

GALAXY Development Kit

Cyclone II Starter Kit

MAX II Development Kit
1.Quartus II Web Edition Design software

2.User Manual.
3.MAX II board
－MAX II (EPM1270T144C5)
－8 User-defined LED
－4 user-defined push-buttons switches
－7-segment LED display
－Serial connectors (RS-232 DB9 port)
－8-bis DIP Switch
4.Accessories
－ByteBlaster II Download Cable
－6V power supply

Stratix II Development Board
• EP2SF1020 Device Family
• Serial Configuration EPROM
– EPCS16SI16N or EPCS64SI16N
• Four Expansion Headers
– Maximum 757 User I/Os
• Clock
– Oscillator (Full or Half Size) or
SMA
• Serial Communication
– UART (2T/2R)
• JTAG Mode Connector
• AS Mode Connector
• Power Connector
• Stack
Stratix III F1517 Development Board
研發電路板設計為 IC 研發驗証所使用
。本研發電路板可支援 Altera
Stratix III Device Family 中，最高規格
的FPGA EP3SL340F1517，可提供 IC
設計最大容量達 338,000 LEs、
20,491,000 bits 內嵌式的記憶體及最
大 960
個可用 I/Os。如果在目前業界最大容
量的 FPGA 仍無法滿足其設計需求
時，亦可以利用本研發電路板，以堆
疊方式來擴充其可使用邏輯的容量。

Stratix II F1508 Development Board

GFEC FPGAX4 Prototyping Platform


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© 2010 Altera Corporation—Confidential

 Introduction to Altera Devices

© 2010 Altera Corporation—Confidential

© 2010 Altera Corporation—Confidential

© 2010 Altera Corporation—Confidential

© 2010 Altera Corporation—Confidential

EPM7032S End Of Life

© 2010 Altera Corporation—Confidential

MAX 7000S MAX II MAX II

© 2010 Altera Corporation—Confidential

© 2010 Altera Corporation—Confidential

Parallel Logic 7000 has two Global Clock

© 2010 Altera Corporation—Confidential

 New Logic Architecture

 On-Chip Voltage Regulator

Convenience of 3.3 V with

© 2010 Altera Corporation—Confidential

© 2010 Altera Corporation—Confidential

Delay for Best-Case

Delay for Worst-

© 2010 Altera Corporation—Confidential

sload sclear aload

© 2010 Altera Corporation—Confidential

© 2010 Altera Corporation—Confidential

Parameter/Feature MAX MAX II

© 2010 Altera Corporation—Confidential

 Lowest system cost

15K LEs + two transceivers in 11 x 11mm package

EP4CGX15 14.4 0.5 0 2 2 1 1

EP4CGX22 21.3 0.8 40 4 2 2 1

EP4CGX30 29.4 1.1 80 4 2 2 1

EP4CGX50 49.9 2.5 140 8 4 4 1

EP4CGX75 73.9 4.2 198 8 4 4 1

EP4CGX110 109.4 5.5 280 8 4 4 1

EP4CGX150 149.8 6.5 360 8 4 4 1

© 2010 Altera Corporation—Confidential

0.5 mm 1.0 mm 1.0 mm 1.0 mm 1.0 mm 1.0 mm

XCV XVC XCV XCV XCV XCV

EP4CGX50 290 4 310 8

EP4CGX150 270 4 393 8 475 8

© 2010 Altera Corporation—Confidential

© 2010 Altera Corporation—Confidential

PCIe Gen1.1 2.5 Yes Yes Altera

XAUI 3.125 (1) Yes Altera

3G Triple Rate SDI 2.97 Yes Altera

 Lower your costs Lowest Cost

 Lower your power

The Lowest Cost, Lowest Power FPGAs

Equivalent Total memory 18 X 18

EP4C6E 6.2 0.27 15 2

EP4C10E 10.3 0.42 23 2

EP4C15E 15.4 0.51 56 4

EP4C30E 28.8 0.6 66 4

EP4C40E 39.6 1.16 116 4

EP4C55E 55.8 2.39 154 4

EP4C75E 75.4 2.8 200 4

EP4C115E 114.4 3.98 266 4

© 2010 Altera Corporation—Confidential

E144 F256 F484 F672

EP4C30E 331 535

EP4C55E 327 377

EP4C75E 295 429

EP4C115E 283 531

Introduction to Altera Devices

New Logic Architecture

On-Chip Voltage Regulator

Lowest system cost

Lower your costs Lowest Cost

Lower your power

Seamless FPGA prototyping to HardCopy