Compact Modeling IBM

IISc Bangalore, February 2008
Compact Modeling
Josef Watts
IBM Semiconductor Research and Development Center
January 2008
© 2006 IBM Corporation

IBM Semiconductor Research and Development Center – Joe Watts
What is a Compact Model?
2
IISc -- February 2008
Compact MOSFET Model

Gate
Compact Cgd=f2(Vgd, Vgs) Cgs=f3(Vgd, Vgs)

Model
Drain Source
Jds = f1(Vds,Vgs)
TCAD
Model
3
PowerPC
microprocessor
2 cores
10 levels of wiring
7.9E8 transistors
65nm SOI MOSFET Transistors

stress liner, halos, gate tunneling,
floating body effects, self heating.
4
Design proceeds simultaneously

at multiple levels of abstraction
Information passes from level to
level via models
o del
g icM
L o
Tim
ing
Mod
el
odel
p a ct M
C o m
5
Design Information
Layout Layout Schematic
Netlister
Data Extractor Data
Net list
Circuit
Circuit Simulator
Characteristics
Compact (PowerSPICE
(delay,
Model HSPICE
gain, etc)
Spectre)
Process Information
6
Circuit Behavior
What does the simulator do? (DC Case)
Enforce Kirkoff's Laws

– V1=V(R1)+V(R2) R1
– V(R2)=V(R3)
– I(V1) = I(R1)
– I(R1) = I(R2) + I(R3) V1
R2 R3
7
What does the simulator do? (DC case)

Enforce Kirkoff's Laws V1
– V1=V(R1)+V(R2)
– V(R2)=V(R3) R1
– I(V1) = I(R1)
– I(R1) = I(R2) + I(R3) V2
– Assign a voltage to every V1
node—by construction
voltage law is satisfied R2 R3
– If I know I(X) as a function of
V(X) I can test current law.
– That’s what the compact V3=0
model supplies: I=f(V)
8

Enforce Kirkoff's Current Law V1
– 0=fR1(V1-V2)-fR2(V2-V3)-fR3(V1-V2)
– Calculate current at each node R1
– This is the error vector E
– If any element is not zero the V2
simulator must adjust the voltages V1
to make all the errors sufficiently
small. R2 R3
V3=0
9

V1
Adjust voltages to zero the
errors
R1
r r
E = [J ]V V1
V2
⎛ dI ( R1) dI ( R 2) dI ( R3) ⎞
E[2] = ⎜ − − ⎟ • ΔV [2]
⎝ dV 2 dV 2 dV 2 ⎠
R2 R3
– Now I need derivatives of I
w.r.t. V
– The Compact model
V3=0
supplies those also
10
What does the simulator do? (AC Case)
Same thing plus

– Account for charge storage R1
in capacitors when the
voltage is not constant
– Also account for emf in
inductors when the current
V1
is not constant
R2 C3
– Compact model must
supply L & C values.
11
Charge Conservation
Consider the gate to source Vb=0

capacitance of a MOSFET. Vb=-1
Cgs
C=C(Vgs, Vgd, Vbs)
V2
Q = ∫ C (Vgs , Vds , Vsb )dVgs 1 2
V1
Integrate around a loop and
net delta Q equals zero
3
But ΔVgs=0 on segment 2
and C on segements 1 & 3
are not equal. Vg
Charge accumulates on the The compact model must
gate
provide both Q and C
12
Kirkoff’s current law becomes
0 = ∑ I ⋅dt + ∑ (Q(ti ) − Q(ti −1 )
To form Jacobian you need

dQ
=C
dt
Compact model must calculate:

I(V), dI(V)/dV, Q(V), dQ(V)/dV
13
Compact model complexity
I = V/R is a compact model for a resistor
14
I = V/(θ*(L-dL)/(W-dW))
Add Geometric Scaling
15
I = V/((θo+TCR*(T-25))*(L-dL)/(W-dW))
Add: Geometric Scaling
Temperature Scaling
16
TR
Jth Rth
I = V/((θo+TCR*(VTR+T-25))*(L-dL)/(W-dW)
Jth = V*I
Rth=Rth/(L*W)
Add: Geometric Scaling
Temperature Scaling
Self Heating
17
Compact Model Anatomy

BSIMSOI3.2 FET model
equations
Process Model BR resistor Process or
Statistical
decoupling model
NFET capacitor
FET model
PFET Annular Diode parameters
Passive
AVNFET Wire_cap component models
OP
OPresistor
resistor
Technology
Model
18
Communication Example
Goal: A digital speed boost for .25u CMOS

– Same ground rules
– Shorten Lpoly by lithography/etch change
– Shorter Leff
• Smaller gate capacitance
• Higher current
– Heavy Halo to control Vt roll-off
• Same Vt means same Ioff
19
Scaling of the FET Ldrawn
Ldrawn is determine by Mask

lithography—what can you Lpoly
resolve on the mask
Gate
Lpoly is determined by
Source Drain
Drain
Ldrawn + develop + etch
Leff
Leff is determine Lpoly + N+
P-
hot processes
Cg_total ~ Lpoly
Id ~ Leff
20
Short Channel Vt
Long device VT determine by 1D electrostatics
Gate
Source Drain
Drain
N+
P-
Short Channel VT is determined by 2D electrostatics
Gate
Source Drain
Drain
N+
P-
21
Vt vs Leff
Threshold Voltage
Vtmin
Lmin Leff
22
Add Halo Implants

Long device has Vt mostly determined Gate
by Substrate doping
Source Drain
Drain
N+
P+ P-
Halo blocks field lines from drain to
source end of channel
Short device has Vt mostly determined
Gate
by halo doping
Source Drain
Drain
N+
P+ P-
23
Vt vs Leff
Halo
Threshold Voltage
No Halo
Lmin Leff
24
The plan
Lpoly 8% less
– Cg_total 8% less
Leff 12% less (at Lmin)
– Id 8% more
Build same design as original process
Microprocessor frequency 16% more
25
Simulation results: Latches don’t work
Latch used NFET

Clock=Vdd
passgates
Data In Data Out
Output does not reach Vdd
At Vdd-Vt device shuts off
Next gate must switch
completely with a “weak
one” on input
Vsource
26
Vt vs Leff
Halo
Threshold Voltage
No Halo
Lmin + 2 grid points
Lmin Leff
27
Simulation results: Latches don’t work
Latch used NFET

Clock=Vdd
passgates
Data=Vdd Pass transistors were
longer than minimum
New NFET had more Vt
rollup
6s+, Lmin
New NFET had more body
Idrain
6s0, Lmin
6s+, Llatch effect
6s0, Llatch
Vsource
28
Model Build Flow

Device
Targets
Target Model
Hardware Model Starts Here
Starts Here
Good Design
Wafer Test Manual
Targets
Measure Fit Model Instance Center Fit Process Package for

Data To Data Effects Model Model Simulator
Test Test Test Inst. Test Model Test Test in

Data Fit Quality Effects Quality Distributions Simulator
Ship Model
29
Hardware Models, Target Models and Everything In

Between
Golden chip: near nominal

for all device specs
←Hardware Model
Hardware meets key
device specs
←Hardware
Hardware usable for roll off
Influenced Model
Output impedance, etc.
Hardware is very far

←Target Model
from targets
No hardware exist
30
Hardware Measurements
Id for various For SOI also need

– Vg – Buried BJT
– Vd – Diode
– Vbody
– Body Resistance
Impact Ionization
– Self Heating
Igate current
For RF model
STI stress effect
– S parameters
Liner Stress
Nwell proximity
Cj
Cov
31
Model Build Flow

Device
Targets
Target Model
Starts Here
Good Design
Wafer Test Manual
Targets


Ship Model
32
Hardware Fitting
FET
– We use standard models: can’t change the equations
– Certain parameters must have physical meanings
– One set of parameters must fit all sizes
– Find values of parameters that gives the best fit.
nonFET there are no standard models
– You can change the equations
– You can change the model topology
33
Fitting by Local Optimization

Different parameters describe the physics of different regions
Adjust small groups of parameters to fit different regions
2nd
Id
4th
L=.12
1st
L=10 3rd
Vg Vd
34
Id
L=.12
L=10
Vg Vd
35

As each group of parameter is adjusted that set of data is well fit
And each previously fit group gets a little worse
The result is multiple iterations to get an adquate fit
Id
L=.12
L=10
Vg Vd
36
Global Optimization
Use a very Robust

Optimizer to fit all the data
in one pass
Requires a good fitness
function to weight all the
data properly
We use a genetic algorithm
developed in house.
37
Genetic Algorithm
Mimics biological evolution

Operates on a “population” of
solutions
Find the fitter individual
solutions and breed the next
generation
Repeat until you have a good
enough solution
38
Genetic Algorithm: The life cycle

Hill Climb
algorithm
Patriarch
Assign
Fitness to Each
Individual
Breed New
Population
Create
Population
by Mutation
Test for
Diversity
39
Fitness Function
Matching to currents
Physical
reasonableness
Mathematical
robustness
Matching to derivatives
40
Model Build Flow

Device
Targets
Target Model
Starts Here
Good Design
Wafer Test Manual
Targets


Ship Model
41
Systematic, Random & Correlated
Systematic…P=P+ΔP(layout)
– Using the layout, we can predict the magnitude and direction of the
effect and
– The prediction is good for any lot though out the life of the program
Random Correlated…P=P+ΔP(layout)*global random #
– Not systematic but
– Using the layout, we can identify classes of devices which will have
the same magnitude and direction of effect.
Random Uncorrelated…P=P+ΔP(layout)*local random #
– Using the layout, we cannot know the magnitude and direction of the
effect and
– We cannot predict how predict that the effect will be the same as any
other device on the chip.
The classification depends not on the physics but how much
knowledge is available to the designer !
42
NW
Nwell Proximity Effect

PC
RX STI stress Effect
CA Random Dopant Fluctuation
Liner Stress
Corner Rounding
Litho & Etch Effects
Are these two FETs

Identical?
43
NW

PC
Systematic
Liner Stress
Corner Rounding
44
Well Proximity Effect
Figure courtesy of P. Drennan, CICC 06

45
NW
PC
Systematic
SA
Systematic
SB SA
Liner Stress
SB
Corner Rounding
46
STI Stress
GATE
Oxide Source
Source Drain
Drain Oxide
Silicon
During processing STI is etched out and filled with oxide

at a high temperature. After cooling mechanical stress is
locked in.
47
NW
PC Systematic
STI stress Effect
RX Systematic
Random Dopant Fluctuation
CA
Uncorrelated
Liner Stress
Corner Rounding
Major memory effect because of

small device size
48
Dopant atoms
are randomly
place
Vt Mismatch
For small FETs
there are few
total atoms
Random
variations are a
larger fractional
change
1/sqrt(W*Leff)[1/u]
49
NW

Adjacent PC PC
Systematic
SA
Systematic
SB SA Uncorrelated
Engineered Stress
SB Systematic
Corner Rounding

1 CA 2 CA
50
Layout-dependent Stress Model

Dense Gate Array
MC or CA proximity
MC or CA strapping
Small Isolate FET

PC proximity
Longitudinal DSL Transverse DSL PFET A
Isolated PC
tension
compression tension
Parallel BP Edge
compression d
PFET B
One PC pair
0.315um pitch
Product Like
tension RX length
Parallel
edge far
away PFET C
d 19 PC pairs
0.315um pitch
tension
This dimension being
varied on the x-axis
of the plot
Reference pfet layouts

51
NW
PC
Systematic
STI stress Effect
RX Systematic
CA Uncorrelated
Liner Stress
Systematic
Corner Rounding
Systematic and
Correlated
52
Corner Rounding Model

width
Rounding (webbing) of
corners makes part of the PC
channel longer
RX
Delta W is used to modify the Nominal
device behavior alignment, small
effect
– Nominal and tolerance of
delta W can be effected
This is a systematic effect—L width
always gets longer

PC
This is a random correlated
effect—size of the effect RX
depends on poly to isolation
alignment
Misalignment can
make effect bigger
or smaller
53
Same Orientation NW
PC Systematic
STI stress Effect
RX Systematic
PC
Pitch Random Dopant Fluctuation
CA
Uncorrelated
Liner Stress
Systematic
Corner Rounding
Uncorrelated
Correlated and
Uncorrelated
Close Proximity
54
Model Build Flow

Device
Targets
Target Model
Starts Here
Good Design
Wafer Test Manual
Targets


Ship Model
55
Model Centering
As Fit Model
My Chip
DM Targets
Centered
Model
56
Model Build Flow

Device
Targets
Target Model
Starts Here
Good Design
Wafer Test Manual
Targets


Ship Model
57
Bibliography
"Modeling of Variation in Submicron CMOS ULSI Technologies", S. Springer, et al IEEE Trans. On

ED. Sept. 2006
“A simple yet accurate mismatch model for circuit simulation”, Z. Jin, et al. Nanotech 2006
“Modeling FET Variation Within a Chip as a Function of Circuit Design and Layout Choices”, Josef
Watts,et al, Nanotech 2005
“Modeling MOSFET Process Variation using PSP”, J. Watts, et al, Nanotech 2007
“A comprehensive MOSFET mismatch model”, P. Drennan and C. McAndrew, IEDM 1999, p. 167-170
“On the correlations between process parameters in statistical modeling”, Slezak, et al, Nanotech
2004, Vol 2, pp144-146
“Statistical timing of parametric yield prediction of digital integrated circuits”, Jess, et al, DAC 2003,
p932-937
Advanced Compact Models for MOSFETs, J. Watts, et al, Nanotech 2005
58

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IISc Bangalore, February 2008

© 2006 IBM Corporation

What is a Compact Model?

Compact MOSFET Model

Compact Cgd=f2(Vgd, Vgs) Cgs=f3(Vgd, Vgs)

65nm SOI MOSFET Transistors

Design proceeds simultaneously

What does the simulator do? (DC Case)

 Enforce Kirkoff's Laws

What does the simulator do? (DC case)

What does the simulator do? (DC case)

What does the simulator do? (DC case)

What does the simulator do? (AC Case)

 Same thing plus

 Consider the gate to source Vb=0

Kirkoff’s current law becomes

0 = ∑ I ⋅dt + ∑ (Q(ti ) − Q(ti −1 )

To form Jacobian you need

Compact model must calculate:

Compact model complexity

I = V/R is a compact model for a resistor

Compact model complexity

I = V/R is a compact model for a resistor

Compact model complexity

I = V/R is a compact model for a resistor

Compact model complexity

I = V/R is a compact model for a resistor

Compact Model Anatomy

 Goal: A digital speed boost for .25u CMOS

Scaling of the FET Ldrawn

 Ldrawn is determine by Mask

 Long device VT determine by 1D electrostatics

 Short Channel VT is determined by 2D electrostatics

Add Halo Implants

Simulation results: Latches don’t work

 Latch used NFET

Lmin + 2 grid points

Simulation results: Latches don’t work

 Latch used NFET

Model Build Flow

Measure Fit Model Instance Center Fit Process Package for

Test Test Test Inst. Test Model Test Test in

Hardware Models, Target Models and Everything In

Golden chip: near nominal

Hardware is very far

 Id for various  For SOI also need

Model Build Flow

Measure Fit Model Instance Center Fit Process Package for

Test Test Test Inst. Test Model Test Test in

Fitting by Local Optimization

Fitting by Local Optimization

Fitting by Local Optimization

 Use a very Robust

 Mimics biological evolution

Genetic Algorithm: The life cycle

Model Build Flow

Measure Fit Model Instance Center Fit Process Package for

Test Test Test Inst. Test Model Test Test in

Systematic, Random & Correlated

Nwell Proximity Effect

RX STI stress Effect

CA Random Dopant Fluctuation

Litho & Etch Effects

Are these two FETs

Enforce Kirkoff's Laws

Same thing plus

Consider the gate to source Vb=0

Goal: A digital speed boost for .25u CMOS

Ldrawn is determine by Mask

Long device VT determine by 1D electrostatics

Short Channel VT is determined by 2D electrostatics

Latch used NFET

Latch used NFET

Id for various For SOI also need

Use a very Robust

Mimics biological evolution

"Modeling of Variation in Submicron CMOS ULSI Technologies", S. Springer, et al IEEE Trans. On