Beruflich Dokumente
Kultur Dokumente
February 2011
Bachelor of Computer Application (BCA) –
Semester 3 BC0046 –
Microprocessor – 4 Credits
(Book ID: B0807)
Assignment Set – 1
321.145 = 321/8^
MVI B, 30H
MVI C, 40H
MOV A, B
CMP C
JZ EQU
JC SML
OUT PORT1
HLT
OUT PORT1
HLT
SML: MOV A, C
OUT PORT1
HLT
OR
.model small
.stack 64
.data
n1 db 08h,02h
res db ?
.code
mov ax,@data
mov ds,ax
mov cx,02
lea si,n1
mov bl,0ffh
mine:mov al,[si]
cmp al,bl
jne loop1
jmp loop2
loop1:jnc loop2
mov bl,al
inc si
loop mine
jmp exit
loop2:inc si
loop mine
exit:mov res,bl
hlt
end
Address Bus
One wire for each bit, therefore 16 bits = 16 wires. Binary number
carried alerts memory to ‘open’ the designated box. Data (binary) can
then be put in or taken out. The Address Bus consists of 16 wires,
therefore 16 bits. Its “width” is 16 bits. A 16 bit binary number allows
216 different numbers, or 32000 different numbers, ie
0000000000000000 up to 1111111111111111. Because memory
consists of boxes, each with a unique address, the size of the address
bus determines the size of memory, which can be used. To
communicate with memory the microprocessor sends an address on
the address bus, eg 0000000000000011 (3 in decimal), to the
memory. The memory selects box number 3 for reading or writing
Control Bus
Control Bus are various lines which have specific functions for
coordinating and controlling microprocessor operations. Eg:
Read/NotWrite line, single binary digit. controls whether memory is
being ‘written to’ (data stored in mem) or ‘read from’ (data taken out
of mem) 1 = Read, 0 = Write. May also include clock line(s) for
timing/synchronising, ‘interrupts’, ‘reset’ etc. Typically microprocessor
has 10 control lines. Cannot function correctly without these vital
control signals.
CPU Architecture
Control Unit
Generates signals within microprocessor to carry out the instruction,
which has been decoded. In reality causes certain connections
between blocks of the microprocessor to be opened or closed, so that
data goes where it is required, and so that ALU operations occur.
Registers
The 8085/8080A-programming model includes six registers, one
accumulator, and one flag register, as shown in Fig. 2.1 In addition, it
has two 16-bit registers: the stack pointer and the program counter.
They are described briefly as follows.
The 8085/8080A has six general-purpose registers to store 8-bit data;
these are identified as B,C,D,E,H and L as shown in the figure. They
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic
unit (ALU). This register is used to store 8-bit data and to perform
arithmetic and logical operations. The result of an operation is stored
in the accumulator. The accumulator is also identified as register A.
Flags
The ALU includes five flip-flops, which are set or reset after an
operation according to data conditions of the result in the accumulator
and other registers. They are called Zero(Z), Carry (CY), Sign (S), Parity
(P), and Auxiliary Carry (AC) flags. The most commonly used flags are
Zero, Carry, and Sign. The microprocessor uses these flags to test data
conditions. For example, after an addition of two numbers, if the sum
in the accumulator is larger than eight bits, the flip-flop uses to
indicate a carry — called the Carry flag (CY) – is set to one. When an
arithmetic operation results in zero, the flip-flop called the Zero(Z) flag
is set to one. The Fig. 2.1 shows an 8-bit register, called the flag
register, adjacent to the accumulator. However, it is not used as a
register; five bit positions out of eight are used to store the outputs of
the five flip-flops. The flags are stored in the 8-bit register so that the
programmer can examine these flags (data conditions) by accessing
the register through an instruction.
These flags have critical importance in the decision-making process of
the micro- processor. The conditions (set or reset) of the flags are
tested through the software instructions. For example, the instruction
JC (Jump on Carry) is implemented to change the sequence of a
program when CY flag is set. The thorough understanding of flag is
essential in writing assembly language programs.
Instruction Register/Decoder
Temporary store for the current instruction of a program. Latest
instruction sent here from memory prior to execution. Decoder then
takes instruction and ‘decodes’ or interprets the instruction. Decoded
instruction then passed to next stage.
Control Generator
Generates signals within microprocessor to carry out the instruction
which has been decoded. In reality causes certain connections
between blocks of the microprocessor to be opened or closed, so that
data goes where it is required, and so that ALU operations occur.
Register Selector
This block controls the use of the register stack in the example. Just a
logic circuit which switches between different registers in the set will
receive instructions from Control Unit.
The data group consists of the AX, BX, CX and DX registers. These
registers can be used to store both operands and results and each of
them can be accessed as a whole, or the upper and lower bytes can be
accessed separately. For example, either the 2 bytes in BX can be used
together, or the upper byte BH or the lower byte BL can be used by
itself by specifying BH or BL, respectively.
The pointer and index group consists of the IP, SP, BP, SI, and DI
registers. The instruction pointer IP and SP registers are essentially the
program counter and stack pointer registers, but the complete
instruction and stack addresses are formed by adding the contents of
these registers to the contents of the code segment (CS) and stack
segment (SS) registers. BP is a base register for accessing the stack
and may be used with other registers and/or a displacement that is
part of the instruction. The SI and DI registers are for indexing.
Although they may be used by themselves, they are often used with
the BX or BP registers and/or a displacement. Except for the IP, a
pointer can be used to hold an operand, but must be accessed as a
whole.
The segment group consists of the CS, SS, DS, and ES registers. As
indicated above, the registers that can be used for addressing, the BX,
IP, SP, BP, SI, and DI registers, are only 16 bits wide and, therefore, an
effective address has only 16 bits. On the other hand, the address put
on the address bus, called the physical address, must contain 20 bits.
The extra 4 bits are obtained by adding the effective address to the
contents of one of the segment registers as shown in Fig. 4.1. The
addition is carried out by appending four 0 bits to the right of the
number in the segment register before the addition is made; thus a 20-
bit result is produced. As an example, if (CS) = 1234 and (IP) = 0002,
then the next instruction will be fetched from
0002 Effective address
+ 12340 beginning segment address
12342 Physical address of instruction
3. Facilitate the use of separate memory areas for a program, its data,
and the stack.Permit a program and/or its data to be put into
different areas of memory each time the program is executed.
The 8086’s PSW contains 16 bits, but 7 of them are not used. Each bit
in the PSW is called a flag. The 8086 flags are divided into the
conditional flags,
which reflect the result of the previous operation involving the ALU,
and the control
flags, which control the execution of special functions. The flags are
summarized in Fig. 4.3
SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 CF = 1
TF (Trap Flag)-If
set, a trap is executed after each instruction
Macro Procedures
Macro is a group of instruction. Procedures are a group of
The macro assembler generates instructions stored as a separate
the code in the program each program in memory and it is
time where the macro is called. called
Macros are defined by MACRO & from the main program whenever
ENDM directives. Creating required. The type of procedure
macro is similar to creating new depends on where the
opcodes that can be used in the procedures are stored in memory.
program If it is in the same code segment
INIT MACRO as that of the main program
ENDM
Accessed during assembly with Accessed by CALL & RET
name given to macro when instruction during program
defined execution
Machine code is generated for Machine code for instruction is put
instruction each time when macro only once in the memory
is called
With Macro more memory is With procedures less memory is
required required
Parameters passed as part of Parameters can be passed in
statement which calls macro registers, memory locations or
stack
first brought up. Users may tailor the other interrupt types according to
their particular applications.
or
SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 CF = 1
TF (Trap Flag)-If
set, a trap is executed after each instruction.
Ans. Program:
DATA ENDS
CODE SEGMENT
February 2011
Bachelor of Computer Application (BCA) –
Semester 3 BC0046 –
Microprocessor – 4 Credits
(Book ID: B0807)
Assignment Set – 2
Here, 'e' stands for equal, 'z' is zero and 'n' is not. These repeat
instructions should NEVER be used with a segment override, since the
8086 will forget the override if hardware interrupt occurs in the middle
of the REP loop.
LODSB : The Load String Byte transfers the byte pointed to by DS:SI
into AL register and increments or decrements SI (depending on the
state of the Direction Flag) to point to the next byte of the string
Logic: al <- (ds:si)
if df = 0 si <- si+1
else si <- si-1
Ans. When working with strings, the advantages of the MOVS and
CMPS instructions over the MOV and CMP instructions are:
determined by the speed with which data pass under the read/write
head and quite often this rate exceeds 200,000 bytes per second.
Thus, there is less than 5 microseconds to transfer each byte to or
from memory. For data rates of this magnitude, block transfers, which
use DMA controllers to communicate directly with memory, are
required.
During any given bus cycle, one of the system components connected
to the system bus is given control of the bus. This component is said to
be the master during that cycle and the component it is
communicating with is said to be the slave. The CPU with its bus
control logic is normally the master, but other specially designed
components can gain control of the bus by sending a bus request to
the CPU. After the current bus cycle is completed the CPU will return a
bus grant signal and the component sending the request will become
the master. Taking control of the bus for a bus cycle is called cycle
stealing. Just like the bus control logic, a master must be capable of
placing addresses on the address bus and directing the bus activity
during a bus cycle. The components capable of becoming masters are
processors (and their bus control logic) and DMA controllers.
Sometimes a DMA controller is associated with a single interface, but
they are often designed to accommodate more than one interface.
The 8086 receives bus requests through its HOLD pin and issues grants
from its hold acknowledge (HLDA) pin. A request is made when a
potential master sends a 1 to the HOLD pin. Normally, after the current
bus cycle is complete the 8086 will respond by putting a 1 on the HLDA
pin. When the requesting device receives this grant signal it becomes
the master. It will remain master until it drops the signal to the HOLD
pin, at which time the 8086 will drop the grant on the HLDA pin. One
exception to the normal sequence is that if a word which begins at an
odd address is being accessed, then two bus cycles are required to
complete the transfer and a grant will not be issued until after the
second bus cycle
ANS. Programmed I/O: It consists of continually examining the status of an interface and
performing an I/O operation with the interface when its status indicates that it has data to
be input or its data-out buffer register is ready to receive data from the CPU. A typical
programmed input operation is flowcharted in Fig.4A.
The program for solving the above problem is given in Fig. 4B. The interface for
Programmed IO is shown in Fig. 4C.
Interrupt I/O
When interfacing a peripheral to a microprocessor, the microprocessor
is not knowing when the peripheral is ready. That is, the peripheral
operates asynchronously with respect to the microprocessor. One
solution is to programme the CPU to repeatedly check the peripheral's
READY flag. However, this has a built-in disadvantage in that all the
resources of the processor are devoted to waiting for this flag. No
other task can be performed. If the peripheral is READY once in every
10,000µsec, the CPU will spend most of its time idling. A more logical
approach would be to have the peripheral "tell the CPU" when it is
ready. This is the purpose of the microprocessor'sin terrup t input. An
interrupt is used to cause a temporary halt in the execution of a
program. The microprocessor responds to the interrupt with an
Interrupt Service Sub-routine (ISS) which is a short programme or a
subroutine that instructs the microprocessor on how to handle the
interrupt.
The 8086 has two interrupt pins labeled INTER and NM1. NM1 is a
nonmaskable interrupt, which means that it requires an immediate
response from the processor and it cannot be blocked. INTR is
maskable via the IF flag. Only when this flag is set will interrupts on
this input be accepted. Interrupts can be generated by both hardware
and software. Interrupts are also prioritized to allow for the case when
more than one interfere
Because the NMI input is nonmaskable, care must be taken when using
this interrupt. This is because there may be some programs which we
do not want to interrupt- reading or writing data to a disk drive, for
example. For this reason, NMI input is normally reserved for
catastrophic events like memory error or impending power failure.
by only one process at a time and other processes must wait until the
one currently using the shared resource is finished with it. A resource
of this type, which is commonly referred to as a serially reusable
resource, must be protected from being simultaneously accessed and
modified by two or more processes. A serially reusable resource may
be a hardware resource (such as a printer, card reader, or tape drive),
a file of data, or a shared memory area.
Process 1
P1 :
JZ TRYAGAIN1
MOV FLAG,0
MOV FLAG, 1
Process 2
P2:
TRYAGAIN2:
TEST FLAG,1
JZ TRYAGAIN2
MOV FLAG, 0
MOV FLAG, 1
The problem with the above approach is that it is possible for both
processes to enter their critical sections. To see how this can happen,
suppose that FLAG = 1 and that the following sequence occurs:
1. The TEST instruction in process 1 is executed.
2. A switch is made to process 2 before the JZ instruction in process 1
is executed.
3. The TEST instruction in process 2 is executed.
At this point both processes are free to enter their critical sections of
code.
To avoid the above problem two flags can be employed, one which
indicates that process 1 is in its critical section and one for indicating
that process 2 is in its critical section. Before either process can enter
its critical section it would first clear its flag to indicate its intention and
then repeatedly test the flag associated with the other process until it
becomes 1. This could be implemented by coding both processes as
follows:
P1 :
MOV FLAG 1, 0
JZ CHECK1
} Critical section
MOV FLAG1, 1
For a solution to the critical section problem that both provides mutual
exclusion and avoids mutual blocking, a third flag is needed that
indicates which process has the higher priority when the mutual
blocking occurs. This concept was first proposed by Dekker and was
discussed by Dijkstra. Dijkstra has also extended this solution to the n-
process case.
P1 :
MOV AL, 0
TEST AL.AL
JZ TRYAGAIN1
} Critical section
MOV FLAG,1
XCHG AL,SEMAPHORE
TEST AL.AL
JNZ NEXT
NEXT:
} Critical section
MOV SEMAPHORE,1
This sets the semaphore to 1 and allows the monitor to move those
processes which were blocked because the shared resource was
unavailable from the blocked list to the ready list. The first of these
processes that resumes its execution will be able to enter its critical
section.
Memory Logical M
C Logical Address management logic
for mapping logical
Address
E
P Control Lines
addresses into
physical addresses Control
M
Lines O
U R
Y
DATA
size of 2n bytes, thus providing each user with a virtual storage of 2m+n
bytes.
The timing diagrams for 8086 minimum mode input and output transfers that require no
wait states are shown in Fig. 7B. When the state of the processor is such that it is ready to
initiate a bus cycle it applies a pulse to the ALE pin during Tl. Before the trailing edge of
the ALE signal the address, BHE, M/IO, DEN, and DT/R signals should be stable, with
DEN= 1 and DT/R = 0 for an input and DT/R = 1 for an output. At the trailing edge of
the ALE signal the 8282s latch the address. During T2 the address is dropped and S3
through S7 are output on AD16/S3-AD19/S6 and BHE/S7, and DEN, is lowered to
enable the 8286 transceivers. If an input is being conducted, RD is activated low during
T2 and AD15-AD0 enter a high-impedance state in preparation for input. If the memory
or I/O interface can perform the transfer immediately, there are no wait states and the
data are put on the bus during T3. After the input data are accepted by the processor, RD
is raised to 1 at the beginning of T4 and, upon detecting this transition, the memory or
I/O interface will drop its data signals. For an output, the processor applies the WR = 0
signal and then the data during T2, and in T4 WR is raised and the data signals are
dropped. For either an input or output, DENis raised during T4 to disable the transceivers
and the M/IO, signal is set according to the next transfer at this time or during a
subsequent T1 state.
The timing diagrams for input and input and output transfers on a maximum mode system
are given in Fig. 7B. The S0, S1 and S2 bits are set just prior to the beginning of the bus
cycle. Upon detecting a change from the passive S0 = S1 = S2 = 1 state, the 8288 bus
controller will output a pulse on its ALE pin and apply the appropriate signal to its DT/R
pin during Tl. In T2, the 8288 will set DEN= 1, thus enabling the transceivers, and, for an
input, will activate either MRDC or IORC. These signals will be maintained until T4′.
For an output, the AMWC or AIOWC is activated from T2 to T4 and the MWTC or
IOWC is activated from T3 to T4. The status bits S0 and S2 will remain active until T3
and will become passive (all 1s) during T3 and T4. As with the minimum mode, if the
READY input is not activated before the beginning of T3, wait states will be inserted
between T3 and T4.
1. Input
(b) Output
1. Input
(b) Output
These signals are active low and are output during the middle portion
of a bus cycle. Clearly, only one of them will be issued during any
given bus cycle.
Ans. Because the 8086 has a 6-byte instruction queue, the instruction
that has just been fetched may not be executed immediately. In order
to allow external logic to monitor the execution sequence, a maximum
mode 8086 outputs the queue status through its QSl and QS0 pins.
During each clock cycle the queue status is examined and the QSl and
QS0 bits are encoded as follows:
0l-The first byte of the current instruction was taken from the queue.
11-A byte other than the first byte of an instruction was taken from the
queue.
By monitoring the bus and the queue status, external logic can
simulate the CPU’s instruction execution sequence and determine
which instruction is currently being executed. This facility is necessary
so that the 8086 can indicate when an instruction is to be executed by
a coprocessor.
MOV AL, 0
TRYAGAIN : XCHG SEMAPHORE,AL
TEST AL, AL
JZ TRYAGAIN
{Critical section in which a process accesses a shared resource}
MOV SEMAPHORE, 1
To avoid this problem, the processor that starts executing its XCHG
instruction first (which in this example is processor A) must have
exclusive use of the bus until the XCHG instruction is completed. On
the 8086 this exclusive use is guaranteed by a LOCK prefix:
1111100001
which for a maximum mode CPU, activates the LOCK output pin during
the execution of the instruction that follows the prefix. The LOCK signal
indicates to the bus control logic that no other processors may gain
control of the system bus until the locked instruction is completed. To
get around the problem encountered in the above example the XCHG
instructions could be replaced with:
During the execution of this instruction the system bus will be reserved
for the sole use of the processor executing the instruction.