Master Index 1

Product Selection Guide 2

The “Better” Program 3

B and UB Series Family Data 4

CMOS Handling and Design Guidelines 5

Data Sheets 6

CMOS Reliability 7

Equivalent Gate Count 8

Packaging Information 9
Including Surface Mounts
 DATA CLASSIFICATION

Product Preview
This heading on a data sheet indicates that the device is in the formative
stages or in design (under development). The disclaimer at the bottom of the
first page reads: “This document contains information on a product under
development. Motorola reserves the right to change or discontinue this
product without notice.”

Advance Information
This heading on a data sheet indicates that the device is in sampling,
preproduction, or first production stages. The disclaimer at the bottom of the
first page reads: “This document contains information on a new product.
Specifications and information herein are subject to change without notice.”

Fully Released
A fully released data sheet contains neither a classification heading nor a
disclaimer at the bottom of the first page. This document contains information
on a product in full production. Guaranteed limits will not be changed without
written notice to your local Motorola Semiconductor Sales Office.

ii MOTOROLA CMOS LOGIC DATA

 CMOS LOGIC
DATA

Prepared by
Technical Information Center

This book presents technical data for the broad line of CMOS logic integrated
circuits and demonstrates Motorola’s continued commitment to Metal–Gate
CMOS. Complete specifications are provided in the form of data sheets. In addi-
tion, a Product Selector Guide and a Handling and Design Guidelines chapter have
been included to familiarize the user with these circuits.
Motorola reserves the right to make changes without further notice to any prod-
ucts herein to improve reliability, function or design. Motorola does not assume any
liability arising out of the application or use of any product or circuit described here-
in; neither does it convey any license under its patent rights nor the rights of others.
Motorola products are not designed, intended, or authorized for use as compo-
nents in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Motorola and its offi-
cers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part. Motorola and are
registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment
Opportunity/Affirmative Action Employer.

Series C
 MOTOROLA INC., 1991
Previous Edition  1990
Printed in U.S.A. “All Rights Reserved”

MOTOROLA CMOS LOGIC DATA iii

iv MOTOROLA CMOS LOGIC DATA
Master Index 1
 MASTER INDEX
This index includes Motorola’s entire MC14000 series CMOS products, although this book contains
data sheets for Logic Devices only. Data sheets for devices in the CMOS/NMOS Special Functions Data
book (DL130) are designated in the page number column as SF.
Products which have been cancelled are designated in the page number column as —.

Device Function Page

MC14000UB Dual 3–Input NOR Gate Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
MC14001B Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14001UB Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14002B Dual 4–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14002UB Dual 4–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14006B 18–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
MC14008B 4–Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
MC14011B Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14011UB Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14012B Dual 4–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14012UB Dual 4–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14013B Dual D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–33
MC14014B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
MC14015B Dual 4–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–41
MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–47
MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–54
MC14018B Presettable Divide–by–N Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–59
MC14020B 14–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–63
MC14021B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–67
MC14023B Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14023UB Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14024B 7–Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–72
MC14025B Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14025UB Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14027B Dual J–K Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–77
MC14028B BCD–to–Decimal/Binary–to–Octal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 6–81
MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 6–86
MC14032B Triple Serial Adder (Positive Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92
MC14034B 8–Bit Universal Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–97
MC14035B 4–Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–104
MC14038B Triple Serial Adder (Negative Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92
MC14040B 12–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–108
MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–112
MC14043B Quad NOR R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116
MC14044B Quad NAND R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116
MC14046B Phase–Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–120

CHAPTER 1 MOTOROLA CMOS LOGIC DATA

1–2
 Device Function Page
MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125
MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–129
MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125
MC14051B 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . 6–133
MC14052B Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . 6–133
MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6–133
MC14060B 14–Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–140
MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–144
MC14067B 16–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . 6–150
MC14068B 8–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–158
MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160
MC14071B Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14072B Dual 4–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14073B Triple 3–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14075B Triple 3–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14076B Quad D–Type Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . 6–162
MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160
MC14078B 8–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14081B Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14082B Dual 4–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–166
MC14094B 8–Stage Shift/Store Register with Tri–State Outputs . . . . . . . . . . . . . . . . . 6–170
MC14097B Dual 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . 6–150
MC14099B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174
MC14106B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–180
MC14160B Synchronous Presettable BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184
MC14161B Synchronous Presettable 4–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . 6–184
MC14162B Synchronous Presettable BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184
MC14163B Synchronous Presettable 4–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . 6–184
MC14174B Hex D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–193
MC14175B Quad D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–197
MC14194B 4–Bit Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–201
MC14415 Quad Precision Timer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–205
MC14433 31/2 Digit A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14442 Microprocessor–Compatible A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14443 6–Channel A/D Converter Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF

MOTOROLA CMOS LOGIC DATA CHAPTER 1

1–3
 Device Function Page
MC14444 Microprocessor–Compatible A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14447 6–Channel A/D Converter Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14457 Remote Control Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14458 Remote Control Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14460 Automotive Speed Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14466 Low Cost Smoke Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14467–1 Low Cost Smoke Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14468 Interconnectable Smoke Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14469 Addressable Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . SF
MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–210
MC14495–1 Hexadecimal–to–7 Segment Latch/Decoder ROM/Driver . . . . . . . . . . . . . . . SF
MC14497 PCM Remote Control Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14499 7–Segment LED Display Decoder/Driver with Serial Interface . . . . . . . . . . . SF
MC14500B Industrial Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–217
MC14501UB Triple Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–223
MC14502B Strobed Hex Inverter/Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–227
MC14503B Hex 3–State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–231
MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . 6–235
MC14506UB Dual Expandable AOI Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–238
MC14508B Dual 4–Bit Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–243
MC14510B Presettable BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–248
MC14511B BCD–to–7–Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . 6–256
MC14512B 8–Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–262
MC14513B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . 6–266
MC14514B 4–Bit Transparent Latch/4–to–16 Line Decoder (High) . . . . . . . . . . . . . . . 6–274
MC14515B 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) . . . . . . . . . . . . . . . 6–274
MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–280
MC14517B Dual 64–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–288
MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–292
MC14519B 4–Bit AND/OR Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–297
MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–292
MC14521B 24–Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–301
MC14522B Presettable BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–307

CHAPTER 1 MOTOROLA CMOS LOGIC DATA

1–4
 Device Function Page
MC14526B Presettable 4–Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–307
MC14527B BCD Rate Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–315
MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–321
MC14529B Dual 4–Channel Analog Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–327
MC14530B Dual 5–Input Majority Logic Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–333
MC14531B 12–Bit Parity Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–338
MC14532B 8–Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–341
MC14534B 5 Cascaded BCD Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–347
MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–354
MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–365
MC14539B Dual 4–Channel Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . 6–373
MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–377
MC14543B BCD–to–7–Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . 6–382
MC14544B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . 6–387
MC14547B High–Current BCD–to–7–Segment Decoder/Driver . . . . . . . . . . . . . . . . . 6–393
MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–398
MC14551B Quad 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6–405
MC14553B 3–Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–412
MC14554B 2 X 2–Bit Parallel Binary Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–418
MC14555B Dual Binary to 1–of–4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . 6–422
MC14556B Dual Binary to 1–of–4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . 6–422
MC14557B 1–to–64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . 6–425
MC14558B BCD–to–7 Segment Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–429
MC14559B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–398
MC14560B NBCD Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–434
MC14561B 9’s Complementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–445
MC14562B 128–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–451
MC14566B Industrial Time Base Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–455
MC14568B Phase Comparator and Programmable Counters . . . . . . . . . . . . . . . . . . . 6–461
MC14569B Programmable Dual 4–Bit Binary/BCD Down Counter . . . . . . . . . . . . . . . 6–471
MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–481
MC14573 Quad Programmable Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14574 Quad Programmable Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14575 Programmable Dual Op Amp/Dual Comparator . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14580B 4 X 4 Multiport Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–484
MC14581B 4–Bit Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–489
MC14582B Look–Ahead Carry Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–494

MOTOROLA CMOS LOGIC DATA CHAPTER 1

1–5
 Device Function Page
MC14583B Dual Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–498
MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–504
MC14585B 4–Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–507
MC14597B 8–Bit Bus–Compatible Counter Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–511
MC14598B 8–Bit Bus–Compatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . 6–511
MC14599B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174
MC144110 Hex D/A Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC144111 Quad D/A Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145000 48–Segment Multiplexed LCD Driver (Master) . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145001 44–Segment Multiplexed LCD Driver (Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145026 Remote Control Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145027 Remote Control Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145028 Remote Control Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145029 Remote Control Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145040 Analog–to–Digital Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . SF
MC145041 Analog–to–Digital Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . SF
MC145104 PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
MC145106 PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145107 PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
MC145109 PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
MC145112 PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
MC145143 PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
MC145144 4–Bit Data Bus Input PLL Frequency Synthesizer
(Not Recommended for New Designs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145145–1 4–Bit Data Bus Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . SF
MC145146–1 4–Bit Data Bus Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . SF
MC145151–1 Parallel Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145152–1 Parallel Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145155–1 Serial Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145156–1 Serial Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145157–1 Serial Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145158–1 Serial Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145159–1 Serial Input PLL Frequency Synthesizer with Analog Phase Detector . . . . . SF
MC145453 33–Segment LCD Driver with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . SF

CHAPTER 1 MOTOROLA CMOS LOGIC DATA

1–6
Product Selection Guide 2
 CMOS Selection Guide by Function

Device Function Page

NAND Gates
MC14011B Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14011UB Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–166
MC14023B Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14023UB Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14012B Dual 4–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14012UB Dual 4–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14068B 8–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

NOR Gates
MC14001B Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14001UB Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14025B Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14025UB Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14000UB Dual 3–Input NOR Gate Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
MC14002B Dual 4–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14002UB Dual 4–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14078B 8–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

AND Gates
MC14081B Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14073B Triple 3–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14082B Dual 4–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

OR Gates
MC14071B Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14075B Triple 3–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14072B Dual 4–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

Complex Gates
MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160
MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160
MC14501UB Triple Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–223
MC14506UB Dual Expandable AOI Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–238
MC14530B Dual 5–Input Majority Logic Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–333
MC14519B 4–Bit AND/OR Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–297
MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–481

Inverters/Buffers/Level Translator
MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125
MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–129
MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125
MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–158
MC14502B Strobed Hex Inverter/Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–227
MC14503B Hex 3–State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–231
MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . 6–235
MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–504

CHAPTER 2 MOTOROLA CMOS LOGIC DATA

2–2
 Device Function Page

Decoders/Encoders
MC14028B BCD–to–Decimal/Binary–to–Octal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 6–81
MC14511B BCD–to–7–Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . 6–256
MC14513B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . 6–266
MC14543B BCD–to–7–Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . 6–382
MC14544B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . 6–387
MC14547B High–Current BCD–to–7–Segment Decoder/Driver . . . . . . . . . . . . . . . . . 6–393
MC14558B BCD–to–7–Segment Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–429
MC14514B 4–Bit Transparent Latch/4–to–16 Line Decoder (High) . . . . . . . . . . . . . . . 6–274
MC14515B 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) . . . . . . . . . . . . . . . 6–274
MC14532B 8–Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–341
MC14555B Dual Binary to 1–of–4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . 6–422
MC14556B Dual Binary to 1–of–4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . 6–422

Multiplexers/Demultiplexers/Bilateral Switches
MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–47
MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–144
MC14551B Quad 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6–405
MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6–133
MC14052B Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . 6–133
MC14097B Dual 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . 6–150
MC14529B Dual 4–Channel Analog Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–327
MC14539B Dual 4–Channel Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . 6–373
MC14067B 16–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . 6–150
MC14051B 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . 6–133
MC14512B 8–Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–262
MC14519B 4–Bit AND/OR Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–297

Schmitt Triggers
MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–166
MC14583B Dual Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–498
MC14106B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–180
MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–504

Flip–Flops/Latches
MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–112
MC14043B Quad NOR R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116
MC14044B Quad NAND R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116
MC14076B Quad D–Type Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . 6–162
MC14175B Quad D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–197
MC14013B Dual D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–33
MC14027B Dual J–K Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–77
MC14508B Dual 4–Bit Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–243
MC14174B Hex D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–193
MC14099B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174
MC14597B 8–Bit Bus–Compatible Counter Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–511
MC14598B 8–Bit Bus–Compatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . 6–511
MC14599B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174

MOTOROLA CMOS LOGIC DATA CHAPTER 2

2–3
 Device Function Page

Shift Registers
MC14015B Dual 4–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–41
MC14517B Dual 64–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–288
MC14562B 128–Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–451
MC14557B 1–to–64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . 6–425
MC14006B 18–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
MC14014B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
MC14021B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
MC14034B 8–Bit Universal Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–97
MC14094B 8–Stage Shift/Store Register with Tri–State Outputs . . . . . . . . . . . . . . . . . 6–170
MC14035B 4–Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–104
MC14194B 4–Bit Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–201
MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–398
MC14559B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–398

Counters
MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–54
MC14018B Presettable Divide–by–N Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–59
MC14020B 14–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–63
MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–67
MC14024B 7–Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–72
MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 6–86
MC14040B 12–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–108
MC14060B 14–Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–140
MC14160B Synchronous Presettable BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184
MC14161B Synchronous Presettable 4–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . 6–184
MC14162B Synchronous Presettable BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184
MC14163B Synchronous Presettable 4–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . 6–184
MC14510B Presettable BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–248
MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–280
MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–292
MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–292
MC14522B Presettable BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–307
MC14526B Presettable 4–Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–307
MC14534B 5 Cascaded BCD Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–347
MC14553B 3–Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–412
MC14566B Industrial Time Base Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–455
MC14569B Programmable Dual 4–Bit Binary/BCD Counter . . . . . . . . . . . . . . . . . . . . . 6–471

Oscillators/Timers
MC14521B 24–Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–301
MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–354
MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–377

Multivibrators
MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–321
MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–365

CHAPTER 2 MOTOROLA CMOS LOGIC DATA

2–4
 Device Function Page

Adders/Comparators
MC14008B 4–Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
MC14032B Triple Serial Adder (Positive Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92
MC14038B Triple Serial Adder (Negative Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92
MC14560B NBCD Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–434
MC14561B 9’s Complementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–445
MC14582B Look–Ahead Carry Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–494
MC14585B 4–Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–507

ALU/Rate Multipliers
MC14527B BCD Rate Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–315
MC14554B 2 X 2 Bit Parallel Binary Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–418
MC14581B 4–Bit Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–489

Parity Checker
MC14531B 12–Bit Parity Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–338

Memory
MC14580B 4 X 4 Multiport Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–484

Microprocessor/Industrial Control
MC14500B Industrial Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–217

Other Complex Functions

MC14046B Phase–Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–120
MC14415 Quad Precision Timer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–205
MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–210
MC14568B Phase Comparator and Programmable Counters . . . . . . . . . . . . . . . . . . . 6–461

MOTOROLA CMOS LOGIC DATA CHAPTER 2

2–5
The “Better” Program 3
  
 
The “BETTER” program is offered on logic only, in dual–in–line plastic packages.

Better Processing — HOW TO ORDER

Standard Product Plus: MC14000B CP D
Part Standard BETTER
Identification Package PROCESSING
Level II (Suffix D) Suffix LEVEL II = SUFFIX D
• 100% burn–in to MIL–STD–883 test conditions — 160
Part Marking
hours at + 125°C or 1.0 eV Arrhenus time/temperature
equivalent. The Standard Motorola part number with the correspond-
ing “BETTER” suffix can be order from your local authorized
• 100% post burn–in functional and dc parametric tests at Motorola distributor or Motorola sales offices. “BETTER”
25°C (or max rated TA at Motorola’s option). Maximum pricing will be quoted as an adder to standard commercial
PDA of 2% (functional) and 5% (DC and functional). product price.

“RAP”
Reliability Audit Program
For Logic Integrated Circuits

1.0 INTRODUCTION
The Reliability Audit Program developed in March 1977 is
the Motorola internal reliability audit which is designed to as-
sess outgoing product performance under accelerated stress
conditions. Logic Reliability Engineering has overall respon-
sibility for RAP, including updating its requirements, interpret-
ing its results, administration at offshore locations, and
monthly reporting of results. These reports are available at
all sales offices. Also available is the “Reliability and Quality
Handbook” which contains data for all Motorola Semiconduc-
tors (#BR518S).
RAP is a system of environmental and electrical tests per-
formed periodically on randomly selected samples of stan-
dard products. Each sample receives the tests specified in
section 2.0. Frequency of testing is specified per internal
document 12MRM15301A.

CHAPTER 3 MOTOROLA CMOS LOGIC DATA

3–2
 2.0 RAP TEST FLOW

Pull 500* piece sample from lot following Group A

acceptance.

45* 340 100

INITIAL
SEAL**
OP LIFE
40 HOURS
PTHB PTH*** TEMP CYCLES
48 HRS 48 HRS 40 CYCLES
INTERIM
ELECTRICAL
INTERIM
TEST
OP LIFE
210 HRS (ADDITIONAL)
ADD 460 CYCLES
FINAL
INTERIM INTERIM INTERIM #
ELECTRICAL TEST ELECTRICAL

ADD 500 CYCLES

FINAL
INTERIM*
TEST
PTH OP LIFE #
48 HRS 750 HRS
(ADDITIONAL) (ADDITIONAL)
TEMP CYCLES #
1000 CYCLES
(ADDITIONAL)
FINAL FINAL FINAL #
ELECTRICAL ELECTRICAL ELECTRICAL
(48 HRS) (96 HRS) (1000 HRS)
FINAL
ELECTRICAL
& SEAL**
(2000 CYCLES)

SCRAP SCRAP SCRAP

#One sample per month for FAST, LS, 10H, 10K, MG CMOS, and HSL CMOS.
* PTHB or PTH not required for hermetic products: reduce total sample size to 450 pcs.
** Seal (Fine & Gross Leak) required only for hermetic products.
*** PTH to be used when sockets for PTHB are not available.

3.0 TEST CONDITIONS AND COMMENTS
PTHB — 15 psig/121°C/100% RH at rated VCC or VEE — to
be performed on plastic encapsulated devices
only.
TEMP CYCLING — MIL–STD–883, Method 1010, Condi-
tion C, – 65°C/+ 150°C.
OP LIFE — MIL–STD–883, Method 1005, Condition C
(Power plus Reverse Bias), TA = 145°C.
NOTES:
1. All standard 25°C dc and functional parameters will be
measured Go/No/Go at each readout.
2. Any indicated failure is first verified and then submitted to
the Product Analysis Lab for detailed analysis.
3. Sampling to include all package types routinely.
4. Device types sampled will be by generic type within each
logic I/C product family (CMOS, TTL, etc.) and will include
all assembly locations (Korea, Philippines, Malaysia, etc.).
5. 16 hrs. PTHB is equivalent to approximately 800 hours of
v
85°C/85% RH THB for VCC 15 V.
6. Only moisture related failures (like corrosion) are criteria
for failure on PTHB test.
7. Special device specifications (48A’s) for logic products will
reference 12MRM15301A as source of generic data for
any customer required monthly audit reports.

MOTOROLA CMOS LOGIC DATA CHAPTER 3

3–3
B and UB Series Family Data 4
  
     

The CMOS Devices in this volume which have a B or UB
suffix meet the minimum values for the industry–standard-
ized# family specification. These standardized values are
shown in the Maximum Ratings and Electrical Characteris-
tics Tables. In addition to a standard minimum specification
for characteristics the B/UB devices feature:
• 3–18 volt operational limits
• Capable of driving two low–power TTL loads or one low–
power Schottky TTL load over the rated temperature
range
• Direct Interface to High–Speed CMOS
• Maximum input current of ± 1 µA at 15 volt power supply
over the temperature range
• Parameters specified at 5.0, 10, and 15 volt supply
• Noise margins: B Series
1.0 V min @ 5.0 V supply
2.0 V min @ 10 V supply
2.5 V min @ 15 V supply
UB Series
0.5 V min @ 5.0 V supply
1.0 V min @ 10 V supply
1.0 V min @ 15 V supply
The industry–standardized maximum ratings are shown at
the bottom of this page. Limits for the static characteristics
are shown in two formats: Table 1 is in the industry format
and Table 2 is in the equivalent Motorola format. The
Motorola format is used throughout this data book. Additional
specification values are shown on the individual data sheets.
Switching characteristics for the B and UB series devices
are specified under the following conditions:
Load Capacitance, CL, of 50 pF
Input Voltage equal to VSS – VDD (Rail–to–Rail swing)
Input pulse rise and fall times of 20 ns
Propagation Delay times measured from 50% point of
input voltage to 50% point of output voltage
Three different supply voltages: 5, 10, and 15 V
Exceptions to the B and UB Series Family
Specification
There are a number of devices which have a B or UB suffix
whose inputs and/or outputs vary somewhat from the family
specification because of functional requirements. Some
categories of notable exceptions are:
Devices with specialized outputs on the chip, such as
NPN emitter–follower drivers or transmission gates, do
not meet output specifications.
#Specifications coordinated by EIA/JEDEC Solid–State Products
Council.
CHAPTER 4
4–2
Devices with specialized inputs, such as oscillator in-
puts, have unique input specifications.
Input Voltage
The input voltage specification is interpreted as the worst-
case input voltage to produce an output level of “1” or “0”.
This “1” or “0” output level is defined as a deviation from the
supply (VDD) and ground (VSS) levels. For a 5.0 V supply,
this deviation is 0.5 V; for a 10 V supply, 1.0 V; and for 15 V,
1.5 V. As an example, in a device operating at a 5.0 V supply,
the device with the input starting at ground is guaranteed to
switch on or before 3.5 V and not to switch up to 1.5 V.
Switching and not switching are defined as within 0.5 V of the
ideal output level for the example with a 5.0 V supply. The
actual switching level referred to the input is between 1.5 V
and 3.5 V.
Noise Margin
The values for input voltages and the defined output devi-
ations lead to the calculated noise margins. Noise margin is
defined as the difference between V IL or V IH and Vout
(output deviation). As an example, for a noninverting buffer at
V DD = 5.0 volts: V IL = 1.5 volts and Vout = 0.5 volts. There-
fore, Noise Margin equals V IL – Vout = 1.0 volt. This figure is
useful while cascading stages (See Figure 1). With the input
to the first stage at a worst–case voltage level (V IL = 1.5 V),
the output is guaranteed to be no greater than 0.5 volts with
a 5.0 volt supply. Since the maximum allowable logic 0 for
the second stage is 1.5 volts, this 0.5 volt output provides a
1.0 volt margin for noise to the next stage.
Output Drive Current
Devices in the B Series are capable of sinking a minimum
of 0.36 mA over the temperature range with a 5.0 V supply.
This value guarantees that these CMOS devices will drive
one low–power Schottky TTL input.
B Series vs UB CMOS
The primary difference between B series and UB series
devices is that UB series gates and inverters are constructed
with a single inverting stage between input and output. The
decreased gain caused by using a single stage results in less
noise immunity and a transfer characteristic that is less ideal.
The decreased gain is quite useful when CMOS Gates and
inverters are used in a “Linear” mode to form oscillators,
monostables, or amplifiers. The decreased gain results in in-
creased stability and a “cleaner” output waveform. In addition
to linear operation, the UB gates and inverters offer an in-
crease in speed, since only a single stage is involved.
The B and UB series, and devices with no suffix can be
used interchangeably in digital circuits that interface to other
CMOS devices, such as High–Speed CMOS Logic.
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎÎ Parameters Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin, lout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD

ÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎÎ
ÎÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎÎ
Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

5.0 V

VIL = 1.5 V Vout = 0.5 V Vout

FIRST STAGE VIL = 1.5 V SECOND STAGE

(NONINVERTING BUFFER) (NONINVERTING BUFFER)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 1.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ

ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ Î ÎÎ
Î ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
T
Temp VDD
TLOW*
Limits
+ 25_C THIGH*

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Parameter
P Range (Vdc) Conditions
C di i Min Max Min Max Min Max Units
U i

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
IDD Quiescent Mil 5 0.25 0.25 7.5 µAdc

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Device Current 10 Vin = VSS or VDD 0.5 0.5 15
15 1.0 1.0 30

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
GATES

ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Comm 5 All valid input 1.0 1.0 7.5 µAdc

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 combinations 2.0 2.0 15
15 4.0 4.0 30

ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Mil 5 1.0 1.0 30 µAdc

ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
VIN = VSS or VDD 2.0
4.0
2.0
4.0
60
120
µAdc

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
BUFFERS, Comm 5 All valid input 4 4.0 30
FLIP–FLOPS 10 combinations 8 8.0 60

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 16 16.0 120

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Mil 5 5 5 150 µAdc

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 VIN = VSS or VDD 10 10 300
15 20 20 600

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
MSI
ÎÎÎ
ÎÎÎ
ÎÎÎ
Comm 5 All valid input 20 20 150 µAdc

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 combinations 40 40 300
15 80 80 600

ÎÎÎÎÎÎ
ÎÎÎÎ
VOL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Low–Level
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
All 5 0.05 0.05 0.05 Vdc

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Output Voltage

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
VIN = VSS or VDD
|IO| < 1 µA
0.05
0.05
0.05
0.05
0.05
0.05

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
VOH High–Level All 5 4.95 4.95 4.95 Vdc
Output Voltage 10 VIN = VSS or VDD 9.95 9.95 9.95

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 |IO| < 1 µA 14.95 14.95 14.95

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
VIL Input All 5 VO = 0.5V or 4.5V 1.5 1.5 1.5 Vdc
Low Voltage#

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 VO = 1.0V or 9.0V 3.0 3.0 3.0
B Types 15 VO = 1.5V or 13.5V 4.0 4.0 4.0

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
|IO| < 1 µA

MOTOROLA CMOS LOGIC DATA CHAPTER 4

4–3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications (continued)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ

ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ TLOW*
Limits
+ 25_C THIGH*

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Temp VDD
Parameter Range (Vdc) Conditions Min Max Min Max Min Max Units

ÎÎÎÎÎÎÎÎÎÎ
VIL

ÎÎÎÎÎÎÎÎÎÎÎÎ
Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
All
ÎÎÎ 5 VO = 0.5V or 4.5V 1.0 1.0 1.0

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ

ÎÎÎ
ÎÎÎ
ÎÎÎ
Low Voltage# 10 VO = 1.0V or 9.0V 2.0 2.0 2.0
UB Types 15 VO = 1.5V or 13.5V 2.5 2.5 2.5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ |IO| < 1 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH Input All 5 VO = 0.5V or 4.5V 3.5 3.5 3.5 Vdc
High Voltage#

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ

ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 VO = 1.0V or 9.0V 7.0 7.0 7.0
B Types 15 VO = 1.5V or 13.5V 11.0 11.0 11.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
|IO| < 1 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH Input All 5 VO = 0.5V or 4.5V 4.0 4.0 4.0 Vdc
High Voltage# 10 VO = 1.0V or 9.0V 8.0 8.0 8.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
UB Types

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
15 VO = 1.5V or 13.5V 12.5 12.5 12.5

ÎÎÎ
|IO| < 1 µA

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
IOL Output Low Mil 5 VO = 0.4V, mAdc
(Sink) Current VIN = 0 or 5V 0.64 0.51 0.36

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ 10 VO = 0.5V,

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIN = 0 or 10V 1.6 1.3 0.9
VO = 1.5V,

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15
VIN = 0 or 15V 4.2 3.4 2.4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Com 5 VO = 0.4V, mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIN = 0 or 5V 0.52 0.44 0.36
10 VO = 0.5V,

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIN = 0 or 10V 1.3 1.1 0.9
VO = 1.5V,

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15
VIN = 0 or 15V 3.6 3.0 2.4

ÎÎÎÎÎÎÎÎÎÎ
IOH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output High
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Mil
ÎÎÎ VO = 4.6V, mAdc

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ

ÎÎÎ
ÎÎÎ
ÎÎÎ
(Source) Current 5 VIN = 0 or 5V – 0.25 – 0.2 – 0.14
VO = 9.5V,

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 VIN = 0 or 10V – 0.62 – 0.5 – 0.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VO = 13.5V,
15 VIN = 0 or 15V – 1.8 – 1.5 – 1.1

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Com

ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5
VO = 4.6V,
VIN = 0 or 5V – 0.2 – 0.16 – 0.12
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VO = 9.5V,
10 VIN = 0 or 10V – 0.5 – 0.4 – 0.3

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VO = 13.5V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 VIN = 0 or 15V – 1.4 – 1.2 – 1.0

ÎÎÎÎ
ÎÎÎÎ
IIN

ÎÎÎÎÎÎ
Input Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Mil

ÎÎÎÎ ÎÎÎ
ÎÎÎ
Comm ÎÎÎ
ÎÎÎ
ÎÎÎ
15
15
VIN = 0 or 15V
VIN = 0 or 15V
± 0.1
± 0.3
± 0.1
± 0.3
± 1.0
± 1.0
µAdc
µAdc

ÎÎÎÎÎÎÎÎÎÎ
Ioz

ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Output

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Mil
ÎÎÎ
ÎÎÎ 15 VIN = 0 or 15V ± 0.4 ± 0.4 ± 12 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Leakage Current Comm 15 VIN = 0 or 15V ± 1.6 ± 1.6 ± 12 µAdc

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
CIN Input Capacitance All — Any Input 7.5 pF
per unit load
* TLOW = – 55_C for Military temperature range device, – 40°C for Commercial temperature range device.
THIGH = + 125_C for Military temperature range device, + 85_C for Commercial temperature range device.
#Applies for Worst Case input combinations.

CHAPTER 4 MOTOROLA CMOS LOGIC DATA

4–4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 2. Motorola Format for CMOS Industry B and UB Series Specifications

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Characteristic
Ch i i ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Symbol
S b l
VDD
Vdc Min
– 55_C
Max Min
25_C
Max
+ 125_C
Min Max Unit
U i

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Voltage “0” Level VOL 5.0 — 0.05 — 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
“1” Level VOH
15
5.0
—
4.95
0.05
—
—
4.95
0.05
—
—
4.95
0.05
— Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = 0 or VDD 10 9.95 — 9.95 — 9.95 —
15 14.95 — 14.95 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Input Voltage B Types
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
“0” Level VIL Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 3.0 — 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 4.0 — 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 — 3.5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
Input Voltage UB Types “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.0 — 1.0 — 1.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 2.0 — 2.0 — 2.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 2.5 — 2.5 — 2.5
“1” Level VIH Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 4.0 — 4.0 — 4.0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 8.0 — 8.0 — 8.0 —
(VO = 1.5 or 13.5 Vdc) 15 12.5 — 12.5 — 12.5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Drive Current B Gates

ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ IOH mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 — – 0.36 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ ÎÎÎÎ ÎÎÎ

ÎÎÎ
ÎÎÎ ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10 – 1.6 — – 1.3 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 — 0.36 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 — 0.9 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Drive Current UB Gates IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 — – 0.7 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 — – 0.14 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 — – 1.1 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 — 0.36 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Output Drive Current Other Devices
ÎÎÎ
ÎÎÎÎÎÎ IOH mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ
(VOH = 4.6 Vdc) Source 5.0 – 0.64 — – 0.51 — – 0.36 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 — 0.36 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Input Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Input Capacitance ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin
Cin
15
—
—
—
± 0.1
—
—
—
± 0.1
7.5
—
—
± 1.0
—
µAdc
pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Vin = 0)
Gate Quiescent Current IDD 5.0 — 0.25 — 0.25 — 7.5 µAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ 10 — 0.5 — 0.5 — 15

ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 1.0 — 1.0 — 30
µAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
Flip–Flop and Buffer Quiescent Current IDD 5.0 — 1.0 — 1.0 — 30
(Per Package) 10 — 2.0 — 2.0 — 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 4.0 — 4.0 — 120

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MSI Quiescent Current IDD 5.0 — 5.0 — 5.0 — 150 µAdc
(Per Package) 10 — 10 — 10 — 300

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 20 — 20 — 600

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
LSI Quiescent Current IDD See Individual Data Sheets.

MOTOROLA CMOS LOGIC DATA CHAPTER 4

4–5
CMOS Handling and Design Guidelines 5
      
  
HANDLING PRECAUTIONS
All MOS devices have insulated gates that are subject to
voltage breakdown. The gate oxide for Motorola CMOS de-
vices is about 900 Å thick and breaks down at a gate–source
potential of about 100 volts. To guard against such a break-
down from static discharge or other voltage transients, the
protection networks shown in Figures 1A and 1B are used on
each input to the CMOS device.
Static damaged devices behave in various ways, depend-
ing on the severity of the damage. The most severely dam-
aged inputs are the easiest to detect because the input has
been completely destroyed and is either shorted to VDD,
shorted to VSS, or open–circuited. The effect is that the de-
vice no longer responds to signals present at the damaged
input. Less severe cases are more difficult to detect because
they show up as intermittent failures or as degraded perfor-
mance. Another effect of static damage is that the inputs
generally have increased leakage currents.
Although the input protection network does provide a great
deal of protection, CMOS devices are not immune to large
static voltage discharges that can be generated during han-
dling. For example, static voltages generated by a person
walking across a waxed floor have been measured in the
4 –15 kV range (depending on humidity, surface conditions,
etc.). Therefore, the following precautions should be
observed:
1. Do not exceed the Maximum Ratings specified by the
data sheet.
2. All unused device inputs should be connected to VDD or
VSS.
3. All low–impedance equipment (pulse generators, etc.)
should be connected to CMOS inputs only after the de-
vice is powered up. Similarly, this type of equipment
should be disconnected before power is turned off.
4. Circuit boards containing CMOS devices are merely
extensions of the devices, and the same handling
precautions apply. Contacting edge connectors wired
directly to device inputs can cause damage. Plastic
wrapping should be avoided. When external connec-
INPUT PROTECTION NETWORK
VDD
CMOS
TO CIRCUIT
INPUT
< 1500 Ω
VSS
Figure 1a. Input Protection Network
Double Diode
CHAPTER 5
5–2
tions to a PC board are connected to an input of a CMOS
device, a resistor should be used in series with the input.
This resistor helps limit accidental damage if the PC
board is removed and brought into contact with static
generating materials. The limiting factor for the series
resistor is the added delay. This is caused by the time
constant formed by the series resistor and input
capacitance. Note that the maximum input rise and fall
times should not be exceeded. In Figure 2, two possible
networks are shown using a series resistor to reduce
ESD (Electrostatic Discharge) damage. For conve-
nience, an equation for added propagation delay and
rise time effects due to series resistance size is given.
5. All CMOS devices should be stored or transported in
materials that are antistatic. CMOS devices must not be
inserted into conventional plastic “snow”, styrofoam, or
plastic trays, but should be left in their original container
until ready for use.
6. All CMOS devices should be placed on a grounded
bench surface and operators should ground them-
selves prior to handling devices, since a worker can be
statically charged with respect to the bench surface.
Wrist straps in contact with skin are strongly recom-
mended. See Figure 3 for an example of a typical work
station.
7. Nylon or other static generating materials should not
come in contact with CMOS devices.
8. If automatic handlers are being used, high levels of
static electricity may be generated by the movement of
the device, the belts, or the boards. Reduce static build–
up by using ionized air blowers or room humidifiers. All
parts of machines which come into contact with the top,
bottom, or sides of IC packages must be grounded to
metal or other conductive material.
9. Cold chambers using CO2 for cooling should be
equipped with baffles, and the CMOS devices must be
contained on or in conductive material.
10. When lead–straightening or hand–soldering is neces-
sary, provide ground straps for the apparatus used and
be sure that soldering ties are grounded.
VDD
CMOS
INPUT
300 Ω
VSS
Figure 1b. Input Protection Network
Triple Diode
MOTOROLA CMOS LOGIC DATA
 11. The following steps should be observed during wave
solder operations:
a. The solder pot and conductive conveyor system of
the wave soldering machine must be grounded to an
earth ground.
b. The loading and unloading work benches should
have conductive tops which are grounded to an earth
ground.
c. Operators must comply with precautions previously
explained.
d. Completed assemblies should be placed in antistatic
containers prior to being moved to subsequent
stations.
12. The following steps should be observed during board–
cleaning operations:
a. Vapor degreasers and baskets must be grounded to
an earth ground.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor
degreaser immediately upon removal from the
antistatic container.
d. Cleaned assemblies should be placed in antistatic
containers immediately after removal from the clean-
ing basket.
e. High velocity air movement or application of solvents
and coatings should be employed only when
assembled printed circuit boards are grounded and
a static eliminator is directed at the board.
13. The use of static detection meters for production line
surveillance is highly recommended.
14. Equipment specifications should alert users to the pres-
ence of CMOS devices and require familiarization with
this specification prior to performing any kind of mainte-
nance or replacement of devices or modules.
15. Do not insert or remove CMOS devices from test
sockets with power applied. Check all power supplies to
be used for testing devices to be certain there are no
voltage transients present.
16. Double check test equipment setup for proper polarity
of VDD and VSS before conducting parametric or func-
tional testing.
17. Do not recycle shipping rails or trays. Repeated use
causes deterioration of their antistatic coating.
RECOMMENDED FOR READING:
“Total Control of the Static in Your Business”
Available by writing to:
3M Company
Static Control Systems
P.O. Box 2963
Austin, Texas 78769–2963
Or by Calling:
1–800–328–1368

VDD

CMOS D1 CMOS
TO OFF–BOARD R1 INPUT TO OFF–BOARD R2 INPUT
CONNECTION OR CONNECTION OR
OUTPUT OUTPUT
D2

Advantage: Requires minimal board area Advantage: R2 < R1 for the same VSS
level of protection.
Disadvantage: R1 > R2 for the same level of Impact on ac and dc
protection, therefore rise and fall characteristics is minimized
times, propagation delays, and output
drives are severely affected. Disadvantage: More board area, higher initial cost
Note: These networks are useful for protecting the following
A digital inputs and outputs C 3–state outputs
B analog inputs and outputs D bidirectional (I/O) ports

PROPAGATION DELAY AND RISE TIME

vs. SERIES RESISTANCE
R [ t
where: C@k
R = the maximum allowable series resistance in ohms
t = the maximum tolerable propagation delay or rise time in seconds
C = the board capacitance plus the driven device’s
= input capacitance in farads
k = 0.7 for propagation delay calculations
k = 2.3 for rise time calculations

Figure 1. Networks for Minimizing ESD and Reducing

CMOS Latch Up Susceptibility

MOTOROLA CMOS LOGIC DATA CHAPTER 5

5–3
 4 NOTES: 1. 1/16 inch conductive sheet stock covering bench
top work area.
2. Ground strap.
1 3. Wrist strap in contact with skin.
4. Static neutralizer. (Ionized air blower directed at
work.) Primarily for use in areas where direct
grounding is impractical.
2
5. Room humidifier. Primarily for use in areas where
5 the relative humidity is less than 45%. Caution:
building heating and cooling systems usually dry
the air causing the relative humidity inside of
3 buildings to be less than outside humidity.

RESISTOR =
1 MEGAOHM
Figure 2. Typical Manufacturing Work Station

POWER SUPPLIES the possibility of latch–up related failures. This system

CMOS devices have low power requirements and the abil-
ity to operate over a wide range of supply voltages. These
two characteristics allow CMOS designs to be implemented
using inexpensive, conventional power supplies, instead of
switching power supplies and power supplies with cooling
fans. In addition, batteries may be used as either a primary
power source or for emergency backup.
The absolute maximum power supply voltage for 14000
Series Metal–gate CMOS is 18.0 Vdc. Figure 4 offers some
insight as to how this specification was derived. In the figure,
VS is the maximum power supply voltage and IS is the sus-
taining current of the latch–up mode. The value of VS was
chosen so that the secondary breakdown effect may be
avoided.
In an ideal system design, a power supply should be
designed to deliver only enough current to insure proper
operation of all devices. The obvious benefit of this type
design is cost savings; an added benefit is protection against
protection can be provided by the power supply filter and/or
voltage regulator.
CMOS devices can be used with battery or battery backup
systems. A few precautions should be taken when designing
battery–operated systems:
1. The recommended power supply voltage should be ob-
served. For battery backup systems such as the one in
Figure 5, the battery voltage must be at least 3.7 Volts
(3 Volts from the minimum power supply voltage and
0.7 Volts to account for the voltage drop across the se-
ries diode).
2. Inputs that might go above the battery backup voltage
should either use a series resistor to limit the input cur-
rent to less than 10 mA or use the MC14049UB or
MC14050B high–to–low voltage translators.
3. Outputs that are subject to voltage levels above VDD or
below VSS should be protected with a series resistor to
limit the current to less than 10 mA or with clamping
diodes.

IDD

LATCH
UP MODE
SECONDARY
BREAKDOWN

LOW CURRENT
JUNCTION
IS
AVALANCHE

VS VDD
VS = DATA SHEET MAXIMUM SUPPLY RATING

Figure 3. Secondary Breakdown Characteristics

CHAPTER 5 MOTOROLA CMOS LOGIC DATA

5–4
 POWER SUPPLY

BATTERY BACKUP
LINE POWER ONLY BATTERY BACKUP RECHARGE
SYSTEM SYSTEM

MC14049UB
CMOS CMOS
MC14050B
SYSTEM SYSTEM

MC14049UB
MC14050B

Figure 4. Battery Backup Interface

INPUTS VDD = 5.0 Vdc

All inputs, while in the recommended operating range (VSS

Vout , OUTPUT VOLTAGE (V)

< Vin < VDD) can be modeled as shown in Figure 6. For input
SINGLE INPUT NAND, AND
voltages in this range, diodes D1 and D2 are modeled as
MULTIPLE INPUT NOR, OR
resistors, representing the reverse bias impedance of the 5.0
diodes. The maximum input current is worst case, 1 µA,
when the inputs are at VDD or VSS, and VDD = 15.0 V. This 4.0 SINGLE INPUT NOR, OR
model does not apply to inputs with pull–up or pull–down MULTIPLE INPUT NAND, AND
3.0
resistors.
2.0

1.0

0
VDD 0 1.0 2.0 3.0 4.0 5.0
R1 = R2 = HIGH Z Vin, INPUT VOLTAGE (V)

R1 Figure 6. Typical Transfer Characteristics

for Buffered Devices

For these reasons, all unused inputs should be connected

R2 7.5 pF
either to VDD or VSS. For applications with inputs going to
edge connectors, a 100 kilohm resistor to VSS should be
used, as well as a series resistor for static protection and
Figure 5. Input Model for VSS v Vin v VDD current limiting (Figure 8). The 100 kilohm resistor will help
eliminate any static charges that might develop on the
printed circuit board. See Figure 2 for other possible
protection arrangements.
When left open–circuited, the inputs may self–bias at or
near the typical switchpoint, where both the P–channel and FROM RS CMOS
EDGE
N–channel transistors are conducting, causing excessive DEVICE
CONNECTOR
current drain. Due to the high gain of the inverters (see
100 k
Figure 7), the device may also go into oscillation from any
noise in the system. Since CMOS devices dissipate the most
power during switching, this oscillation can cause very large
current drain and undesired switching. Figure 7. External Protection

MOTOROLA CMOS LOGIC DATA CHAPTER 5

5–5
 For input voltages outside of the recommended operating
range, the CMOS input is modeled as in Figure 9. The
resistor–diode protection network allows the user greater
freedom when designing a worst case system. The device
inputs are guaranteed to withstand voltages from VSS – 0.5 V
to VDD + 0.5 V and a maximum current of 10 mA. With the
above input ratings, most designs will require no special
terminations or design considerations.
D1
 1.5 k
D2 7.5 pF
Figure 8. Input Model for Vin > VDD or Vin < VSS
Other specifications that should be noted are the maxi-
mum input rise and fall times. Figure 10 shows the
oscillations that may result from exceeding the 15 µs
maximum rise and fall time at VDD = 5.0 V, 5 µs at 10 V, or
4 µs at 15 V. As the voltage passes through the switching
threshold region with a slow rise time, any noise that is on the
input is amplified, and passed through to the output, causing
oscillations. The oscillation may have a low enough fre-
quency to cause succeeding stages to switch, giving
unexpected results. If input rise or fall times are expected to
exceed 15 µs at 5.0 V, 5 µs at 10 V, or 4 µs at 15 V,
Schmitt–trigger devices such as the MC14093B, MC14583B,
MC14584B, MC14106B, HC14, or HC132 are recommended
for squaring–up these slow transitions.
VDD
Vin
VSS
VOH
Vout
VOL
Figure 9. Maximum Rise and Fall Time Violations
OUTPUTS
All CMOS B–Series outputs are buffered to insure consis-
tent output voltage and current performance. All buffered out-
puts have guaranteed output voltages of VOL = 0.05 V and
VOH = VDD – 0.05 V for Vin = VDD or VSS and lout = 0 µA. The
output drives for all buffered CMOS devices are such that
1 LSTTL load can be driven across the full temperature
range.
CHAPTER 5
5–6
CMOS outputs are limited to externally forced output
voltages of VSS – 0.5 V v Vout v VDD + 0.5 V. When
voltages are forced outside of this range, a silicon controlled
rectifier (SCR) formed by parasitic transistors can be
triggered, causing the device to latch up. For more informa-
tion on this, see the explanation of CMOS Latch Up in this
section.
The maximum rated output current for most outputs is
10 mA. The output short–circuit currents of these devices
typically exceed these limits. Care must be taken not to ex-
ceed the maximum ratings found on every data sheet.
For applications that require driving high capacitive loads
where fast propagation delays are needed (e.g., driving
power MOSFETs), two or more outputs on the same chip
may be externally paralleled.
CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
prevent it.
Figure 11 shows the cross–section of a typical CMOS in-
verter and Figure 12 shows the parasitic bipolar devices. The
circuit formed by the parasitic transistors and resistors is the
basic configuration of a silicon controlled rectifier, or SCR. In
the latch up condition, transistors Q1 and Q2 are turned ON,
each providing the base current necessary for the other to
remain in saturation, thereby latching the devices in the ON
state. Unlike a conventional SCR, where the device is turned
ON by applying a voltage to the base of the NPN transistor,
the parasitic SCR is turned ON by applying a voltage to the
emitter of either transistor. The two emitters that trigger the
SCR are the same point, the CMOS output. Therefore, to
latch up the CMOS device, the output voltage must be great-
er than VDD + 0.5 V or less than VSS – 0.5 V and have suffi-
cient current to trigger the SCR. The latch–up mechanism is
similar for the inputs.
Once a CMOS device is latched up, if the supply current is
not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below:
1. Insure that inputs and outputs are limited to the maxi-
mum rated values, as follows:
v
– 0.5 V ≤ Vin or Vout VDD + 0.5 V (referenced to VSS)
v
|Iin or Iout| 10 mA (unless otherwise indicated on the
data sheet)
2. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
to limit the expected worst case current to the maximum
rating of 10 mA. (See Figure 2).
3. Sequence power supplies so that the inputs or outputs
of CMOS devices are not active before the supply pins
are powered up (e.g., recessed edge connectors and/
or series resistors may be used in plug–in board ap-
plications).
4. Voltage regulating or filtering should be used in board
design and layout to insure that power–supply lines are
free of excessive noise.
5. Limit the available power supply current to the devices
that are subject to latch–up conditions. This can be ac-
complished with the power supply filtering network or
with a current–limiting regulator.
MOTOROLA CMOS LOGIC DATA
 P–CHANNEL N–CHANNEL
INPUT

VDD VDD P–CHANNEL N–CHANNEL VSS

OUTPUT
OUTPUT OUTPUT

N+
FIELD OXIDE ÇÇÇ
P+ P+
FIELD OXIDE
N+
ÇÇ N+ P+
FIELD OXIDE

N – SUBSTRATE P – WELL

Figure 10. CMOS Wafer Cross Section

Q1
N–CHANNEL OUTPUT
N+ N+ N– N–SUBSTRATE RESISTANCE
VDD
VSS N–
P–
P+
VDD
VSS P–
P–WELL RESISTANCE P+
Q2 P–CHANNEL OUTPUT

Figure 11. Latch Up Circuit Schematic

MOTOROLA CMOS LOGIC DATA CHAPTER 5

5–7
CMOS Handling and Design Guidelines 5
      
  
HANDLING PRECAUTIONS
All MOS devices have insulated gates that are subject to
voltage breakdown. The gate oxide for Motorola CMOS de-
vices is about 900 Å thick and breaks down at a gate–source
potential of about 100 volts. To guard against such a break-
down from static discharge or other voltage transients, the
protection networks shown in Figures 1A and 1B are used on
each input to the CMOS device.
Static damaged devices behave in various ways, depend-
ing on the severity of the damage. The most severely dam-
aged inputs are the easiest to detect because the input has
been completely destroyed and is either shorted to VDD,
shorted to VSS, or open–circuited. The effect is that the de-
vice no longer responds to signals present at the damaged
input. Less severe cases are more difficult to detect because
they show up as intermittent failures or as degraded perfor-
mance. Another effect of static damage is that the inputs
generally have increased leakage currents.
Although the input protection network does provide a great
deal of protection, CMOS devices are not immune to large
static voltage discharges that can be generated during han-
dling. For example, static voltages generated by a person
walking across a waxed floor have been measured in the
4 –15 kV range (depending on humidity, surface conditions,
etc.). Therefore, the following precautions should be
observed:
1. Do not exceed the Maximum Ratings specified by the
data sheet.
2. All unused device inputs should be connected to VDD or
VSS.
3. All low–impedance equipment (pulse generators, etc.)
should be connected to CMOS inputs only after the de-
vice is powered up. Similarly, this type of equipment
should be disconnected before power is turned off.
4. Circuit boards containing CMOS devices are merely
extensions of the devices, and the same handling
precautions apply. Contacting edge connectors wired
directly to device inputs can cause damage. Plastic
wrapping should be avoided. When external connec-
INPUT PROTECTION NETWORK
VDD
CMOS
TO CIRCUIT
INPUT
< 1500 Ω
VSS
Figure 1a. Input Protection Network
Double Diode
CHAPTER 5
5–2
tions to a PC board are connected to an input of a CMOS
device, a resistor should be used in series with the input.
This resistor helps limit accidental damage if the PC
board is removed and brought into contact with static
generating materials. The limiting factor for the series
resistor is the added delay. This is caused by the time
constant formed by the series resistor and input
capacitance. Note that the maximum input rise and fall
times should not be exceeded. In Figure 2, two possible
networks are shown using a series resistor to reduce
ESD (Electrostatic Discharge) damage. For conve-
nience, an equation for added propagation delay and
rise time effects due to series resistance size is given.
5. All CMOS devices should be stored or transported in
materials that are antistatic. CMOS devices must not be
inserted into conventional plastic “snow”, styrofoam, or
plastic trays, but should be left in their original container
until ready for use.
6. All CMOS devices should be placed on a grounded
bench surface and operators should ground them-
selves prior to handling devices, since a worker can be
statically charged with respect to the bench surface.
Wrist straps in contact with skin are strongly recom-
mended. See Figure 3 for an example of a typical work
station.
7. Nylon or other static generating materials should not
come in contact with CMOS devices.
8. If automatic handlers are being used, high levels of
static electricity may be generated by the movement of
the device, the belts, or the boards. Reduce static build–
up by using ionized air blowers or room humidifiers. All
parts of machines which come into contact with the top,
bottom, or sides of IC packages must be grounded to
metal or other conductive material.
9. Cold chambers using CO2 for cooling should be
equipped with baffles, and the CMOS devices must be
contained on or in conductive material.
10. When lead–straightening or hand–soldering is neces-
sary, provide ground straps for the apparatus used and
be sure that soldering ties are grounded.
VDD
CMOS
INPUT
300 Ω
VSS
Figure 1b. Input Protection Network
Triple Diode
MOTOROLA CMOS LOGIC DATA
 11. The following steps should be observed during wave
solder operations:
a. The solder pot and conductive conveyor system of
the wave soldering machine must be grounded to an
earth ground.
b. The loading and unloading work benches should
have conductive tops which are grounded to an earth
ground.
c. Operators must comply with precautions previously
explained.
d. Completed assemblies should be placed in antistatic
containers prior to being moved to subsequent
stations.
12. The following steps should be observed during board–
cleaning operations:
a. Vapor degreasers and baskets must be grounded to
an earth ground.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor
degreaser immediately upon removal from the
antistatic container.
d. Cleaned assemblies should be placed in antistatic
containers immediately after removal from the clean-
ing basket.
e. High velocity air movement or application of solvents
and coatings should be employed only when
assembled printed circuit boards are grounded and
a static eliminator is directed at the board.
13. The use of static detection meters for production line
surveillance is highly recommended.
14. Equipment specifications should alert users to the pres-
ence of CMOS devices and require familiarization with
this specification prior to performing any kind of mainte-
nance or replacement of devices or modules.
15. Do not insert or remove CMOS devices from test
sockets with power applied. Check all power supplies to
be used for testing devices to be certain there are no
voltage transients present.
16. Double check test equipment setup for proper polarity
of VDD and VSS before conducting parametric or func-
tional testing.
17. Do not recycle shipping rails or trays. Repeated use
causes deterioration of their antistatic coating.
RECOMMENDED FOR READING:
“Total Control of the Static in Your Business”
Available by writing to:
3M Company
Static Control Systems
P.O. Box 2963
Austin, Texas 78769–2963
Or by Calling:
1–800–328–1368

VDD

CMOS D1 CMOS
TO OFF–BOARD R1 INPUT TO OFF–BOARD R2 INPUT
CONNECTION OR CONNECTION OR
OUTPUT OUTPUT
D2

Advantage: Requires minimal board area Advantage: R2 < R1 for the same VSS
level of protection.
Disadvantage: R1 > R2 for the same level of Impact on ac and dc
protection, therefore rise and fall characteristics is minimized
times, propagation delays, and output
drives are severely affected. Disadvantage: More board area, higher initial cost
Note: These networks are useful for protecting the following
A digital inputs and outputs C 3–state outputs
B analog inputs and outputs D bidirectional (I/O) ports

PROPAGATION DELAY AND RISE TIME

vs. SERIES RESISTANCE
R [ t
where: C@k
R = the maximum allowable series resistance in ohms
t = the maximum tolerable propagation delay or rise time in seconds
C = the board capacitance plus the driven device’s
= input capacitance in farads
k = 0.7 for propagation delay calculations
k = 2.3 for rise time calculations

Figure 1. Networks for Minimizing ESD and Reducing

CMOS Latch Up Susceptibility

MOTOROLA CMOS LOGIC DATA CHAPTER 5

5–3
 4 NOTES: 1. 1/16 inch conductive sheet stock covering bench
top work area.
2. Ground strap.
1 3. Wrist strap in contact with skin.
4. Static neutralizer. (Ionized air blower directed at
work.) Primarily for use in areas where direct
grounding is impractical.
2
5. Room humidifier. Primarily for use in areas where
5 the relative humidity is less than 45%. Caution:
building heating and cooling systems usually dry
the air causing the relative humidity inside of
3 buildings to be less than outside humidity.

RESISTOR =
1 MEGAOHM
Figure 2. Typical Manufacturing Work Station

POWER SUPPLIES the possibility of latch–up related failures. This system

CMOS devices have low power requirements and the abil-
ity to operate over a wide range of supply voltages. These
two characteristics allow CMOS designs to be implemented
using inexpensive, conventional power supplies, instead of
switching power supplies and power supplies with cooling
fans. In addition, batteries may be used as either a primary
power source or for emergency backup.
The absolute maximum power supply voltage for 14000
Series Metal–gate CMOS is 18.0 Vdc. Figure 4 offers some
insight as to how this specification was derived. In the figure,
VS is the maximum power supply voltage and IS is the sus-
taining current of the latch–up mode. The value of VS was
chosen so that the secondary breakdown effect may be
avoided.
In an ideal system design, a power supply should be
designed to deliver only enough current to insure proper
operation of all devices. The obvious benefit of this type
design is cost savings; an added benefit is protection against
protection can be provided by the power supply filter and/or
voltage regulator.
CMOS devices can be used with battery or battery backup
systems. A few precautions should be taken when designing
battery–operated systems:
1. The recommended power supply voltage should be ob-
served. For battery backup systems such as the one in
Figure 5, the battery voltage must be at least 3.7 Volts
(3 Volts from the minimum power supply voltage and
0.7 Volts to account for the voltage drop across the se-
ries diode).
2. Inputs that might go above the battery backup voltage
should either use a series resistor to limit the input cur-
rent to less than 10 mA or use the MC14049UB or
MC14050B high–to–low voltage translators.
3. Outputs that are subject to voltage levels above VDD or
below VSS should be protected with a series resistor to
limit the current to less than 10 mA or with clamping
diodes.

IDD

LATCH
UP MODE
SECONDARY
BREAKDOWN

LOW CURRENT
JUNCTION
IS
AVALANCHE

VS VDD
VS = DATA SHEET MAXIMUM SUPPLY RATING

Figure 3. Secondary Breakdown Characteristics

CHAPTER 5 MOTOROLA CMOS LOGIC DATA

5–4
 POWER SUPPLY

BATTERY BACKUP
LINE POWER ONLY BATTERY BACKUP RECHARGE
SYSTEM SYSTEM

MC14049UB
CMOS CMOS
MC14050B
SYSTEM SYSTEM

MC14049UB
MC14050B

Figure 4. Battery Backup Interface

INPUTS VDD = 5.0 Vdc

All inputs, while in the recommended operating range (VSS

Vout , OUTPUT VOLTAGE (V)

< Vin < VDD) can be modeled as shown in Figure 6. For input
SINGLE INPUT NAND, AND
voltages in this range, diodes D1 and D2 are modeled as
MULTIPLE INPUT NOR, OR
resistors, representing the reverse bias impedance of the 5.0
diodes. The maximum input current is worst case, 1 µA,
when the inputs are at VDD or VSS, and VDD = 15.0 V. This 4.0 SINGLE INPUT NOR, OR
model does not apply to inputs with pull–up or pull–down MULTIPLE INPUT NAND, AND
3.0
resistors.
2.0

1.0

0
VDD 0 1.0 2.0 3.0 4.0 5.0
R1 = R2 = HIGH Z Vin, INPUT VOLTAGE (V)

R1 Figure 6. Typical Transfer Characteristics

for Buffered Devices

For these reasons, all unused inputs should be connected

R2 7.5 pF
either to VDD or VSS. For applications with inputs going to
edge connectors, a 100 kilohm resistor to VSS should be
used, as well as a series resistor for static protection and
Figure 5. Input Model for VSS v Vin v VDD current limiting (Figure 8). The 100 kilohm resistor will help
eliminate any static charges that might develop on the
printed circuit board. See Figure 2 for other possible
protection arrangements.
When left open–circuited, the inputs may self–bias at or
near the typical switchpoint, where both the P–channel and FROM RS CMOS
EDGE
N–channel transistors are conducting, causing excessive DEVICE
CONNECTOR
current drain. Due to the high gain of the inverters (see
100 k
Figure 7), the device may also go into oscillation from any
noise in the system. Since CMOS devices dissipate the most
power during switching, this oscillation can cause very large
current drain and undesired switching. Figure 7. External Protection

MOTOROLA CMOS LOGIC DATA CHAPTER 5

5–5
 For input voltages outside of the recommended operating
range, the CMOS input is modeled as in Figure 9. The
resistor–diode protection network allows the user greater
freedom when designing a worst case system. The device
inputs are guaranteed to withstand voltages from VSS – 0.5 V
to VDD + 0.5 V and a maximum current of 10 mA. With the
above input ratings, most designs will require no special
terminations or design considerations.
D1
 1.5 k
D2 7.5 pF
Figure 8. Input Model for Vin > VDD or Vin < VSS
Other specifications that should be noted are the maxi-
mum input rise and fall times. Figure 10 shows the
oscillations that may result from exceeding the 15 µs
maximum rise and fall time at VDD = 5.0 V, 5 µs at 10 V, or
4 µs at 15 V. As the voltage passes through the switching
threshold region with a slow rise time, any noise that is on the
input is amplified, and passed through to the output, causing
oscillations. The oscillation may have a low enough fre-
quency to cause succeeding stages to switch, giving
unexpected results. If input rise or fall times are expected to
exceed 15 µs at 5.0 V, 5 µs at 10 V, or 4 µs at 15 V,
Schmitt–trigger devices such as the MC14093B, MC14583B,
MC14584B, MC14106B, HC14, or HC132 are recommended
for squaring–up these slow transitions.
VDD
Vin
VSS
VOH
Vout
VOL
Figure 9. Maximum Rise and Fall Time Violations
OUTPUTS
All CMOS B–Series outputs are buffered to insure consis-
tent output voltage and current performance. All buffered out-
puts have guaranteed output voltages of VOL = 0.05 V and
VOH = VDD – 0.05 V for Vin = VDD or VSS and lout = 0 µA. The
output drives for all buffered CMOS devices are such that
1 LSTTL load can be driven across the full temperature
range.
CHAPTER 5
5–6
CMOS outputs are limited to externally forced output
voltages of VSS – 0.5 V v Vout v VDD + 0.5 V. When
voltages are forced outside of this range, a silicon controlled
rectifier (SCR) formed by parasitic transistors can be
triggered, causing the device to latch up. For more informa-
tion on this, see the explanation of CMOS Latch Up in this
section.
The maximum rated output current for most outputs is
10 mA. The output short–circuit currents of these devices
typically exceed these limits. Care must be taken not to ex-
ceed the maximum ratings found on every data sheet.
For applications that require driving high capacitive loads
where fast propagation delays are needed (e.g., driving
power MOSFETs), two or more outputs on the same chip
may be externally paralleled.
CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
prevent it.
Figure 11 shows the cross–section of a typical CMOS in-
verter and Figure 12 shows the parasitic bipolar devices. The
circuit formed by the parasitic transistors and resistors is the
basic configuration of a silicon controlled rectifier, or SCR. In
the latch up condition, transistors Q1 and Q2 are turned ON,
each providing the base current necessary for the other to
remain in saturation, thereby latching the devices in the ON
state. Unlike a conventional SCR, where the device is turned
ON by applying a voltage to the base of the NPN transistor,
the parasitic SCR is turned ON by applying a voltage to the
emitter of either transistor. The two emitters that trigger the
SCR are the same point, the CMOS output. Therefore, to
latch up the CMOS device, the output voltage must be great-
er than VDD + 0.5 V or less than VSS – 0.5 V and have suffi-
cient current to trigger the SCR. The latch–up mechanism is
similar for the inputs.
Once a CMOS device is latched up, if the supply current is
not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below:
1. Insure that inputs and outputs are limited to the maxi-
mum rated values, as follows:
v
– 0.5 V ≤ Vin or Vout VDD + 0.5 V (referenced to VSS)
v
|Iin or Iout| 10 mA (unless otherwise indicated on the
data sheet)
2. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
to limit the expected worst case current to the maximum
rating of 10 mA. (See Figure 2).
3. Sequence power supplies so that the inputs or outputs
of CMOS devices are not active before the supply pins
are powered up (e.g., recessed edge connectors and/
or series resistors may be used in plug–in board ap-
plications).
4. Voltage regulating or filtering should be used in board
design and layout to insure that power–supply lines are
free of excessive noise.
5. Limit the available power supply current to the devices
that are subject to latch–up conditions. This can be ac-
complished with the power supply filtering network or
with a current–limiting regulator.
MOTOROLA CMOS LOGIC DATA
 P–CHANNEL N–CHANNEL
INPUT

VDD VDD P–CHANNEL N–CHANNEL VSS

OUTPUT
OUTPUT OUTPUT

N+
FIELD OXIDE ÇÇÇ
P+ P+
FIELD OXIDE
N+
ÇÇ N+ P+
FIELD OXIDE

N – SUBSTRATE P – WELL

Figure 10. CMOS Wafer Cross Section

Q1
N–CHANNEL OUTPUT
N+ N+ N– N–SUBSTRATE RESISTANCE
VDD
VSS N–
P–
P+
VDD
VSS P–
P–WELL RESISTANCE P+
Q2 P–CHANNEL OUTPUT

Figure 11. Latch Up Circuit Schematic

MOTOROLA CMOS LOGIC DATA CHAPTER 5

5–7
Data Sheets 6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14000UB
Dual 3-Input NOR" Gate
Plus Inverter L SUFFIX
CERAMIC
The MC14000UB dual 3–input NOR gate plus inverter is constructed with CASE 632
MOS P–channel and N–channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find primary
use where low power dissipation and/or high noise immunity is desired. P SUFFIX
PLASTIC
• Diode Protection on All Inputs
CASE 646
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Pin–for–Pin Replacement for CD4000UB D SUFFIX

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SOIC
MAXIMUM RATINGS* (Voltages Referenced to VSS) CASE 751A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VDD
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage
Parameter Value
– 0.5 to + 18.0
Unit
V
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
MC14XXXUBCP Plastic
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V MC14XXXUBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
MC14XXXUBD SOIC
lin, lout Input or Output Current (DC or Transient), ± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
Î ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C
LOGIC DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C 3

4 6
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 5
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
11

12 10

CIRCUIT SCHEMATIC 13

14 11 12 13 8
VDD 8 9
VDD = PIN 14
3 VSS = PIN 7

4
PIN ASSIGNMENT
9
5 NC 1 14 VDD
NC 2 13 IN 3B
IN 1A 3 12 IN 2B
IN 2A 4 11 IN 1B
IN 3A 5 10 OUTB

VSS OUTA 6 9 OUTC

7 6 10
VSS 7 8 IN 1C

NC = NO CONNECTION

MC14000UB MOTOROLA CMOS LOGIC DATA

6–2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C + 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc

ÎÎÎÎÎÎÎÎÎÎ
(VO = 4.5 Vdc)

ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.0

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.0

ÎÎÎÎ
—

ÎÎÎ
1.0
(VO = 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 13.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
2.0
2.5
—
—
4.50
6.75
2.0
2.5
—
—
2.0
2.5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 Vdc) 5.0 4.0 — 4.0 2.75 — 4.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VO = 1.0 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VO = 1.5 Vdc)
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
8.0
12.5
—
—
8.0
12.5
5.50
8.25
—
—
8.0
12.5
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
Quiescent Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Per Package)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.3 µA/kHz) f + IDD/N µAdc
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD/N

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Per Gate, CL = 50 pF) 15 IT = (0.8 µA/kHz) f + IDD/N
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14000UB

6–3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (1.5 ns/pF) CL + 25 ns

ÎÎÎÎÎ
5.0

ÎÎÎÎ
—

ÎÎÎÎ
100

ÎÎÎÎ
200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
tTHL = (0.75 ns/pF) CL + 12.5 ns

ÎÎÎÎÎÎÎ
tTHL = (0.55 ns/pF) CL + 9.5 ns
10
15
—
—
50
40
100
80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 30 ns tPHL 5.0 — 115 230

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 22 ns 10 — 55 110

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.50 ns/pF) CL + 15 ns 15 — 40 80
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD
20 ns 20 ns
VDD
14 INPUT 90%
INPUT 50%
PULSE 10% VSS
GENERATOR OUTPUT tPHL tPLH
90% VOH
7 VSS CL OUTPUT 50%
10%
VOL
tTHL tTLH

Figure 1. Switching Time Test Circuit and Waveforms

16 16
VDD = 15 Vdc VDD = 15 Vdc
TA = 25°C UNUSED INPUTS
14 14 CONNECTED TO VSS
a
Vout , OUTPUT VOLTAGE (Vdc)

Vout , OUTPUT VOLTAGE (Vdc)

a ONE INPUT ONLY

ID , DRAIN CURRENT (mAdc)

12 12
c b AND INVERTER 10 Vdc
10 Vdc
10 b TWO INPUTS 10 a TA = + 125°C
a b
c THREE INPUTS a b b TA = – 55°C
c b a
8.0 8.0 8.0

6.0 5.0 Vdc ID = 15 Vdc 6.0 6.0 5.0 Vdc

b
4.0 4.0 4.0
c a ID = 10 Vdc
a b
2.0 2.0 2.0

0 0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 2.0 4.0 6.0 8.0 10 12 14 16
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 2. Typical Voltage and Current Figure 3. Typical Voltage Transfer

Transfer Characteristics Characteristics versus Temperature

MC14000UB MOTOROLA CMOS LOGIC DATA

6–4
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14001B
Quad 2-Input NOR Gate
B-Suffix Series CMOS Gates MC14002B
The B Series logic gates are constructed with P and N channel Dual 4-Input NOR Gate
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
MC14011B
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
Quad 2-Input NAND Gate
• All Outputs Buffered
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14012B
Schottky TTL Load Over the Rated Temperature Range. Dual 4-Input NAND Gate
• Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
• Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix
MC14023B
Devices (Exceptions: MC14068B and MC14078B) Triple 3-Input NAND Gate

MC14025B
Triple 3-Input NOR Gate

MC14068B
8-Input NAND Gate
L SUFFIX P SUFFIX D SUFFIX
CERAMIC
CASE 632
PLASTIC
CASE 646
SOIC
CASE 751A MC14071B
Quad 2-Input OR Gate
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
Plastic
Ceramic MC14072B
MC14XXXBD SOIC Dual 4-Input OR Gate

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.
MC14073B
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit
Triple 3-Input AND Gate

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VDD

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
MC14075B
Triple 3-Input OR Gate

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
lin, lout

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input or Output Current (DC or Transient),

ÎÎÎÎÎÎ
ÎÎÎ
per Pin
± 10 mA
MC14078B
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ 8-Input NOR Gate
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C
MC14081B
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur. Quad 2-Input AND Gate
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C MC14082B
Dual 4-Input AND Gate
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA MC14001B

6–5
 LOGIC DIAGRAMS

NOR NAND OR AND

MC14001B MC14011B MC14071B MC14081B

Quad 2–Input NOR Gate Quad 2–Input NAND Gate Quad 2–Input OR Gate Quad 2–Input AND Gate

1 1 1 1
3 3 3 3
2 2 2 2

5 5 5 5
2 INPUT

4 4 4 4
6 6 6 6

8 8 8 8
10 10 10 10
9 9 9 9

12 12 12 12
11 11 11 11
13 13 13 13

MC14025B MC14023B MC14075B MC14073B

Triple 3–Input NOR Gate Triple 3–Input NAND Gate Triple 3–Input OR Gate Triple 3–Input AND Gate

1 1 1 1
2 9 2 9 2 9 2 9
8 8 8 8
3 INPUT

3 3 3 3
4 6 4 6 4 6 4 6
5 5 5 5
11 11 11 11
12 10 12 10 12 10 12 10
13 13 13 13

MC14002B MC14012B MC14072B MC14082B

Dual 4–Input NOR Gate Dual 4–Input NAND Gate Dual 4–Input OR Gate Dual 4–Input AND Gate

2 2 2 2
3 1 3 1 3 1 3 1
4 4 4 4
4 INPUT

5 5 5 5
9 9 9 9
10 13 10 13 10 13 10 13
11 11 11 11
12 12 12 12
NC = 6, 8 NC = 6, 8 NC = 6, 8 NC = 6, 8

MC14078B MC14068B
8–Input NOR Gate 8–Input NAND Gate
VDD = PIN 14
2 2
VSS = PIN 7
3 3
4 4 FOR ALL DEVICES
8 INPUT

5 5
13 13
9 9
10 10
11 11
12 NC = 6, 8 12 NC = 6, 8

MC14001B MOTOROLA CMOS LOGIC DATA

6–6
 PIN ASSIGNMENTS

MC14001B MC14002B MC14011B MC14012B

Quad 2–Input NOR Gate Dual 4–Input NOR Gate Quad 2–Input NAND Gate Dual 4–Input NAND Gate

IN 1A 1 14 VDD OUTA 1 14 VDD IN 1A 1 14 VDD OUTA 1 14 VDD

IN 2A 2 13 IN 2D IN 1A 2 13 OUTB IN 2A 2 13 IN 2D IN 1A 2 13 OUTB
OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTA 3 12 IN 1D IN 2A 3 12 IN 4B
OUTB 4 11 OUTD IN 3A 4 11 IN 3B OUTB 4 11 OUTD IN 3A 4 11 IN 3B
IN 1B 5 10 OUTC IN 4A 5 10 IN 2B IN 1B 5 10 OUTC IN 4A 5 10 IN 2B
IN 2B 6 9 IN 2C NC 6 9 IN 1B IN 2B 6 9 IN 2C NC 6 9 IN 1B
VSS 7 8 IN 1C VSS 7 8 NC VSS 7 8 IN 1C VSS 7 8 NC

MC14023B MC14025B MC14068B MC14071B

Triple 3–Input NAND Gate Triple 3–Input NOR Gate 8–Input NAND Gate Quad 2–Input OR Gate

IN 1A 1 14 VDD IN 1A 1 14 VDD NC 1 14 VDD IN 1A 1 14 VDD

IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C IN 1 2 13 OUT IN 2A 2 13 IN 2D
IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C IN 2 3 12 IN 8 OUTA 3 12 IN 1D
IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C IN 3 4 11 IN 7 OUTB 4 11 OUTD
IN 3B 5 10 OUTC IN 3B 5 10 OUTC IN 4 5 10 IN 6 IN 1B 5 10 OUTC
OUTB 6 9 OUTA OUTB 6 9 OUTA NC 6 9 IN 5 IN 2B 6 9 IN 2C
VSS 7 8 IN 3A VSS 7 8 IN 3A VSS 7 8 NC VSS 7 8 IN 1C

MC14072B MC14073B MC14075B MC14078B

Dual 4–Input OR Gate Triple 3–Input AND Gate Triple 3–Input OR Gate 8–Input NOR Gate

OUTA 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD NC 1 14 VDD

IN 1A 2 13 OUTB IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C IN 1 2 13 OUT
IN 2A 3 12 IN 4B IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C IN 2 3 12 IN 8
IN 3A 4 11 IN 3B IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C IN 3 4 11 IN 7
IN 4A 5 10 IN 2B IN 3B 5 10 OUTC IN 3B 5 10 OUTC IN 4 5 10 IN 6
NC 6 9 IN 1B OUTB 6 9 OUTA OUTB 6 9 OUTA NC 6 9 IN 5
VSS 7 8 NC VSS 7 8 IN 3A VSS 7 8 IN 3A VSS 7 8 NC

MC14081B MC14082B
Quad 2–Input AND Gate Dual 4–Input AND Gate

IN 1A 1 14 VDD OUTA 1 14 VDD

IN 2A 2 13 IN 2D IN 1A 2 13 OUTB
OUTA 3 12 IN 1D IN 2A 3 12 IN 4B
OUTB 4 11 OUTD IN 3A 4 11 IN 3B
IN 1B 5 10 OUTC IN 4A 5 10 IN 2B
IN 2B 6 9 IN 2C NC 6 9 IN 1B
VSS 7 8 IN 1C VSS 7 8 NC NC = NO CONNECTION

MOTOROLA CMOS LOGIC DATA MC14001B

6–7
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc

ÎÎÎÎÎÎÎÎÎÎ
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
Quiescent Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Per Package)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.3 µA/kHz) f + IDD/N µAdc
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD/N

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Per Gate, CL = 50 pF) 15 IT = (0.9 µA/kHz) f + IDD/N
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.

MC14001B MOTOROLA CMOS LOGIC DATA

6–8
 B–SERIES GATE SWITCHING TIMES

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Rise Time, All B–Series Gates tTLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tTLH = (1.35 ns/pF) CL + 33 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/PF) CL + 20 ns
5.0
10
—
—
100
50
200
100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Fall Time, All B–Series Gates tTHL ns
tTHL = (1.35 ns/pF) CL + 33 ns 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTHL = (0.40 ns/pF) CL + 20 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time tPLH, tPHL ns
MC14001B, MC14011B only

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns 5.0 — 125 250

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns 10 — 50 100
tPLH, tPHL = (0.26 ns/pF) CL + 27 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
All Other 2, 3, and 4 Input Gates
tPLH, tPHL = (0.90 ns/pF) CL + 115 ns 5.0 — 160 300

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 47 ns 10 — 65 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 15 — 50 100
8–Input Gates (MC14068B, MC14078B)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 155 ns 5.0 — 200 350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 62 ns 10 — 80 150
tPLH, tPHL = (0.26 ns/pF) CL + 47 ns 15 — 60 110
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

14 VDD 20 ns 20 ns
VDD
INPUT 90%
INPUT 50%
PULSE 10% 0V
OUTPUT tPHL tPLH
GENERATOR

CL 90% VOH
* 50%
OUTPUT 10%
INVERTING VOL
tTHL tTLH
tPLH tPHL
7 VSS OUTPUT VOH
90%
NON–INVERTING 50%
* All unused inputs of AND, NAND gates must be connected to VDD. 10% VOL
All unused inputs of OR, NOR gates must be connected to VSS. tTLH tTHL

Figure 1. Switching Time Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14001B

6–9
 CIRCUIT SCHEMATIC
NOR, OR GATES

MC14001B, MC14071B
One of Four Gates Shown
VDD
14 VDD
1, 6, 8, 13

*
2, 5, 9, 12

3, 4, 10, 11
MC14025B, MC14075B
One of Three Gates Shown

7 VSS VDD
VSS
1, 3, 11
* Inverter omitted in MC14001B

2, 4, 12

14 VDD

*
MC14002B, MC14072B
One of Two Gates Shown VSS
9, 6, 10
VDD VDD
3, 9
8, 5, 13
2, 10
7 VSS
14 VDD
VSS
* * Inverter omitted in MC14025B

VSS 1, 13

5, 11 SAME AS
4, 12 ABOVE
7 VSS
* Inverter omitted in MC14002B

VDD MC14078B
Eight Input Gate
2

14 VDD

VSS
4 SAME AS
5 ABOVE
SAME AS 13
9
10 ABOVE
11 SAME AS
12 ABOVE
7 VSS

MC14001B MOTOROLA CMOS LOGIC DATA

6–10
 CIRCUIT SCHEMATIC
NAND, AND GATES

MC14011B, MC14081B
One of Four Gates Shown
14 VDD

MC14023B, MC14073B
3, 4, 10, 11
One of Three Gates Shown
VDD 2, 5, 9, 12

1, 6, 8, 13
7 VSS
* Inverter omitted in MC14011B

2, 4, 12 14 VDD

1, 3, 11
VSS
*
VDD

9, 6, 10
MC14012B, MC14082B
8, 5, 13
One of Two Gates Shown
VDD
7 VSS
VSS
* Inverter omitted in MC14023B

14 VDD
MC14068B
VDD Eight Input Gate 2, 10

*
3, 9
VSS
1, 13
4, 12 SAME AS
VDD 5, 11 ABOVE
2
* Inverter omitted in MC14012B 7 VSS

VSS
5 SAME AS
4 ABOVE
14 VDD

VSS

VDD
9 SAME AS
13
10 ABOVE
11 SAME AS
12 ABOVE

7 VSS

VSS

MOTOROLA CMOS LOGIC DATA MC14001B

6–11
 TYPICAL B–SERIES GATE CHARACTERISTICS

N–CHANNEL DRAIN CURRENT P–CHANNEL DRAIN CURRENT

(SINK) (SOURCE)
5.0 – 10
– 9.0
4.0 – 8.0 TA = – 55°C
ID , DRAIN CURRENT (mA)

ID , DRAIN CURRENT (mA)

– 7.0
TA = – 55°C – 40°C
3.0 – 6.0
– 40°C
– 5.0
+ 85°C + 25°C + 25°C
2.0 – 4.0 + 85°C
+ 125°C
– 3.0 + 125°C
1.0 – 2.0
– 1.0
0 0
0 1.0 2.0 3.0 4.0 5.0 0 – 1.0 – 2.0 – 3.0 – 4.0 – 5.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = – 5.0 Vdc

20 – 50
18 – 45
TA = – 55°C
16 – 40
ID , DRAIN CURRENT (mA)

ID , DRAIN CURRENT (mA)

14 – 40°C – 35
12 + 25°C – 30 TA = – 55°C
+ 85°C
10 – 25 – 40°C
8.0 + 125°C – 20 + 25°C
+ 85°C
6.0 – 15
4.0 – 10 + 125°C

2.0 – 5.0
0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 – 1.0 – 2.0 – 3.0 – 4.0 – 5.0 – 6.0 – 7.0 – 8.0 – 9.0 – 10
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

Figure 4. VGS = 10 Vdc Figure 5. VGS = – 10 Vdc

50 – 100
45 – 90
40 – 80
ID , DRAIN CURRENT (mA)

ID , DRAIN CURRENT (mA)

35 TA = – 55°C – 70
30 – 40°C – 60
TA = – 55°C
25 + 25°C – 50 – 40°C
20 + 85°C – 40 + 25°C
+ 125°C + 85°C
15 – 30
+ 125°C
10 – 20
5.0 – 10
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0 – 2.0 – 4.0 – 6.0 – 8.0 – 10 – 12 – 14 – 16 – 18 – 20
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

Figure 6. VGS = 15 Vdc Figure 7. VGS = – 15 Vdc

These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.

MC14001B MOTOROLA CMOS LOGIC DATA

6–12
 TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)

V out , OUTPUT VOLTAGE (Vdc) VOLTAGE TRANSFER CHARACTERISTICS

V out , OUTPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND SINGLE INPUT NAND, AND
5.0 MULTIPLE INPUT NOR, OR MULTIPLE INPUT NOR, OR
10

4.0 8.0
SINGLE INPUT NOR, OR SINGLE INPUT NOR, OR
3.0 MULTIPLE INPUT NAND, AND 6.0 MULTIPLE INPUT NAND, AND
2.0 4.0

1.0 2.0

0 0
0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc

16 DC NOISE MARGIN
SINGLE INPUT NAND, AND
14 MULTIPLE INPUT NOR, OR The DC noise margin is defined as the input voltage range
V out , OUTPUT VOLTAGE (Vdc)

from an ideal “1” or “0” input level which does not produce
12
output state change(s). The typical and guaranteed limit val-
SINGLE INPUT NOR, OR
10 MULTIPLE INPUT NAND, AND
ues of the input values VIL and VIH for the output(s) to be at a
fixed voltage VO are given in the Electrical Characteristics
8.0 table. VIL and VIH are presented graphically in Figure 11.
Guaranteed minimum noise margins for both the “1” and
6.0
“0” levels =
4.0 1.0 V with a 5.0 V supply
2.0 2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
0
0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc)

Figure 10. VDD = 15 Vdc

Vout VDD Vout VDD

VO VO

VO VO

VDD VDD
0 Vin 0 Vin

VIL VIH VIL VIH

VSS = 0 VOLTS DC
(a) Inverting Function (b) Non–Inverting Function

Figure 11. DC Noise Immunity

MOTOROLA CMOS LOGIC DATA MC14001B

6–13
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14001UB
Quad 2-Input NOR Gate
UB-Suffix Series CMOS Gates MC14002UB
The UB Series logic gates are constructed with P and N channel Dual 4-Input NOR Gate
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
MC14011UB
non–buffered functions. Quad 2-Input NAND Gate
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linear and Oscillator Applications MC14012UB
• Capable of Driving Two Low–power TTL Loads or One Low–power Dual 4-Input NAND Gate
Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
• Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix
MC14023UB
Devices Triple 3-Input NAND Gate

MC14025UB
LOGIC DIAGRAMS Triple 3-Input NOR Gate
MC14001UB MC14002UB MC14011UB
Quad 2–Input Dual 4–Input Quad 2–Input
NOR Gate NOR Gate NAND Gate
L SUFFIX
1 2 1
3 3 CERAMIC
2 3 2 CASE 632
1
5 4 5
4 4
6 5 6
8 9 8
10 10 P SUFFIX
9 10 9
13 PLASTIC
12 11 12
11 11 CASE 646
13 12 13
NC = 6, 8

D SUFFIX
MC14012UB MC14023UB MC14025UB
SOIC
Dual 4–Input Triple 3–Input Triple 3–Input
CASE 751A
NAND Gate NAND Gate NOR Gate
1 1 ORDERING INFORMATION
2 2 9
2 9 MC14XXXUBCP Plastic
3
1 8 8 MC14XXXUBCL Ceramic
4 3 3 MC14XXXUBD SOIC
5
4 6 4 6 TA = – 55° to 125°C for all packages.
9
5 5
10
13 11 11
11
12 10 12 10 This device contains protection circuitry to
12
NC = 6, 8 13 13 guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
VDD = PIN 14 any voltage higher than maximum rated volt-
VSS = PIN 7 ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
v v
FOR ALL DEVICES
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.

MC14001UB MOTOROLA CMOS LOGIC DATA

6–14
 PIN ASSIGNMENTS

MC14001UB MC14002UB MC14011UB

Quad 2–Input NOR Gate Dual 4–Input NOR Gate Quad 2–Input NAND Gate

IN 1A 1 14 VDD OUTA 1 14 VDD IN 1A 1 14 VDD

IN 2A 2 13 IN 2D IN 1A 2 13 OUTB IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTA 3 12 IN 1D
OUTB 4 11 OUTD IN 3A 4 11 IN 3B OUTB 4 11 OUTD
IN 1B 5 10 OUTC IN 4A 5 10 IN 2B IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C NC 6 9 IN 1B IN 2B 6 9 IN 2C
VSS 7 8 IN 1C VSS 7 8 NC VSS 7 8 IN 1C

MC14012UB MC14023UB MC14025UB

Dual 4–Input NAND Gate Triple 3–Input NAND Gate Triple 3–Input NOR Gate

OUTA 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD

IN 1A 2 13 OUTB IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C
IN 2A 3 12 IN 4B IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C
IN 3A 4 11 IN 3B IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C
IN 4A 5 10 IN 2B IN 3B 5 10 OUTC IN 3B 5 10 OUTC
NC 6 9 IN 1B OUTB 6 9 OUTA OUTB 6 9 OUTA
VSS 7 8 NC VSS 7 8 IN 3A VSS 7 8 IN 3A

NC = NO CONNECTION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
PD

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
_C

†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MOTOROLA CMOS LOGIC DATA MC14001UB

6–15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc

ÎÎÎÎÎÎÎÎÎÎ
(VO = 4.5 Vdc)

ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.0

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.0

ÎÎÎÎ
—

ÎÎÎ
1.0
(VO = 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 13.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
2.0
2.5
—
—
4.50
6.75
2.0
2.5
—
—
2.0
2.5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 Vdc) “1” Level IIH 5.0 4.0 — 4.0 2.75 — 4.0 — Vdc
(VO = 1.0 Vdc) 10 8.0 — 8.0 5.50 — 8.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VO = 1.5 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
Output Drive Current ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 12.5 — 12.5 8.25 — 12.5 —
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
– 0.62
– 1.8
—
—
– 0.5
– 1.5
– 0.9
– 3.5
—
—
– 0.35
– 1.1
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Gate CL = 50 pF)
ÎÎÎ
IT 5.0
10
15
IT = (0.3 µA/kHz) f + IDD/N
IT = (0.6 µA/kHz) f + IDD/N
IT = (0.8 µA/kHz) f + IDD/N
µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.

MC14001UB MOTOROLA CMOS LOGIC DATA

6–16
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (1.5 ns/pF) CL + 25 ns

ÎÎÎÎÎ
5.0

ÎÎÎÎ
—

ÎÎÎÎ
100

ÎÎÎÎ
200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
tTHL = (0.75 ns/pF) CL + 12.5 ns

ÎÎÎÎ
tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎ
10
15
—
—
50
40
100
80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, tPHL ns
tPLH, tPHL = (1.7 ns/pF) CL + 30 ns 5.0 — 90 180

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 22 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.50 ns/pF) CL + 15 ns 15 — 40 80
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns
VDD
14 INPUT VDD
90%
50%
PULSE INPUT OUTPUT 10% 0V
GENERATOR tPHL tPLH
* CL 90% VOH
OUTPUT 50%
INVERTING
10% VOL
7 VSS
* All unused inputs of AND, NAND gates must be tTHL tTLH
connected to VDD.
All unused inputs of OR, NOR gates must be
connected to VSS.

Figure 1. Switching Time Test Circuit and Waveforms

MC14001UB CIRCUIT SCHEMATIC MC14002UB CIRCUIT SCHEMATIC

(1/2 of Device Shown)
VDD VDD 14
3 14 10 2, 9

1 8 3, 10

2 9 4, 11

5, 12

1, 13

6 13

5 12
VSS 7

4 7 11
VSS

MOTOROLA CMOS LOGIC DATA MC14001UB

6–17
 MC14011UB CIRCUIT SCHEMATIC MC14012UB CIRCUIT SCHEMATIC MC14023UB CIRCUIT SCHEMATIC
(1/4 of Device Shown) (1/2 of Device Shown) (1/3 of Device Shown)

14 VDD
14 VDD 14 VDD

3, 4, 10, 11 1, 13
6, 9, 10
1, 6, 8, 13 2, 9
5, 1, 11
2, 5, 9, 12 3, 10

7 VSS 4, 11 4, 2, 12

5, 12
3, 8, 13
7 VSS
7 VSS

MC14025UB CIRCUIT SCHEMATIC 16 16

VDD = 15 Vdc TA = + 25°C VDD = 15 Vdc Unused input
(1/3 of Device Shown) 14 Unused input 14 connected to
b
Vout , OUTPUT VOLTAGE (Vdc)

Vout , OUTPUT VOLTAGE (Vdc)

connected to a VSS.

I D, DRAIN CURRENT (mAdc)

14 VDD 12 12
VSS.
10 Vdc a One input only 10 Vdc a TA = + 125°C
1, 3, 11 10 b Both inputs 10
b TA = – 55°C
2, 4, 12 8.0 8.0 8.0
b a a b
8, 5, 13
6.0 6.0 6.0
9, 6, 10 5.0 Vdc 5.0 Vdc
15 Vdc
4.0 b a 4.0 4.0
a 10 Vdc a b
b
2.0 2.0 2.0
7 VSS 0 0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 2.0 4.0 6.0 8.0 10 12 14 16
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 2. Typical Voltage and Figure 3. Typical Voltage Transfer

Current Transfer Characteristics Characteristics versus
Temperature

0 10
c a 15 Vdc
b a
VGS = – 5.0 Vdc c
– 2.0 8.0
I D, DRAIN CURRENT (mAdc)

b VGS = 10 Vdc
I D, DRAIN CURRENT (mAdc)

a b
a TA = – 55°C
b TA = + 25°C c
– 4.0 6.0
c TA = + 125°C
a TA = – 55°C
c b TA = + 25°C
– 6.0 4.0 c TA = + 125°C
– 10 Vdc b
c a
– 8.0 b – 15 Vdc 2.0
b 5.0 Vdc
c
a a
– 10 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0 2.0 4.0 6.0 8.0 10
VDS, DRAIN VOLTAGE (Vdc) VDS, DRAIN VOLTAGE (Vdc)

Figure 4. Typical Output Source Figure 5. Typical Output Sink

Characteristics Characteristics

MC14001UB MOTOROLA CMOS LOGIC DATA

6–18
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14006B
18-Bit Static Shift Register
The MC14006B shift register is comprised of four separate shift register L SUFFIX
CERAMIC
sections sharing a common clock: two sections have four stages, and two
CASE 632
sections have five stages with an output tap on both the fourth and fifth
stages. This makes it possible to obtain a shift register of 4, 5, 8, 9, 10, 12,
13, 14, 16, 17, or 18 bits by appropriate selection of inputs and outputs. This
part is particularly useful in serial shift registers and time delay circuits. P SUFFIX
PLASTIC
• Output Transitions Occur on the Falling Edge of the Clock Pulse CASE 646
• Fully Static Operation
• Can be Cascaded to Provide Longer Shift Register Lengths
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
• Capable of Driving Two Low–power TTL Loads or One Low–power SOIC
Schottky TTL Load Over the Rated Temperature Range CASE 751A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Pin–for–Pin Replacement for CD4006B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCP Plastic
Symbol Parameter Value Unit MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C
TRUTH TABLE
(Single Stage)
Dn C Qn+1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
0 0
TL Lead Temperature (8–Second Soldering) 260 _C 1 1
* Maximum Ratings are those values beyond which damage to the device may occur. x Qn
X = Don’t Care
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

BLOCK DIAGRAM
1 13 4 11 12 5 10 6 8 9
DP1 Q4 DP5 Q8 Q9 DP10 Q13 DP14 Q17 Q18

VDD = PIN 14 D D D D D D
VSS = PIN 7 4 4 1 4 4 1
NC = PIN 2 STAGES STAGES STAGE STAGES STAGES STAGE
C C C C C C

CLOCK 3

LOGIC DIAGRAM
(ONE REGISTER STAGE)
C C
#
*
DATA D+1
* Transmission Gate (C) #Inverter used only on the first stage of
1 C C each four–stage element.

Input to output is
IN OUT (A) A bidirectional low impedance when control input 1 is “low” and control input 2 is “high”.
(B) An open circuit when control input 1 is “high” and control input 2 is “low”.
2
(C)

MOTOROLA CMOS LOGIC DATA MC14006B

6–19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ
—

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ
—

ÎÎÎÎ
7.0

ÎÎÎ
—
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (1.3 µA/kHz) f + IDD
IT = (2.6 µA/kHz) f + IDD
IT = (3.9 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT

DP1 1 14 VDD
NC 2 13 Q4
C 3 12 Q9
DP5 4 11 Q8
DP10 5 10 Q13
DP14 6 9 Q18
VSS 7 8 Q17

NC = NO CONNECTION

MC14006B MOTOROLA CMOS LOGIC DATA

6–20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns

ÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 77 ns
tPHL 5.0
10
—
—
300
110
600
220

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 55 ns 15 — 80 160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 200 100 — ns
10 120 60 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl
15

5.0
80

—
40

5.0
—

2.5 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 8.3 4.2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 12 6.0
µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Time** tTLH 5.0 — — 15
tTHL 10 — — 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu
15

5.0
—

0
—

– 50
4

— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 0 – 15 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 0 – 8.0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Time th 5.0 180 75 — ns
10 90 25 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
* The formulas given are for the typical characteristics only at 25_C.
15 75 20

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
—

** When shift register sections are cascaded, the maximum rise and fall times of the clock input should be equal to or less than the rise and fall times
** of the data outputs driving data inputs, plus the propagation delay of the output driving stage for the output capacitance load.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

VDD = – VGS Vout VDD = VGS Vout

14 14

CLOCK Q4 CLOCK Q4
DP1 Q8 DP1 Q8
Q9 Q9
DP5 Q13 DP5 Q13
DP10 Q17 IOH DP10 Q17 IOL
DP14 Q18 DP14 Q18

7 VSS EXTERNAL VSS EXTERNAL

POWER POWER
SUPPLY SUPPLY

Figure 1. Typical Output Source Current Figure 2. Typical Output Sink Current
Characteristics Test Circuit Characteristics Test Circuit

MOTOROLA CMOS LOGIC DATA MC14006B

6–21
 VDD
14
PULSE
GENERATOR CLOCK Q4
DP1 Q8
Q9
DP5 Q13 CL CL
DP10 Q17 14
TEST 8 9
DP14 Q18
1/3 MC14000
PRESET 7
7 VSS CL CL CL CL OR EQUIV
50
ID
µF

1
f
CLOCK 50%

DATA

Figure 3. Power Dissipation Test Circuit and Waveforms

VDD

14

PULSE
CLOCK Q4
GENERATOR 1
DP1 Q8
Q9
DP5
Q13 CL
DP10 Q17 CL
PULSE CL
DP14 Q18
GENERATOR 2 CL
CL
7 VSS CL

20 ns 20 ns tWL tWH

90% VDD
CLOCK 50%
10% VSS
th “1” th “0”
tsu “1” tsu “0”
90% VDD
DATA 50%
10% VSS

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
4–STAGE 20 ns 20 ns tPLH tPHL

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
OUTPUT VOH
90%
Q4, Q8 50%
10% VOL
Q13, Q17 tTLH tTHL

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
tPHL
5–STAGE VOH

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
OUTPUT 90%
50%
Q9, Q18 10% VOL

ÉÉÉ
tTLH tTHL

ÉÉÉ
Output state can change since data previously clocked in might be in either state.

Figure 4. Switching Time Test Circuit and Waveforms

MC14006B MOTOROLA CMOS LOGIC DATA

6–22
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14007UB
Dual Complementary Pair
Plus Inverter L SUFFIX
CERAMIC
The MC14007UB multi–purpose device consists of three N–channel and CASE 632
three P–channel enhancement mode devices packaged to provide access to
each device. These versatile parts are useful in inverter circuits, pulse–
shapers, linear amplifiers, high input impedance amplifiers, threshold P SUFFIX
detectors, transmission gating, and functional gating. PLASTIC
CASE 646
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
D SUFFIX
Schottky TTL Load Over the Rated Temperature Range SOIC
• Pin–for–Pin Replacement for CD4007A or CD4007UB CASE 751A
• This device has 2 outputs without ESD Protection. Anti–static

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
precautions must be taken. ORDERING INFORMATION

ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXUBCP Plastic
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXUBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit MC14XXXUBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA
PIN ASSIGNMENT

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW D–PB 1 14 VDD
S–PB 2 13 D–PA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C
GATEB 3 12 OUTC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur. S–NB 4 11 S–PC
†Temperature Derating: D–NB 5 10 GATEC
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C GATEA 6 9 S–NC
VSS 7 8 D–NA
A A
D = DRAIN
12 9 S = SOURCE
B
1 B
2
C 3 SCHEMATIC
INPUT 14 13 2 1 11
VDD 5 4
14 C
11 6 12
13
INPUT OUTPUT CONDITION INPUT
6 8 10
1 A = C, B = OPEN
0 A = B, C = OPEN

7 VSS 7 8 3 4 5 10 9
Substrates of P–channel devices internally VDD = PIN 14
connected to VDD; substrates of N–channel VSS = PIN 7
devices internally connected to VSS.

Figure 1. Typical Application: 2–Input Analog Multiplexer

MOTOROLA CMOS LOGIC DATA MC14007UB

6–23
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.0

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.0

ÎÎÎÎ
—

ÎÎÎ
1.0
(VO = 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 13.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
2.0
2.5
—
—
4.50
6.75
2.0
2.5
—
—
2.0
2.5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 Vdc) “1” Level VIH 5.0 4.0 — 4.0 2.75 — 4.0 — Vdc
(VO = 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
8.0

ÎÎÎÎ
—

ÎÎÎ
8.0

ÎÎÎÎ
5.50

ÎÎÎ
—

ÎÎÎÎ
8.0

ÎÎÎ
—
(VO = 1.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 12.5 — 12.5 8.25 — 12.5 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 5.0 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 1.0 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.5 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 10 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 1.0 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.5 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 10 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Gate) (CL = 50 pF)
ÎÎÎ
IT 5.0
10
15
IT = (0.7 µA/kHz) f + IDD/6
IT = (1.4 µA/kHz) f + IDD/6
IT = (2.2 µA/kHz) f + IDD/6
µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14007UB MOTOROLA CMOS LOGIC DATA

6–24
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.2 ns/pF) CL + 30 ns 5.0 — 90 180
tTLH = (0.5 ns/pF) CL + 20 ns 10 — 45 90

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Output Fall Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tTLH = (0.4 ns/pF) CL + 15 ns

ÎÎÎÎÎÎÎ tTHL
15 — 35 70
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (1.2 ns/pF) CL + 15 ns 5.0 — 75 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.5 ns/pF) CL + 15 ns 10 — 40 80
tTHL = (0.4 ns/pF) CL + 10 ns 15 — 30 60

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Turn–Off Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tPLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (1.5 ns/pF) CL + 35 ns 5.0 — 60 125

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.2 ns/pF) CL + 20 ns 10 — 30 75
tPLH = (0.15 ns/pF) CL + 17.5 ns 15 — 25 55

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Turn–On Delay Time
tPHL = (1.0 ns/pF) CL + 10 ns 5.0 — 60 125

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.3 ns/pF) CL + 15 ns 10 — 30 75
tPHL = (0.2 ns/pF) CL + 15 ns 15 — 25 55
* The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD = – VGS VDD = VGS

14
IOH VDS = VOH – VDD 14
IOL VDS = VOL
7 VSS
7 VSS

All unused inputs connected to ground. All unused inputs connected to ground.

0 20
a VGS = 15 Vdc
b
c
c
IOL , DRAIN CURRENT (mAdc)
IOH , DRAIN CURRENT (mAdc)

– 4.0 16
VGS = – 5.0 Vdc b a
10 Vdc
– 8.0 a TA = – 55°C a 12
b TA = + 25°C b c
c TA = + 125°C a TA = – 55°C
c b
– 12 8.0 b TA = + 25°C
b c TA = + 125°C
c
– 10 Vdc a – 15 Vdc a
– 16 4.0
a b 5.0 Vdc
c
– 20 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 –0 0 2.0 4.0 6.0 8.0 10
VDS, DRAIN VOLTAGE (Vdc) VDS, DRAIN VOLTAGE (Vdc)

Figure 2. Typical Output Source Characteristics Figure 3. Typical Output Sink Characteristics

These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.

MOTOROLA CMOS LOGIC DATA MC14007UB

6–25
 VDD
20 ns 20 ns
0.01 µF VDD
90%
500 µF ID CERAMIC Vin 50%
10% VSS
14 tPHL tPLH
PULSE Vin VOH
Vout 90%
GENERATOR Vout 50%
7 VSS CL 10%
VOL
tTHL tTLH

Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms

APPLICATIONS

The MC14007UB dual pair plus inverter, which has access VDD
to all its elements offers a number of unique circuit applica- 14 OUT = A+B•C
tions. Figures 1, 5, and 6 are a few examples of the device
flexibility.
13
+ VDD 11 2
2
DISABLE 3
10 12 1
1 B OUTPUT
8
11

9 7
INPUT 10 12 OUTPUT 5
3
C
9 4
8
6
DISABLE 6 A
7
Substrates of P–channel devices internally connected to VDD;
Substrates of N–channel devices internally connected to VSS.
INPUT DISABLE OUTPUT
1 0 0 Figure 6. AOI Functions Using Tree Logic
0 0 1
X 1 OPEN
X = Don’t Care

Figure 5. 3–State Buffer

MC14007UB MOTOROLA CMOS LOGIC DATA

6–26
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14008B
4-Bit Full Adder
The MC14008B 4–bit full adder is constructed with MOS P–channel and L SUFFIX
CERAMIC
N–channel enhancement mode devices in a single monolithic structure. This
CASE 620
device consists of four full adders with fast internal look–ahead carry output.
It is useful in binary addition and other arithmetic applications. The fast
parallel carry output bit allows high–speed operation when used with other
adders in a system. P SUFFIX
PLASTIC
• Look–Ahead Carry Output CASE 648
• Diode Protection on All Inputs
• All Outputs Buffered
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
• Capable of Driving Two Low–power TTL Loads or One Low–power SOIC
Schottky TTL Load Over the Rated Temperature Range CASE 751B
• Pin–for–Pin Replacement for CD4008B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
± 10

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), mA
per Pin TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
(One Stage)
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Cin B A Cout S
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
0 0 0 0 0
TL Lead Temperature (8–Second Soldering) 260 _C 0 0 1 0 1
* Maximum Ratings are those values beyond which damage to the device may occur. 0 1 0 0 1
†Temperature Derating: 0 1 1 1 0
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 1 0 0 0 1
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 1 0 1 1 0
1 1 0 1 0
BLOCK DIAGRAM 1 1 1 1 1

HIGH–SPEED
14 Cout
PARALLEL CARRY PIN ASSIGNMENT

A4 1 16 VDD
B4 15 ADDER
13 S4 B3 2 15 B4
A4 1 4
A3 3 14 Cout
C4
B3 2 B2 4 13 S4
ADDER
12 S3
A3 3 3 A2 5 12 S3

C3 B1 6 11 S2
B2 4 ADDER A1 7 10 S1
11 S2
A2 5 2 VSS 8 9 Cin
C2
B1 6 ADDER
10 S1
A1 7 1
VDD = PIN 16
Cin 9 VSS = PIN 8

MOTOROLA CMOS LOGIC DATA MC14008B

6–27
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ
—

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ
—

ÎÎÎÎ
7.0

ÎÎÎ
—
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (1.7 µA/kHz) f + IDD
IT = (3.4 µA/kHz) f + IDD
IT = (5.0 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14008B MOTOROLA CMOS LOGIC DATA

6–28
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ
Propagation Delay Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎÎÎÎ tPLH, tPHL

15 — 40 80
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Sum in to Sum Out

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns 5.0 — 400 800
tPLH, tPHL = (0.66 ns/pF) CL + 127 ns 10 — 160 320

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 90 ns 15 — 115 230

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Sum In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns 5.0 — 305 610

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 112 ns 10 — 145 290

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns 15 — 110 220

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Carry In to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 290 ns 5.0 — 375 750

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 122 ns 10 — 155 310

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 90 ns 15 — 115 230
Carry In to Carry Out

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 85 ns 5.0 — 170 340

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 — 75 150
tPLH, tPHL = (0.5 ns/pF) CL + 30 ns —
15 55 110
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD = – VGS Vout VDD = VGS Vout

16 16

B4 S4 B4 S4
A4 A4
B3 S3 B3 S3
A3 A3
B2 S2 B2 S2
A2 A2
B1 S1 IOH B1 S1 IOL
A1 A1
Cin Cout Cin Cout
EXTERNAL EXTERNAL
8 VSS POWER 8 VSS POWER
SUPPLY SUPPLY

Figure 1. Typical Source Current Figure 2. Typical Sink Current

Characteristics Test Circuit Characteristics Test Circuit

MOTOROLA CMOS LOGIC DATA MC14008B

6–29
 VDD

16

B4 S4
A4
B3 S3
20 ns 20 ns A3
B2 S2
VDD A2
90% CL
Vin B1 S1
10% VSS CL
A1
PULSE CL
Cin Cout
GENERATOR CL
CL
8 VSS

500 µF IDD

Figure 3. Dynamic Power Dissipation Test Circuit and Waveform

VDD

16

B4 S4
A4
B3 S3
A3
B2 S2
A2
B1 S1 CL
A1 CL
PULSE CL
Cin Cout
GENERATOR CL
8 VSS CL

IDD

20 ns 20 ns
VDD
90%
Cin 50%
10% VSS
tPHL tPLH
90% VOH
S1 – S4 50%
10% VOL
tTHL tTLH
VOH
Cout 50%
VOL
tPLH tPHL

Figure 4. Switching Time Test Circuit and Waveforms

MC14008B MOTOROLA CMOS LOGIC DATA

6–30
 Cout

B4

S4
A4

B3

S3
A3

B2

S2
A2

B1

S1
A1

Cin

Figure 5. Logic Diagram

MOTOROLA CMOS LOGIC DATA MC14008B

6–31
 TYPICAL APPLICATION

WORD A + B INPUTS

A1 B4 A1 B4 A1 B4 A1 B4

CHIP CHIP CHIP CHIP

Cin Cout Cin Cout Cin Cout Cin Cout
1 2 3 4

S1 S4 S1 S4 S1 S4 S1 S4

SUM OUTPUTS

Calculation of 16–bit adder speed:

tP total = tP (Sum to Carry) + tP (Carry to Sum) + 2 tP (Carry to Carry)
The guaranteed 16–bit adder speed at 10 V, 25°C, CL = 50 pF is:
tp total = 290 + 310 + 300 = 900 ns

Figure 6. Using the MC14008B in a 16–Bit Adder Configuration

MC14008B MOTOROLA CMOS LOGIC DATA

6–32
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14013B
Dual Type D Flip-Flop
The MC14013B dual type D flip–flop is constructed with MOS P–channel L SUFFIX
CERAMIC
and N–channel enhancement mode devices in a single monolithic structure.
CASE 632
Each flip–flop has independent Data, (D), Direct Set, (S), Direct Reset, (R),
and Clock (C) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flip–flops for counter and
toggle applications. P SUFFIX
PLASTIC
• Static Operation CASE 646
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Flip–Flop Design D SUFFIX
Logic state is retained indefinitely with clock level either high or low; SOIC
information is transferred to the output only on the positive–going edge CASE 751A
of the clock pulse
• Capable of Driving Two Low–power TTL Loads or One Low–power ORDERING INFORMATION
Schottky TTL Load Over the Rated Temperature Range MC14XXXBCP Plastic
• Pin–for–Pin Replacement for CD4013B MC14XXXBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA 6
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
S
PD Power Dissipation, per Package† 500 mW 5 D Q 1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C 3 C
R
Q 2

4
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 8

S
9 D Q 13
TRUTH TABLE
Inputs Outputs
Clock† Data Reset Set Q Q 11 C Q 12
R
0 0 0 0 1
10
1 0 0 1 0
No VDD = PIN 14
X 0 0 Q Q VSS = PIN 7
Change
X X 1 0 0 1
X X 0 1 1 0
X X 1 1 1 1
X = Don’t Care
† = Level Change

MOTOROLA CMOS LOGIC DATA MC14013B

6–33
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ
—

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ
—

ÎÎÎÎ
7.0

ÎÎÎ
—
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 1.0 — 0.002 1.0 — 30 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 2.0 — 0.004 2.0 — 60
15 — 4.0 — 0.006 4.0 — 120

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (0.75 µA/kHz) f + IDD
IT = (1.5 µA/kHz) f + IDD
IT = (2.3 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated QA 1 14 VDD
voltages to this high-impedance circuit. For proper operation, Vin and QA 2 13 QB
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage CA 3 12 QB
level (e.g., either VSS or VDD). Unused outputs must be left open. RA 4 11 CB
DA 5 10 RB
SA 6 9 DB
VSS 7 8 SB

MC14013B MOTOROLA CMOS LOGIC DATA

6–34
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q, Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 — 175 350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 — 75 150

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 — 175 350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 — 75 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns 5.0 — 225 450

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns 10 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns 15 — 75 150
Setup Times** tsu ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
5.0

ÎÎÎÎ
40

ÎÎÎÎ
20

ÎÎÎÎ
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
10
15
20
15
10
7.5
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Times** th 5.0 40 20 — ns
10 20 10 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWL, tWH
15
5.0
15
250
7.5
125
—
— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50 —
15 70 35 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ fcl 5.0 — 4.0 2.0 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 10 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 14 7.0
µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Time tTLH 5.0 — — 15
tTHL 10 — — 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — — 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set and Reset Pulse Width tWL, tWH 5.0 250 125 — ns
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50
15 70 35 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Removal Times
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ trem ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set 5 80 0 —
10 45 5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15
5
35
50
5
– 35
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 30 – 10 —
15 25 –5 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.

LOGIC DIAGRAM
(1/2 of Device Shown)
S
C C Q

C C Q
C C

C C
C C
C
R

MOTOROLA CMOS LOGIC DATA MC14013B

6–35
 20 ns 20 ns
VDD
90%
D 50%
10% 20 ns 20 ns
tsu (L) VSS
tsu (H) 90% VDD
th 20 ns SET OR
VDD 50%
90% RESET 10%
C 50% VSS
10% tw trem
VSS 20 ns 20 ns
tWH tWL 90% VDD
CLOCK 50%
1 10%
VSS
fcl
tPLH tPHL tPLH tw
VOH tPHL
90%
Q 50% VOH
10% VOL Q OR Q 50%
VOL
tTLH tTHL

Inputs R and S low.

Figure 1. Dynamic Signal Waveforms Figure 2. Dynamic Signal Waveforms

(Data, Clock, and Output) (Set, Reset, Clock, and Output)

TYPICAL APPLICATIONS

n–STAGE SHIFT REGISTER

1 2 nth
D D Q D Q D Q Q

C Q C Q C Q

CLOCK

BINARY RIPPLE UP–COUNTER (Divide–by–2n)

1 2 nth
D Q D Q D Q Q

CLOCK C Q C Q C Q

T FLIP–FLOP

MODIFIED RING COUNTER (Divide–by–(n+1))

1 2 nth
D Q D Q D Q Q

C Q C Q C Q

CLOCK

MC14013B MOTOROLA CMOS LOGIC DATA

6–36
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14014B
MC14021B
8-Bit Static Shift Register
The MC14014B and MC14021B 8–bit static shift registers are constructed
with MOS P–channel and N–channel enhancement mode devices in a single
monolithic structure. These shift registers find primary use in parallel–to– L SUFFIX
serial data conversion, synchronous and asynchronous parallel input, serial CERAMIC
output data queueing; and other general purpose register applications CASE 620
requiring low power and/or high noise immunity.
• Synchronous Parallel Input/Serial Output (MC14014B)
P SUFFIX
• Asynchronous Parallel Input/Serial Output (MC14021B)
PLASTIC
• Synchronous Serial Input/Serial Output CASE 648
• Full Static Operation
• “Q” Outputs from Sixth, Seventh, and Eighth Stages
• Double Diode Input Protection D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
• Capable of Driving Two Low–power TTL Loads or One Low–power CASE 751B
Schottky TTL Load Over the Rated Temperature Range
ORDERING INFORMATION
• MC14014B Pin–for–Pin Replacement for CD4014B
MC14XXXBCP Plastic
• MC14021B Pin–for–Pin Replacement for CD4021B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCL Ceramic
MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V SERIAL OPERATION:

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA Q6 Q7 Q8
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
t Clock DS P/S t=n+6 t=n+7 t=n+8
PD Power Dissipation, per Package† 500 mW n 0 0 0 ? ?

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature – 65 to + 150 _C
n+1 1 0 1 0 ?

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
n+2 0 0 0 1 0
TL Lead Temperature (8–Second Soldering) 260 _C n+3 1 0 1 0 1
* Maximum Ratings are those values beyond which damage to the device may occur. X 0 Q6 Q7 Q8
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C PARALLEL OPERATION:
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Clock
MC14014B MC14021B DS P/S Pn *Qn
X X 1 0 0
X X 1 1 1
* Q6, Q7, & Q8 are available externally
LOGIC DIAGRAM X = Don’t Care

P1 P2 P3 P6 P7 P8
9 7 6 5 14 15 1
P/S

11
DS D Q D Q D Q D Q D Q D

C C C C Q C Q C Q

10
CLOCK

VDD = PIN 16 P4 = PIN 4

VSS = PIN 8 P5 = PIN 13 2 12 3
Q6 Q7 Q8

MOTOROLA CMOS LOGIC DATA MC14014B MC14021B

6–37
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ
—

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ
—

ÎÎÎÎ
7.0

ÎÎÎ
—
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 15 — 0.015 15 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (0.75 µA/kHz) f + IDD
IT = (1.50 µA/kHz) f + IDD
IT = (2.25 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0015.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
P8 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q6 2 15 P7
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Q8 3 14 P6
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. P4 4 13 P5
P3 5 12 Q7
P2 6 11 DS
P1 7 10 C
VSS 8 9 P/S

MC14014B MC14021B MOTOROLA CMOS LOGIC DATA

6–38
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time (Clock to Q, P/S to Q) tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL, tPLH = (1.7 ns/pF) CL + 315 ns tPHL 5.0 — 400 800
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns 10 — 170 340

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL, tPLH = (0.5 ns/pF) CL + 90 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 115 230

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tWH 5.0
10
400
175
150
75
—
—
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 135 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Frequency fcl 5.0 — 3.0 1.5 MHz
10 — 6.0 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parallel/Serial Control Pulse Width tWH
15

5.0
—

400
8.0

150
4.0

— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 175 75 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 135 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time tsu 5.0 200 100 — ns
P/S to Clock 10 100 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th
15

5.0
80

20
40

– 2.5
—

— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to P/S 10 20 – 10 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 25 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time tsu 5.0 350 150 — ns
Data (Parallel or Serial) to 10 80 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Clock or P/S

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th
15

5.0
60

45
30

0
—

— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Ds 10 35 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 35 5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Time th 5.0 50 25 — ns
Clock to Pn 10 45 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 45 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Clock Rise Time tr(cl) 5.0 — — 15 µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — — 5
15 — — 4
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD Vout VDD Vout

P/S Q6 P/S Q6
PULSE PULSE
C C
GENERATOR GENERATOR
P6 Q7 P6 Q7
P7 P7
P8 IOH P8 IOL
DS Q8 DS Q8

EXTERNAL EXTERNAL
POWER POWER
SUPPLY SUPPLY

Preset output under test to a logic “1” level.

Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit

MOTOROLA CMOS LOGIC DATA MC14014B MC14021B

6–39
 VDD

500 µF ID

0.01 µF
CERAMIC
P/S
PULSE
C Q6
GENERATOR 1
P1
P2 CL
P3
P4 Q7
P5
P6 CL
P7
PULSE P8 Q8
DS
GENERATOR 2
CL
VSS

1
f
CLOCK 50%

DATA

Figure 3. Power Dissipation Test Circuit and Waveform

SW 1
VDD
PULSE 1 VDD
GENERATOR 1 20 ns 20 ns
PARALLEL OR VDD
2 90%
P/S SERIAL DATA
50%
C Q6 INPUT 10% VSS
P1 tsu
2 2 P2
PULSE tWH tTHL
P3
GENERATOR 2 VDD
1 1 P4 Q7 CLOCK OR P/S 90%
P5 INPUT 50%
10% VSS
P6 CL tWH tWL
P7 tPLH tPHL
P8 Q8 VOH
DS Q 90%
OUTPUT 50%
SWITCH POSITION 1 = PARALLEL IN 10% VOL
SWITCH POSITION 2 = SERIAL IN VSS
SW 2
tTLH tTHL

tWL = tWH = 50% DUTY CYCLE

Figure 4. Switching Time Test Circuit and Waveforms

MC14014B MC14021B MOTOROLA CMOS LOGIC DATA

6–40
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14015B
Dual 4-Bit Static Shift Register
The MC14015B dual 4–bit static shift register is constructed with MOS L SUFFIX
CERAMIC
P–channel and N–channel enhancement mode devices in a single
CASE 620
monolithic structure. It consists of two identical, independent 4–state
serial–input/parallel–output registers. Each register has independent Clock
and Reset inputs with a single serial Data input. The register states are type
D master–slave flip–flops. Data is shifted from one stage to the next during P SUFFIX
the positive–going clock transition. Each register can be cleared when a high PLASTIC
CASE 648
level is applied on the Reset line. These complementary MOS shift registers
find primary use in buffer storage and serial–to–parallel conversion where
low power dissipation and/or noise immunity is desired.
D SUFFIX
• Diode Protection on All Inputs
SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 751B
• Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low; ORDERING INFORMATION
information is transferred to the output only on the positive going edge MC14XXXBCP Plastic
of the clock pulse. MC14XXXBCL Ceramic
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14XXXBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range. TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit
BLOCK DIAGRAM

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Q0 5
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V 7 D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Q1 4
lin, lout Input or Output Current (DC or Transient), ± 10 mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin Q2 3
9 C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW R Q3 10
_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150
6
TL Lead Temperature (8–Second Soldering) 260 _C
Q0 13
* Maximum Ratings are those values beyond which damage to the device may occur. 15 D
†Temperature Derating: Q1 12
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Q2 11
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 1 C
R Q3 2
TRUTH TABLE
14
C D R Q0 Qn VDD = PIN 16
0 0 0 Qn–1 VSS = PIN 8

1 0 1 Qn–1
X 0 No Change No Change
X X 1 0 0
X = Don’t Care
Qn = Q0, Q1, Q2, or Q3, as applicable.
Qn–1 = Output of prior stage.

MOTOROLA CMOS LOGIC DATA MC14015B

6–41
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or .05 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
Output Drive Current ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
– 1.6
– 4.2
—
—
– 1.3
– 3.4
– 2.25
– 8.8
—
—
– 0.9
– 2.4
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (1.2 µA/kHz)f + IDD
IT = (2.4 µA/kHz)f + IDD
IT = (3.6 µA/kHz)f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
CB 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q3B 2 15 DB
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Q2A 3 14 RB
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Q1A 4 13 Q0B
Q0A 5 12 Q1B
RA 6 11 Q2B
DA 7 10 Q3A
VSS 8 9 CA

MC14015B MOTOROLA CMOS LOGIC DATA

6–42
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock, Data to Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 225 ns 5.0 — 310 750

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 92 ns 10 — 125 250

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns 15 — 90 170
Reset to Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 375 ns 5.0 — 460 750

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns 10 — 180 250
tPLH, tPHL = (0.5 ns/pF) CL + 95 ns 15 — 120 170

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 400 185 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 175 85 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 135 55 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 2.0 1.5 MHz
10 — 6.0 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 7.5 3.75

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Times tTLH, tTHL 5.0 — — 15 µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — — 5
15 — — 4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWH 5.0 400 200 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 160 80 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 120 60 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time tsu 5.0 350 100 — ns
10 100 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 75 40 —
* The formulas given are for typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD
0.01 µF
PULSE 500 µF ID CERAMIC
GENERATOR VDD
2
D Q0
Q1 CL
PULSE Q2 CL
GENERATOR C Q3
CL
1 R CL

VSS

1
f
CLOCK 50%

DATA

Figure 1. Power Dissipation Test Circuit and Waveform

MOTOROLA CMOS LOGIC DATA MC14015B

6–43
 tTLH tTHL
DATA VDD
90%
INPUT 50%
10% 0V
tsu
VDD tTLH t– tTHL
PULSE
GENERATOR D 90% VDD
Q0 CLOCK
2 CL 50%
Q1 INPUT 10%
SYNC CL 0V
PULSE Q2 tWH tWL
C Q3 CL tPLH tPHL
GENERATOR
1 R CL
90%
VSS 50%
Q0 10%

tWL = tWH = 50% Duty Cycle

tTLH = tTHL ≤ 20 ns tTLH tTHL

Figure 2. Switching Test Circuit and Waveforms

VDD
PULSE
CLOCK VDD
GENERATOR D Q0 50%
2 CL INPUT 0V
Q1 tsu
SYNC CL
PULSE Q2
C Q3 CL th
GENERATOR
1 R CL DATA VDD
50%
VSS INPUT 0V

Figure 3. Setup and Hold Time Test Circuit and Waveforms

MC14015B MOTOROLA CMOS LOGIC DATA

6–44
 MOTOROLA CMOS LOGIC DATA

SINGLE BIT

VDD Q

RESET

CLOCK

DATA TO D OF
IN NEXT BIT

CIRCUIT SCHEMATICS
VSS

DATA INPUT BUFFER RESET INPUT BUFFER CLOCK INPUT BUFFER

VDD VDD
VDD

RESET CLOCK CLOCK

DATA DATA TO RESET
TO 4 BITS IN TO 4 BITS
IN FIRST BIT IN

VSS
MC14015B

VSS VSS
6–45
 LOGIC DIAGRAMS

SINGLE BIT

C C Q
TO D OF
DATA NEXT BIT

C C C C

C C
RESET

C
C
C

COMPLETE DEVICE

5 4 3 10
Q0 Q1 Q2 Q3

DATA INPUT BUFFER

D
7 D Q D Q D Q D Q

C Q C Q C Q C Q
CLOCK INPUT BUFFER R R R R
C
9
R
6
13 12 11 2
RESET INPUT BUFFER Q0 Q1 Q2 Q3

DATA INPUT BUFFER

D
15 D Q D Q D Q D Q

C Q C Q C Q C Q
CLOCK INPUT BUFFER R R R R
C
1
VDD = PIN 16
R VSS = PIN 8
14

RESET INPUT BUFFER

MC14015B MOTOROLA CMOS LOGIC DATA

6–46
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14016B

Quad Analog Switch/Quad

Multiplexer L SUFFIX
CERAMIC
The MC14016B quad bilateral switch is constructed with MOS P–channel CASE 632
and N–channel enhancement mode devices in a single monolithic structure.
Each MC14016B consists of four independent switches capable of
controlling either digital or analog signals. The quad bilateral switch is used P SUFFIX
in signal gating, chopper, modulator, demodulator and CMOS logic PLASTIC
implementation. CASE 646

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc
D SUFFIX
• Linearized Transfer Characteristics SOIC
• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical CASE 751A
• Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved
transfer characteristic design causes more parasitic coupling ORDERING INFORMATION
capacitance than CD4016) MC14XXXBCP Plastic
• For Lower RON, Use The HC4016 High–Speed CMOS Device or The MC14XXXBCL Ceramic
MC14066B MC14XXXBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• This Device Has Inputs and Outputs Which Do Not Have ESD TA = – 55° to 125°C for all packages.
Protection. Antistatic Precautions Must Be Taken.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VDD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
CONTROL 1
13
2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
1 OUT 1
lin Input Current (DC or Transient), ± 10 mA IN 1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Control Pin 5
CONTROL 2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Isw Switch Through Current ± 25 mA 3
4 OUT 2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW IN 2
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 6
CONTROL 3 9
TL Lead Temperature (8–Second Soldering) 260 _C OUT 3
8
* Maximum Ratings are those values beyond which damage to the device may occur. IN 3
†Temperature Derating: 12
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C CONTROL 4 10
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 11
OUT 4
IN 4
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must VDD = PIN 14
be taken to avoid applications of any voltage higher than maximum rated VSS = PIN 7
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage Control Switch
level (e.g., either VSS or VDD). Unused outputs must be left open.
0 = VSS Off
1 = VDD On
LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
OUT

CONTROL

LOGIC DIAGRAM RESTRICTIONS IN

VSS ≤ Vin ≤ VDD
VSS ≤ Vout ≤ VDD

MOTOROLA CMOS LOGIC DATA MC14016B

6–47
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Figure Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input Voltage

ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Control Input ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
1 VIL 5.0
10
—
—
—
—
—
—
1.5
1.5
0.9
0.9
—
—
—
—
Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — — — 1.5 0.9 — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH 5.0 — — 3.0 2.0 — — — Vdc
10 — — 8.0 6.0 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — — 13 11 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Control — Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance — Cin pF

ÎÎÎÎÎÎÎÎÎÎÎ
Control

ÎÎÎÎ
ÎÎÎ
ÎÎÎ
—

ÎÎÎ
—

ÎÎÎ
—

ÎÎÎ
—

ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎ
—

ÎÎÎ
—
Switch Input

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Switch Output
Feed Through
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
—
—
—
—
—
—
—
—
5.0
5.0
0.2
—
—
—
—
—
—
—
—
—

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Quiescent Current

ÎÎÎ
(Per Package) ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
2,3 IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
“ON” Resistance 4,5,6 RON — — Ohms
(VC = VDD, RL = 10 kΩ) — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 5.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = ± 0.25 Vdc)
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = – 5.0 Vdc) VSS = – 5.0 Vdc
5.0
—
—
—
600
600
600
—
—
—
300
300
280
660
660
660
—
—
—
840
840
840

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
(Vin = + 7.5 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = ± 0.25 Vdc)
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = – 7.5 Vdc) VSS = – 7.5 Vdc
—
—
360
360
—
—
240
240
400
400
—
—
520
520

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
7.5 — 360 — 180 400 — 520
(Vin = + 10 Vdc) — 600 — 260 660 — 840

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = + 5.6 Vdc) ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
(Vin = + 0.25 Vdc) VSS = 0 Vdc

ÎÎÎ
ÎÎÎ
10
—
—
600
600
—
—
310
310
660
660
—
—
840
840

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 15 Vdc) — 360 — 260 400 — 520
(Vin = + 0.25 Vdc) VSS = 0 Vdc — 360 — 260 400 — 520

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 9.3 Vdc) 15 — 360 — 300 400 — 520

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
∆ “ON” Resistance — ∆RON Ohms

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Between any 2 circuits in a common
package

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VC = VDD)
(Vin = ± 5.0 Vdc, VSS = – 5.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0 — — — 15 — — —
(Vin = ± 7.5 Vdc, VSS = – 7.5 Vdc) 7.5 — — — 10 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
(VC = VSS) ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Input/Output Leakage Current

ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
— —

± 0.1 ± 0.0015 ± 0.1 ± 1.0

µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 7.5, Vout = – 7.5 Vdc) 7.5 — — —
(Vin = – 7.5, Vout = + 7.5 Vdc) 7.5 — ± 0.1 — ± 0.0015 ± 0.1 — ± 1.0
NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** For voltage drops across the switch (∆V switch) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e., the
current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.

MC14016B MOTOROLA CMOS LOGIC DATA

6–48
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
Characteristic Figure Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time (VSS = 0 Vdc) 7 tPLH, 5.0 — 15 45 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
Vin to Vout tPHL 10 — 7.0 15
(VC = VDD, RL = 10 kΩ) 15 — 6.0 12

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Control to Output
v ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ 8 tPHZ, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
(Vin 10 Vdc, RL = 10 kΩ) tPLZ, 5.0 — 34 90
tPZH, 10 — 20 45

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎ
Crosstalk, Control to Output (VSS = 0 Vdc) 9
tPZL
—
15
5.0
—
—
15
30
35
— mV

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
(VC = VDD, Rin = 10 kΩ, Rout = 10 kΩ, 10 — 50 —
f = 1.0 kHz) 15 — 100 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Crosstalk between any two switches (VSS = 0 Vdc)

ÎÎÎ
— — 5.0 — – 80 — dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
(RL = 1.0 kΩ, f = 1.0 MHz,

+
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
V
crosstalk 20 log10 out1)
Vout2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Noise Voltage (VSS = 0 Vdc)
ÎÎÎÎÎÎÎ 10,11 — 5.0 — 24 — nV/√Cycle

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
(VC = VDD, f = 100 Hz) 10 — 25 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
15 — 30 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
(VC = VDD, f = 100 kHz) 5.0 — 12 —
10 — 12 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
15 — 15 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Second Harmonic Distortion (VSS = – 5.0 Vdc) — — 5.0 — 0.16 — %
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
RL = 10 kΩ, f = 1.0 kHz)
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Insertion Loss (VC = VDD, Vin = 1.77 Vdc, 12 — 5.0 dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
VSS = – 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)

+ V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
Iloss 20 log10 out) — 2.3 —
Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
(RL = 1.0 kΩ) — 0.2 —
(RL = 10 kΩ) — 0.1 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
(RL = 100 kΩ) — 0.05 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
(RL = 1.0 MΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
Bandwidth (– 3.0 dB) 12,13 BW 5.0 MHz
(VC = VDD, Vin = 1.77 Vdc, VSS = – 5.0 Vdc,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
RMS centered @ 0.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
(RL = 1.0 kΩ)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
—

ÎÎÎÎ
54 —
(RL = 10 kΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(RL = 100 kΩ)
(RL = 1.0 MΩ)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
—
—
—
40
38
37
—
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
OFF Channel Feedthrough Attenuation — — 5.0 kHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VSS = – 5.0 Vdc)
+
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
(VC = VSS, 20 log10

ÎÎÎÎ
Vout
Vin ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
–50 dB)
— 1250 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
(RL = 1.0 kΩ)
— 140 —
(RL = 10 kΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
— 18 —
(RL = 100 kΩ)
— 2.0 —
(RL = 1.0 MΩ)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

PIN ASSIGNMENT

IN 1 1 14 VDD
OUT 1 2 13 CONTROL 1
OUT 2 3 12 CONTROL 4
IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3

MOTOROLA CMOS LOGIC DATA MC14016B

6–49
 VC IS

Vin Vout

VIL: VC is raised from VSS until VC = VIL.

VIL: at VC = VIL: IS = ±10 µA with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.

Figure 1. Input Voltage Test Circuit

10,000
VDD = 15 Vdc 10 Vdc

PD , POWER DISSIPATION (µW)

VDD TA = 25°C
5.0 Vdc
1000

ID
100

VDD Vout
TO ALL
10 k 10
PULSE 4 CIRCUITS CONTROL
GENERATOR INPUT
fc

VSS Vin 1.0

PD = VDD x ID 5.0 k 10 k 100 k 1.0 M 10 M 50 M
fc, FREQUENCY (Hz)

Figure 2. Quiescent Power Dissipation Figure 3. Typical Power Dissipation per Circuit
Test Circuit (1/4 of device shown)

TYPICAL RON versus INPUT VOLTAGE

700 700
RL = 10 kΩ VSS = 0 Vdc
600 TA = 25°C 600 RL = 10 kΩ
R ON, “ON” RESISTANCE (OHMS)

R ON, “ON” RESISTANCE (OHMS)

TA = 25°C
500 500

400 VC = VDD = 5.0 Vdc 400

VSS = – 5.0 Vdc VC = VDD = 10 Vdc
300 300

200 200 VC = VDD = 15 Vdc

VC = VDD = 7.5 Vdc
100 VSS = – 7.5 Vdc 100

0 0
– 10 – 8.0 – 4.0 0 4.0 8.0 10 0 2.0 6.0 10 14 18 20
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 4. VSS = – 5.0 V and – 7.5 V Figure 5. VSS = 0 V

MC14016B MOTOROLA CMOS LOGIC DATA

6–50
 Vout

RL CL

Vin

Vout 20 ns 20 ns
RL VDD
Vin 90%
VC 50% 10%
VSS
tPLH tPHL

Vout 50%
Vin

Figure 6. RON Characteristics Figure 7. Propagation Delay Test Circuit

Test Circuit and Waveforms

Vout
VC RL CL

Vin VX
20 ns
VDD Vout
90%
VC 50%
10% VC 10 k 15 pF
VSS
tPZH tPHZ
Vin = VDD
90% Vx = VSS
Vout 10% Vin
tPZL tPLZ
90% 1k
Vout Vin = VSS
10%
Vx = VDD

Figure 8. Turn–On Delay Time Test Circuit Figure 9. Crosstalk Test Circuit
and Waveforms

35

30
VDD = 15 Vdc
NOISE VOLTAGE (nV/ CYCLE)

25
10 Vdc
20
5.0 Vdc
15
OUT QUAN–TECH 10
MODEL
VC = VDD
2283
5.0
IN OR EQUIV
0
10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz)

Figure 10. Noise Voltage Test Circuit Figure 11. Typical Noise Characteristics

MOTOROLA CMOS LOGIC DATA MC14016B

6–51
 2.0
RL = 1 MΩ AND 100 kΩ
TYPICAL INSERTION LOSS (dB) 0
10 kΩ
– 2.0
1.0 kΩ
– 4.0 – 3.0 dB (RL = 1.0 MΩ )
Vout
– 6.0 – 3.0 dB (RL = 10 kΩ ) RL
VC
– 3.0 dB (RL = 1.0 kΩ )
– 8.0

– 10 + 2.5 Vdc
Vin 0.0 Vdc
– 12 – 2.5 Vdc
10 k 100 k 1.0 M 10 M 100 M
fin, INPUT FREQUENCY (Hz)

Figure 12. Typical Insertion Loss/Bandwidth Figure 13. Frequency Response Test Circuit
Characteristics

ON SWITCH

CONTROL
SECTION
OF IC

LOAD
V

SOURCE

Figure 14. ∆V Across Switch

MC14016B MOTOROLA CMOS LOGIC DATA

6–52
 APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Switch. The 0–to–5 V
Digital Control signal is used to directly control a 5 V p–p ana-
log signal.
The digital control logic levels are determined by V DD and
V SS. The V DD voltage is the logic high voltage; the V SS volt-
age is logic low. For the example, V DD = + 5 V logic high at
the control inputs; V SS = GND = 0 V logic low.
The maximum analog signal level is determined by VDD
and V SS. The analog voltage must not swing higher than
V DD or lower than V SS.
The example shows a 5 V p–p signal which allows no
margin at either peak. If voltage transients above V DD and/or
below V SS are anticipated on the analog channels, external
diodes (Dx) are recommended as shown in Figure B. These
diodes should be small signal types able to absorb the
maximum anticipated current surges during clipping.
The absolute maximum potential difference between V DD
and VSS is 18.0 V. Most parameters are specified up to 15 V
which is the recommended maximum difference between
V DD and V SS.

+5 V

VDD VSS
+ 5.0 V

+5 V 5 Vp–p SWITCH
ANALOG SIGNAL IN
SWITCH 5 Vp–p
+ 2.5 V
OUT ANALOG SIGNAL
EXTERNAL
CMOS 0–TO–5 V DIGITAL
GND
DIGITAL CONTROL SIGNALS MC14016B
CIRCUITRY

Figure A. Application Example

VDD VDD

Dx Dx

SWITCH SWITCH
IN OUT
Dx Dx

VSS VSS

Figure B. External Germanium or Schottky Clipping Diodes

MOTOROLA CMOS LOGIC DATA MC14016B

6–53
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14017B
Decade Counter
The MC14017B is a five–stage Johnson decade counter with built–in code L SUFFIX
CERAMIC
converter. High speed operation and spike–free outputs are obtained by use
CASE 620
of a Johnson decade counter design. The ten decoded outputs are normally
low, and go high only at their appropriate decimal time period. The output
changes occur on the positive–going edge of the clock pulse. This part can
be used in frequency division applications as well as decade counter or P SUFFIX
decimal decode display applications. PLASTIC
CASE 648
• Fully Static Operation
• DC Clock Input Circuit Allows Slow Rise Times
• Carry Out Output for Cascading D SUFFIX
• Divide–by–N Counting SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 751B
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range ORDERING INFORMATION
• Pin–for–Pin Replacement for CD4017B MC14XXXBCP Plastic
MC14XXXBCL Ceramic
• Triple Diode Protection on All Inputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
FUNCTIONAL TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V (Positive Logic)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA Clock Decode
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Clock Enable Reset Output=n

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW 0 X 0 n
X 1 0 n
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150
X X 1 Q0
TL Lead Temperature (8–Second Soldering) 260 _C 0 0 n+1
* Maximum Ratings are those values beyond which damage to the device may occur. X 0 n
†Temperature Derating: X 0 n
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 1 0 n+1
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C X = Don’t Care. If n < 5 Carry = “1”,
Otherwise = “0”.
LOGIC DIAGRAM

Q5 Q1 Q7 Q3 Q9
1 2 6 7 11 BLOCK DIAGRAM

CLOCK 14 Q0 3
14 Q1 2
CLOCK Q2 4
CLOCK 12 Q3 7
ENABLE 13 C Q C Q C Q C Q C Q
CARRY
C C C C C Q4 10
D Q D Q D Q D Q D Q CLOCK
R R R R R R R R R R 13 Q5 1
15 ENABLE
RESET Q6 5
Q7 6
Q8 9
Q9 11
RESET 15 Cout 12

VDD = PIN 16
3 5 4 9 10 VSS = PIN 8
Q0 Q6 Q2 Q3 Q4

MC14017B MOTOROLA CMOS LOGIC DATA

6–54
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.27 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.55 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (0.83 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0011.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
Q5 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q1 2 15 RESET
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Q0 3 14 CLOCK
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Q2 4 13 CE
Q6 5 12 Cout
Q7 6 11 Q9
Q3 7 10 Q4
VSS 8 9 Q8

MOTOROLA CMOS LOGIC DATA MC14017B

6–55
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Decode Output tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns

ÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/PF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
5.0
10
15
—
—
—
500
230
175
1000
460
350

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Cout
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 142 ns
tPHL
5.0
10
—
—
400
175
800
350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ
Propagation Delay Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 100 ns

ÎÎÎÎÎÎÎ tPLH,
15 — 125 250
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Decode Output tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns 5.0 — 500 1000

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns 10 — 230 460

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns 15 — 175 350

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Turn–Off Delay Time tPLH ns
Reset to Cout

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (1.7 ns/pF) CL + 315 ns 5.0 — 400 800

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.66 ns/pF) CL + 142 ns 10 — 175 350
tPLH = (0.5 ns/pF) CL + 100 ns 15 — 125 250

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tw(H) 5.0 250 125 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 75 35 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Frequency fcl 5.0 — 5.0 2.0 MHz
10 — 12 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 16 6.7

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tw(H) 5.0 500 250 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 250 125 —
15 190 95 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Reset Removal Time
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ trem 5.0 750 375 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 275 135 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15 210 105 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Clock Input Rise and Fall Time tTLH, 5.0 —
tTHL 10 No Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Enable Setup Time tsu 5.0 350 175 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 150 75 —
15 115 52 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Clock Enable Removal Time
ÎÎÎÎÎÎÎÎÎÎÎ trem 5.0 420 260 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 200 100 —
15 140 70 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14017B MOTOROLA CMOS LOGIC DATA

6–56
 VDD

Vout Output Output

VSS CLOCK Q0
Sink Drive Source Drive
ENABLE
Q1
Clock to
Q2 Decode desired
Q3 (S1 to A)
Outputs outputs
A Q4 (S1 to B)
VDD S1 ID
RESET Q5 Clock to 5
B Q6
VSS S1 Carry thru 9 S1 to A
Q7 (S1 to B)
Q8
VGS = VDD – VDD
Q9 EXTERNAL
CLOCK Cout POWER VDS = Vout Vout – VDD
SUPPLY
VSS

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit

VDD

0.01 µF
500 µF ID
CERAMIC

Q0
Q1
CLOCK Q2
ENABLE Q3
Q4
RESET Q5
Q6
PULSE fc Q7
CLOCK Q8
GENERATOR
Q9
Cout
VSS CL CL CL CL CL CL CL CL CL CL CL

Figure 2. Typical Power Dissipation Test Circuit

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are se-
quential within each stage and from stage to stage, with no dead time (except propagation delay).

RESET RESET RESET

CLOCK CLOCK CLOCK
CE MC14017B CE MC14017B CE MC14017B
Q0 Q1 • • • Q8 Q9 Q0Q1 • • • Q8 Q9 Q1 • • • Q8 Q9

8 DECODED
9 DECODED 8 DECODED
OUTPUTS
OUTPUTS OUTPUTS

CLOCK
FIRST STAGE INTERMEDIATE STAGES LAST STAGE

Figure 3. Counter Expansion

MOTOROLA CMOS LOGIC DATA MC14017B

6–57
 Pcp Ncp 90% VDD
CLOCK 50%
10% VSS
trem tsu 20 ns 20 ns
CLOCK VDD
ENABLE VSS
trem 20 ns 20 ns 20 ns
RESET VDD
20 ns VSS
tPHL tPLH tPLH
Q0 VOH
tTLH VOL
tPLH tPHL
90% VOH
10% 50%
Q1 VOL
tPLH tPHL tTLH tTHL
VOH
Q2 VOL
tPLH tPHL tTLH tTHL
VOH
50%
Q3 VOL
tPLH tPHL tTLH tTHL
VOH
Q4 tTHL VOL
tPLH tPHL tTLH
tPHL
VOH
Q5 VOL
tPLH tPHL tTLH tTHL
90% VOH
Q6 10% VOL
tTHL tTHL
tPLH tPHL VOH
Q7 VOL
tTHL
tPLH VOH
Q8 VOL
tTLH tTHL
tPLH tPHL
VOH
Q9 VOL
tPHL tTLH tTHL tPHL
Cout tPLH VOH
VOL
tTHL
tTLH

Figure 4. AC Measurement Definition and Functional Waveforms

MC14017B MOTOROLA CMOS LOGIC DATA

6–58
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14018B
Presettable Divide-By-N
Counter L SUFFIX
CERAMIC
The MC14018B contains five Johnson counter stages which are CASE 620
asynchronously presettable and resettable. The counters are synchronous,
and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input. Data on P SUFFIX
the Jam inputs will then be transferred to their respective Q outputs PLASTIC
(inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic CASE 648
1 state.
Division by any number from 2 to 10 can be accomplished by connecting
appropriate Q outputs to the data input, as shown in the Function Selection D SUFFIX
table. Anti–lock gating is included in the MC14018B to assure proper SOIC
counting sequence. CASE 751B

• Fully Static Operation

ORDERING INFORMATION
• Schmitt Trigger on Clock Input
MC14XXXBCP Plastic
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14XXXBCL Ceramic
Schottky TTL Load Over the Rated Temperature Range MC14XXXBD SOIC
• Pin–for–Pin Replacement for CD4018B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit
FUNCTIONAL TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Preset Jam
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Clock Reset Enable Input Qn

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA 0 0 X Qn

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin 0 0 X Dn*
X 0 1 0 1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW
X 0 1 1 0
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 X 1 X X 1
TL Lead Temperature (8–Second Soldering) 260 _C * Dn is the Data input for that stage. Stage 1
has Data brought out to Pin 1.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C PIN ASSIGNMENT

Din 1 16 VDD
JAM 1 2 15 R
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must JAM 2 3 14 C
be taken to avoid applications of any voltage higher than maximum rated
Q2 4 13 Q5
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Q1 5 12 JAM 5
Unused inputs must always be tied to an appropriate logic voltage
Q3 6 11 Q4
level (e.g., either VSS or VDD). Unused outputs must be left open.
JAM 3 7 10 PE
VSS 8 9 JAM 4

MOTOROLA CMOS LOGIC DATA MC14018B

6–59
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ
—

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ
—

ÎÎÎÎ
7.0

ÎÎÎ
—
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (0.3 µA/kHz) f + IDD
IT = (0.7 µA/kHz) f + IDD
IT = (1.0 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14018B MOTOROLA CMOS LOGIC DATA

6–60
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ All Types

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tTLH, tTHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns 10 — 50 100
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q tPHL
tPLH, tPHL = (0.90 ns/pF) CL + 265 ns 5.0 — 310 620

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 102 ns 10 — 120 240

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 72 ns 15 — 85 170

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Q ns
tPLH = (0.90 ns/pF) CL + 325 ns 5.0 — 370 740

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.36 ns/pF) CL + 132 ns
ÎÎÎ 10 — 150 300

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.26 ns/pF) CL + 81 ns 15 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Preset Enable to Q ns
tPLH, tPHL = (0.90 ns/pF) CL + 325 ns 5.0 — 370 740

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 132 ns 10 — 150 300

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 81 ns 15 — 100 200

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time tsu ns
Data (Pin 1) to Clock 5.0 200 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 0 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 80 0 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Jam Inputs to Preset Enable 5.0 200 0 — ns
10 100 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 80 0 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data (Jam Inputs)–to–Preset th 5.0 540 270 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Enable Hold Time 10 500 250 —
15 480 240 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 400 200 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 200 100 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 160 80 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset or Preset Enable tWH 5.0 290 145 — ns
Pulse Width 10 130 65 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 110 55 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Clock Rise and Fall Time tTLH, tTHL 5.0 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
10 No Limit
15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 2.5 1.25 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 6.5 3.25
15 — 8.0 4.0
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns
VDD
90%
ANY INPUT 50%
10% VSS

tPLH tPHL

VOH
90%
ANY OUTPUT 50%
10% VOL
tTLH tTHL

Figure 1. Switching Time Waveforms

MOTOROLA CMOS LOGIC DATA MC14018B

6–61
 1
CLOCK
0
1
RESET
0
1
PRESET ENABLE
0
1
JAM 1
0
JAM 2 1
0
1
TIMING DIAGRAM JAM 3 DON’T CARE
UNTIL PRESET ENABLE 0
(Q5 Connected to Data Input) 1
GOES HIGH
JAM 4 0
1
JAM 5 0
1
Q1
0
1
Q2
0
1
Q3
0
1
Q4 0
1
Q5
0

FUNCTION SELECTION
Connect
Counter Data Input
Mode (Pin 1) to: Comments
Divide by 10 Q5
Divide by 8 Q4
No external
Divide by 6 Q3
components needed.
Divide by 4 Q2
Divide by 2 Q1
Divide by 9 Q5 • Q4 Gate package needed LOGIC DIAGRAM
Divide by 7 Q4 • Q3 to provide AND
Divide by 5 Q3 • Q2 function. Counter
JAM 1 JAM 2 JAM 3 JAM 4 JAM 5
Divide by 3 Q2 • Q1 Skips all 1’s state 2 3 7 9 12

CLOCK
CLOCK 14
SHAPER
S S S S S
DATA 1 D Q D Q D Q D Q D Q
C C C C C
Q
R P R P R P R P R P
RESET 15

PRESET ENABLE 10

VDD = PIN 16
VSS = PIN 8
5 4 6 11 13

Q1 Q2 Q3 Q4 Q5

MC14018B MOTOROLA CMOS LOGIC DATA

6–62
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14020B
14-Bit Binary Counter
The MC14020B 14–stage binary counter is constructed with MOS L SUFFIX
CERAMIC
P–channel and N–channel enhancement mode devices in a single
CASE 620
monolithic structure. This part is designed with an input wave shaping circuit
and 14 stages of ripple–carry binary counter. The device advances the count
on the negative–going edge of the clock pulse. Applications include time
delay circuits, counter controls, and frequency–dividing circuits. P SUFFIX
PLASTIC
• Fully Static Operation CASE 648
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power D SUFFIX
Schottky TTL Load Over the Rated Temperature Range SOIC
• Buffered Outputs Available from stages 1 and 4 thru 14 CASE 751B
• Common Reset Line

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Pin–for–Pin Replacement for CD4020B ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎÎÎÎÎÎÎ
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
lin, lout
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Input or Output Current (DC or Transient),

ÎÎÎ
per Pin
± 10 mA

Clock
TRUTH TABLE
Reset Output State

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
PD Power Dissipation, per Package† 500 mW 0 No Change

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Î ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C 0 Advance to Next State
X 1 All Outputs are Low

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
X = Don’t Care
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

LOGIC DIAGRAM

Q1 Q4 Q5 Q12 Q13 Q14

9 7 5 1 2 3

CLOCK
10 C Q C Q C Q C Q C Q C Q

C Q C Q C Q C Q C Q C
R R R R R R

RESET
11

Q6 = PIN 4 Q9 = PIN 12 VDD = PIN 16

Q7 = PIN 6 Q10 = PIN 14 VSS = PIN 8
Q8 = PIN 13 Q11 = PIN 15

MOTOROLA CMOS LOGIC DATA MC14020B

6–63
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.42 µA/kHz)f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.85 µA/kHz)f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (1.43 µA/kHz)f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must Q12 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q13 2 15 Q11
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Q14 3 14 Q10
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Q6 4 13 Q8
Q5 5 12 Q9
Q7 6 11 R
Q4 7 10 C
VSS 8 9 Q1

MC14020B MOTOROLA CMOS LOGIC DATA

6–64
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns
tPHL

ÎÎÎÎ
Clock to Q1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPHL, tPLH = (1.7 ns/pF) CL + 175 ns

ÎÎÎÎÎÎÎ
tPHL, tPLH = (0.66 ns/pF) CL + 82 ns
tPHL, tPLH = (0.5 ns/pF) CL + 55 ns
5.0
10
15
—
—
—
260
115
80
520
230
160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q14
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tPHL, tPLH – (1.7 ns/pF) CL + 1735 ns

ÎÎÎ
tPHL, tPLH = (0.66 ns/pF) CL + 772 ns
tPHL, tPLH = (0.5 ns/pF) CL + 535 ns
5.0
10
15
—
—
—
1820
805
560
3900
1725
1200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Qn

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tPHL = (1.7 ns/pF) CL + 285 ns
tPHL = (0.66 ns/pF) CL + 122 ns
ÎÎÎ
ÎÎÎ
5.0
10
—
—
370
155
740
310

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.5 ns/pF) CL + 90 ns 15 — 115 230

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 500 140 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 165 55 —
15 125 38 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ fcl 5.0 — 2.0 1.0 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 6.0 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15 — 8.0 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Clock Rise and Fall Time tTLH, tTHL 5.0 —
10 No Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWL 5.0 3000 320 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 550 120 —
15 420 80 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Removal Time trem 5.0 130 65 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 50 25 —
15 30 15 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD VDD

0.01 µF
500 µF ID CERAMIC PULSE
C Q1
GENERATOR
Q4
Qn CL
PULSE R
C Q1 CL
GENERATOR CL
Q4 VSS
Qn CL
R
CL
CL 20 ns 20 ns
VSS
CLOCK 90%
50%
10%
20 ns 20 ns
VDD tWH
90% tPLH tPHL
CLOCK 50%
10% VSS Q 90%
50%
50% DUTY CYCLE 10%
tTLH tTHL

Figure 1. Power Dissipation Test Circuit Figure 2. Switching Time Test Circuit
and Waveform and Waveforms

MOTOROLA CMOS LOGIC DATA MC14020B

6–65
 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16,384
CLOCK
RESET

Q1
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14

Figure 3. Timing Diagram

MC14020B MOTOROLA CMOS LOGIC DATA

6–66
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14022B
Octal Counter
The MC14022B is a four–stage Johnson octal counter with built–in code L SUFFIX
CERAMIC
converter. High–speed operation and spike–free outputs are obtained by
CASE 620
use of a Johnson octal counter design. The eight decoded outputs are
normally low, and go high only at their appropriate octal time period. The
output changes occur on the positive–going edge of the clock pulse. This
part can be used in frequency division applications as well as octal counter P SUFFIX
or octal decode display applications. PLASTIC
CASE 648
• Fully Static Operation
• DC Clock Input Circuit Allows Slow Rise Times
• Carry Out Output for Cascading D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
• Capable of Driving Two Low–power TTL Loads or One Low–power CASE 751B
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4022B ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Triple Diode Protection on All Inputs MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VDD

ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
FUNCTIONAL TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA (Positive Logic)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
per Pin
Clock

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW Clock Enable Reset Output=n

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C 0 X 0 n
X 1 0 n

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
0 0 n+1
* Maximum Ratings are those values beyond which damage to the device may occur. X 0 n
†Temperature Derating: 1 0 n+1
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C X 0 n
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C X X 1 Q0
X = Don’t Care. If n < 4 Carry = 1,
LOGIC DIAGRAM Otherwise = 0.

11 1 5 7
Q4 Q1 Q6 Q3
BLOCK DIAGRAM
CLOCK
14 Q0 2
CLOCK 14
CARRY Q1 1
13
CLOCK C Q C Q C Q C Q Q2 3
VDD 12
ENABLE C C C C Q3 7
D RQ D RQ D RQ D RQ
CLOCK
13 Q4 11
VSS ENABLE
Q5 4
15
Q6 5
RESET
Q7 10
RESET 15 Cout 12
VDD = PIN 16
VSS = PIN 8

NC = PIN 6, 9
Q0 Q5 Q2 Q7
2 4 3 10

MOTOROLA CMOS LOGIC DATA MC14022B

6–67
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.28 µA/kHz)f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.56 µA/kHz)f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (0.85 µA/kHz)f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.00125.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
Q1 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q0 2 15 R
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Q2 3 14 C
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Q5 4 13 CE
Q6 5 12 Cout
NC 6 11 Q4
Q3 7 10 Q7
VSS 8 9 NC

NC = NO CONNECTION

MC14022B MOTOROLA CMOS LOGIC DATA

6–68
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Decode Output tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns

ÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
5.0
10
15
—
—
—
500
230
175
1000
460
350

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Cout
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 142 ns
tPHL
5.0
10
—
—
400
175
800
350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ
Propagation Delay Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 100 ns

ÎÎÎÎÎÎÎ tPLH,
15 — 125 250
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Decode Output tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns 5.0 — 275 1000

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns 10 — 125 460

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns 15 — 95 350

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Turn–Off Delay Time tPLH ns
Reset to Cout

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (1.7 ns/pF) CL + 315 ns 5.0 — 400 800

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.66 ns/pF) CL + 142 ns 10 — 175 350
tPLH = (0.5 ns/pF) CL + 100 ns 15 — 125 250

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 250 125 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 75 35 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Frequency fcl 5.0 — 5.0 2.0 MHz
10 — 12 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 16 6.7

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWH 5.0 500 250 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 250 125 —
15 190 95 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Reset Removal Time
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ trem 5.0 750 375 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 275 135 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15 210 105 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Clock Input Rise and Fall Time tTLH, tTHL 5.0 —
10 No Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Enable Setup Time tsu 5.0 350 175 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 150 75 —
15 115 52 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Clock Enable Removal Time
ÎÎÎÎÎÎÎÎÎÎÎ trem 5.0 420 260 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 200 100 —
15 140 70 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14022B

6–69
 VDD

Output Output
Vout Sink Drive Source Drive
CLOCK Q0
VSS
ENABLE Q1 Clock to desired
VDD A Q2 Output
Q3 Outputs (S1 to A) (S1 to B)
RESET Q4 Clock to Q5
S1 Q5 ID Carry thru Q7 S1 to A
VSS B
Q6 (S1 to B)
Q7 VGS = VDD – VDD
CLOCK C
out
VDS = Vout Vout – VDD
EXTERNAL
VSS POWER
SUPPLY

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit

VDD

0.01 µF
500 µF ID
CERAMIC

Q0
Q1
CLOCK Q2
ENABLE
Q3
Q4
RESET Q5
Q6
PULSE fc Q7
CLOCK Cout
GENERATOR

VSS CL CL CL CL CL CL CL CL CL

Figure 2. Typical Power Dissipation Test Circuit

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are se-
quential within each stage and from stage to stage, with no dead time (except propagation delay).

R R R
C C C
CE MC14022B CE MC14022B CE MC14022B
Q0 Q1 • • • Q6 Q7 Q0 Q1 • • • Q6 Q7 Q1 • • • Q6 Q7

6 DECODED
7 DECODED 6 DECODED
OUTPUTS
OUTPUTS OUTPUTS

CLOCK
FIRST STAGE INTERMEDIATE STAGES LAST STAGE

Figure 3. Counter Expansion

MC14022B MOTOROLA CMOS LOGIC DATA

6–70
 tWH
tWL 90% V
50% DD
CLOCK 10% VSS
trel tsu 20 ns
20 ns
CLOCK VDD
ENABLE VSS
trem 20 ns 20 ns 20 ns
RESET VDD
VSS
tPHL tPLH tPLH
Q0 VOH
50%
VOL
tPLH tPHL tTHL
90% 50% VOH
Q1 10% VOL
tPLH tPHL tTLH
VOH
Q2 VOL
tPLH tPHL tTLH
VOH
Q3 VOL
tPLH tPHL tTLH
VOH
Q4 VOL
tPLH tPHL tTLH tPHL
VOH
Q5 VOL
tTLH tTHL tTLH tTHL
tPLH tPHL
VOH
Q6 VOL
tPLH tPHL
VOH
Q7 VOL
tPHL tTLH tTHL tPLH
Cout tPHL VOH
VOL
tTLH tTHL

Figure 4. AC Measurement Definition and Functional Waveforms

MOTOROLA CMOS LOGIC DATA MC14022B

6–71
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14024B
7-Stage Ripple Counter
The MC14024B is a 7–stage ripple counter with short propagation delays L SUFFIX
CERAMIC
and high maximum clock rates. The Reset input has standard noise
CASE 632
immunity, however the Clock input has increased noise immunity due to
Hysteresis. The output of each counter stage is buffered.
• Diode Protection on All Inputs
P SUFFIX
• Output Transitions Occur on the Falling Edge of the Clock Pulse PLASTIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 646
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4024B D SUFFIX

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
SOIC
CASE 751A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V MC14XXXBD SOIC
± 10

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), mA TA = – 55° to 125°C for all packages.
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C PIN ASSIGNMENT

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C
CLOCK
RESET
1
2
14
13
VDD
NC
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Q7 3 12 Q1
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
Q6 4 11 Q2
Q5 5 10 NC
LOGIC DIAGRAM Q4 6 9 Q3

1 VSS 7 8 NC
CLOCK C Q C Q C Q C Q
VDD = PIN 14
VSS = PIN 7
NC = NO CONNECTION
R Q R Q R Q R Q
2
RESET

12 11 4 3
Q1 Q2 Q6 Q7

Q3 = PIN 9
Q4 = PIN 6
Q5 = PIN 5

MC14024B MOTOROLA CMOS LOGIC DATA

6–72
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ
—

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ
—

ÎÎÎÎ
7.0

ÎÎÎ
—
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (0.31 µA/kHz) f + IDD
IT = (0.60 µA/kHz) f + IDD
IT = (1.89 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14024B

6–73
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q1
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 295 ns
tPLH, tPHL = (0.66 ns/pF) CL + 117 ns
tPHL
5.0
10
—
—
380
150
600
230

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns 15 — 110 175

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q7
tPLH, tPHL = (1.7 ns/pF) CL + 915 ns 5.0 — 1000 2000

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 367 ns 10 — 400 750

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 275 ns 15 — 300 565
Reset to Qn

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns 5.0 — 500 800

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 217 ns 10 — 250 400
tPLH, tPHL = (0.5 ns/pF) CL + 155 ns 15 — 180 300

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 500 200 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 165 60 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 125 40 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWH 5.0 600 375 — ns
10 350 200 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 260 150 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Removal Time trem 5.0 625 250 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
10

ÎÎÎÎ
190

ÎÎÎÎ
75

ÎÎÎÎ
—

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Input Rise and Fall Time ÎÎÎ
ÎÎÎÎÎÎÎ tTLH, tTHL
15
5.0
145
—
50
—
—
1.0 s

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — — 8.0 ms
15 — — 200 µs

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Input Pulse Frequency

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ fcl 5.0 — 2.5 1.0 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
* The formulas given are for the typical characteristics only at 25_C.
10
15
—
—
8.0
12
3.0
4.0

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

TRUTH TABLE
Clock Reset State
0 0 No Change
0 1 All Outputs Low
1 0 No Change
1 1 All Outputs Low
0 No Change
1 All Outputs Low
0 Advance One Count
1 All Outputs Low

MC14024B MOTOROLA CMOS LOGIC DATA

6–74
 VDD VOL = Vout VDD VOH = Vout
VDD

C Qn C Qn
R IOH R IOL

EXTERNAL EXTERNAL
COUNT Qn TO A VSS POWER VSS POWER
LOGIC “1” LEVEL. SUPPLY SUPPLY

Figure 1. Typical Output Source Figure 2. Typical Output Sink

Characteristics Test Circuit Characteristics Test Circuit

VDD

0.01 µF
500 µF ID CERAMIC

PULSE f
C Q1
GENERATOR CL
Q2
CL
Q3
CL
Q4
CL
Q5
CL
Q6
CL
R Q7
CL
VSS

Figure 3. Power Dissipation Test Circuit

MOTOROLA CMOS LOGIC DATA MC14024B

6–75
6–76
MC14024B

t WL
t WH
VDD
1 50% 2 4 8 16 32 64 128 255
CLOCK (1) VSS
t rem
RESET (2) VDD
50%
VSS
t PLH1 t PHL1 t R1
90% VOH
50%
Q1 (12) 10% VOL
Figure 4. Functional Waveforms

t TLH t PHL2 t THL t R2

t PLH2
VOH
90%
50%
Q2 (11) 10% VOL
t TLH t PHL3 t THL t R3
t PLH3
VOH
50%
Q3 (9) VOL
t TLH t PHL4 t THL t R4
t PLH4 VOH
50%
Q4 (6) VOL
t TLH t PHL5 t THL t R5
t PLH5 VOH
50%
Q5 (5) t PHL6 VOL
t TLH t THL t R6
t PLH6
90% VOH
50%
MOTOROLA CMOS LOGIC DATA

10%
Q6 (4) VOL
t TLH t PHL7 t THL t R7
t PLH7 VOH

Q7 (3) VOL
t TLH t THL

Input t TLH and t THL = 20 ns

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14027B
Dual J-K Flip-Flop
The MC14027B dual J–K flip–flop has independent J, K, Clock (C), Set (S)
and Reset (R) inputs for each flip–flop. These devices may be used in L SUFFIX
control, register, or toggle functions. CERAMIC
CASE 620
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout P SUFFIX
• Logic Edge–Clocked Flip–Flop Design — PLASTIC
Logic state is retained indefinitely with clock level either high or low; CASE 648
information is transferred to the output only on the positive–going edge
of the clock pulse
• Capable of Driving Two Low–power TTL Loads or One Low–power D SUFFIX

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range SOIC
• Pin–for–Pin Replacement for CD4027B CASE 751B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCP Plastic
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBD SOIC
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
lin, lout Input or Output Current (DC or Transient), ± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW
BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C 7
* Maximum Ratings are those values beyond which damage to the device may occur. S
†Temperature Derating: 6 J Q 1
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 3 C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
5 K Q 2
TRUTH TABLE R
Inputs Outputs* 4
C† J K S R Qn‡ Qn+1 Qn+1
1 X 0 0 0 1 0 9

X 0 0 0 1 1 0 S
10 J Q 15
0 X 0 0 0 0 1
13 C
X 1 0 0 1 0 1
11 K Q 14
1 1 0 0 Qo Qo Qo R
X X 0 0 X Qn Qn No
Change 12
X X X 1 0 X 1 0
VDD = PIN 16
X X X 0 1 X 0 1
VSS = PIN 8
X X X 1 1 X 1 1
X = Don’t Care ‡ = Present State
† = Level Change * = Next State

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA MC14027B

6–77
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ
—

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ
—

ÎÎÎÎ
7.0

ÎÎÎ
—
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 1.0 — 0.002 1.0 — 30 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 2.0 — 0.004 2.0 — 60
15 — 4.0 — 0.006 4.0 — 120

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (0.8 µA/kHz) f + IDD
IT = (1.6 µA/kHz) f + IDD
IT = (2.4 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT

QA 1 16 VDD
QA 2 15 QB
CA 3 14 QB
RA 4 13 CB
KA 5 12 RB
JA 6 11 KB
SA 7 10 JB
VSS 8 9 SB

MC14027B MOTOROLA CMOS LOGIC DATA

6–78
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Times**

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q, Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPHL
5.0
10
—
—
175
75
350
150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set to Q, Q
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 — 175 350
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 — 75 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Q, Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns 5.0 — 350 450
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns 10 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns 15 — 75 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Times
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu 5.0 140 70 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 50 25 —
15 35 17 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Times
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th 5.0 140 70 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
10
15
50
35
25
17
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH, tWL 5.0 330 165 — ns
10 110 55 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 75 38 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 3.0 1.5 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 9.0 4.5
15 — 13 6.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 — — 15 µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — — 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — — 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Removal Times trem ns
5 90 10 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set 10 45 5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 35 3 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5 50 – 30 —
Reset 10 25 – 15 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 20 – 10 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set and Reset Pulse Width tWH 5.0 250 125 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50 —
15 70 35 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14027B

6–79
 20 ns 20 ns
VDD
90%
J 50%
10% VSS
20 ns 20 ns
VDD
K 90%
tsu 50%
10% VSS
tsu th
20 ns 20 ns
90% VDD
C 50%
10% VSS 20 ns 20 ns
tWH tWL 90% VDD
1 SET OR 50%
fcl RESET 10% VSS
tPLH tPHL tw trem
VOH 20 ns 20 ns
90% VDD
Q 50% 90%
CLOCK 50%
10% VOL 10% VSS
tTLH tTHL tw
tPLH
tPHL
Inputs R and S low. VOH
For the measurement of tWH, I/fcl, and PD Q or Q 50%
the Inputs J and K are kept high. VOL

Figure 1. Dynamic Signal Waveforms Figure 2. Dynamic Signal Waveforms

(J, K, Clock, and Output) (Set, Reset, Clock, and Output)

LOGIC DIAGRAM
(1/2 of Device Shown)

S
Q
C

J
C
C

C
K C C

C C
R
Q

C
C C

MC14027B MOTOROLA CMOS LOGIC DATA

6–80
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14028B
BCD-To-Decimal Decoder
Binary-To-Octal Decoder L SUFFIX
CERAMIC
The MC14028B decoder is constructed so that an 8421 BCD code on the CASE 620
four inputs provides a decimal (one–of–ten) decoded output, while a 3–bit
binary input provides a decoded octal (one–of–eight) code output with D
forced to a logic “0”. Expanded decoding such as binary–to–hexadecimal P SUFFIX
(one–of–16), etc., can be achieved by using other MC14028B devices. The PLASTIC
part is useful for code conversion, address decoding, memory selection CASE 648
control, demultiplexing, or readout decoding.
• Diode Protection on All Inputs
D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
SOIC
• Capable of Driving Two Low–power TTL Loads or One Low–power CASE 751B
Schottky TTL Load Over the Rated Temperature Range
• Positive Logic Design ORDERING INFORMATION
• Low Outputs on All Illegal Input Combinations MC14XXXBCP Plastic
• Similar to CD4028B. MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
± 10

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
PD

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C TRUTH TABLE
D C B A Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 0 0 0 0 0 0 1
BLOCK DIAGRAM 0 0 0 1 0 0 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 0 0 0 1 0 0
0 0 1 1 0 0 0 0 0 0 1 0 0 0
10 A Q0 3
0 1 0 0 0 0 0 0 0 1 0 0 0 0
Q1 14
0 1 0 1 0 0 0 0 1 0 0 0 0 0
3–BIT Q2 2 0 1 1 0 0 0 0 1 0 0 0 0 0 0
BINARY 13 B Q3 15 OCTAL
8421 0 1 1 1 0 0 1 0 0 0 0 0 0 0
INPUTS Q4 1 DECODED DECIMAL
BCD OUTPUTS 1 0 0 0 0 1 0 0 0 0 0 0 0 0
Q5 6 DECODED
INPUTS 1 0 0 1 1 0 0 0 0 0 0 0 0 0
OUTPUTS
12 C Q6 7 1 0 1 0 0 0 0 0 0 0 0 0 0 0
Q7 4 1 0 1 1 0 0 0 0 0 0 0 0 0 0
Q8 9 1 1 0 0 0 0 0 0 0 0 0 0 0 0
11 D Q9 5 1 1 0 1 0 0 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0
VDD = PIN 16
VSS = PIN 8

MOTOROLA CMOS LOGIC DATA MC14028B

6–81
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL
5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD VOH 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5

ÎÎÎ
VIL
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—

ÎÎÎ
VIH
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IOH 5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ IOL
5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.3 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (0.9 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must Q4 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q2 2 15 Q3
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Q0 3 14 Q1
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Q7 4 13 B
Q9 5 12 C
Q5 6 11 D
Q6 7 10 A
VSS 8 9 Q8

MC14028B MOTOROLA CMOS LOGIC DATA

6–82
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎÎ
ÎÎÎ tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPHL 5.0 — 300 600
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 260

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
* The formulas given are for the typical characteristics only at 25_C.
15 — 90

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
180

20 ns 20 ns
Inputs B, C, and D VDD All outputs connected
switching in respect 90% to respective CL loads.
INPUT A 50%
to a BCD code. f in respect to a system
10%
VSS clock.
1/f

20 ns 20 ns
VDD
INPUT C 90%
50%
10%
VSS
Inputs A, B, and D low. tPLH tPHL

VOH
90%
Q4 50%
10%
VOL
tTLH tTHL

Figure 1. Dynamic Signal Waveforms

MOTOROLA CMOS LOGIC DATA MC14028B

6–83
 LOGIC DIAGRAM

Q0

Q1
A
Q2

Q3
B
Q4

Q5
C
Q6

Q7
D
Q8

Q9

APPLICATIONS INFORMATION
INPUTS
Expanded decoding can be performed by using the
MC14028B and other CMOS Integrated Circuits. The circuit D C B A
in Figure 2 converts any 4–bit code to a decimal or hexadeci-
mal code. The accompanying table shows the input binary
combinations, the associated “output numbers” that go “high”
when selected, and the “redefined output numbers” needed D C B A D C B A
for the proper code. For example: For the combination DCBA
MC14028B MC14028B
= 0111 the output number 7 is redefined for the 4–bit binary,
Q9 Q0 Q9 Q0
4–bit gray, excess–3, or excess–3 gray codes as 7, 5, 4, or 2,
respectively. Figure 3 shows a 6–bit binary 1–of–64 decoder
using nine MC14028B circuits and two MC14069UB in- 15 –8 15 –0
verters.
OUTPUT NUMBERS
The MC14028B can be used in decimal digit displays,
such as, neon readouts or incandescent projection indicators
Figure 2. Code Conversion Circuit and Truth Table
as shown in Figure 4.

Code and Redefined

Output Numbers
Hexadecimal Excess–3 Decimal

Inputs Output Numbers Excess–3

Binary

Aiken
4–Bit

4–Bit
Gray

Gray

4221
D C B A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 3 0 2 2
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 2 0 3 3
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 4 7 1 4 4
0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 5 6 2 3
0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 6 4 3 1 4
0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 7 5 4 2
1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 8 15 5
1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 9 14 6 5
1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 10 12 7 9 6
1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 11 13 8 5
1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 12 8 9 5 6
1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 13 9 6 7 7
1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 11 8 8 8
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 10 7 9 9

MC14028B MOTOROLA CMOS LOGIC DATA

6–84
 INPUTS

A B C D E F INHIBIT
(NO SELECTION)
A B C –D
MC14028B
Q0 Q9

A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
MC14028B MC14028B MC14028B MC14028B MC14028B MC14028B MC14028B MC14028B
Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9

0 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63
*1/6 MC14069UB 64 OUTPUTS (SELECTED OUTPUT IS HIGH)

Figure 3. Six–Bit Binary 1–of–64 Decoder

APPROPRIATE APPROPRIATE
Q0 VOLTAGE VOLTAGE
A Q1 NEON INCANDESCENT
Q2 DISPLAY DISPLAY
B Q3
Q4 OR
MC14028B Q5
C Q6
Q7 0
Q8 9 9 2 1 0
D Q9

Figure 4. Decimal Digit Display Application

MOTOROLA CMOS LOGIC DATA MC14028B

6–85
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14029B

Binary/Decade Up/Down
Counter L SUFFIX
CERAMIC
The MC14029B Binary/Decade up/down counter is constructed with MOS CASE 620
P–channel and N–channel enhancement mode devices in a single
monolithic structure. The counter consists of type D flip–flop stages with a
gating structure to provide toggle flip–flop capability. The counter can be P SUFFIX
used in either Binary or BCD operation. This complementary MOS counter PLASTIC
finds primary use in up/down and difference counting and frequency CASE 648
synthesizer applications where low power dissipation and/or high noise
immunity is desired. It is also useful in A/D and D/A conversion and for
magnitude and sign generation. D SUFFIX
SOIC
• Diode Protection on All Inputs
CASE 751B
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Internally Synchronous for High Speed ORDERING INFORMATION
• Logic Edge–Clocked Design — Count Occurs on Positive Going Edge MC14XXXBCP Plastic
of Clock MC14XXXBCL Ceramic
• Asynchronous Preset Enable Operation MC14XXXBD SOIC
• Capable of Driving Two Low–power TTL Loads or One Low–power TA = – 55° to 125°C for all packages.
Schottky TTL Load Over the Rated Temperature Range
• Pin for Pin Replacement for CD4029B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PIN ASSIGNMENT

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit PE 1 16 VDD

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Q3 2 15 CLK
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
P3 3 14 Q2
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
P0 4 13 P2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA
per Pin Cin 5 12 P1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C
Q0
Cout
6
7
11
10
Q1
U/D

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
_C VSS 8 9 B/D

†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

TRUTH TABLE
Preset
Carry In Up/Down Enable Action
1 X 0 No Count
0 1 0 Count Up
0 0 0 Count Down
X X 1 Preset
X = Don’t Care

MC14029B MOTOROLA CMOS LOGIC DATA

6–86
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.58 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.20 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (1.70 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14029B

6–87
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ All Types

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH,
tTHL 5.0 — 100 200
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clk to Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns 5.0 — 200 400

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clk to Cout tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎÎ
5.0

ÎÎÎÎ
—

ÎÎÎÎ
250

ÎÎÎÎ
500

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns

ÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
10
15
—
—
130
85
260
190

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin to Cout tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 95 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎÎ
5.0

ÎÎÎÎ
—

ÎÎÎÎ
175

ÎÎÎÎ
360

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 47 ns

ÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns
10
15
—
—
50
50
120
100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
PE to Q tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎÎ
5.0

ÎÎÎÎ
—

ÎÎÎÎ
235

ÎÎÎÎ
470

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns

ÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
10
15
—
—
100
80
200
160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
PE to Cout tPLH, ns
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL 5.0 — 320 640
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns 10 — 145 290

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns 15 — 105 210

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tW(cl) 5.0 180 90 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 80 40 —
15 60 30 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 4.0 2.0 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 8.0 4.0
15 — 10 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Preset Removal Time

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
The Preset Signal must be low prior to a positive–going
trem 5.0
10
160
80
80
40
—
—
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
transition of the clock. 15 60 30 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Rise and Fall Time tr(cl) 5.0 — — 15 µs
tf(cl) 10 — — 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Carry In Setup Time tsu
15
5.0
—
150
—
75
4
— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 60 30 —
15 40 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Up/Down Setup Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
5.0
10
340
140
170
70
—
—
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 100 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Binary/Decade Setup Time 5.0 320 160 — ns
10 140 70 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 100 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Preset Enable Pulse Width tW 5.0 130 65 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 70 35 —
15 50 25 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14029B MOTOROLA CMOS LOGIC DATA

6–88
 VDD

500 pF ID 0.01 µF
CERAMIC

PE Q0
Cin
B/D Q1
PULSE U/D
CLK Q2
GENERATOR CL
P0
P1 Q3 CL
P2 CL
P3 Cout CL
CL

20 ns 20 ns
VDD
50% 90%
CLK 10%
VSS
VARIABLE
WIDTH

Figure 1. Power Dissipation Test Circuit and Waveform

VDD

PE Q0
PROGRAMMABLE Cin
PULSE B/D Q1
GENERATOR U/D
CLK Q2
P0 CL
P1 Q3 CL
P2 CL
P3 Cout CL
CL
VSS

tW
tsu trem
CARRY IN OR 1/fcl
VDD
UP/DOWN 50%
OR BINARY/DECADE VSS
VDD
CLOCK 50%
VSS
tW VDD
PRESET ENABLE
VSS
20 ns
Cout ONLY tTLH
VOH
Q0 OR CARRY OUT 90% 10% 90%
10% VOL
tPLH
tTHL tPHL tPLH

Figure 2. Switching Time Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14029B

6–89
 TIMING DIAGRAM

CLOCK

CARRY IN
UP/DOWN
BINARY/DECADE
PE

P0
P1
P2
P3

Q0
Q1
Q2
Q3

CARRY OUT
COUNT 0 1 2 3 4 5 6 7 8 9 8 7 6 5 4 3 2 1 0 0 9 6 7 0

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
Cout MC14029B Cin Cout Cin Cout MC14029B Cin
U/D U/D MC14029B U/D
MSD LSD
B/D PE B/D PE B/D PE OUTPUT
P3 P2 P1 P0 CLK P3 P2 P1 P0 CLK P3 P2 P1 P0 CLK

VDD VDD VDD VDD

“1” “2” “3”
INPUT
CLOCK

CLOCK

Cout 1 (LSD)

Cout 2

Cout 3 (MSD)

PE
123
122
121
120

101

100

123
122
119

99

10
11

COUNT
9

1
0

* tW ^ 900 ns @ VDD = 5 V
Figure 3. Divide by N BCD Down Counter and Timing Diagram
(Shown for N = 123)

MC14029B MOTOROLA CMOS LOGIC DATA

6–90
 MOTOROLA CMOS LOGIC DATA

9 4 P0 12 P1 13 P2 3 P3
BINARY/DECADE

1
PRESET ENABLE

LOGIC DIAGRAM
5 PE P0 PE P1 PE P2 PE P3
CARRY IN TE Q0 TE Q1 TE Q2 TE Q3
7

CLK Q0 CLK Q1 CLK Q2 CLK Q3 CARRY OUT

10
UP/DOWN

15
CLOCK

6 Q0 1 Q1 14 Q2 2 Q3
MC14029B
6–91
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14032B
MC14038B
Triple Serial Adders
The MC14032B and MC14038B triple serial adders have the clock and
carry reset inputs common to all three adders. The carry is added on the
L SUFFIX
positive–going clock transition for the MC14032B, and on the negative–
CERAMIC
going clock transition for the MC14038B. Typical applications include serial CASE 620
arithmetic units, digital correlators, digital servo control systems, datalink
computers, and flight control computers.
• Buffered Outputs P SUFFIX
• Single–Phase Clocking PLASTIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 648
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range. D SUFFIX
• Pin–for–Pin Replacement for CD4032B and CD4038B. SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
ORDERING INFORMATION
CASE 751B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit
MC14XXXBCP Plastic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
± 10

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C
BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
A1 10
TL Lead Temperature (8–Second Soldering) 260 _C B1 11
ADDER 1 9 S1
* Maximum Ratings are those values beyond which damage to the device may occur. INVERT 1 7
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C A2 13
B2 12
ADDER 2 4 S2
This device contains protection circuitry to guard against damage INVERT 2 5
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated VDD = PIN 16
voltages to this high-impedance circuit. For proper operation, Vin and VSS = PIN 8
A3 15
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. B3 14
ADDER 3 1 S3
Unused inputs must always be tied to an appropriate logic voltage INVERT 3 2
level (e.g., either VSS or VDD). Unused outputs must be left open. CLOCK 3
CARRY RESET 6
LOGIC DIAGRAMS
MC14032B (ONE SECTION AND COMMON INPUTS SHOWN) MC14038B
A A
B S B S

D Q D Q

CR CR

INVERT INVERT
CARRY D Q CARRY D Q
RESET RESET
C TO C TO
NEXT NEXT
CLOCK CLOCK
STAGE STAGE

MC14032B MC14038B MOTOROLA CMOS LOGIC DATA

6–92
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.96 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.93 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (2.80 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.

PIN ASSIGNMENT

S3 1 16 VDD
INV 3 2 15 A3
C 3 14 B3
S2 4 13 A2
INV 2 5 12 B2
CARRY
RESET 6 11 B1
INV 1 7 10 A1
VSS 8 9 S1

MOTOROLA CMOS LOGIC DATA MC14032B MC14038B

6–93
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns
A, B or Invert to Sum tPHL

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
5.0
10
15
—
—
—
280
120
90
1400
300
230

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Sum

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns

ÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns
tPLH, tPHL = (0.5 ns/pF) CL + 110 ns
5.0
10
15
—
—
—
500
180
135
2400
600
450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Setup Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu 5.0 10 – 10 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
10
15
10
10
0
0
—
—

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 4.0 1.0 MHz
10 — 10 2.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 12 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Rise and Fall Times tTHL, tTLH 5.0 — — 15 µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — — 5
15 — — 4
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

TIMING DIAGRAMS

MC14032B MC14038B

WORD 1 + WORD 2 WORD 3 + WORD 4 WORD 1 + WORD 2 WORD 3 + WORD 4

A A
B B
C C
INV INV
CR CR
S S

TRUE SUM COMPLEMENTED TRUE SUM COMPLEMENTED

SUM SUM
WORD 1: 0.0111100 = + 60 WORD 3: 1.1011011 = – 37 WORD 1: 1.1000011 = – 61 WORD 3: 0.0100100 = + 36
WORD 2: 0.0110010 = + 50 WORD 4: 1.1001110 = – 50 WORD 2: 1.1001101 = – 51 WORD 4: 0.0110001 = + 49
0.1101110 = + 110 1.0101001 = – 87 1.0010000 = – 112 0.1010101 = + 85

NOTE: Unused input pins must be connected to either VDD or VSS.

MC14032B MC14038B MOTOROLA CMOS LOGIC DATA

6–94
 VDS = VOH – VDD VDS = VOL

VDD = – VGS VOH VDD = VGS VOL

VDD VDD

A1 S1 A1 S1
B1 B1
INV1 INV1
A2 A2
B2 B2
INV2 S2 INV2 S2
A3 A3
B3 B3
INV3 IOH INV3 IOL
CLOCK CLOCK
CR S3 CR S3

EXTERNAL EXTERNAL
VSS VSS
POWER POWER
SUPPLY SUPPLY

Figure 1. Typical Output Source Test Circuit Figure 2. Typical Output Sink Test Circuit

VDD

0.01 µF
500 pF ID
CERAMIC

VDD

A1 S1
B1 20 ns 20 ns
INV1
A2 VDD
PROGRAMMABLE 90%
B2 CLOCK 50%
PULSE INV2 S2 10% VSS
GENERATOR CL VARIABLE
A3
WIDTH
B3 VDD
90%
INV3
CL A,B
CLOCK 10% VSS
CR S3 tTHL tTLH
CL
VSS

Figure 3. Power Dissipation Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14032B MC14038B

6–95
 VDD

A1 S1
B1
INV1
PROGRAMMABLE A2
B2
PULSE
INV2 S2
GENERATOR CL
A3
B3
INV3 CL
CLOCK
CR S3

VSS CL

MC14032B

VDD
A 50%
VSS

VDD
B 50%
VSS
tsu
VDD
CLOCK 50%
VSS
tPLH tPHL tPLH tPHL
VOH
90%
SUM 50%
10% VOL
tTLH tTHL

MC14038B
A
VDD
50%
VSS
B
VDD
50%
VSS
tsu
CLOCK
VDD
50%
VSS
tPHL tPLH tPHL tPLH
SUM
90% VOH
50%
10% VOL
tTHL tTLH

Figure 4. Switching Time Test Circuit and Waveforms

MC14032B MC14038B MOTOROLA CMOS LOGIC DATA

6–96
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14034B
8-Bit Universal Bus Register
The MC14034B is a bidirectional 8–bit static parallel/serial, input/output L SUFFIX
CERAMIC
bus register. The device contains two sets of input/output lines which allows
CASE 623
the bidirectional transfer of data between two buses; the conversion of serial
data to parallel form, or the conversion of parallel data to serial form.
Additionally the serial data input allows data to be entered shift/right, while
shift/left can be accomplished by hard–wiring each parallel output to the P SUFFIX
previous parallel bit input. PLASTIC
CASE 709
Other useful applications for this device include pseudo–random code
generation, sample and hold register, frequency and phase–comparator,
address or buffer register, and serial/parallel input/output conversions.
DW SUFFIX
• Bidirectional Parallel Data Input
SOIC
• Diode Protection on All Inputs CASE 751E
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power ORDERING INFORMATION
Schottky TTL Load Over the Rated Temperature Range. MC14XXXBCP Plastic
• Pin–for–Pin Replacement for CD4034B. MC14XXXBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBDW SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
PIN ASSIGNMENT

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA B8 1 24 VDD

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin B7 2 23 A8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW B6 3 22 A7
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 B5 4 21 A6
TL Lead Temperature (8–Second Soldering) 260 _C B4 5 20 A5
* Maximum Ratings are those values beyond which damage to the device may occur. B3 6 19 A4
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C B2 7 18 A3
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C B1 8 17 A2
A ENABLE 9 16 A1
DS 10 15 C
This device contains protection circuitry to guard against damage
A/B 11 14 A/S
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated VSS 12 13 P/S
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA MC14034B

6–97
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 1.2

ÎÎÎÎ
—

ÎÎÎ
– 1.0

ÎÎÎÎ
– 1.7

ÎÎÎ
—

ÎÎÎÎ
– 0.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.25
– 0.62
– 1.8
—
—
—
– 0.2
– 0.5
– 1.5
– 0.36
– 0.9
– 3.5
—
—
—
– 0.14
– 0.35
– 1.1
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.010
0.020
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.030 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (2.2 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (4.4 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (6.6 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
3–State Output Leakage Current
ÎÎÎ ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 —
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
± 3.0 µAdc

** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

MC14034B MOTOROLA CMOS LOGIC DATA

6–98
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time A or B tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.5 ns/pF) CL + 15 ns
ÎÎÎ 10 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time A or B tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns
A (B) Synchronous Parallel Data Input, tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
B (A) Parallel Data Output

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 440 ns 5.0 — 525 1050
tPHL, tPHL = (0.66 ns/pF) CL + 172 ns 10 — 205 410

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 120 ns 15 — 145 290

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns
A (B) Asynchronous Parallel Data Input tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
B (A) Parallel Data Output

ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 420 ns 5.0 — 505 1010
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns 10 — 180 360

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 105 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH
15
5.0
—
340
130
170
260
— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 140 70 —
15 110 55 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 2.5 1.2 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 6.0 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 8.0 4.0
µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise tTLH, tTHL 5.0 — — 15
10 — — 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — — 4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
A, B Input Setup Time tsu 5.0 100 35 — ns
10 45 15 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
High Level SE, P/S, A/S Pulse Width tWH
15
5.0
35
600
12
200
—
— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 270 90 —
15 200 80 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

TRUTH TABLE
“A” Enable P/S A/B A/S Mode Operation†
0 0 0 X Serial Synchronous Serial data input, A and B Parallel data outputs disabled.
0 0 1 X Serial Synchronous Serial data input, B–Parallel data output.
0 1 0 0 Parallel B Synchronous Parallel data inputs, A–Parallel data outputs disabled.
0 1 0 1 Parallel B Asynchronous Parallel data inputs, A–Parallel data outputs disabled.
0 1 1 0 Parallel A–Parallel data inputs disabled, B–Parallel data outputs.
0 1 1 1 Parallel A–Parallel data inputs disabled, B–Parallel data outputs.
1 0 0 X Serial Synchronous serial data input, A–Parallel data output.
1 0 1 X Serial Synchronous serial data input, B–Parallel data output.
1 1 0 0 Parallel B–Synchronous Parallel data input, A–Parallel data output.
1 1 0 1 Parallel B–Asynchronous Parallel data input, A–Parallel data output.
1 1 1 0 Parallel A–Synchronous Parallel data input, B–Parallel data output.
1 1 1 1 Parallel A–Asynchronous Parallel data input, B–Parallel data output.
X = Don’t Care
†Outputs change at positive transition of clock in the serial mode and when the A/S input is low in the parallel mode. During transfer from parallel
to serial operation, A/S should remain low in order to prevent DS transfer into flip–flops.

MOTOROLA CMOS LOGIC DATA MC14034B

6–99
 EXPANDED BLOCK DIAGRAM

DATA
A1 A2 A3 A4 A5 A6 A7 A8
SERIAL DATA INPUT
ENABLE A
A/B
CONTROL
PARALLEL/SERIAL P/S 8–BIT REGISTER
LOGIC
ASYN/SYN A/S
CLOCK

B1 B2 B3 B4 B5 B6 B7 B8
DATA

OPERATING CHARACTERISTICS

The MC14034B is composed of eight register cells con-
nected in cascade with additional control logic. Each register
cell is composed of one “D” master–slave flip–flop with sepa-
rate internal clocks, and two data transfer gates allowing the
data to be transferred bi–directionally from bus A to bus B
and from bus B to bus A, and to be memorized. Besides the
single phase clock and the serial data inputs, the control log-
ic provides four other features:
A Enable Input — When high, this input enables the bus A
data lines.
A/B Input (Data A or B) — This input controls the direc-
tion of data flow: when high, the data flows from bus A to bus
B; when low, the data flows from bus B to bus A.
P/S Input (Parallel/Serial) — This input controls the data
input mode (parallel or serial). When high, the data is trans-
ferred to the register in a parallel asynchronous mode or a
parallel synchronous mode (positive clock transition). When
low, the data is entered into the register in a serial synchro-
nous mode (positive clock transition).
A/S Input (Asynchronous/Synchronous to the Clock)
— When this input is high, the data is transferred indepen-
dently from the clock rate; when low, the clock is enabled and
the data is transferred synchronously.

LOGIC DIAGRAM

A1 A2 A3 A4 A5 A6 A7 A8
16 17 18 19 20 21 22 23

VDD VDD
A ENABLE 9
*D
FLIP–
FLOP
A/B 11 *D FLIP FLOP 6 STAGES
SERIAL DATA 10 (SAME AS D Q
CM CS
PARALLEL SERIAL 13 STAGE 1)
CM CS

VDD
ASYN/SYN 14

CLOCK 15

8 7 6 5 4 3 2 1
B1 B2 B3 B4 B5 B6 B7 B8

MC14034B MOTOROLA CMOS LOGIC DATA

6–100
 INPUT
A(B)

tsu 20 ns
20 ns

CLOCK 50% 90%

10%

tPLH tPHL

OUTPUT
B(A)
tTLH tTHL

Figure 1. Propagation Delay and Transition Times Waveforms

PROPAGATION AND TRANSITION TIME TEST CIRCUITS

VDD VDD
CL

A1 A2 A3 A4 A5 A6 A7 A8 A1 A2 A3 A4 A5 A6 A7 A8
A ENABLE A ENABLE
P/S P/S
PROGRAMMABLE PROGRAMMABLE
PULSE DS PULSE DS
GENERATOR A/B GENERATOR A/B
A/S A/S
C C
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
VSS

CL VSS

Figure 2. A Synchronous Data Input, B Parallel Figure 3. B Synchronous Data Input, A Parallel
Data Output and Setup Time Data Output and Setup Time

MOTOROLA CMOS LOGIC DATA MC14034B

6–101
 VDD

20 ns
A1 A2 A3 A4 A5 A6 A7 A8 20 ns
90% VDD
AE CLOCK 50%
10% VSS
P/S tWH
DS
tWL
PROGRAMMABLE A/B
PULSE DS 90% VDD
A/S
GENERATOR 10% 50%
C VSS
20 ns 20 ns
B1 B2 B3 B4 B5 B6 B7 B8 1/f
VSS tWH = tWL = 50% DUTY CYCLE
CL
CL
CL
CL
CL
CL
CL
CL

Figure 4. Power Dissipation Test Circuit and Waveforms

VDD VDD

A1 A2 A3 A4 A5 A6 A7 A8 A1 A2 A3 A4 A5 A6 A7 A8
A ENABLE A ENABLE
P/S SERIAL P/S
SERIAL DATA
DATA DS DS
MC14034B
VDD A/B VDD A/B
A/S A/S
C B1 B2 B3 B4 B5 B6 B7 B8 C B1 B2 B3 B4 B5 B6 B7 B8
SERIAL
DATA
P/S
A/S
CLOCK

Figure 5. 16–Bit Parallel In/Parallel Out, Parallel In/Serial Out,

Serial In/Parallel Out, Serial In/Serial Out Register

MC14034B MOTOROLA CMOS LOGIC DATA

6–102
 SHIFT LEFT OUTPUT

A ENABLE
AE
P/S
SHIFT LEFT/
SHIFT RIGHT
SHIFT RIGHT
OUTPUT

A1 A8 A1 A8
AE AE
REGISTER 1 P/S P/S
SHIFT RIGHT MC14034B REGISTER 2
DS DS
INPUT MC14034B
A/B A/B
A/S A/S
CLOCK C B1 B8 CB1 B8
SHIFT LEFT
INPUT*
A/S PARALLEL A/S
ENTRY
COCK

AE

A1 A8 A1 A8
AE AE
P/S P/S
DS REGISTER 3 DS REGISTER 4
MC14034B MC14034B
A/B A/B
A/S A/S
C B1 B8 C B1 B8

VDD VDD

A “High” (“Low”) on the Shift Left/Shift Right input allows serial data on the Shift Left Input (Shift Right Input) to enter the register
on the positive transition of the lock signal. A “high” on the “A” Enable Input disables the “A” parallel data lines on Reg. 1 and 2
and enables the “A” data lines on registers 3 and 4 and allows parallel data into registers 1 and 2. Other logic schemes may be
used in place of registers 3 and 4 for parallel loading.
When parallel inputs are not used, Reg. 3 and 4 and associated logic are not required.
*Shift left input must be disabled during parallel entry.

Figure 6. Shift Right/Shift Left with Parallel Inputs

MOTOROLA CMOS LOGIC DATA MC14034B

6–103
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14035B
4-Bit Parallel-In/Parallel-Out
Shift Register L SUFFIX
The MC14035B 4–bit shift register is constructed with MOS P–channel CERAMIC
CASE 620
and N–channel enhancement mode devices in a single monolithic structure.
It consists of a 4–stage clocked serial–shift register with synchronous
parallel inputs and buffered parallel outputs. The Parallel/Serial (P/S) input
allows serial–right shifting of data or synchronous parallel loading via inputs P SUFFIX
DP0 thru DP3. The True/Complement (T/C) input determines whether the PLASTIC
CASE 648
outputs display the Q or Q outputs of the flip–flop stages. J–K logic forms the
serial input to the first stage. With the J and K inputs connected together they
operate as a serial “D” input.
This device may be effectively used for shift–right/shift–left registers, D SUFFIX
parallel–to–serial/serial–to–parallel conversion, sequence generation, up/ SOIC
down Johnson or ring counters, pseudo–random code generation, frequen- CASE 751B
cy and phase comparators, sample and hold registers, etc . . .
ORDERING INFORMATION
• 4–Stage Clocked Serial–Shift Operation
MC14XXXBCP Plastic
• Synchronous Parallel Loading of all Four Stages MC14XXXBCL Ceramic
• J–K Serial Inputs on First Stage MC14XXXBD SOIC
• Asynchronous True/Complement Control of all Outputs TA = – 55° to 125°C for all packages.
• Fully Static Operation
• Asynchronous Master Reset
• Data Transfer Occurs on the Positive–Going Clock Transition
PIN ASSIGNMENT
• No Limit on Clock Rise and Fall Times
• All Inputs are Buffered Q0 1 16 VDD
• Supply Voltage Range = 3.0 Vdc to 18 Vdc T/C 2 15 Q1
• Capable of Driving Two Low–power TTL Loads or One Low–power K 3 14 Q2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range
J 4 13 Q3

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
R 5 12 DP3

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit
C 6 11 DP2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
P/S 7 10 DP1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
VSS 8 9 DP0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
TRUTH TABLE
Inputs
tn Output
C J K R Q0
0 0 0 0
0 1 0 Q0 (n – 1)
1 0 0 Q0 (n – 1)
1 1 0 1 X = Don’t Care
P/S = 0 = Serial Mode
X X 0 Q0 (n – 1)
T/C = 1 = True Outputs
X X X 1 0

MC14035B MOTOROLA CMOS LOGIC DATA

6–104
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (1.0 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.0 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs all
buffers switching)
15 IT = (3.0 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14035B

6–105
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C, See Figure 1)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns
TTLH, TTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TTLH, TTHL = (0.55 ns/pF) CL + 12.5 ns 15 — 40 80
Propagation Delay Time, Clock or Reset to Q tPLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TPLH, TPHL = (1.75 ns/pF) CL + 223 ns tPHL 5.0 — 300 600

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TPLH, TPHL = (0.70 ns/pF) CL + 89 ns 10 — 130 260
TPLH, TPHL = (0.53 ns/pF) CL + 67 ns 15 — 95 190

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tWH 5.0 335 135 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 165 45 —
15 125 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWH 5.0 400 80 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 175 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 130

ÎÎÎÎ
35

ÎÎÎÎ
—
Reset Removal Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
trem 5.0
10
80
30
40
15
—
—
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15 25 10 —
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ 10 No Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 2.5 1.2 MHz
10 — 6.0 2.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 10 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
J–K to Clock Setup Time tsu 5.0 500 120 — ns
10 200 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 150 30 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to J–K Hold Time th 5.0 40 – 40 — ns
10 30 –5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
P/S to Clock Setup Time tsu
15
5.0
25
500
0
25
—
— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 200 10 —
15 150 7.5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to P/S Hold Time th 5.0 30 – 70 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 20 – 20 —
15 20 – 10 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
DP to Clock Setup Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu 5.0 500 90 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 200 20 —
15 150 15 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to DP Hold Time th 5.0 90 – 25 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 40 0 —
15 40 5 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

RESET 50%
trem
CLOCK 50% tWH
INPUT
1/fcl th
J–K
50%
INPUT
tsu tsu
P/S
50% tsu
INPUT th

DP0
50%
INPUT
tTHL tTLH th tsu
Q0 90% 50%
10%
T/C INPUT LOW
tPHL tPLH tPHL tPLH

Figure 1. Timing Diagram

MC14035B MOTOROLA CMOS LOGIC DATA

6–106
 LOGIC DIAGRAM

DP3 12

DP2 11

DP1 10

DP0 9

P/S 7
J 4

D Q D Q D Q D Q 13 Q3
K 3 C C C C
R R R R

14 Q2

C 6

15 Q1

R 5

T/C 2 1 Q0

APPLICATION DIAGRAM
Shift Left/Shift Right Register
LEFT SHIFT
Q0
SERIAL OUTPUT
Q1

Q2
LEFT SHIFT
SERIAL INPUT
VDD RIGHT SHIFT
Q3
SERIAL OUTPUT

16 15 14 13 12 11 10 9
VDD Q1 Q2 Q3 DP3 DP2 DP1 DP0

Q0 T/C K J R C P/S VSS

1 2 3 4 5 6 7 8

VDD
RIGHT SHIFT
SERIAL INPUT
RESET

CLOCK
LEFT/RIGHT
SHIFT SELECT

MOTOROLA CMOS LOGIC DATA MC14035B

6–107
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14040B
12-Bit Binary Counter
The MC14040B 12–stage binary counter is constructed with MOS L SUFFIX
CERAMIC
P–channel and N–channel enhancement mode devices in a single
CASE 620
monolithic structure. This part is designed with an input wave shaping circuit
and 12 stages of ripple–carry binary counter. The device advances the count
on the negative–going edge of the clock pulse. Applications include time
delay circuits, counter controls, and frequency–driving circuits. P SUFFIX
PLASTIC
• Fully Static Operation CASE 648
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power D SUFFIX
Schottky TTL Load Over the Rated Temperature Range SOIC
• Common Reset Line CASE 751B
• Pin–for–Pin Replacement for CD4040B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
MAXIMUM RATINGS* (Voltages Referenced to VSS)
MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA TRUTH TABLE
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Clock Reset Output State
0 No Change

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW
0 Advance to next state
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 X 1 All Outputs are low
TL Lead Temperature (8–Second Soldering) 260 _C X = Don’t Care
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

LOGIC DIAGRAM

Q1 Q2 Q3 Q10 Q11 Q12

9 7 6 14 15 1

CLOCK
10 C Q C Q C Q C Q C Q C Q

C Q C Q C Q C Q C Q C
R R R R R R

RESET
11

Q4 = PIN 5 Q7 = PIN 4 VDD = PIN 16

Q5 = PIN 3 Q8 = PIN 13 VSS = PIN 8
Q6 = PIN 2 Q9 = PIN 12

MC14040B MOTOROLA CMOS LOGIC DATA

6–108
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.42 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.85 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (1.43 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
Q12 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q6 2 15 Q11
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Q5 3 14 Q10
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Q7 4 13 Q8
Q4 5 12 Q9
Q3 6 11 R
Q2 7 10 C
VSS 8 9 Q1

MOTOROLA CMOS LOGIC DATA MC14040B

6–109
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TTLH, TTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TTLH, TTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH,
Clock to Q1 tPHL ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPHL, tPLH = (1.7 ns/pF) CL + 315 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns
tPHL, tPLH = (0.5 ns/pF) CL + 95 ns
5.0
10
15
—
—
—
260
115
80
520
230
160
Clock to Q12
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tPHL, tPLH = (1.7 ns/pF) CL + 2415 ns

ÎÎÎ
tPHL, tPLH = (0.66 ns/pF) CL + 867 ns
tPHL, tPLH = (0.5 ns/pF) CL + 475 ns
5.0
10
15
—
—
—
1625
720
500
3250
1440
1000

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Qn

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (1.7 ns/pF) CL + 485 ns 5.0 — 370 740
tPHL = (0.86 ns/pF) CL + 182 ns 10 — 155 310

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.5 ns/pF) CL + 145 ns 15 — 115 230

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 385 140 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 150 55 —
15 115 38 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ fcl 5.0 — 2.1 1.5 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 7.0 3.5
15 — 10.0 4.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Rise and Fall Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH, tTHL 5.0 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
10
15
No Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWH 5.0 960 320 — ns
10 360 120 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 270 80 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Removal Time trem 5.0 130 65 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 50 25 —
15 30 15 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD
VDD

0.01 µF PULSE
500 µF ID C Q1
CERAMIC GENERATOR
Q2
Q CL
R n CL
PULSE
C Q1 CL
GENERATOR VSS
Q2
Q CL
R n CL
VSS CL
20 ns 20 ns
CLOCK
90%
50%
10%
20 ns 20 ns tWH
VDD tPLH tPHL
CLOCK 90%
50% 90%
10% VSS Q 50%
50% DUTY CYCLE 10%
tTLH tTHL

Figure 1. Power Dissipation Test Circuit Figure 2. Switching Time Test Circuit
and Waveform and Waveforms

MC14040B MOTOROLA CMOS LOGIC DATA

6–110
 1 2 4 8 16 32 64 128 256 512 1024 2048 4096
CLOCK

RESET
Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8
Q9

Q10

Q11

Q12

Figure 3. Timing Diagram

APPLICATIONS INFORMATION

TIME–BASE GENERATOR outputs Q5, Q10, Q11, and Q12 division by 3600 is ac-
A 60 Hz sinewave obtained through a 1.0 Megohm resistor complished. The MC14012B decodes the counter outputs,
connected directly to a standard 120 Vac power line is produces a single output pulse, and resets the binary count-
applied to the clock input of the MC14040B. By selecting er. The resulting output frequency is 1.0 pulse/minute.

VDD

1.0 M MC14040B
C Q5 1.0 PULSE/MINUTE
≥ 20 pF Q10 OUTPUT
1/2 1/2
120 Vac MC14012B MC14012B
Q11
60 Hz
R Q12

VSS

MOTOROLA CMOS LOGIC DATA MC14040B

6–111
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS L SUFFIX
CERAMIC
P–channel and N–channel enhancement mode devices in a single
CASE 620
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity input.
Information present at the data input is transferred to outputs Q and Q during P SUFFIX
the clock level which is determined by the polarity input. When the polarity PLASTIC
CASE 648
input is in the logic “0” state, data is transferred during the low clock level,
and when the polarity input is in the logic “1” state the transfer occurs during
the high clock level.
D SUFFIX
• Buffered Data Inputs
SOIC
• Common Clock CASE 751B
• Clock Polarity Control
• Q and Q Outputs ORDERING INFORMATION
• Double Diode Input Protection MC14XXXBCP Plastic
• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc MC14XXXBCL Ceramic
MC14XXXBD SOIC
• Capable of Driving Two Low–power TTL Loads or One Low–power

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
Symbol ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit PIN ASSIGNMENT

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
Q3
Q0
1
2
16
15
VDD
Q3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA
Q0 3 14 D3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin
PD Power Dissipation, per Package† 500 mW D0 4 13 D2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature – 65 to + 150 _C CLOCK 5 12 Q2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
POLARITY
D1
6
7
11
10
Q2
Q1

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C VSS 8 9 Q1
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

LOGIC DIAGRAM
TRUTH TABLE
D0 LATCH Q0
5 4 2 Clock Polarity Q
CLOCK 1
Q0 0 0 Data
POLARITY 3
6 1 0 Latch
1 1 Data
D1 LATCH Q1 0 1 Latch
7 10
2
Q1
9

D2 LATCH Q2
13 11
3
Q2
12
VDD = PIN 16
VSS = PIN 8
D3 LATCH Q3
14 1
4
Q3
15

MC14042B MOTOROLA CMOS LOGIC DATA

6–112
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
1.0
2.0
—
—
0.002
0.004
1.0
2.0
—
—
30
60
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 4.0 — 0.006 4.0 — 120

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (1.0 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.0 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs all
buffers switching)
15 IT = (3.0 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14042B

6–113
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time, D to Q, Q tPLH, no

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPHL 5.0 — 220 440
tPLH, tPHL = (0.66 ns/pF) CL + 57 ns 10 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns

ÎÎÎÎ
ÎÎÎ
Propagation Delay Time, Clock to Q, Q tPLH,
15 — 60 120
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPHL 5.0 — 220 440
tPLH, tPHL = (0.66 ns/pF) CL + 57 ns 10 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
Clock Pulse Width ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns

ÎÎÎÎ
ÎÎÎ tWH
15 — 60 120
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0 300 150 —
10 100 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 80 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Rise and Fall Time tTLH, µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL 5.0 — — 15
10 — — 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — — 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Hold Time th ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0 100 50 —
10 50 25 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 40 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Setup Time tsu ns

ÎÎÎÎ
5.0 50 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
* The formulas given are for the typical characteristics only at 25_C.
10
15
30
25
0
0
—
—

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD
1
16
f
20 ns 20 ns
5 90%
CLOCK Q0 2 50%
6 10%
Q0 3 DATA INPUT
POLARITY tPLH tPHL
PULSE 4 Q1 10
D0 Q1 9 90%
GENERATOR 1 50%
7 Q2 11 10%
D1 Q OUTPUT
13 Q2 12 tTLH tTHL
D2
14 Q3 1 tPHL
D3 Q3 15 Q OUTPUT
90%
50%
10%
8 VSS
For Power Dissipation test, each output tTHL tTLH
is loaded with capacitance CL.

Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram

(Data to Output)

MC14042B MOTOROLA CMOS LOGIC DATA

6–114
 VDD
16

PULSE 5
CLOCK Q0 2
GENERATOR 1
6 Q0 3
POLARITY
4 Q1 10
PULSE
D0 Q1 9
GENERATOR 2 7
D1 Q2 11
13 Q2 12
D2 Q3 1
14
D3 Q3 15

NOTE: CL connected to output under test. 8 VSS

20* ns 20 ns

90%
50%
CLOCK INPUT 10% tWH
P.G. 1 20 ns
90%
50%
DATA INPUT tsu th
P.G. 2
tPLH
Q OUTPUT 90%
50%
10%

* Input clock rise time is 20 ns except for maximum rise time test.

Figure 2. AC Test Circuit and Timing Diagram

(Clock to Output)

MOTOROLA CMOS LOGIC DATA MC14042B

6–115
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14043B
MC14044B
CMOS MSI
Quad R–S Latches
The MC14043B and MC14044B quad R–S latches are constructed with
L SUFFIX
MOS P–channel and N–channel enhancement mode devices in a single CERAMIC
monolithic structure. Each latch has an independent Q output and set and CASE 620
reset inputs. The Q outputs are gated through three–state buffers having a
common enable input. The outputs are enabled with a logical “1” or high on
the enable input; a logical “0” or low disconnects the latch from the Q
P SUFFIX
outputs, resulting in an open circuit at the Q outputs. PLASTIC
• Double Diode Input Protection CASE 648
• Three–State Outputs with Common Enable
• Outputs Capable of Driving Two Low–power TTL Loads or One Low–
Power Schottky TTL Load Over the Rated Temperature Range D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
CASE 751B

ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.

MC14043B MC14044B
4 4
S0 2 R0 13
Q0 Q0

3 3
R0 S0
6 6
S1 9 R1 9
Q1 Q1

7 VDD = PIN 16 7 VDD = PIN 16

R1 S1
VSS = PIN 8 VSS = PIN 8
12 NC = PIN 13 12 NC = PIN 2
S2 10 R2 10
Q2 Q2

11 11
R2 S2
14 14
S3 1 TRUTH TABLE R3 1 TRUTH TABLE
Q3 Q3
S R E Q S R E Q
X X 0 High X X 0 High
15 Impedance Impedance
15
R3 0 0 1 No Change S3 0 0 1 0
0 1 1 0 0 1 1 1
5 1 0 1 1 5 1 0 1 0
ENABLE 1 1 1 1 1 1 1 No Change
ENABLE
X = Don’t Care X = Don’t Care

MC14043B MC14044B MOTOROLA CMOS LOGIC DATA

6–116
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
1.0
2.0
—
—
0.002
0.004
1.0
2.0
—
—
30
60
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 4.0 — 0.006 4.0 — 120

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.58 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.15 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs all
buffers switching)
15 IT = (1.73 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
Current ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Three–State Output Leakage

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 —

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
± 3.0 µAdc

** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages – 12 mW/_C From 100_C To 125_C

MOTOROLA CMOS LOGIC DATA MC14043B MC14044B

6–117
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎ Parameter Value Unit This device contains protection circuitry to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VDD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout

ÎÎÎÎÎÎÎÎÎ
DC Supply Voltage

ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA any voltage higher than maximum rated volt-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
per Pin ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
PD
v v
Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
to the range VSS (Vin or Vout) VDD.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Unused inputs must always be tied to an
TL Lead Temperature (8–Second Soldering) 260 _C appropriate logic voltage level (e.g., either VSS
* Maximum Ratings are those values beyond which damage to the device may occur. or VDD). Unused outputs must be left open.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit
Output Rise Time tTLH ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
tTLH = (1.35 ns/pF) CL + 32.5 ns 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
tTLH = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTLH = (0.40 ns/pF) CL + 20 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ

tTHL = (1.35 ns/pF) CL + 32.5 ns 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
tTHL = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTHL = (0.40 ns/pF) CL + 20 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ

tPLH = (0.90 ns/pF) CL + 130 ns 5.0 — 175 350
tPLH = (0.36 ns/pF) CL + 57 ns 10 — 75 175

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
tPLH = (0.26 ns/pF) CL + 47 ns 15 — 60 120

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.90 ns/pF) CL + 130 ns tPHL 5.0 — 175 350 ns
tPHL = (0.90 ns/pF) CL + 57 ns 10 — 75 175

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.26 ns/pF) CL + 47 ns
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set, Set Pulse Width tW
15
5.0
—
200
60
80
120
— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
10 100 40 —
15 70 30 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset, Reset Pulse Width tW 5.0 200 80 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
10 100 40 —
15 70 30 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Three–State Enable/Disable Delay

ÎÎÎÎ ÎÎÎ tPLZ, 5.0 — 150 300 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ

tPHZ, 10 — 80 160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
tPZL, 15 — 55 110
tPZH
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

AC WAVEFORMS
MC14043B MC14044B
20 ns 20 ns 20 ns 20 ns
VDD VDD
90% 90%
50% 50%
SET 10% SET 10%
VSS VSS
20 ns 20 ns 20 ns 20 ns
VDD
90% 90% VDD
50% 50%
RESET 10% RESET 10%
VSS VSS
tTHL tTLH
tTLH tTHL
VOH VOH
90% 90%
Q 10% 50% Q 50%
VOL 10% VOL
tPHL tPLH
tPLH tPHL

MC14043B MC14044B MOTOROLA CMOS LOGIC DATA

6–118
 THREE–STATE ENABLE/DISABLE DELAYS

Set, Reset, Enable, and Switch Conditions for 3–State Tests VDD

MC14043B MC14044B
Test Enable S1 S2 Q S R S R
S1
tPZH Open Closed A VDD VSS VSS VDD
TO
tPZL Closed Open B VSS VDD VDD VSS 1k
OUTPUT
tPHZ Open Closed A VDD VSS VSS VDD UNDER CL
TEST 50 pF
tPLZ Closed Open B VSS VDD VDD VSS
S2

VSS

VDD
ENABLE 50%
VSS

tPZH VDD
90%
QA 10%
tPHZ VOL
tPZL
tPLZ VOH
QB
10%
VSS

PIN ASSIGNMENT

MC14043B MC14044B
Q3 1 16 VDD Q3 1 16 VDD
Q0 2 15 R3 NC 2 15 S3
R0 3 14 S3 S0 3 14 R3
S0 4 13 NC R0 4 13 Q0
E 5 12 S2 E 5 12 R2
S1 6 11 R2 R1 6 11 S2
R1 7 10 Q2 S1 7 10 Q2
VSS 8 9 Q1 VSS 8 9 Q1

NC = NO CONNECTION

MOTOROLA CMOS LOGIC DATA MC14043B MC14044B

6–119
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14046B
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators, a L SUFFIX
CERAMIC
voltage–controlled oscillator (VCO), source follower, and zener diode. The
CASE 620
comparators have two common signal inputs, PCAin and PCBin. Input PCAin
can be used directly coupled to large voltage signals, or indirectly coupled
(with a series capacitor) to small voltage signals. The self–bias circuit
adjusts small voltage signals in the linear region of the amplifier. Phase P SUFFIX
comparator 1 (an exclusive OR gate) provides a digital error signal PC1out, PLASTIC
CASE 648
and maintains 90° phase shift at the center frequency between PCAin and
PCBin signals (both at 50% duty cycle). Phase comparator 2 (with leading
edge sensing logic) provides digital error signals, PC2 out and LD, and
maintains a 0° phase shift between PCA in and PCB in signals (duty cycle is DW SUFFIX
immaterial). The linear VCO produces an output signal VCO out whose SOIC
frequency is determined by the voltage of input VCO in and the capacitor and CASE 751G
resistors connected to pins C1A, C1B, R1, and R2. The source–follower
ORDERING INFORMATION
output SFout with an external resistor is used where the VCO in signal is
needed but no loading can be tolerated. The inhibit input Inh, when high, MC14XXXBCP Plastic
disables the VCO and source follower to minimize standby power MC14XXXBCL Ceramic
MC14XXXBDW SOIC
consumption. The zener diode can be used to assist in power supply
regulation. TA = – 55° to 125°C for all packages.
Applications include FM and FSK modulation and demodulation, fre-
quency synthesis and multiplication, frequency discrimination, tone decod-
ing, data synchronization and conditioning, voltage–to–frequency PIN ASSIGNMENT
conversion and motor speed control.
LD 1 16 VDD
• Buffered Outputs Compatible with MHTL and Low–Power TTL
• Diode Protection on All Inputs PC1out 2 15 ZENER
• Supply Voltage Range = 3.0 to 18 V PCBin 3 14 PCAin
• Pin–for–Pin Replacement for CD4046B VCOout 4 13 PC2out
• Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited
INH 5 12 R2
• Phase Comparator 2 switches on Rising Edges and is not Duty Cycle
Limited C1A 6 11 R1
C1B 7 10 SFout
VSS 8 9 VCOin
BLOCK DIAGRAM

SELF BIAS PHASE

PCAin 14 2 PC1out
CIRCUIT COMPARATOR 1
PHASE 13 PC2out
PCBin 3 COMPARATOR 2 1 LD
VOLTAGE 4 VCOout
VCOin 9 11 R1
CONTROLLED
12 R2
VDD = PIN 16 OSCILLATOR 6 C1A
VSS = PIN 8 (VCO) 7 C1B

INH 5 SOURCE FOLLOWER 10 SFout

VSS 15 ZENER

MC14046B MOTOROLA CMOS LOGIC DATA

6–120
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Rating Symbol Value Unit

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
DC Supply Voltage

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Input Voltage, All Inputs
VDD
Vin
– 0.5 to + 18
– 0.5 to VDD + 0.5
Vdc
Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
DC Input Current, per Pin Iin ± 10 mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Power Dissipation, per Package† PD 500 mW

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Operating Temperature Range TA – 55 to + 125 _C

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature Range Tstg – 65 to + 150 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
Characteristic

ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Symbol
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ Max Min
125_C
Max Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = 0 or VDD
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
“1” Level

ÎÎÎ
VOH 5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
Input Voltage #

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VO = 4.5 or 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
“0” Level

ÎÎÎ
VIL
5.0 — 1.5 — 2.25 1.5 — 1.5
Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VO = 1.0 or 9.0 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
“1” Level

ÎÎÎ
VIH 5.0
10
3.5
7.0
—
—
3.5
7.0
2.75
5.50
—
—
3.5
7.0
—
—
Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — — —
Input Capacitance Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Quiescent Current

ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) Inh = PCAin = VDD,
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Zener = VCOin = 0 V, PCBin = VDD 15 — 20 — 0.015 20 — 600
or 0 V, Iout = 0 µA

ÎÎÎÎÎÎÎÎÎÎÎ
R ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current†

ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
R1 = 1.0 MΩ, R2 =
ÎÎÎ
(Inh = “0”, fo = 10 kHz, CL = 50 pF,
RSF = ∞,
IT 5.0
10
15
IT = (1.46 µA/kHz) f + IDD
IT = (2.91 µA/kHz) f + IDD
IT = (4.37 µA/kHz) f + IDD
mAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
and 50% Duty Cycle)
ÎÎÎ
#Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level = 1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc

ǒ Ǔ ǒ Ǔ
†To Calculate Total Current in General:

IT [ 2.2 x VDD
VCOin – 1.65 VDD – 1.35 3/4
R1
+
R2
+ 1.6 x
VCOin – 1.65 3/4
RSF
+ 1 x 10–3 (CL + 9) VDD f +

1 x 10–1 VDD2 ǒ 100% Duty Cycle of PCAin

100
Ǔ + IQ where: IT in µA, CL in pF, VCOin, VDD in Vdc, f in kHz, and
R1, R2, RSF in MΩ, CL on VCOout.

MOTOROLA CMOS LOGIC DATA MC14046B

6–121
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25°C)

ÎÎÎÎ
ÎÎÎ Minimum Maximum

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Device Typical Device Units

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Output Rise Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH
5.0
10
—
—
180
90
350
150
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Output Fall Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
tTLH = (1.1 ns/pF) CL + 10 ns

ÎÎÎÎ
ÎÎÎ tTHL
15 — 65 110
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 175
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 75

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎ
ÎÎÎ
15 — 37 55

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
PHASE COMPARATORS 1 and 2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
Input Resistance — PCAin

ÎÎÎÎ
ÎÎÎ
Rin 5.0 1.0 2.0 — MΩ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 0.2 0.4 —
15 0.1 0.2 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
— PCBin
ÎÎÎÎ
ÎÎÎ Rin 15 150 1500 — MΩ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
Minimum Input Sensitivity

ÎÎÎÎ
AC Coupled — PCAin ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Vin 5.0
10
—
—
200
400
300
600
mV p–p

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
C series = 1000 pF, f = 50 kHz 15 — 700 1050

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
DC Coupled — PCAin, PCBin — 5 to 15 See Noise Immunity

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VOLTAGE CONTROLLED OSCILLATOR (VCO)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Frequency fmax 5.0 0.5 0.7 — MHz
(VCOin = VDD, C1 = 50 pF 10 1.0 1.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
R1 = 5.0 kΩ, and R2 = ∞) 15 1.4 1.9 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Temperature — Frequency Stability — 5.0 — 0.12 — %/_C
(R2 = ∞ )

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 0.04 —
15 — 0.015 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Linearity (R2 = ∞ )

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VCOin = 2.5 V ± 0.3 V, R1 > 10 kΩ)
(VCOin = 5.0 V ± 2.5 V, R1 > 400 kΩ)
—
5.0 — 1.0 —
%

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 1.0 —
(VCOin = 7.5 V ± 5.0 V, R1 ≥ 1000 kΩ) 15 — 1.0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Output Duty Cycle
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
Input Resistance — VCOin
ÎÎÎÎ
ÎÎÎ
—
Rin
5 to 15
15
—
150
50
1500
—
—
%
MΩ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SOURCE–FOLLOWER

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Offset Voltage
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VCOin minus SFout, RSF > 500 kΩ)
— 5.0
10
15
—
—
—
1.65
1.65
1.65
2.2
2.2
2.2
V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Linearity
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VCOin = 2.5 V ± 0.3 V, RSF > 50 kΩ)
—
5.0 — 0.1 —
%

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VCOin = 5.0 V ± 2.5 V, RSF > 50 kΩ) 10 — 0.6 —
(VCOin = 7.5 V ± 5.0 V, RSF > 50 kΩ) 15 — 0.8 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ZENER DIODE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
Zener Voltage (Iz = 50 µA)

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Dynamic Resistance (Iz = 1.0 mA)
VZ
RZ
—
—
6.7
—
7.0
100
7.3
—
V
Ω
* The formula given is for the typical characteristics only.

MC14046B MOTOROLA CMOS LOGIC DATA

6–122
 PHASE COMPARATOR 1
Input Stage
00 01
X X
11 10
PCAin PCBin

PC1out 0 1

PHASE COMPARATOR 2
Input Stage

X X 00 00 00

01 10 10 01 01 10
PCAin PCBin

11 11 11

3–State
PC2out 0 1
Output Disconnected
LD
0 1 0
(Lock Detect)
Refer to Waveforms in Figure 3.

Figure 1. Phase Comparators State Diagrams

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Using Phase Comparator 1 Using Phase Comparator 2

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
No signal on input PCAin.

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
VCO in PLL system adjusts to center
frequency (f0).
VCO in PLL system adjusts to minimum
frequency (fmin).

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Phase angle between PCAin and PCBin. 90° at center frequency (f0), approaching 0_ Always 0_ in lock (positive rising edges).

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
and 180° at ends of lock range (2fL)

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Locks on harmonics of center frequency. Yes No

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Signal input noise rejection. High Low

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Lock frequency range (2fL).

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2fL = full VCO frequency range = fmax – fmin.

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Capture frequency range (2fC).

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Depends on low–pass filter characteristics fC = fL
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
(see Figure 3). fC fL

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Center frequency (f0). The frequency of VCOout, when VCOin = 1/2 VDD

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCO output frequency (f). 1
fmin = (VCO input = VSS)

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
R2(C1 + 32 pF)

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Note: These equations are intended to be 1
fmax = + fmin (VCO input = VDD)

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
a design guide. Since calculated component
R1(C1 + 32 pF)
values may be in error by as much as a

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v v
factor of 4, laboratory experimentation may Where: 10K R1 1M
v v
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
be required for fixed designs. Part to part 10K R2 1M
v v
frequency variation with identical passive
100pF C1 .01 µF

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
components is typically less than ± 20%.

Figure 2. Design Information

MOTOROLA CMOS LOGIC DATA MC14046B

6–123
 9 SOURCE 10 SFout
FOLLOWER
VCOin RSF

PCAin 14 EXTERNAL
PHASE 2 OR 13 9 VCO 4 VCOout
@ FREQUENCY f′ 3 LOW–PASS
COMPARATOR PC1out 11 12 6 7 @ FREQUENCY Nf′ = f
FILTER
PCBin OR CIA CIB
PC2out R1 R2
CI
EXTERNAL
÷N
COUNTER

Typical Low–Pass Filters

Ǹ
Typically:
+ fmax
(a) R3 (a) R3
OUTPUT OUTPUT R4 C2 6N – N
INPUT INPUT 2 pD f
2 p fL
C2
2fC [p
1
R3 C2
R4
(R3 ) 3, 000W) C2 + 100N Df – R 4 C2
fmax2
C2
∆ f = fmax – fmin

NOTE: Sometimes R3 is split into two series resistors each R3 ÷ 2. A capacitor CC is then placed from the midpoint to ground. The value for
CC should be such that the corner frequency of this network does not significantly affect ωn. In Figure B, the ratio of R3 to R4 sets the
damping, R4 ^
(0.1)(R3) for optimum results.
LOW–PASS FILTER

Ǹ Ǹ
Filter A Filter B
Definitions: N = Total division ratio in feedback loop
KfKVCO KfKVCO
wn + wn +
Kφ = VDD/π for Phase Comparator 1
Kφ = VDD/4 π for Phase Comparator 2 NR3C2 NC2(R3 R4) )
2 p D fVCO
KVCO + Nw
VDD – 2 V
2 p fr z + 2K K n z + 0.5 wn ) KfKNVCO)
for a typical design ωn ^ 10
(at phase detector input) f VCO
(R3C2

^ R3C2S ) 1
+ R3C21S ) 1 F(s) +
ζ 0.707
S(R3C2 ) R4C2) ) 1
F(s)

Waveforms

Phase Comparator 1 Phase Comparator 2

VDD VDD
PCAin PCAin
VSS VSS

VOH VOH
PCBin PCBin
VOL VOL
VOH VOH
PC1out LD
VOL VOL
VOH VOH
VCOin PC2out
VOL VOL
VOH
VCOin
VOL
Note: for further information, see:
(1) F. Gardner, “Phase–Lock Techniques”, John Wiley and Son, New York, 1966.
(2) G. S. Moschytz, “Miniature RC Filters Using Phase–Locked Loop”, BSTJ, May, 1965.
(3) Garth Nash, “Phase–Lock Loop Design Fundamentals”, AN–535, Motorola Inc.
(4) A. B. Przedpelski, “Phase–Locked Loop Design Articles”, AR254, reprinted by Motorola Inc.

Figure 3. General Phase–Locked Loop Connections and Waveforms

MC14046B MOTOROLA CMOS LOGIC DATA

6–124
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14049B
MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting Hex
Buffer are constructed with MOS P–Channel and N–Channel enhancement
mode devices in a single monolithic structure. These complementary MOS L SUFFIX
devices find primary use where low power dissipation and/or high noise CERAMIC
immunity is desired. These devices provide logic level conversion using only CASE 620
one supply voltage, VDD.
The input–signal high level (VIH) can exceed the VDD supply voltage for
logic level conversions. Two TTL/DTL loads can be driven when the devices P SUFFIX
are used as a CMOS–to–TTL/DTL converter (VDD = 5.0 V, VOL 0.4 V, v PLASTIC
IOL ≥ 3.2 mA). CASE 648
Note that pins 13 and 16 are not connected internally on these devices;
consequently connections to these terminals will not affect circuit operation.
• High Source and Sink Currents D SUFFIX
SOIC
• High–to–Low Level Converter
CASE 751B
• Supply Voltage Range = 3.0 V to 18 V
• VIN can exceed VDD ORDERING INFORMATION
• Meets JEDEC B Specifications MC14XXXBCP Plastic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Improved ESD Protection On All Inputs MC14XXXBCL Ceramic
MC14XXXBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS1 (Voltages Referenced to VSS)

ÎÎÎÎÎÎ
ÎÎÎ
Characteristic Symbol Value Unit
TA = – 55° to 125°C for all packages.

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage VDD – 0.5 to + 18.0 Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Input Voltage (DC or Transient) VIN – 0.5 to + 18.0 Vdc
PIN ASSIGNMENT

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Output Voltage (DC or Transient) Vout – 0.5 to VDD + 0.5 Vdc
Input Current (DC or Transient), per Pin Iin ± 10 mA VDD 1 16 NC

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Output Current (DC or Transient), per Pin Iout + 45 mA OUTA 2 15 OUTF

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
Power Dissipation, per Package2

ÎÎÎÎÎÎ
ÎÎÎ
(Plastic/Ceramic)
PD
825
mW INA
OUTB
3
4
14
13
INF
NC

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
(SOIC) 740
INB 5 12 OUTE
_C

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature Tstg – 65 to + 150
OUTC 6 11 INE
Lead Temperature (8 – Second Soldering) TL 260 _C
1Maximum Ratings are those values beyond which damage to the device may occur. INC 7 10 OUTD
2Temperature Derating: See Figure 3. VSS 8 9 IND
LOGIC DIAGRAM
MC14049B MC14050B
3 2 3 2

5 4 5 4

7 6 7 6

9 10 9 10

11 12 11 12

14 15 14 15

NC = PIN 13, 16 NC = PIN 13, 16

VSS = PIN 8 VSS = PIN 8
VDD = PIN 1 VDD = PIN 1

MOTOROLA CMOS LOGIC DATA MC14049B MC14050B

6–125
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C + 25_C + 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ1 Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ
Vin = VDD ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 13.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 1.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 1.6

ÎÎÎÎ
—

ÎÎÎ
– 1.25

ÎÎÎÎ
– 2.5

ÎÎÎ
—

ÎÎÎÎ
– 1.0

ÎÎÎ
—
(VOH = 9.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
– 1.6
– 4.7
—
—
– 1.30
– 3.75
– 2.6
– 10
—
—
– 1.0
– 3.0
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 3.75 — 3.2 6.0 — 2.6 — mAdc
(VOL = 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 10 — 8.0 16 — 6.6 —
(VOL = 1.5 Vdc) 15 30 — 24 40 19 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input Current

ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Input Capacitance (Vin = 0) ÎÎÎ
ÎÎÎ
ÎÎÎ
Iin
Cin
15
—
—
—
± 0.1
—
—
—
±0.00001
10
± 0.1
20
—
—
± 1.0
—
µAdc
pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current (Per Package)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
1.0
2.0
—
—
0.002
0.004
1.0
2.0
—
—
30
60
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
15 — 4.0 — 0.006 4.0 — 120
Total Supply Current 2,3 IT = (1.8 µA/kHz) f + IDD µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
IT 5.0
(Dynamic plus Quiescent, 10 IT = (3.5 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
per package) 15 IT = (5.3 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching
ÎÎÎ
1 Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
2 The formulas given are for the typical characteristics only at + 25_C
3 To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
Where: IT is in µA (per Package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency and k = 0.002.

This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields
referenced to the VSS pin only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum
rated voltages to this high-impedance circuit. For proper operation, the ranges VSS v
Vin v
18 V and VSS Vout v VDD arev
recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be
left open.

MC14049B MC14050B MOTOROLA CMOS LOGIC DATA

6–126
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC SWITCHING CHARACTERISTICS1 (CL = 50 pF, TA = + 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ2 Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (0.7 ns/pF) CL + 65 ns 5.0 — 100 160
tTLH = (0.25 ns/pF) CL + 37.5 ns 10 — 50 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (0.2 ns/pF) CL + 30 ns 15 — 40 60

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.2 ns/pF) CL + 30 ns

ÎÎÎÎÎ
5.0

ÎÎÎÎ
—

ÎÎÎÎ
40

ÎÎÎÎ
60

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
tTHL = (0.06 ns/pF) CL + 17 ns

ÎÎÎÎÎÎÎ
tTHL = (0.04 ns/pF) CL + 13 ns
10
15
—
—
20
15
40
30

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH ns
tPLH = (0.33 ns/pF) CL + 63.5 ns 5.0 — 80 140

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.19 ns/pF) CL + 30.5 ns 10 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.06 ns/pF) CL + 27 ns 15 — 30 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPHL ns
tPHL = (0.2 ns/pF) CL + 30 ns 5.0 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.1 ns/pF) CL + 15 ns 10 — 20 40
tPHL = (0.05 ns/pF) CL + 12.5 ns 15 — 15 30
1 The formulas given are for the typical characteristics only at 25_C.
2 Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14049B MC14050B MC14049B MC14050B

VDD VDD VDD VDD
1 1 1 1

IOH IOL IOL IOH

VOH VOL VOL VOH
VSS 8 VSS 8 VSS VSS
8 8
VDS = VOH – VDD VDD = VOL

0 160
I OH , OUTPUT SOURCE CURRNT (mAdc)

VGS = 15 Vdc
I OL, OUTPUT SINK CURRENT (mAdc)

VGS = 5.0 Vdc

– 10
120

– 20
VGS = 10 Vdc
80
– 30 VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
40
– 40 VGS = 15 Vdc
MAXIMUM CURRENT LEVEL VGS = 5.0 Vdc

– 50 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0 2.0 4.0 6.0 8.0 10
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

Figure 1. Typical Output Source Characteristics Figure 2. Typical Output Sink Characteristics

MOTOROLA CMOS LOGIC DATA MC14049B MC14050B

6–127
 1200

PD , MAXIMUM POWER DISSIPATION (mW)

1100
1000
900
825
800

PER PACKAGE
740 (L) CERAMIC
700
600
(P) PDIP
500
400
300 (D) SOIC
260 mW (L)
200 175 mW (P)
100 120 mW (D)
0
25 50 75 100 125 150 175
TA, AMBIENT TEMPERATURE (°C)

Figure 3. Ambient Temperature Power Derating

20 ns 20 ns

VDD
INPUT 90%
50%
VDD 10% VSS
tPHL tPLH
1
# 90% VOH
OUTPUT
PULSE 50%
MC14049B
GENERATOR 10%
Vin Vout VOL
tPLH tTHL tTLH
8 VSS CL tPHL tPHL
VOH
OUTPUT 90%
MC14050B 50%
# Invert on MC14049B only 10% VOL

tTLH tTHL

Figure 4. Switching Time Test Circuit and Waveforms

MC14049B MC14050B MOTOROLA CMOS LOGIC DATA

6–128
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS P–channel L SUFFIX
CERAMIC
and N–channel enhancement mode devices in a single monolithic structure.
CASE 620
This complementary MOS device finds primary use where low power
dissipation and/or high noise immunity is desired. This device provides
logic–level conversion using only one supply voltage, VDD. The input–signal
high level (V IH ) can exceed the V DD supply voltage for logic–level P SUFFIX
conversions. Two TTL/DTL Loads can be driven when the device is used as PLASTIC
CMOS–to–TTL/DTL converters (VDD = 5.0 V, VOL v0.4 V, IOL ≥ 3.2 mA).
CASE 648
Note that pins 13 and 16 are not connected internally on this device;
consequently connections to these terminals will not affect circuit operation.
D SUFFIX
• High Source and Sink Currents
SOIC
• High–to–Low Level Converter CASE 751B
• Supply Voltage Range = 3.0 V to 18 V
• Meets JEDEC UB Specifications ORDERING INFORMATION
•

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIN can exceed VDD MC14XXXBCP Plastic
• Improved ESD Protection on All Inputs MC14XXXBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
Rating Symbol Value Unit

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
DC Supply Voltage

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Input Voltage (DC or Transient)
VDD
Vin
– 0.5 to + 18
– 0.5 to + 18
V
V LOGIC DIAGRAM

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
Output Voltage (DC or Transient)

ÎÎÎÎÎÎ
ÎÎÎ
Input Current (DC or Transient), per Pin
Vout
Iin
– 0.5 to VDD + 0.5
± 10
V
mA
MC14049UB

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
3 2
Output Current (DC or Transient), per Pin Iout + 45 mA

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
Plastic/Ceramic
ÎÎÎ
PD
825
mW 5 4

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
SOIC 740
7 6

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature Tstg – 65 to + 150 _C

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) TL 260 _C 9 10
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: All Packages: See Figure 4. 11 12

CIRCUIT SCHEMATIC
14 15
(1/6 OF CIRCUIT SHOWN)
NC = PIN 13, 16
MC14049UB VSS = PIN 8
VDD = PIN 1
VDD

VSS

MOTOROLA CMOS LOGIC DATA MC14049UB

6–129
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.0

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.0

ÎÎÎÎ
—

ÎÎÎ
1.0
(VO = 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 13.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
2.0
2.5
—
—
4.50
6.75
2.0
2.5
—
—
2.0
2.5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
4.0

ÎÎÎÎ
—

ÎÎÎ
4.0

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
4.0

ÎÎÎ
—
(VO = 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 1.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
8.0
12.5
—
—
8.0
12.5
5.50
8.25
—
—
8.0
12.5
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 1.6

ÎÎÎÎ
—

ÎÎÎ
– 1.25

ÎÎÎÎ
– 2.5

ÎÎÎ
—

ÎÎÎÎ
– 1.0

ÎÎÎ
—
(VOH = 9.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
– 1.6
– 4.7
—
—
– 1.3
– 3.75
– 2.6
– 10
—
—
– 1.0
– 3.0
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 3.75 — 3.2 6.0 — 2.6 — mAdc
(VOL = 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 10 — 8.0 16 — 6.6 —
(VOL = 1.5 Vdc) 15 30 — 24 40 — 19 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 10 20 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 1.0 — 0.002 1.0 — 30 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 2.0 — 0.004 2.0 — 60
15 — 4.0 — 0.006 4.0 — 120

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,

ÎÎÎ
IT 5.0
10
IT = (1.8 µA/kHz) f + IDD
IT = (3.5 µA/kHz) f + IDD
IT = (5.3 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Per Package) 15
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

MC14049UB MOTOROLA CMOS LOGIC DATA

6–130
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (0.8 ns/pF) CL + 60 ns 5.0 — 100 160
tTLH = (0.3 ns/pF) CL + 35 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (0.27 ns/pF) CL + 26.5 ns 15 — 40 60

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.3 ns/pF) CL + 25 ns

ÎÎÎÎÎ
5.0

ÎÎÎÎ
—

ÎÎÎÎ
40

ÎÎÎÎ
60
tTHL = (0.12 ns/pF) CL + 14 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
tTHL = (0.1 ns/pF) CL + 10 ns

ÎÎÎ
10
15
—
—
20
15
40
30

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH ns
tPLH = (0.38 ns/pF) CL + 61 ns 5.0 — 80 120

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.20 ns/pF) CL + 30 ns
ÎÎÎ 10 — 40 65

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.11 ns/pF) CL + 24.5 ns 15 — 30 50

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPHL ns
tPHL = (0.38 ns/pF) CL + 11 ns 5.0 — 30 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.12 ns/PF) CL + 9 ns 10 — 15 30
tPHL = (0.11 ns/pF) CL + 4.5 ns 15 — 10 20
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

18

VDD = 15 Vdc
Vout , OUTPUT VOLTAGE (Vdc)

15

VDD = 10 Vdc
10 – 55°C

VDD = 5 Vdc
5
+125°C

5 10 15 18
Vin, INPUT VOLTAGE (Vdc)

Figure 1. Typical Voltage Transfer Characteristics versus Temperature

MOTOROLA CMOS LOGIC DATA MC14049UB

6–131
 VDD VDD
1 1

IOH IOL
VOH VOL
VSS 8 VSS
8
VDS = VOH – VDD VDD = VOL
0 160
I OH , OUTPUT SOURCE CURRNT (mAdc)

VGS = 15 Vdc

I OL, OUTPUT SINK CURRENT (mAdc)

VGS = 5.0 Vdc
– 10
120

– 20
VGS = 10 Vdc
80
– 30 VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
40
– 40 VGS = 15 Vdc
MAXIMUM CURRENT LEVEL VGS = 5.0 Vdc

– 50 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0 2.0 4.0 6.0 8.0 10
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

Figure 2. Typical Output Source Characteristics Figure 3. Typical Output Sink Characteristics

VDD
1
PULSE
Vout
1200 GENERATOR
Vin
PD , MAXIMUM POWER DISSIPATION (mW)

1100
8 VSS CL
1000
900
825
800 20 ns 20 ns
PER PACKAGE

740 (L) CERAMIC

700
VDD
600 INPUT 90%
(P) PDIP
500 50%
400 10% VSS
300 (D) SOIC tPHL tPLH
260 mW (L)
200 175 mW (P) 90% VOH
100 120 mW (D) OUTPUT
50%
0 10%
25 50 75 100 125 150 175 VOL
tTHL tTLH
TA, AMBIENT TEMPERATURE (°C)

Figure 4. Ambient Temperature Power Derating Figure 5. Switching Time Test Circuit
and Waveforms

PIN ASSIGNMENT
This device contains circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the VSS pin, VDD 1 16 NC
only. Extra precautions must be taken to avoid applications of any volt-
age higher than the maximum rated voltages to this high-impedance cir- OUTA 2 15 OUTF
cuit. For proper operation, the ranges VSS ≤ Vin ≤ 18 V and VSS ≤ Vout ≤ VDD INA 3 14 INF
are recommended.
Unused inputs must always be tied to an appropriate logic voltage OUTB 4 13 NC
level (e.g., either VSS or VDD). Unused outputs must be left open. INB 5 12 OUTE
OUTC 6 11 INE
INC 7 10 OUTD
VSS 8 9 IND

NC = NO CONNECTION

MC14049UB MOTOROLA CMOS LOGIC DATA

6–132
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14051B
Analog
MC14052B
Multiplexers/Demultiplexers
MC14053B
The MC14051B, MC14052B, and MC14053B analog multiplexers are
digitally–controlled analog switches. The MC14051B effectively implements
an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a
Triple SPDT. All three devices feature low ON impedance and very low OFF
leakage current. Control of analog signals up to the complete supply voltage L SUFFIX
range can be achieved. CERAMIC
• Triple Diode Protection on Control Inputs CASE 620
• Switch Function is Break Before Make
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V P SUFFIX
Note: VEE must be VSSv PLASTIC
CASE 648
• Linearized Transfer Characteristics
• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical
• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053
D SUFFIX
• For 4PDT Switch, See MC14551B SOIC
• For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed CASE 751B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CMOS Devices

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
MC14XXXBCP Plastic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage (Referenced to VEE, MC14XXXBD SOIC
VSS ≥ VEE) – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
Vin, Vout Input or Output Voltage (DC or Transient)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
(Referenced to VSS for Control Inputs and
VEE for Switch I/O) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input Current (DC or Transient),

ÎÎÎÎÎÎ
ÎÎÎ
per Control Pin ± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Isw Switch Through Current ± 25 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation. per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
MC14051B MC14052B MC14053B
8–Channel Analog Dual 4–Channel Analog Triple 2–Channel Analog
Multiplexer/Demultiplexer Multiplexer/Demultiplexer Multiplexer/Demultiplexer
6 INHIBIT 6 INHIBIT 6 INHIBIT
11 A CONTROLS 10 A 11 A X 14
CONTROLS X 13 CONTROLS
10 B 9 B 10 B
9 C 12 X0 9 C
13 X0 14 X1 12 X0 Y 15 COMMONS
COMMONS
14 X1 15 X2 13 X1 OUT/IN
X 3 OUT/IN
15 X2 SWITCHES 11 X3 SWITCHES 2 Y0
COMMON
SWITCHES 12 X3 IN/OUT 1 Y0 IN/OUT 1 Y1
OUT/IN Y 3 Z 4
IN/OUT 1 X4 5 Y1 5 Z0
5 X5 2 Y2 3 Z1
2 X6 4 Y3
4 X7

VDD = PIN 16 VDD = PIN 16 VDD = PIN 16

VSS = PIN 8 VSS = PIN 8 VSS = PIN 8
VEE = PIN 7 VEE = PIN 7 VEE = PIN 7

Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.

MOTOROLA CMOS LOGIC DATA MC14051B MC14052B MC14053B

6–133
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
Characteristic
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol

ÎÎ
ÎÎÎ
VDD Test Conditions Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
Power Supply Voltage
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VDD — VDD – 3.0 ≥ VSS ≥ VEE 3.0 18 3.0 — 18 3.0 18 V

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Range

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
v ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Quiescent Current Per IDD 5.0 Control Inputs: — 5.0 — 0.005 5.0 — 150 µA
Package 10 Vin = VSS or VDD, — 10 — 0.010 10 — 300

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎ
ÎÎ
v
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
15 Switch I/O: VEE VI/O — 20 — 0.015 20 — 600

ÎÎ
VDD, and
v ∆Vswitch 500 mV**

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ
ID(AV)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5.0 TA = 25_C only (The µA

ÎÎ
(0.07 µA/kHz) f + IDD
(Dynamic Plus 10 channel component,
Typical (0.20 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quiescent, Per Package 15 (Vin – Vout)/Ron, is
(0.36 µA/kHz) f + IDD
not included.)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
Low–Level Input Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIL

ÎÎ
ÎÎÎ
5.0
10
Ron = per spec,
Ioff = per spec
—
—
1.5
3.0
—
—
2.25
4.50
1.5
3.0
—
—
1.5
3.0
V

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
15 — 4.0 — 6.75 4.0 — 4.0

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
High–Level Input Voltage VIH 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
10 Ioff = per spec 7.0 — 7.0 5.50 — 7.0 —

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎ
15 11 — 11 8.25 — 11 —

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — 1.0 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Recommended VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD VPP

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Peak–to–Peak Voltage
Into or Out of the Switch

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
Recommended Static or

ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
∆Vswitch

ÎÎÎ
— Channel On 0 600 0 — 600 0 300 mV

ÎÎ ÎÎ
Dynamic Voltage Across
the Switch** (Figure 5)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
Output Offset Voltage
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VOO — Vin = 0 V, No Load — — — 10 — — — µV

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ON Resistance v
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
Ron

ÎÎÎ
5.0 ∆Vswitch 500 mV**, — 800 — 250 1050 — 1200 Ω

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎ
10
15
Vin = VIL or VIH
(Control), and Vin =
0 to VDD (Switch)
—
—
400
220
—
—
120
80
500
280
—
—
520
300

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
∆ON Resistance Between

ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
∆Ron

ÎÎÎ
5.0 — 70 — 25 70 — 135 Ω

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Any Two Channels in the

ÎÎ
ÎÎÎÎÎÎÎ
Same Package

ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎ
10
15
—
—
50
45
—
—
10
10
50
45
—
—
95
65

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — ± 100 — ± 0.05 ± 100 — ± 1000 nA
Current (Figure 10) (Control) Channel to

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎ
ÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎ
ÎÎÎ
Channel or Any One
Channel

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Capacitance, Switch I/O CI/O — Inhibit = VDD — — — 10 — — — pF

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
Capacitance, Common O/I CO/I — Inhibit = VDD pF
(MC14051B) — — — 60 — — —

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(MC14052B) — — — 32 — — —

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(MC14053B) — — — 17 — — —

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Capacitance, Feedthrough CI/O — Pins Not Adjacent — — — 0.15 — — — pF
(Channel Off) — Pins Adjacent — — — 0.47 — — —
#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
* For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)

MC14051B MC14052B MC14053B MOTOROLA CMOS LOGIC DATA

6–134
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C) (VEE

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VSS unless otherwise indicated)
VDD – VEE Typ #

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc All Types Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Propagation Delay Times (Figure 6) tPLH, tPHL ns
Switch Input to Switch Output (RL = 10 kΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MC14051

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns 5.0 35 90
tPLH, tPHL = (0.08 ns/pF) CL + 11 ns 10 15 40

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns 15 12 30

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MC14052 ns
tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns 5.0 30 75

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns 10 12 30

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns 15 10 25

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MC14053 ns
tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns 5.0 25 65

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns 10 8.0 20
tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns 15 6.0 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Inhibit to Output (RL = 10 kΩ, VEE = VSS)

ÎÎÎÎÎ
ÎÎÎ
Output “1” or “0” to High Impedance, or
tPHZ, tPLZ,
tPZH, tPZL
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
High Impedance to “1” or “0” Level
MC14051B 5.0 350 700

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
10 170 340

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
15

ÎÎÎÎÎ
140

ÎÎÎÎÎ
280
MC14052B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
5.0
10
300
155
600
310
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
15 125 250

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MC14053B 5.0 275 550 ns
10 140 280

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
15 110 220

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Control Input to Output (RL = 10 kΩ, VEE = VSS) tPLH, tPHL ns
MC14051B 5.0 360 720

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
10 160 320

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
15 120 240
MC14052B 5.0 325 650 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
10
15
130
90
260
180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MC14053B 5.0 300 600 ns
10 120 240

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
15 80 160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Second Harmonic Distortion — 10 0.07 — %
(RL = 10KΩ, f = 1 kHz) Vin = 5 VPP

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Bandwidth (Figure 7)
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF
BW 10 17 — MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
20 Log (Vout/Vin) = – 3 dB)
Off Channel Feedthrough Attenuation (Figure 7) — 10 – 50 — dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p

ÎÎÎÎÎ
fin = 4.5 MHz — MC14051B
fin = 30 MHz — MC14052B
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
fin = 55 MHz — MC14053B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Channel Separation (Figure 8) — 10 – 50 — dB
(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
fin = 3.0 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Crosstalk, Control Input to Common O/I (Figure 9) — 10 75 — mV

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(R1 = 1 kΩ, RL = 10 kΩ
Control tTLH = tTHL = 20 ns, Inhibit = VSS)
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs
must be left open.

MOTOROLA CMOS LOGIC DATA MC14051B MC14052B MC14053B

6–135
 VDD VDD V
DD
IN/OUT OUT/IN

VEE

VDD

LEVEL
CONVERTED
IN/OUT OUT/IN
CONTROL

CONTROL
VEE

Figure 1. Switch Circuit Schematic

TRUTH TABLE 16 VDD

Control Inputs INH 6 BINARY TO 1–OF–8

Select ON Switches A 11 LEVEL
DECODER WITH
B 10 CONVERTER
Inhibit C* B A MC14051B MC14052B MC14053B C 9 INHIBIT
0 0 0 0 X0 Y0 X0 Z0 Y0 X0
0 0 0 1 X1 Y1 X1 Z0 Y0 X1 8 VSS 7 VEE
X0 13
0 0 1 0 X2 Y2 X2 Z0 Y1 X0
0 0 1 1 X3 Y3 X3 Z0 Y1 X1 X1 14
X2 15
0 1 0 0 X4 Z1 Y0 X0
0 1 0 1 X5 Z1 Y0 X1 X3 12 3 X

0 1 1 0 X6 Z1 Y1 X0 X4 1
0 1 1 1 X7 Z1 Y1 X1 X5 5
1 x x x None None None X6 2
* Not applicable for MC14052 X7 4
x = Don’t Care
Figure 2. MC14051B Functional Diagram

16 VDD
16 VDD
INH 6 BINARY TO 1–OF–4
LEVEL
A 10 DECODER WITH INH 6 BINARY TO 1–OF–2
CONVERTER A 11 LEVEL
B 9 INHIBIT DECODER WITH
B 10 CONVERTER
C 9 INHIBIT
8 VSS 7 VEE
X0 12 8 VSS 7 VEE
X1 14
13 X
X2 15 X0 12
14 X
X3 11 X1 13
Y0 1 Y0 2
15 Y
Y1 5 Y1 1
3 Y
Y2 2 Z0 5
4 Z
Y3 4 Z1 3

Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram

MC14051B MC14052B MC14053B MOTOROLA CMOS LOGIC DATA

6–136
 TEST CIRCUITS

ON SWITCH

CONTROL A
PULSE
SECTION B
GENERATOR
OF IC C
LOAD Vout
V CL
INH RL

SOURCE

VDD VEE VEE VDD

Figure 5. ∆V Across Switch Figure 6. Propagation Delay Times,

Control and Inhibit to Output

A, B, and C inputs used to turn ON or OFF

the switch under test.

A RL
B A
C B ON
Vout
C
VSS INH RL CL = 50 pF
INH OFF
Vout
Vin RL CL = 50 pF

VDD – VEE
2 VDD – VEE Vin
2

Figure 7. Bandwidth and Off–Channel Figure 8. Channel Separation

Feedthrough Attenuation (Adjacent Channels Used For Setup)

OFF CHANNEL UNDER TEST

VDD
VEE
A CONTROL
B SECTION OTHER
C CHANNEL(S)
Vout OF IC VEE

INH RL CL = 50 pF VDD

R1
VEE
COMMON
VDD

Figure 9. Crosstalk, Control Input to Figure 10. Off Channel Leakage

Common O/I

NOTE: See also Figures 7 and 8 on Page 6–51.

MOTOROLA CMOS LOGIC DATA MC14051B MC14052B MC14053B

6–137
 VDD KEITHLEY 160
DIGITAL
MULTIMETER
10 k

1 kΩ
VDD RANGE X–Y
PLOTTER
VEE = VSS

Figure 11. Channel Resistance (RON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTICS

350 350

300 300
R ON , “ON” RESISTANCE (OHMS)

R ON , “ON” RESISTANCE (OHMS)

250 250

200 200

150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C – 55°C
50 50

0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 7.5 V, VEE = – 7.5 V Figure 13. VDD = 5.0 V, VEE = – 5.0 V

700 350
TA = 25°C
600 300
R ON , “ON” RESISTANCE (OHMS)
RON , “ON” RESISTANCE (OHMS)

500 250 VDD = 2.5 V

400 200

300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V

100 – 55°C 50

0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)
Figure 14. VDD = 2.5 V, VEE = – 2.5 V Figure 15. Comparison at 25°C, VDD = – VEE

PIN ASSIGMENT
MC14051B MC14052B MC14053B
X4 1 16 VDD Y0 1 16 VDD Y1 1 16 VDD
X6 2 15 X2 Y2 2 15 X2 Y0 2 15 Y
X 3 14 X1 Y 3 14 X1 Z1 3 14 X
X7 4 13 X0 Y3 4 13 X Z 4 13 X1
X5 5 12 X3 Y1 5 12 X0 Z0 5 12 X0
INH 6 11 A INH 6 11 X3 INH 6 11 A
VEE 7 10 B VEE 7 10 A VEE 7 10 B
VSS 8 9 C VSS 8 9 B VSS 8 9 C

MC14051B MC14052B MC14053B MOTOROLA CMOS LOGIC DATA

6–138
 APPLICATIONS INFORMATION

Figure A illustrates use of the on–chip level converter de-
tailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control sig-
nal is used to directly control a 9 Vp–p analog signal.
The digital control logic levels are determined by V DD and
V SS. The V DD voltage is the logic high voltage; the V SS volt-
age is logic low. For the example, V DD = + 5 V = logic high at
the control inputs; V SS = GND = 0 V = logic low.
The maximum analog signal level is determined by V DD
and V EE. The V DD voltage determines the maximum recom-
mended peak above V SS. The V EE voltage determines the
maximum swing below V SS. For the example, V DD – V SS =
5 V maximum swing above V SS ; V SS – V EE = 5 V maximum
swing below VSS. The example shows a ± 4.5 V signal which
allows a 1/2 volt margin at each peak. If voltage transients
above V DD and/or below V EE are anticipated on the analog
channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.
The absolute maximum potential difference between V DD
and V EE is 18.0 V. Most parameters are specified up to 15 V
which is the recommended maximum difference between
V DD and V EE.
Balanced supplies are not required. However, V SS must
be greater than or equal to V EE. For example, V DD = + 10 V,
V SS = + 5 V, and V EE – 3 V is acceptable. See the Table
below.

+5 V –5 V

VDD VSS VEE

+ 4.5 V

9 Vp–p SWITCH
ANALOG SIGNAL I/O COMMON 9 Vp–p
GND
+5 V MC14051B O/I ANALOG SIGNAL
MC14052B
MC14053B
– 4.5 V
EXTERNAL 0–TO–5 V DIGITAL INHIBIT,
CMOS A, B, C
CONTROL SIGNALS
DIGITAL
CIRCUITRY

Figure A. Application Example

VDD VDD

DX DX

ANALOG COMMON
I/O O/I
DX DX

VEE VEE

Figure B. External Germanium or Schottky Clipping Diodes

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
POSSIBLE SUPPLY CONNECTIONS

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Control Inputs

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
VDD VSS VEE Logic High/Logic Low Maximum Analog Signal Range
In Volts In Volts In Volts In Volts In Volts

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
+8

ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎ
+5
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
0

ÎÎÎÎÎÎÎÎÎÎ
0
–8

– 12
+ 8/0

+ 5/0
+ 8 to – 8 = 16 Vp–p

+ 5 to – 12 = 17 Vp–p

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
+5 0 0 + 5/0 + 5 to 0 = 5 Vp–p

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
+5 0 –5 + 5/0 + 5 to – 5 = 10 Vp–p

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
+ 10 +5 –5 + 10/ + 5 + 10 to – 5 = 15 Vp–p

MOTOROLA CMOS LOGIC DATA MC14051B MC14052B MC14053B

6–139
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14060B
14-Bit Binary Counter and
Oscillator L SUFFIX
CERAMIC
The MC14060B is a 14–stage binary ripple counter with an on–chip CASE 620
oscillator buffer. The oscillator configuration allows design of either RC or
crystal oscillator circuits. Also included on the chip is a reset function which
places all outputs into the zero state and disables the oscillator. A negative P SUFFIX
transition on Clock will advance the counter to the next state. Schmitt trigger PLASTIC
action on the input line permits very slow input rise and fall times. CASE 648
Applications include time delay circuits, counter controls, and frequency
dividing circuits.
• Fully static operation D SUFFIX
SOIC
• Diode Protection on All Inputs CASE 751B
• Supply Voltage Range = 3.0 V to 18 V
• Capable of Driving Two Low–power TTL Loads or One Low–power ORDERING INFORMATION
Schottky TTL Load Over the Rated Temperature Range MC14XXXBCP Plastic
• Buffered Outputs Available from Stages 4 Through 10 and MC14XXXBCL Ceramic
12 Through 14 MC14XXXBD SOIC
• Common Reset Line TA = – 55° to 125°C for all packages.
• Pin–for–Pin Replacement for CD4060B

TRUTH TABLE PIN ASSIGNMENT

Clock Reset Output State
Q12 1 16 VDD
L No Change
L Advance to next state Q13 2 15 Q10
X H All Outputs are low
Q14 3 14 Q8
X = Don’t Care
Q6 4 13 Q9
Q5 5 12 RESET
Q7 6 11 CLOCK
Q4 7 10 OUT 1
VSS 8 9 OUT 2

LOGIC DIAGRAM
OUT 2
9 Q4 Q5 Q12 Q13 Q14
OUT 1 7 5 1 2 3
10
CLOCK
11 C Q C Q C Q C Q C Q C Q

C Q C Q C Q C Q C Q C Q
R R R R R R

RESET
12
Q6 = PIN 4 Q8 = PIN 14 Q10 = PIN 15 VDD = PIN 16
Q7 = PIN 6 Q9 = PIN 13 VSS = PIN 8

MC14060B MOTOROLA CMOS LOGIC DATA

6–140
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit This device contains protection circuitry to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VDD

ÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ± 10
Iin, Iout Input or Output Current (DC or Transient), mA any voltage higher than maximum rated volt-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
per Pin ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW to the range VSS (Vin or Vout) VDD.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C or VDD). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages – 12 mW/_C From 100_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎ
ÎÎÎ
Î
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
VDD – 55_C 25_C 125_C
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Characteristic Symbol Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 V
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — V
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Input Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
“0” Level VIL
15 14.95 — 14.95 15 — 14.95 —
V

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 4.5 or 0.5 V) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 V) 10 — 3.0 — 4.50 3.0 — 3.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VO = 13.5 or 1.5 V)

ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ

ÎÎÎÎ
(VO = 0.5 or 4.5 V) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
“1” Level VIH
15

5.0
—

3.5
4.0

—
—

3.5
6.75

2.75
4.0

—
—

3.5
4.0

— V

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 1.0 or 9.0 V) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 V) 15 11.0 — 11.0 8.25 — 11.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Input Voltage
ÎÎÎÎ
(VO = 4.5 Vdc)ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
“0” Level
(For Input 11ÎÎÎ
ÎÎÎ
VIL
5.0 — 1.0 — 2.25 1.0 — 1.0
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 9.0 Vdc) and Output 10) 10 — 2.0 — 4.50 2.0 — 2.0
(VO = 13.5 Vdc) 15 — 2.5 — 6.75 2.5 — 2.5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
“1” Level VIH 5.0
10
4.0
8.0
—
—
4.0
8.0
2.75
5.50
—
—
4.0
8.0
—
—
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 1.5 Vdc) 15 12.5 — 12.5 8.25 — 12.5 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Output Drive Current IOH mA

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOH = 2.5 V) (Except Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 V) Pins 9 and 10) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOH = 9.5 V) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 V)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
15

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎ
– 3.4

ÎÎÎÎ
– 8.8

ÎÎÎ
—

ÎÎÎÎ
– 2.4

ÎÎÎ
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.4 V)
(VOL = 0.5 V)
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mA

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOL = 1.5 V) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µA

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µA
(Per Package) 10 — 10 — 0.010 10 — 300

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ 15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
ÎÎÎ
IT 5.0
10
15
IT = (0.25 µA/kHz) f + IDD
IT = (0.54 µA/kHz) f + IDD
IT = (0.85 µA/kHz) f + IDD
µA

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs,
all buffers switching)
# Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.

MOTOROLA CMOS LOGIC DATA MC14060B

6–141
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time (Counter Outputs) tTLH 5.0 — 40 200 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 25 100
15 — 20 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time (Counter Outputs) tTHL 5.0 — 50 200 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 30 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 20 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH 5.0 — 415 740 ns
Clock to Q4 tPHL 10 — 175 300

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 125 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q14 5.0 — 1.5 2.7 µs
10 — 0.7 1.3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width twH
15
5.0
—
100
0.4
65
1.0
— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 40 30 —
15 30 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
fφ 5.0
10
—
—
5
14
3.5
8
MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 17 12

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Clock Rise and Fall Time tTLH 5.0 ns
tTHL 10 No Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw 5.0
10
15
120
60
40
40
15
10
—
—
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPHL 5.0 — 170 350 ns
Reset to On 10 — 80 160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 60 100
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD
VDD

PULSE CLOCK
500 µF ID 0.01 µF Q4
GENERATOR
NC OUT1 Q5
NC OUT2
Qn CL
R CL
PULSE CLOCK
Q4 VSS CL
GENERATOR
NC OUT1 Q5
NC OUT2 Qn CL
R 20 ns 20 ns
CL
VSS CL 90%
CLOCK
50%
10%
tWH
20 ns 20 ns tPLH tPHL
VDD
90% 90%
50% 50%
CLOCK 10% Q
VSS 10%
50% DUTY CYCLE tTLH tTHL

Figure 1. Power Dissipation Test Circuit Figure 2. Switching Time Test Circuit
and Waveform and Waveforms

MC14060B MOTOROLA CMOS LOGIC DATA

6–142
 CLOCK 11
f [ 2.3 R1tcCtc
if 1 kHz ≤ f ≤ 100 kHz
RESET 10 OUT 1 9 OUT 2 and 2Rtc < RS < 10Rtc
Rtc (f in Hz, R in ohms, C in farads)
The formula may vary for other frequencies. Recommended
maximum value for the resistors in 1 MΩ.
RS Ctc

Figure 3. Oscillator Circuit Using RC Configuration

TYPICAL RC OSCILLATOR CHARACTERISTICS

8.0 100
VDD = 10 V
VDD = 15 V 50

f, OSCILLATOR FREQUENCY (kHz)

4.0 f AS A FUNCTION
FREQUENCY DEVIATION (%)

20
OF RTC
0 10 (C = 1000 pF)
(RS ≈ 2RTC)
1.0 V 5
– 4.0
2 f AS A FUNCTION
OF C
– 8.0 1 (RTC = 56 kΩ)
5.0 V
0.5 (RS = 120 k)
– 12
RTC = 56 kΩ RS = 0, f = 10.15 kHz @ VDD = 10, TA = 25°C 0.2
C = 1000 pF RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
– 16 0.1
– 55 – 25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 M
TA, AMBIENT TEMPERATURE (°C) RTC, RESISTANCE (OHMS)
0.0001 0.001 0.01 0.1
C, CAPACITANCE (µF)

Figure 4. RC Oscillator Stability Figure 5. RC Oscillator Frequency as a

Function of RTC and C

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
CLOCK
500 kHz 32 kHz
11

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Circuit Circuit Unit

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Crystal Characteristics
RESET 10 OUT 1 9 OUT 2

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Resonant Frequency 500 32 kHz
18M Equivalent Resistance, RS 1.0 6.2 kΩ

RO ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
External Resistor/Capacitor Values
RO 47 750 kΩ

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
CT 82 82 pF
CS CT CS 20 20 pF

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Frequency Stability
Frequency Changes as a Function

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Figure 6. Typical Crystal Oscillator Circuit
of VDD (TA = 25_C)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD Change from 5.0 V to 10 V + 6.0 + 2.0 ppm
VDD Change from 10 V to 15 V + 2.0 + 2.0 ppm

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Frequency Change as a Function

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
of Temperature (VDD = 10 V)
TA Change from – 55_C to + 100 + 120 ppm

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
+ 25_C Complete Oscillator*
TA Change from + 25_C to

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
– 160 – 560 ppm
+ 125_C Complete Oscillator*
* Complete oscillator includes crystal, capacitors, and resistors.

Figure 7. Typical Data for Crystal Oscillatgor Circuit

MOTOROLA CMOS LOGIC DATA MC14060B

6–143
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14066B

Quad Analog Switch/Quad

Multiplexer L SUFFIX
CERAMIC
The MC14066B consists of four independent switches capable of CASE 632
controlling either digital or analog signals. This quad bilateral switch is useful
in signal gating, chopper, modulator, demodulator and CMOS logic
implementation. P SUFFIX
The MC14066B is designed to be pin–for–pin compatible with the PLASTIC
MC14016B, but has much lower ON resistance. Input voltage swings as CASE 646
large as the full supply voltage can be controlled via each independent
control input.
• Triple Diode Protection on All Control Inputs D SUFFIX
SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 751A
• Linearized Transfer Characteristics
• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical ORDERING INFORMATION
• Pin–for–Pin Replacement for CD4016, CD4016, MC14016B MC14XXXBCP Plastic
• For Lower RON, Use The HC4066 High–Speed CMOS Device MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) TA = – 55° to 125°C for all packages.
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VDD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input Current (DC or Transient), per

ÎÎÎÎÎÎ
ÎÎÎ
Control Pin
± 10 mA
CONTROL 1
13
2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Isw Switch Through Current ± 25 mA 1 OUT 1
IN 1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW 5
CONTROL 2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C 3
4 OUT 2
TL Lead Temperature (8–Second Soldering) 260 _C IN 2
* Maximum Ratings are those values beyond which damage to the may occur. 6
CONTROL 3
†Temperature Derating: 9
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 8 OUT 3
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C IN 3
12
CONTROL 4 10
CIRCUIT SCHEMATIC OUT 4
11
(1/4 OF CIRCUIT SHOWN) IN 4 VDD = PIN 14
VSS = PIN 7

VDD VDD VDD

LOGIC DIAGRAM AND TRUTH TABLE

(1/4 OF DEVICE SHOWN)
VSS
IN/OUT OUT/IN

VDD CONTROL
VDD VDD VDD
Control Switch Logic Diagram Restrictions
CMOS
INPUT 0 = VSS OFF VSS ≤ Vin ≤ VDD
300 Ω VSS ≤ Vout ≤ VDD
1 = VDD ON

VSS VSS

MC14066B MOTOROLA CMOS LOGIC DATA

6–144
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Characteristic

ÎÎÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol

ÎÎ
ÎÎÎ
VDD Test Conditions Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Power Supply Voltage
ÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VDD — 3.0 18 3.0 — 18 3.0 18 V

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Range

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
v ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Quiescent Current Per IDD 5.0 Control Inputs: — 0.25 — 0.005 0.25 — 7.5 µA
Package 10 Vin = VSS or VDD, — 0.5 — 0.010 0.5 — 15

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
v
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
15 Switch I/O: VSS VI/O — 1.0 — 0.015 1.0 — 30

ÎÎ ÎÎ
VDD, and
v ∆Vswitch 500 mV**

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic Plus Quiescent, ÎÎÎ
ID(AV)

ÎÎÎ
5.0
10
TA = 25_C only The
channel component,
Typical
(0.07 µA/kHz) f + IDD
(0.20 µA/kHz) f + IDD
µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Per Package 15 (Vin – Vout)/Ron, is
(0.36 µA/kHz) f + IDD
not included.)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CONTROL INPUTS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Low–Level Input Voltage

ÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
VIL

ÎÎÎ
5.0
10
Ron = per spec,
Ioff = per spec
—
—
1.5
3.0
—
—
2.25
4.50
1.5
3.0
—
—
1.5
3.0
V

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
15 — 4.0 — 6.75 4.0 — 4.0

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
High–Level Input Voltage VIH 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
10 Ioff = per spec 7.0 — 7.0 5.50 — 7.0 —

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
15 11 — 11 8.25 — 11 —

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHES IN AND OUT (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Recommended Peak–to– VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD Vp–p

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Peak Voltage Into or Out
of the Switch

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Recommended Static or
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
∆Vswitch

ÎÎÎ
— Channel On 0 600 0 — 600 0 300 mV

ÎÎ ÎÎ
Dynamic Voltage Across
the Switch** (Figure 1)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Output Offset Voltage
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VOO — Vin = 0 V, No Load — — — 10 — — — µV

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ON Resistance

ÎÎÎ
v
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
Ron

ÎÎÎ
5.0 ∆Vswitch 500 mV**, — 800 — 250 1050 — 1200 Ω

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎ
10
15
Vin = VIL or VIH
(Control), and Vin =
0 to VDD (Switch)
—
—
400
220
—
—
120
80
500
280
—
—
520
300

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
∆ON Resistance Between
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
∆Ron

ÎÎÎ
5.0 — 70 — 25 70 — 135 Ω
Any Two Channels

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
in the Same Package
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎ
10
15
—
—
50
45
—
—
10
10
50
45
—
—
95
65

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — ± 100 — ± 0.05 ± 100 — ± 1000 nA
Current (Figure 6) (Control) Channel to

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎ
ÎÎÎ
Channel or Any One
Channel

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Capacitance, Switch I/O CI/O — Switch Off — — — 10 15 — — pF

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Capacitance, Feedthrough CI/O — — — — 0.47 — — — pF
(Switch Off) —
#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
** For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)

MOTOROLA CMOS LOGIC DATA MC14066B

6–145
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C unless otherwise noted.)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Times VSS = 0 Vdc tPLH, tPHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input to Output (RL = 10 kΩ)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns

ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns
tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns
5.0
10
15
—
—
—
20
10
7.0
40
20
15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Control to Output (RL = 1 kΩ) (Figure 2)

ÎÎÎÎ
ÎÎÎ
Output “1” to High Impedance
tPHZ
5.0 — 40 80
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 35 70
15 — 30 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Output “0” to High Impedance

ÎÎÎÎ
ÎÎÎ
tPLZ 5.0
10
—
—
40
35
80
70
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 30 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
High Impedance to Output “1” tPZH 5.0 — 60 120 ns
10 — 20 40

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 15 30

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
High Impedance to Output “0”

ÎÎÎÎ
ÎÎÎ
tPZL 5.0
10
15
—
—
—
60
20
15
120
40
30
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Second Harmonic Distortion

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
VSS = – 5 Vdc — 5.0 — 0.1 — %

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
RL = 10 kΩ, f = 1.0 kHz)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Bandwidth (Switch ON) (Figure 3) VSS = – 5 Vdc — 5.0 — 65 — MHz
(RL = 1 kΩ, 20 Log (Vout/Vin) = – 3 dB, CL = 50 pF,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Vin = 5 Vp–p)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Feedthrough Attenuation (Switch OFF) VSS = – 5 Vdc — 5.0 — – 50 — dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Vin = 5 Vp–p, RL = 1 kΩ, fin = 1.0 MHz) (Figure 3)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Channel Separation (Figure 4) VSS = – 5 Vdc — 5.0 — – 50 — dB
(Vin = 5 Vp–p, RL = 1 kΩ, fin = 8.0 MHz)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Switch A ON, Switch B OFF)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Crosstalk, Control Input to Signal Output (Figure 5) mVp–p

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VSS = – 5 Vdc — 5.0 — 300 —
(R1 = 1 kΩ, RL = 10 kΩ, Control tTLH = tTHL = 20 ns)
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated IN 1 1 14 VDD
voltages to this high-impedance circuit. For proper operation, Vin and OUT 1 2 13 CONTROL 1
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage OUT 2 3 12 CONTROL 4
level (e.g., either VSS or VDD). Unused outputs must be left open. IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3

MC14066B MOTOROLA CMOS LOGIC DATA

6–146
 TEST CIRCUITS

Vout
VC
RL CL
ON SWITCH
Vin Vx
CONTROL 20 ns
SECTION VDD
90%
OF IC VC 50%
10%
tPZH VSS
tPHZ
LOAD 90%
V Vout Vin = VDD
10%
tPZL tPLZ Vx = VSS
90%
Vout Vin = VSS
SOURCE 10% Vx = VDD

Figure 1. ∆V Across Switch Figure 2. Turn–On Delay Time Test Circuit

and Waveforms

VDD – VSS
VC = VDD FOR BANDWIDTH TEST 2
VC = VSS FOR FEEDTHROUGH TEST

VDD – VSS Vin

2
RL CL
VDD
Vin Vout

RL CL

VC
RL CL
VSS
VDD VSS

Figure 3. Bandwidth and Figure 4. Channel Separation

Feedthrough Attenuation

OFF CHANNEL UNDER TEST

VDD
Vin
A
Vout VSS
1k CONTROL
RL CL = 50 pF SECTION
10 k OF IC
VSS

VC = – 5.0 V TO + 5.0 V SWING VDD

Figure 5. Crosstalk, Figure 6. Off Channel Leakage

Control to Output

MOTOROLA CMOS LOGIC DATA MC14066B

6–147
 VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k

1 kΩ
VDD RANGE X–Y
PLOTTER
VSS

Figure 7. Channel Resistance (RON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTICS

350 350

300 300
R ON , “ON” RESISTANCE (OHMS)

R ON , “ON” RESISTANCE (OHMS)

250 250

200 200

150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C – 55°C
50 50

0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)

Figure 8. VDD = 7.5 V, VSS = – 7.5 V Figure 9. VDD = 5.0 V, VSS = – 5.0 V

700 350
TA = 25°C
600 300
RON , “ON” RESISTANCE (OHMS)
R ON , “ON” RESISTANCE (OHMS)

500 250 VDD = 2.5 V

400 200

300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V

100 – 55°C 50

0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)

Figure 10. VDD = 2.5 V, VSS = – 2.5 V Figure 11. Comparison at 25°C, VDD = – VSS

MC14066B MOTOROLA CMOS LOGIC DATA

6–148
 APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Switch. The 0–
to–5 volt digital control signal is used to directly control a
5 volt peak–to–peak analog signal.
The digital control logic levels are determined by V DD and
V SS. The V DD voltage is the logic high voltage, the V SS volt-
age is logic low. For the example, V DD = + 5 V = logic high at
the control inputs; V SS = GND = 0 V = logic low.
The maximum analog signal level is determined by V DD
and VSS. The analog voltage must not swing higher than V DD
or lower than V SS.
The example shows a 5 volt peak–to–peak signal which
allows no margin at either peak. If voltage transients above
V DD and/or below V SS are anticipated on the analog chan-
nels, external diodes (Dx) are recommended as shown in
Figure B. These diodes should be small signal types able to
absorb the maximum anticipated current surges during
clipping.
The absolute maximum potential difference between V DD
and V SS is 18.0 volts. Most parameters are specified up to
15 volts which is the recommended maximum difference
between V DD and V SS.

+5 V

VDD VSS

+ 5.0 V

5 Vp–p SWITCH
ANALOG SIGNAL IN SWITCH 5 Vp–p
+ 2.5 V
+5 V OUT ANALOG SIGNAL

GND
EXTERNAL 0–TO–5 V DIGITAL MC14066B
CMOS
CONTROL SIGNALS
DIGITAL
CIRCUITRY

Figure A. Application Example

VDD VDD

DX DX

SWITCH SWITCH
IN OUT
DX DX

VSS VSS

Figure B. External Germanium or Schottky Clipping Diodes

MOTOROLA CMOS LOGIC DATA MC14066B

6–149
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14067B
MC14097B
Analog
Multiplexers/Demultiplexers

The MC14067 and MC14097 multiplexers/demultiplexers are digitally L SUFFIX

controlled analog switches featuring low ON resistance and very low CERAMIC
leakage current. These devices can be used in either digital or analog CASE 623
applications.
The MC14067 is a 16–channel multiplexer/demultiplexer with an inhibit
and four binary control inputs A, B, C, and D. These control inputs select P SUFFIX
1–of–16 channels by turning ON the appropriate analog switch (see PLASTIC
MC14067 truth table.) CASE 709
The MC14097 is a differential 8–channel multiplexer/demultiplexer with an
inhibit and three binary control inputs A, B, and C. These control inputs
select 1 of 8 pairs of channels by turning ON the appropriate analog switches DW SUFFIX
(see MC14097 truth table). SOIC
• Low OFF Leakage Current CASE 751E
• Matched Channel Resistance
ORDERING INFORMATION
• Low Quiescent Power Consumption
MC14XXXBCP Plastic
• Low Crosstalk Between Channels MC14XXXBCL Ceramic
• Wide Operating Voltage Range: 3 to 18 V MC14XXXBDW SOIC
• Low Noise TA = – 55° to 125°C for all packages.
• Pin for Pin Replacement for CD4067B and CD4097B

MC14067B MC14097B
16–Channel Analog Dual 8–Channel Analog
Multiplexer/Demultiplexer Multiplexer/Demultiplexer

15 INHIBIT 13 INHIBIT
10 A 10 A
CONTROLS
CONTROLS 11 B 11 B
14 C 14 C
13 D
9 X0 9 X0
8 X1 8 X1
7 X2 7 X2
6 X3 6 X3
X 1
5 X4 5 X4
COMMON
4 X5 X 1 4 X5
OUT/IN
3 X6 3 X6
SWITCHES 2 X7 SWITCHES 2 X7 COMMONS
IN/OUT 23 X8 IN/OUT 23 Y0 OUT/IN
22 X9 22 Y1
21 X10 21 Y2
20 X11 20 Y3
Y 17
19 X12 19 Y4
18 X13 18 Y5
17 X14 VDD = PIN 24 16 Y6
16 X15 VSS = PIN 12 15 Y7

MC14067B MC14097B MOTOROLA CMOS LOGIC DATA

6–150
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit This device contains protection circuitry to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
VDD

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin Input Current (DC or Transient), ± 10 mA any voltage higher than maximum rated volt-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Control Pin ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Isw Switch Through Current ± 25 mA to the range VSS (Vin or Vout) VDD.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be tied to an
PD Power Dissipation, per Package† 500 mW
appropriate logic voltage level (e.g., either VSS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C or VDD). Unused outputs must be left open.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MC14067 TRUTH TABLE MC14097 TRUTH TABLE

Control Inputs Control Inputs
Selected Selected
A B C D Inh Channel A B C Inh Channels

X X X X 1 None X X X 1 None
0 0 0 0 0 X0 0 0 0 0 X0 Y0
1 0 0 0 0 X1 1 0 0 0 X1 Y1
0 1 0 0 0 X2 0 1 0 0 X2 Y2
1 1 0 0 0 X3 1 1 0 0 X3 Y3
0 0 1 0 0 X4 0 0 1 0 X4 Y4
1 0 1 0 0 X5 1 0 1 0 X5 Y5
0 1 1 0 0 X6 0 1 1 0 X6 Y6
1 1 1 0 X7 Y7
1 1 1 0 0 X7
0 0 0 1 0 X8 X = Don’t Care
1 0 0 1 0 X9
0 1 0 1 0 X10
1 1 0 1 0 X11
0 0 1 1 0 X12
1 0 1 1 0 X13
0 1 1 1 0 X14
1 1 1 1 0 X15

MC14067 FUNCTIONAL DIAGRAM MC14097 FUNCTIONAL DIAGRAM

INHIBIT
A INHIBIT
CONTROL CONTROL A
B 1–OF–16 DECODER 1–OF–8 DECODER
INPUTS C INPUTS B
D C

X0 X0
X1 X1
X2 X2
X3 X X3 X
X4 IN/OUT X4
X5 X5 OUT/IN
X6 X6
X X7 X X7
IN/OUT X8 Y0
X9 OUT/IN Y1
X10 Y2
X11 Y Y3 Y
X12 IN/OUT Y4 OUT/IN
X13 Y5
X14 Y6
X15 Y7

MOTOROLA CMOS LOGIC DATA MC14067B MC14097B

6–151
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎ – 55°C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Characteristic

ÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol

ÎÎ
ÎÎÎ
VDD Test Conditions Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SUPPLY REQUIREMENTS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Power Supply Voltage
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
ÎÎ
ÎÎÎ — 3.0 18 3.0 — 18 3.0 18 V

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Range

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎv ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Quiescent Current Per IDD 5.0 Control Inputs: Vin = — 5.0 — 0.005 5.0 — 150 µA
Package 10 VSS or VDD, — 10 — 0.010 10 — 300

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎ
v
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
15 Switch I/O: VSS VI/O — 20 — 0.015 20 — 600

ÎÎ ÎÎ
VDD, and
v ∆Vswitch 500 mV**

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Total Supply Current

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ID(AV)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5.0 TA = 25_C only (The µA

ÎÎ
(0.07 µA/kHz) f + IDD
(Dynamic Plus 10 channel component,
Typical (0.20 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quiescent, 15 (Vin – Vout)/Ron, is
(0.36 µA/kHz) f + IDD
Per Package not included.)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
CONTROL INPUTS — INHIBIT, A, B, C, D (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
Low–Level Input Voltage

ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
VIL
ÎÎÎ
ÎÎ
ÎÎÎ
5.0
10
15
Ron = per spec,
Ioff = per spec
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
V

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
High–Level Input Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
VIH
ÎÎÎ
ÎÎÎ
5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
10 Ioff = per spec 7.0 — 7.0 5.50 — 7.0 —

ÎÎ ÎÎ ÎÎ
15 11 — 11 8.25 — 11 —

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — 1.0 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
Recommended Peak–to– VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD Vp–p
Peak Voltage Into or

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Out of the Switch

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Recommended Static or ∆Vswitch — Channel On 0 600 0 — 600 0 300 mV

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
Dynamic Voltage
Across the Switch’*

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Figure 1)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV
v
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ON Resistance Ron 5.0 ∆Vswitch 500 mV**, — 800 — 250 1050 — 1300 Ω

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
10 Vin = VIL or VIH — 400 — 120 500 — 550
15 (Control), and Vin — 220 — 80 280 — 320

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
0 to VDD (Switch)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
∆ON Resistance Between ∆Ron 5.0 — 70 — 25 70 — 135 Ω
Any Two Channels 10 — 50 — 10 50 — 95

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
in the Same Package
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ 15 — 45 — 10 45 — 65

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Off–Channel Leakage

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎ
Ioff

ÎÎÎ ÎÎÎ
15 Vin = VIL or VIH — ± 100 — ± 0.05 ± 100 — ± 1000 nA

ÎÎ ÎÎ ÎÎ
Current (Figure 2) (Control) Channel to
Channel or Any One

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
Capacitance, Switch I/O ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
CI/O
ÎÎÎ —
Channel
Inhibit = VDD — — — 10 — — — pF

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
Capacitance, Common O/I

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
CO/I
ÎÎÎ
ÎÎ
ÎÎÎ
— Inhibit = VDD
(MC14067B)
(MC14097B)
—
—
—
—
—
—
100
60
—
—
—
—
—
—
pF

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
(Channel Off) ÎÎ
ÎÎÎ
Capacitance, Feedthrough
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎ
CI/O
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
—
—
Pins Not Adjacent
Pins Adjacent
— — — 0.47 — —

Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
— pF

** For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e.
the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)

MC14067B MC14097B MOTOROLA CMOS LOGIC DATA

6–152
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ VDD – VSS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Times tPLH, tPHL ns
Channel Input–to–Channel Output (RL = 200 kΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14067B
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 3) 5.0
10
15
35
15
12
90
40
30

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14097B
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0
10
25
10
65
25
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 7 18

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Control Input–to–Channel Output tPZH, tPZL ns
Channel Turn–On Time (RL = 10 kΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
MC14067B/097B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 4) 5.0
10
15
240
115
75
600
290
190

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
MC14067B/097B ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Channel Turn–Off Time (RL = 300 kΩ)

ÎÎÎÎ
ÎÎÎ
tPHZ, tPLZ ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 4) 5.0 250 625
10 120 300

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 75 190

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Any Pair of Address Inputs to Output tPLH, tPHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC14067B
5.0 280 700

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 115 290

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 85 215

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC14097B ns
(Figure 10) 5.0 250 625

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 100 250

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 75 190

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Second Harmonic Distortion — 10 0.3 — %
(RL = 10 kΩ, f = 1 kHz, Vin = 5 Vp–p)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ON Channel Bandwidth

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
[RL = 1 kΩ, Vin = 1/2 (VDD – VSS) p–p(sine–wave)]
BW MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
20 Log10 (Vout/Vin) = – 3 dB MC14067B (Figure 5) 10 15 —
MC14097B 10 25 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Off Channel Feedthrough Attenuation

ÎÎÎÎ
ÎÎÎ
[RL = 1 kΩ, Vin = 1/2 (VDD–VSS) p–p(sine–wave)]
— 10 – 40 — dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 20 MHz – MC14067B (Figure 5)
fin = 12 MHz – MC14097B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Channel Separation

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
[RL = 1 kΩ, Vin = 1/2 (VDD–VSS) p–p (sine–wave)]
fin = 20 MHz
—

(Figure 6)
10 – 40 — dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
(R1 = 1 kΩ, RL = 10 kΩ, ÎÎÎ
Crosstalk, Control Inputs–to–Common O/I

ÎÎÎÎ
ÎÎÎ
— 10 30 — mV

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Control tr = tf = 20 ns, Inhibit = VSS) (Figure 7)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14067B MC14097B

6–153
 OFF CHANNEL UNDER TEST
ON SWITCH VDD
A VSS
CONTROL
SECTION CONTROL
OF IC SECTION OTHER
OF IC CHANNEL(S) VSS
LOAD
V VDD

SOURCE
VSS
VDD

Figure 1. ∆V Across Switch Figure 2. Off Channel Leakage

MC14067B MC14097B
PIN ASSIGNMENT PIN ASSIGNMENT

X 1 24 VDD X 1 24 VDD
X7 2 23 X8 X7 2 23 Y0
X6 3 22 X9 X6 3 22 Y1
X5 4 21 X10 X5 4 21 Y2
X4 5 20 X11 X4 5 20 Y3
X3 6 19 X12 X3 6 19 Y4

X2 7 18 X13 X2 7 18 Y5
X1 8 17 X14 X1 8 17 Y
X0 9 16 X15 X0 9 16 Y6
A 10 15 INHIBIT A 10 15 Y7
B 11 14 C B 11 14 C
VSS 12 13 D VSS 12 13 INHIBIT

MC14067B MC14097B MOTOROLA CMOS LOGIC DATA

6–154
 VC
PULSE A
B
GENERATOR C
VDD Vout
D
A CL = 50 pF
B INH RL
C
D Vout Vin VX
INH RL CL = 50 pF VDD VSS VSS VDD

Vin 20 ns 20 ns
90%
VC 50%
20 ns 20 ns 10%
VDD
90%
Vin 50% 90% Vin = VDD
10% Vout
VSS 50% VX = VSS
tPLH tPHL
tPZH, tPZL tPHZ, tPLZ
Vout 50%
Vout 50% Vin = VSS
10% VX = VDD

Figure 3. Propagation Delay Test Circuit Figure 4. Turn–On and Delay Turn–Off
and Waveforms Vin to Vout Test Circuit and Waveforms

VDD
A, B, and C inputs used to turn ON or OFF RL
the switch under test. A
B ON
C
A D
B
C INH OFF
D Vout Vout

INH RL CL = 50 pF
RL CL = 50 pF

Vin Vin

Figure 5. Bandwidth and Off–Channel Figure 6. Channel Separation

Feedthrough Attenuation (Adjacent Channels Used for Setup)

A
VC B
C
D Vout
INH RL CL = 50 pF

R1

Figure 7. Crosstalk, Control to Common O/I

MOTOROLA CMOS LOGIC DATA MC14067B MC14097B

6–155
 VA A
VB B
C
D
INH VDD

VDD CL
Vout
KEITHLEY 160
DIGITAL
MULTIMETER
VA 50%
10 k
VDD
1 kΩ
RANGE X–Y VB 50%
PLOTTER
VSS tPHL tPLH

Vout 50%

Figure 8. Channel Resistance (RON) Test Circuit Figure 9. Propagation Delay, Any Pair of
Address Inputs to Output

TYPICAL RESISTANCE CHARACTERISTICS

350 350

300 300
R ON , “ON” RESISTANCE (OHMS)

R ON , “ON” RESISTANCE (OHMS)

250 250

200 200

150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C – 55°C
50 50

0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)

Figure 10. VDD = 7.5 V, VSS = – 7.5 V Figure 11. VDD = 5.0 V, VSS = – 5.0 V

700 350
TA = 25°C
600 300
RON , “ON” RESISTANCE (OHMS)
R ON , “ON” RESISTANCE (OHMS)

500 250 VDD = 2.5 V

400 200

300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V

100 – 55°C 50

0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)

Figure 12. VDD = 2.5 V, VSS = – 2.5 V Figure 13. Comparison at 25°C, VDD = – VSS

MC14067B MC14097B MOTOROLA CMOS LOGIC DATA

6–156
 APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Multiplexer/Demulti-
plexer. The 0–to–5 volt Digital Control signal is used to
directly control a 5 Vp–p analog signal.
The digital control logic levels are determined by VDD and
VSS. The VDD voltage is the logic high voltage; the VSS volt-
age is logic low. For the example. VDD = + 5 V = logic high at
the control inputs; VSS = GND = 0 V = logic low.
The maximum analog signal level is determined by V DD
and V SS. The analog voltage must swing neither higher than
V DD nor lower than V SS. The example shows a 5 V p–p signal
which allows no margin at either peak. If voltage transients
above V DD and/or below V SS are anticipated on the analog
channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.
The absolute maximum potential difference between VDD
and VSS is 18.0 volts. Most parameters are specified up to
15 V which is the recommended maximum difference
between VDD and VSS.

+5 V

VDD VSS

+ 5.0 V

5 Vp–p SWITCH
ANALOG SIGNAL I/O COMMON 5 Vp–p
+ 2.5 V
+5 V O/I ANALOG SIGNAL

GND
MC14067B
EXTERNAL 0–TO–5 V DIGITAL MC14097B
CMOS
CONTROL SIGNALS
DIGITAL
CIRCUITRY

Figure A. Application Example

VDD VDD

DX DX

SWITCH COMMON
I/O O/I
DX DX

VSS VSS

Figure B. External Germanium or Schottky Clipping Diodes

MOTOROLA CMOS LOGIC DATA MC14067B MC14097B

6–157
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure. L SUFFIX
These inverters find primary use where low power dissipation and/or high CERAMIC
noise immunity is desired. Each of the six inverters is a single stage to CASE 632
minimize propagation delays.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–Power TTL Loads or One Low–Power P SUFFIX
Schottky TTL Load Over the Rated Temperature Range PLASTIC
• Triple Diode Protection on All Inputs (see Page 5–2) CASE 646
• Pin–for–Pin Replacement for CD4069UB
• Meets JEDEC UB Specifications

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
D SUFFIX

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) SOIC
CASE 751A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V MC14XXXUBCP Plastic
MC14XXXUBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA MC14XXXUBD SOIC
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering)

†Temperature Derating:
260
* Maximum Ratings are those values beyond which damage to the device may occur.
_C PIN ASSIGNMENT

IN 1 1 14 VDD

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C OUT 1 2 13 IN 6
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C IN 2 3 12 OUT 6
OUT 2 4 11 IN 5
LOGIC DIAGRAM CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN) IN 3 5 10 OUT 5

1 2 VDD OUT 3 6 9 IN 4

VDD = PIN 14 VSS 7 8 OUT 4

3 4 VSS = PIN 7

5 6 INPUT* OUTPUT

9 8

11 10 VSS
* Double diode protection on all
13 12 inputs not shown.

20 ns 20 ns
VDD
VDD
14 90%
PULSE OUTPUT INPUT 50%
10% VSS
GENERATOR INPUT tPHL tPLH
7 VSS CL 90% VOH
OUTPUT 50%
10% VOL

tTHL tTLH

Figure 1. Switching Time Test Circuit and Waveforms

MC14069UB MOTOROLA CMOS LOGIC DATA

6–158
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ
Vin = VDD ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.0

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.0

ÎÎÎÎ
—

ÎÎÎ
1.0
(VO = 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 13.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
2.0
2.5
—
—
4.50
6.75
2.0
2.5
—
—
2.0
2.5

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
4.0

ÎÎÎÎ
—

ÎÎÎ
4.0

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
4.0

ÎÎÎ
—
(VO = 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 1.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
8.0
12.5
—
—
8.0
12.5
5.50
8.25
—
—
8.0
12.5
—
—

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.3 µA/kHz) f + IDD/6 µAdc
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD/6

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Gate) (CL = 50 pF)
ÎÎÎ 15 IT = (0.9 µA/kHz) f + IDD/6

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(CL = 50 pF)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Output Rise and Fall Times**

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns
tTLH,
tTHL 5.0
10
—
—
—
—
—
—
100
50
200
100
—
—
—
—
ns

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
tTLH, tTHL = (0.60 ns/pF) CL + 20 ns

ÎÎÎ
ÎÎÎ
tTLH, tTHL = (0.40 ns/pF) CL + 20 ns
15 — — — 40 80 — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Propagation Delay Times** tPLH, ns
(CL = 50 pF) tPHL

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 20 ns 5.0 — — — 65 125 — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 22 ns 10 — — — 40 75 — —
tPLH, tPHL = (0.26 ns/pF) CL + 17 ns 15 — — — 30 55 — —
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14069UB

6–159
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14070B
CMOS SSI MC14077B
Quad Exclusive “OR” and “NOR” Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P–channel and N–channel
enhancement mode devices in a single monolithic structure. These L SUFFIX
complementary MOS logic gates find primary use where low power CERAMIC
dissipation and/or high noise immunity is desired. CASE 632
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low–Power TTL Loads or One Low–Power P SUFFIX
Schottky TTL Load Over the Rated Temperature Range PLASTIC
CASE 646
• Double Diode Protection on All Inputs
• MC14070B — Replacement for CD4030B and CD4070B Types

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• MC14077B — Replacement for CD4077B Type

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
D SUFFIX
MAXIMUM RATINGS* (Voltages Referenced to VSS) SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
CASE 751A
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VDD

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
ORDERING INFORMATION
MC14XXXBCP Plastic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCL Ceramic
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin
TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C MC14070B MC14077B
QUAD Exclusive OR QUAD Exclusive NOR
* Maximum Ratings are those values beyond which damage to the device may occur.
Gate Gate
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 1 1
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 3 3
2 2
20 ns 20 ns 5 5
4 4
VDD VDD 6 6
90%
50% 8 8
Vin 10% 10 10
IDD VSS
9 9
1/f 12 12
Vin * 50% DUTY CYCLE 11 11
13 13
CL
VDD = PIN 14
* Inverted output on MC14077B only. VSS = PIN 7
(BOTH DEVICES)
Figure 1. Power Dissipation Test Circuit and Waveform

VDD 20 ns 20 ns
PIN ASSIGNMENT
VDD
PULSE 90%
INPUT 50% IN 1A 1 14 VDD
*
GENERATOR 10%
# VSS IN 2A 2 13 IN 2D
CL tPHL tPLH
90% VOH OUTA 3 12 IN 1D
VSS
OUTPUT 50% OUTB 4 11 OUTD
10% VOL
tTHL tTLH IN 1B 5 10 OUTC
* Inverted output on MC14077B only.
IN 2B 6 9 IN 2C
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
VSS 7 8 IN 1C
Figure 2. Switching Time Test Circuit and Waveforms

MC14070B MC14077B MOTOROLA CMOS LOGIC DATA

6–160
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
“0” Level

ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
5.0

ÎÎÎÎ
—

ÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
5.0

ÎÎÎÎ
3.5

ÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
5.0

ÎÎÎÎ
– 3.0

ÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Quiescent Current

ÎÎÎÎ
(Per Package) ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.3 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (0.9 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(CL = 50 pF) ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Output Rise and Fall Times**

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
tTLH,
tTHL
ns

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns 5.0 — — — 100 200 — —
tTLH, tTHL = (0.60 ns/pF) CL + 20 ns 10 — — — 50 100 — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
tTLH, tTHL = (0.40 ns/pF) CL + 20 ns 15 — — — 40 80 — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(CL = 50 pF)
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Propagation Delay Times**

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 130 ns
tPLH,
tPHL
5.0 — — — 175 350 — —
ns

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 57 ns 10 — — — 75 150 — —
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 15 — — — 55 110 — —
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14070B MC14077B

6–161
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14076B
4-Bit D-Type Register
with Three-State Outputs L SUFFIX
CERAMIC
The MC14076B 4–Bit Register consists of four D–type flip–flops operating CASE 620
synchronously from a common clock. OR gated output–disable inputs force
the outputs into a high–impedance state for use in bus organized systems.
OR gated data–disable inputs cause the Q outputs to be fed back to the D P SUFFIX
inputs of the flip–flops. Thus they are inhibited from changing state while the PLASTIC
clocking process remains undisturbed. An asynchronous master root is CASE 648
provided to clear all four flip–flops simultaneously independent of the clock
or disable inputs.
• Three–State Outputs with Gated Control Lines D SUFFIX
SOIC
• Fully Independent Clock Allows Unrestricted Operation for the Two CASE 751B
Modes: Parallel Load and Do Nothing
• Asynchronous Master Reset ORDERING INFORMATION
• Four Bus Buffer Registers MC14XXXBCP Plastic
• Supply Voltage Range = 3.0 Vdc to 18 Vdc MC14XXXBCL Ceramic
• Capable of Driving Two Low–Power TTL Loads or One Low–Power MC14XXXBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
Symbol ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit
BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD
Vin, Vout ÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V 15 RESET Q0 3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
14 D0
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
13 D1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
per Pin
12 D2 Q1 4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW 11 D3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C 10 B DATA
DISABLE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C 9 A Q2 5
7 CLOCK
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: 2 B OUTPUT
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 1 A DISABLE Q3 6
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
VDD = PIN 16
FUNCTION TABLE VSS = PIN 8

Inputs
Data Disable
Data Output
Reset Clock A B D Q
1 X X X X 0
0 0 X X X Qn
0 1 X X Qn
0 X 1 X Qn
0 0 0 0 0
0 0 0 1 1
When either output disable A or B (or both) is (are) high the
output is disabled to the high–impedance state; however
sequential operation of the flip–flops is not affected.
X = Don’t Care.

MC14076B MOTOROLA CMOS LOGIC DATA

6–162
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.75 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.50 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (2.25 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Three–State Leakage Current
ÎÎÎ
ÎÎÎ ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 —
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
± 3.0 µAdc

** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

MOTOROLA CMOS LOGIC DATA MC14076B

6–163
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, tTHL ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, tPHL ns
Clock to Q

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 92 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
5.0
10
15
—
—
—
300
125
90
600
250
180
Reset to Q
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns

ÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 92 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
5.0
10
15
—
—
—
300
125
90
600
250
180

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Propagation Delay, Output “1” or “0”

ÎÎÎÎ
tPHZ, tPLZ 5.0 — 150 300 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
to High Impedance

ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
10
15
—
—
60
45
120
90

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Propagation Delay, High Impedance tPZH, tPZL 5.0 — 200 400 ns
to “1” or “0” Level 10 — 80 160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
15 — 60 120

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 260 130 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
10 110 55 —
15 80 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWH 5.0 370 185 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
10 150 75 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 110 55 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Data Setup Time tsu 5.0 30 15 — ns
10 10 5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
15 4 2 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data Hold Time th 5.0 130 65 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
10 60 30 —
15 50 25 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data Disable Setup Time tsu 5.0 220 110 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
10 80 40 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 50 25 —
µs

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 — — 15
10 — — 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
15 — — 4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 3.6 1.8 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
10 — 9.0 4.5
15 — 12 6.0
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14076B MOTOROLA CMOS LOGIC DATA

6–164
 20 ns 20 ns
OUTPUT VDD
90%
DISABLE 50% 50% 10%
INPUT RISE AND FALL 20 ns A OR B VSS
INPUT 90% VDD tPLZ tPZL
D 50% ANY Q VOH
INFORMATION 90%
10% ≈ 2.5 V @ VDD = 5 V,
VSS OUTPUT
th th 10% 10 V, AND 15 V
tsu tsu tPHZ tPZH ≈ 2 V @ VDD = 5 V
20 ns
VDD ANY Q 90% ≈ 6 V @ VDD = 10 V
90%
50% OUTPUT 10% ≈ 10 V @ VDD = 15 V
10% VSS VOL
tWH tWL
OUTPUTS OUTPUTS OUTPUTS
fcl
tPHL CONNECTED DISCONNECTED CONNECTED
tPLH
VOH
90% ANY Q
Q OUTPUT 50%
10% OUTPUT
VOL
tTLH tTHL OTHER RL = 1 kΩ VDD FOR tPLZ AND tPZL
INPUTS MC14076B VSS FOR tPHZ AND tPZH
RESET = 0
OUTPUT CL
DATA DISABLE A AND B = 0
DISABLE
OUTPUT DISABLE A AND B = 0
A OR B

Figure 1. Timing Diagram Figure 2. Three–State Propagation Delay

Waveshape and Circuit

EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM PIN ASSIGNMENT

{B
OUTPUT DISABLE A 1 OUTPUT A 1 16 VDD
OUTPUT DISABLE B 2
DISABLE 2 15 R
D Q Q0 3 14 D0
D0 14

C Q1 4 13 D1
R Q 3 Q0
DATA DISABLE A 9 Q2 5 12 D2
DATA DISABLE B 10
Q3 6 11 D3

D Q
C 7 10 B
} DATA
DISABLE
D1 13 VSS 8 9 A

C
R Q 4 Q1

CLOCK 7

D Q
D2 12

C
R Q 5 Q2

D Q
D3 11

C
R Q 6 Q3

RESET 15

MOTOROLA CMOS LOGIC DATA MC14076B

6–165
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14093B
Quad 2-Input NAND"
Schmitt Trigger L SUFFIX
CERAMIC
The MC14093B Schmitt trigger is constructed with MOS P–channel and CASE 632
N–channel enhancement mode devices in a single monolithic structure.
These devices find primary use where low power dissipation and/or high
noise immunity is desired. The MC14093B may be used in place of the P SUFFIX
MC14011B quad 2–input NAND gate for enhanced noise immunity or to PLASTIC
“square up” slowly changing waveforms. CASE 646

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–Power TTL Loads or One Low–Power
D SUFFIX
Schottky TTL Load Over the Rated Temperature Range
SOIC
• Triple Diode Protection on All Inputs CASE 751A
• Pin–for–Pin Compatible with CD4093
• Can be Used to Replace MC14011B ORDERING INFORMATION
• Independent Schmitt–Trigger at each Input

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VDD

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
LOGIC DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Iin, Iout

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Input or Output Current (DC or Transient),

ÎÎÎÎÎÎ
ÎÎÎ
per Pin
± 10 mA
1
2
3

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C 5
4
6

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur. 8
9 10
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 12
11
13
EQUIVALENT CIRCUIT SCHEMATIC VDD = PIN 14
(1/4 OF CIRCUIT SHOWN) VSS = PIN 7

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MC14093B MOTOROLA CMOS LOGIC DATA

6–166
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (1.2 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.4 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (3.6 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Hysteresis Voltage

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VH† 5.0
10
0.3
1.2
2.0
3.4
0.3
1.2
1.1
1.7
2.0
3.4
0.3
1.2
2.0
3.4
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 1.6 5.0 1.6 2.1 5.0 1.6 5.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Threshold Voltage Vdc
Positive–Going VT+ 5.0 2.2 3.6 2.2 2.9 3.6 2.2 3.6

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 4.6 7.1 4.6 5.9 7.1 4.6 7.1

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 6.8 10.8 6.8 8.8 10.8 6.8 10.8

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Negative–Going VT– 5.0 0.9 2.8 0.9 1.9 2.8 0.9 2.8 Vdc
10 2.5 5.2 2.5 3.9 5.2 2.5 5.2

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 4.0 7.4 4.0 5.8 7.4 4.0 7.4
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

MOTOROLA CMOS LOGIC DATA MC14093B

6–167
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH 5.0 — 100 200 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 50 100
15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL 5.0 — 100 200 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 50 100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, tPHL 5.0 — 125 250 ns
10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 40 80
#Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD
20 ns 20 ns

14 VDD
INPUT 90%
50%
PULSE OUTPUT 10% VSS
GENERATOR tPHL tPLH
INPUT VOH
7 VSS CL 90%
OUTPUT 50%
10% VOL

tTHL tTLH

Figure 1. Switching Time Test Circuit and Waveforms

VH VDD VH VDD

Vin Vin

VSS VSS

VDD VDD

Vout Vout
VSS VSS

(a) Schmitt Triggers will square up (b) A Schmitt trigger offers maximum
(a) inputs with slow rise and fall times. (b) noise immunity in gate applications.

Figure 2. Typical Schmitt Trigger Applications

MC14093B MOTOROLA CMOS LOGIC DATA

6–168
 14 14
IOH IOL
VGS
Vout Vout

7 7
All unused inputs All unused inputs
connected to ground. VGS connected to ground.

0 10
c a b c 15 Vdc
b
VGS = – 5.0 Vdc a
IOH, DRAIN CURRENT (mAdc)

IOL , DRAIN CURRENT (mAdc)

– 2.0 a 8.0 VGS = 10 Vdc
b
a TA = – 55°C
b TA = + 25°C
– 4.0 6.0 c
b TA = + 125°C
a TA = – 55°C
c b TA = + 25°C
– 6.0 4.0 c TA = + 125°C
– 10 Vdc b c b – 15 Vdc a
– 8.0 2.0 b 5.0 Vdc
c
a a
– 10 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0 2.0 4.0 6.0 8.0 10
VDS, DRAIN VOLTAGE (Vdc) VDS, DRAIN VOLTAGE (Vdc)

Figure 3. Typical Output Source Figure 4. Typical Output Sink

Characteristics Test Circuit Characteristics Test Circuit

VDD PIN ASSIGNMENT

Vout , OUTPUT VOLTAGE (Vdc)

IN 1A 1 14 VDD
IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D
OUTB 4 11 OUTD
IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C
VSS 7 8 IN 1C

0
0 VT– VT+ VDD
VH
Vin, INPUT VOLTAGE (Vdc)

Figure 5. Typical Transfer Characteristics

MOTOROLA CMOS LOGIC DATA MC14093B

6–169
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14094B
8-Stage Shift/Store Register
with Three-State Outputs L SUFFIX
CERAMIC
The MC14094B combines an 8–stage shift register with a data latch for
CASE 620
each stage and a three–state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The QS output data is for use in
high–speed cascaded systems. The Q′S output data is shifted on the P SUFFIX
PLASTIC
following negative clock transition for use in low–speed cascaded systems.
CASE 648
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while strobe
is high.
Outputs of the eight data latches are controlled by three–state buffers D SUFFIX
which are placed in the high–impedance state by a logic Low on Output SOIC
CASE 751B
Enable.
• Three–State Outputs ORDERING INFORMATION
• Capable of Driving Two Low–Power TTL Loads or One Low–Power MC14XXXBCP Plastic
Schottky TTL Load Over the Rated Temperature Range MC14XXXBCL Ceramic
• Input Diode Protection MC14XXXBD SOIC
• Data Latch TA = – 55° to 125°C for all packages.
• Dual Outputs for Data Out on Both Positive and Negative Clock
Transitions
• Useful for Serial–to–Parallel Data Conversion
PIN ASSIGNMENT

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Pin–for–Pin Compatible with CD4094B
STROBE 1 16 VDD

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) OUTPUT
DATA 2 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Symbol Parameter Value Unit ENABLE
CLOCK 3 14 Q5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
Q1 4 13 Q6

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
± 10 Q2 5 12 Q7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Iin, Iout Input or Output Current (DC or Transient), mA
per Pin Q3 6 11 Q8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Î ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎ
ÎÎÎ
500 mW Q4 7 10 Q′S
Tstg

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
Storage Temperature

ÎÎÎÎÎÎÎÎÎ
Lead Temperature (8–Second Soldering)
– 65 to + 150
260
* Maximum Ratings are those values beyond which damage to the device may occur.
_C
_C
VSS 8 9 QS

†Temperature Derating:
This device contains protection circuitry to
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
guard against damage due to high static
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
voltages or electric fields. However, pre-
Parallel Outputs Serial Outputs cautions must be taken to avoid applications of
Output any voltage higher than maximum rated volt-
Clock Enable Strobe Data Q1 QN QS* Q′S ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
0 X X Z Z Q7 No Chg.
to the range VSS v (Vin or Vout) v VDD.
0 X X Z Z No Chg. Q7 Unused inputs must always be tied to an
1 0 X No Chg. No Chg. Q7 No Chg. appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
1 1 0 0 QN–1 Q7 No Chg.
1 1 1 1 QN–1 Q7 No Chg.
1 1 1 No Chg. No Chg. No Chg. Q7
Z = High Impedance X = Don’t Care
* At the positive clock edge, information in the 7th shift register stage is transferred to
Q8 and QS.

MC14094B MOTOROLA CMOS LOGIC DATA

6–170
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (4.1 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (14 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (140 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
3–State Output Leakage Current
ÎÎÎ ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 —
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
± 3.0 µA

** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MOTOROLA CMOS LOGIC DATA MC14094B

6–171
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns tTHL 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns 10 — 50 100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns 15 — 40 80
Propagation Delay Time tPLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Serial out QS tPHL

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 305 ns 5.0 — 350 600
tPLH, tPHL = (0.36 ns/pF) CL + 107 ns 10 — 125 250

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) C L + 82 ns 15 — 95 190

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Serial out Q’S

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 350 ns 5.0 — 230 460
tPLH, tPHL = (0.36 ns/pF) CL + 149 ns 10 — 110 220

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 62 ns 15 — 75 150

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Parallel out

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 375 ns 5.0 — 420 840
tPLH, tPHL = (0.35 ns/pF) CL + 177 ns 10 — 195 390

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 122 ns 15 — 135 270

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Strobe to Parallel out

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 245 ns 5.0 — 290 580
tPLH, tPHL = (0.36 ns/pF) C L + 127 ns 10 — 145 290

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 87 ns 15 — 100 200

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Enable to Output
tPHZ, 5.0 — 140 280

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns
tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns tPZL 10 — 75 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns 15 — 55 110

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ, tPZH = (0.90 ns/pF) CL + 180 ns tPLZ, 5.0 — 225 450
tPLZ, tPZH = (0.36 ns/pF) CL + 77 ns tPZH 10 — 95 190

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ, tPZH = (0.26 ns/pF) CL + 57 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time tsu
15
5.0
—
125
70
60
140
— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data in to Clock 10 55 30 —
15 35 20 —
Hold Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th 5.0 0 – 40 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Data 10 20 – 10 —

ÎÎÎÎ
15 20 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
Clock Pulse Width, High

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
tWH 5.0
10
200
100
100
50
—
—
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 83 40 —
Clock Rise and Fall Time tr(cl) 5 — — 15 µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
tf(cl) 10
15
—
—
—
—
5.0
4.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 2.5 1.25 MHz
10 — 5.0 2.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 6.0 3.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Strobe Pulse Width tWL 5.0 200 100 — ns
10 80 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 70 35 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3–STATE TEST CIRCUIT

FOR tPHZ AND tPZH FOR tPLZ AND tPZL
VSS VDD

O.E.
1k
DATA
OUTPUT
ST
50 pF
CLOCK

MC14094B MOTOROLA CMOS LOGIC DATA

6–172
 BLOCK DIAGRAM

REGISTER STAGE 1 LATCH 1 3–STATE BUFFER 1

CLOCK CLOCK STROBE VDD
2 *
SERIAL CLOCK CLOCK STROBE STROBE 4 Q1
DATA IN

CLOCK CLOCK STROBE

15 *
2 5 Q2
OUTPUT REGISTER STAGE 2 LATCH 2 3–STATE BUFFER 2
ENABLE 3
REGISTER STAGE 3 LATCH 3 3–STATE BUFFER 3 6 Q3

4 7 Q4
REGISTER STAGE 4 LATCH 4 3–STATE BUFFER 4

5 14 Q5
REGISTER STAGE 5 LATCH 5 3–STATE BUFFER 5

6 13 Q6
REGISTER STAGE 6 LATCH 6 3–STATE BUFFER 6

7 12 Q7
REGISTER STAGE 7 LATCH 7 3–STATE BUFFER 7

8 REGISTER STAGE 8 LATCH 8 3–STATE BUFFER 8 11 Q8

CLOCK
CLOCK CLOCK STROBE STROBE
10 Q′S
3 * CLOCK
CLOCK CLOCK
CLOCK
CLOCK

1 STROBE *Input Protection Diodes

* CLOCK
STROBE 9 QS
STROBE

DYNAMIC TIMING DIAGRAM

tWH
tr tf

90%
3 CLOCK 50% 50%
10%
tsu th

2 DATA IN
tWL

1 STROBE

15
OUTPUT 50% 50%
ENABLE
tPLH tPHL tPLH tPHZ tPZH tPLZ tPZL

N Q1 ³ Q7 90% 90%
10%
90%
10%
90%
10% 10%
tTLH tTHL tPLH tPHL

9 QS 50% 50%

tPLH tPHL
10 Q′S 50% 50%

MOTOROLA CMOS LOGIC DATA MC14094B

6–173
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14099B
8-Bit Addressable Latches MC14599B
The MC14099B and MC14599B are 8–bit addressable latches. Data is
entered in serial form when the appropriate latch is addressed (via address
pins A0, A1, A2) and write disable is in the low state. Chip enable must be
high for writing into MC14599B. For the MC14599B the data pin is a L SUFFIX
CERAMIC
bidirectional data port and for the MC14099B the input is a unidirectional
CASE 620
write only port. The Write/Read line controls this port in the MC14599B.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip Enable.
A Master Reset capability is available on both parts. P SUFFIX
PLASTIC
• Serial Data Input CASE 648
• Parallel Output
• Master Reset
• Supply Voltage Range = 3.0 Vdc to 18 Vdc DW SUFFIX
• Capable of Driving Two Low–power TTL Loads or One Low–Power SOIC
Schottky TTL Load over the Rated Temperature Range CASE 751G

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• MC14099B pin for pin compatible with CD4099B
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14099BCP Plastic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit MC14099BCL Ceramic
MC14099BDW SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
PD ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin
Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C L SUFFIX
CERAMIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C CASE 726
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P SUFFIX
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
PLASTIC
MC14099B MC14599B CASE 707
CHIP ENABLE 8
WRITE/READ 10
WRITE DISABLE 4 11
4 9 Q0
WRITE DISABLE
10
Q0 DATA 3 12 Q1 ORDERING INFORMATION
DATA 3 Q1 13
11 8 Q2
5 8 12
Q2 A0 5 8 LATCHES
14 Q3
MC14599BCP Plastic
A0 8 Q3 6 15
A1 6 13 Q4 A1 DECODER
16
Q4 MC14599BCL Ceramic
DECODER LATCHES 14 7 Q5
A2 7 Q5 A2 17
15
Q6 2 1
Q6 TA = – 55° to 125°C for all packages.
2 1 Q7 RESET Q7
RESET VDD = 18
VDD = 16
VSS = 9
VSS = 8
PIN ASSIGNMENT
This device contains protection circuitry to
PIN ASSIGNMENT Q7 1 18 VDD guard against damage due to high static
voltages or electric fields. However, pre-
Q7 1 16 VDD RESET 2 17 Q6 cautions must be taken to avoid applications of
RESET 2 15 Q6 DATA 3 16 Q5 any voltage higher than maximum rated volt-
WRITE ages to this high–impedance circuit. For proper
DATA 3 14 Q5 4 15 Q4 operation, Vin and Vout should be constrained
v v
DISABLE
WRITE to the range VSS (Vin or Vout) VDD.
DISABLE 4 13 Q4 A0 5 14 Q3
Unused inputs must always be tied to an
A0 5 12 Q3 A1 6 13 Q2 appropriate logic voltage level (e.g., either VSS
A1 6 11 Q2 A2 7 12 Q1 or VDD). Unused outputs must be left open.

A2 7 10 Q1 CE 8 11 Q0
VSS 8 9 Q0 WRITE/
VSS 9 10 READ

MC14099B MC14599B MOTOROLA CMOS LOGIC DATA

6–174
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
MC14599B — Data (pin 3) ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 15 22.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ 15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (1.5 µA/kHz) f + IDD
IT = (3.0 µA/kHz) f + IDD
IT = (4.5 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

MOTOROLA CMOS LOGIC DATA MC14099B MC14599B

6–175
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPHL, ns
tPLH

ÎÎÎÎ
Data to Output Q 5.0 — 200 400

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
10
15
—
—
75
50
150
100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Write Disable to Output Q 5.0 — 200 400 ns
10 — 80 160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Output Q
15
5.0
—
—
60
175
120
350 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 80 160
15 — 65 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CE to Output Q (MC14599B only)

ÎÎÎÎ ÎÎÎ 5.0 — 225 450 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
10
15
—
—
100
75
200
150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time, MC14599B only tPHL, ns
Chip Enable, Write/Read to Data tPLH 5.0 — 200 400

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 80 160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 65 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Address to Data 5.0 — 200 400 ns
10 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 75 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Pulse Widths tw(H) ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset tw(L) 5.0 150 75 —
10 75 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 50 25 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Write Disable 5.0 320 160 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 160 80 —
15 120 60 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set Up Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Data to Write Disable ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
tsu
5.0 100 50 —
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 50 25 —
15 35 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Time
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Write Disable to Data 5.0 150 75 —
10 75 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set Up Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu
15
5.0
50
100
25
45
—
— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Address to Write Disable 10 80 30 —
15 40 10 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Removal Time
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ trem 5.0 0 – 80 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Write Disable to Address

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
* The formulas given are for the typical characteristics only at 25_C.
10
15
0
0
– 40
– 40
—
—

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14099B MC14599B MOTOROLA CMOS LOGIC DATA

6–176
 MC14099B
FUNCTION DIAGRAM

RESET 2

9 Q0
DATA 3

WRITE
4
DISABLE
EACH LATCH
TO
OTHER
LATCHES ZERO
SELECT
10 Q1
A0 5
11 Q2
12 Q3
ADDRESS OTHER LATCHES 13 Q4
A1 6
DECODER
14 Q5

15 Q6
A2 7
(M.S.B.) 1 Q7

TRUTH TABLE
Write Addressed Unaddressed CAUTION: To avoid unintentional data changes in the latches, Write
Disable Reset Latch Latches Disable must be active (high) during transitions on the
0 0 Data Qn* address inputs A0, A1, and A2.

0 1 Data Reset†
1 0 Qn* Qn*
1 1 Reset Reset
* Qn is previous state of latch.
†Reset to zero state.

SWITCHING WAVEFORMS
VDD
DATA OR
50%
WRITE DISABLE
VSS
VDD
tPLH tPHL
ADDRESS 50%
90%
VSS
50%
OUTPUT Q tsu tw(L) trem
10%
VDD
tTLH tTHL WRITE
50%
DISABLE
VSS

tw(H) tsu th
VDD VDD
RESET 50% DATA 50%
VSS VSS
tPHL

OUTPUT Q

MOTOROLA CMOS LOGIC DATA MC14099B MC14599B

6–177
 MC14599B
FUNCTION DIAGRAM

RESET 2

11 Q0

DATA 3
VDD

TO
OTHER EACH LATCH
VSS LATCHES

ZERO
SELECT
CHIP
8
ENABLE

WRITE/READ 10

WRITE
4
DISABLE
12 Q1
A0 5
13 Q2
14 Q3
A1 6 ADDRESS OTHER LATCHES 15 Q4
DECODER
16 Q5

A2 7 17 Q6
(M.S.B.) 1 Q7

TRUTH TABLE
Chip Write Addressed Other Data
Enable Write/Read Disable Reset Latch Latches Pin
0 X X 0 * * Z
1 1 0 0 Data * Input
1 1 1 0 * * Z
1 0 X 0 * * Qn
X X X 1 0 0 Z/0
X = Don’t care.
* = No change in state of latch.
Z = High impedance.
Qn = State of addressed latch.

CAUTION: To avoid unintentional data changes in the latches, Write Disable must be active (high) during transitions on
the address inputs A0, A1, and A2.

MC14099B MC14599B MOTOROLA CMOS LOGIC DATA

6–178
 MC14599B
SWITCHING WAVEFORMS

DATA WRITE

Q0 50%

Q7 tPHL tTLH tPHL

90% 90%
10% 10% tPLH
tTHL
tPLH
VDD
RESET
VSS
tw(H)
VDD
CE
VSS

VDD
A2, A1, A0 50%
VSS

VDD
DATA 50%
VSS
tsu tw(L) trem th
tsu VDD
90% 50% 50%
WRITE DISABLE
10% 10%
VSS
20 ns 20 ns

DATA READ

VDD
W/R
VSS
VDD
CE 50%
tPLH, VSS

ÇÇÇÇÇÇÇ
tPHL
VDD

ÇÇÇÇÇÇÇ
DATA 1 50%
VSS
tPLH,
tPHL VDD
A2, A1, A0
VSS

NOTE: 1. Invalid Data Output

2. Reset in LOW State

MOTOROLA CMOS LOGIC DATA MC14099B MC14599B

6–179
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14106B
Hex Schmitt Trigger
The MC14106B hex Schmitt Trigger is constructed with MOS P–channel L SUFFIX
CERAMIC
and N–channel enhancement mode devices in a single monolithic structure.
CASE 632
These devices find primary use where low power dissipation and/or high
noise immunity is desired. The MC14106B may be used in place of the
MC14069UB hex inverter for enhanced noise immunity or to “square up”
slowly changing waveforms. P SUFFIX
PLASTIC
• Increased Hysteresis Voltage Over the MC14584B CASE 646
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range D SUFFIX
• Pin–for–Pin Replacement for CD40106B and MM74C14 SOIC
• Can Be Used to Replace the MC14584B or MC14069UB CASE 751A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCP Plastic
Symbol Parameter Value Unit MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Iin, Iout

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Input or Output Current (DC or Transient),

ÎÎÎÎÎÎ
ÎÎÎ
per Pin
± 10 mA

LOGIC DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C 1 2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur. 3 4
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 5 6
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

9 8

EQUIVALENT CIRCUIT SCHEMATIC

(1/6 OF CIRCUIT SHOWN) 11 10

13 12

VDD = PIN 14
VSS = PIN 7

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MC14106B MOTOROLA CMOS LOGIC DATA

6–180
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ
Vin = VDD ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Hysteresis Voltage VH† 5.0 0.3 2.0 0.3 1.1 2.0 0.3 2.0 Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 1.2 3.4 1.2 1.7 3.4 1.2 3.4
15 1.6 5.0 1.6 2.1 5.0 1.6 5.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
Threshold Voltage

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Positive–Going ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VT+ 5.0
10
2.2
4.6
3.6
7.1
2.2
4.6
2.9
5.9
3.6
7.1
2.2
4.6
3.6
7.1
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Negative–Going ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ VT–
15
5.0
6.8
0.9
10.8
2.8
6.8
0.9
8.8
1.9
10.8
2.8
6.8
0.9
10.8
2.8 Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 2.5 5.2 2.5 3.9 5.2 2.5 5.2
15 4.0 7.4 4.0 5.8 7.4 4.0 7.4

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Output Drive Current

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 2.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Source
IOH
5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input Current

ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Input Capacitance
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Iin
Cin
15
—
—
—
± 0.1
—
—
—
± 0.00001
5.0
± 0.1
7.5
—
—
± 1.0
—
µAdc
pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package)
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
ÎÎÎ
IT 5.0
10
IT = (1.8 µA/kHz) f + IDD
IT = (3.6 µA/kHz) f + IDD
IT = (5.4 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Per Package) 15
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
†VH = VT+ – VT– (But maximum variation of VH is specified as less that VT+ max – VT– min).

MOTOROLA CMOS LOGIC DATA MC14106B

6–181
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH 5.0 — 100 200 ns
10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
15 — 40 80

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL 5.0 — 100 200 ns
10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, tPHL 5.0 — 125 250 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
10 — 50 100
15 — 40 80
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD 20 ns 20 ns
14
INPUT VDD
PULSE OUTPUT 90%
50%
GENERATOR INPUT 10% VSS
7 VSS CL tPHL tPLH
90% VOH
OUTPUT 50%
10%
VOL
tf tr
Figure 1. Switching Time Test Circuit and Waveforms

VDD
Vout , OUTPUT VOLTAGE (Vdc)

0
0 VT– VT+ VDD
VH
Vin, INPUT VOLTAGE (Vdc)

Figure 2. Typical Transfer Characteristics

APPLICATIONS

Vin Vout

VH VDD VH VDD

Vin Vin
VSS VSS

VDD VDD

Vout Vout
VSS VSS

(a) Schmitt Triggers will square up (b) A Schmitt trigger offers maximum
inputs with slow rise and fall times. noise immunity in gate applications.
Figure 3.

MC14106B MOTOROLA CMOS LOGIC DATA

6–182
 VDD VDD

R
tw C
tw
Rs Rs
Vout Vout

C R
VDD
tw = RC IN
VT+

Useful as Pushbutton/Keyboard Debounce Circuit.

Figure 4. Monostable Multivibrator

1
f
R A
Vin Vout
R t1
C
t2
VDD
Vin VT+
VSS
C
[ RC ln VTT)
V
* t1 VDD
– VT+
A

ƪǒ Ǔǒ Ǔƫ
* t2 [ RC ln
VDD – VT –
VDD – VT )
VSS

VT )
[ RC ln VDD – VT – VDD
1
Vout VT+
f VDD – VT ) VT –
VSS
*t1 + t2 & tPHL + tPLH Useful in discriminating against short pulse durations.

Figure 5. Astable Multivibrator Figure 6. Integrator

C
Vin
Vin

R + EDGE

– EDGE C C C
– EDGE + EDGE
VDD Vin

tw R R R
VDD
tw = RC ln
VT+
Useful as an edge detector circuit.

Figure 7. Differentiator Figure 8. Positive Edge Time Delay Circuit

MOTOROLA CMOS LOGIC DATA MC14106B

6–183
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14160B
CMOS MSI MC14161B
MC14162B
Synchronous Presettable 4–Bit Counters
The MC14160B — MC14163B are synchronous programmable counters
MC14163B
constructed with complementary MOS P–Channel and N–Channel en-
hancement mode devices in a single monolithic structure. These counters
are functionally equivalent to the 74160 — 74163 TTL counters.
Two are synchronous programmable BCD counters with asynchronous
and synchronous clear inputs respectively (MC14160B, MC14162B). The L SUFFIX
other two are synchronous programmable 4–bit binary counters with the CERAMIC
asynchronous and synchronous clear respectively (MC14161B, MC14163B). CASE 620
• Internal Look–Ahead for Fast Counting
• Carry Output for N–Bit Cascading
• Synchronously Programmable P SUFFIX
PLASTIC
• Synchronous Counting
CASE 648
• Load Control Line
• Synchronous or Asynchronous Clear
• Positive Edge Clocked

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
D SUFFIX
SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) CASE 751B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
MC14XXXBCP Plastic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V MC14XXXBCL Ceramic
MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
BLOCK DIAGRAM
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur. 7 PE Q1 14
†Temperature Derating:
10 TE
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 1 CLEAR Q2 13
9 LOAD
2 CLOCK Q3 12

This device contains protection circuitry to guard against damage 3 P1

due to high static voltages or electric fields. However, precautions must 4 P2 Q4 11
be taken to avoid applications of any voltage higher than maximum rated
5 P3
voltages to this high-impedance circuit. For proper operation, Vin and CARRY
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. 6 P4
OUT
15
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. VDD = PIN 16
VSS = PIN 8

MC14160B MC14161B MC14162B MC14163B MOTOROLA CMOS LOGIC DATA

6–184
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.56 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.10 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (1.90 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT
CLEAR 1 16 VDD
CLOCK 2 15 CARRY OUT
P1 3 14 Q1
P2 4 13 Q2
P3 5 12 Q3
P4 6 11 Q4
PE 7 10 TE
VSS 8 9 LOAD

MOTOROLA CMOS LOGIC DATA MC14160B MC14161B MC14162B MC14163B

6–185
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns
5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL ns
5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 50 100
15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.9 ns/pF) CL + 305 ns 5.0 — 350 700
tPLH, tPHL = (0.36 ns/pF) CL + 132 ns 10 — 150 300

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 87 ns 15 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Carry Out
tPLH, tPHL = (0.9 ns/pF) CL + 395 ns 5.0 — 440 880

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 167 ns 10 — 185 370

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 112 ns 15 — 125 250
TE to Carry Out

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.9 ns/pF) CL + 225 ns 5.0 — 300 600
tPLH, tPHL = (0.36 ns/pF) CL + 112 ns 10 — 130 260

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 77 ns 15 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clear to Q (MC14160B, MC14161B only)
tPLH, tPHL = (0.9 ns/pF) CL + 110 ns 5.0 — 350 700

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 37 ns

ÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 22 ns
10
15
—
—
150
100
300
200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Times tsu ns
Data to Clock 5.0 320 160 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 130 65 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 90 45 —
Load to Clock

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 5.0 600 300 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 260 130 —
15 180 90 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Enable to Clock (PE or TE)

ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5.0 420 210 —
10 170 85 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
Clear to Clock (MC14162B, MC14163B only)
15 120 60 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5.0 310 155 —
10 110 55 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 70 35 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Times th ns
Clock to Data 5.0 –10 –60 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
10
15
–5.0
0
–25
–15
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Load 5.0 –40 –195 —
10 –10 –80 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 –5.0 –50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to PE 5.0 –40 –175 —
10 –10 –70 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to TE ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15
5.0
0
–150
–40
–280
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 –30 –130 —
15 –20 –80 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Clear (MC14162B, MC14163B only) 5.0 80 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 30 15 —
15 –10 –70 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clear Removal Time (MC14160B, MC14161B only) trem 5.0 90 30 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 65 20 —
15 55 20 —

MC14160B MC14161B MC14162B MC14163B MOTOROLA CMOS LOGIC DATA

6–186
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) (Continued)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clear Pulse Width, Low (MC14160B, MC14161B only) tWL 5.0 200 100 — ns
10 90 45 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 60 30 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width, High tWH 5.0 250 125 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50 —
15 70 35 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Clock Rise and Fall Time

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
tr, tf 5.0
10
15
—
—
—
—
—
—
15
5.0
4.0
ms

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 2.0 1.0 mHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 5.0 2.5
15 — 8.0 4.0
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14160B MC14161B MC14162B MC14163B

6–187
 SWITCHING WAVEFORMS

FUNCTIONAL DESCRIPTION

These counters are fully programmable; that is the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after the
next clock pulse regardless of the levels of the enable inputs.
The clear function for the MC14160B, MC14161B is asynch–
ronous and a low level at the clear input sets all four of the
flip—flop outputs low regardless of the levels of the clock,
load or enable inputs. The clear function for the MC14162B
and MC14163B is synchronous and a low level at the clear
inputs sets all four of the flip—flop outputs low after the next
clock pulse, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modi-
fied easily; decoding the maximum count desired can be ac-
complished with one external NAND gate. The gate output is
connected to the clear input to synchronously clear the
counter to 0000(LLLL).
The carry look—ahead circuitry provides for cascading
counters for n—bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function are
two count—enable inputs and a carry output. Both count—
enable inputs (PE, TE) must be high to count, and enable in-
put TE fed forward to enable the carry output. The carry
output thus enabled will produce a positive output pulse with
a duration approximately equal to the positive portion of the
Q1 output. This positive overflow carry pulse can be used to
enable successive cascaded stages.

MC14160B MC14161B MC14162B MC14163B MOTOROLA CMOS LOGIC DATA

6–188
 MC14160B, MC14162B LOGIC DIAGRAM
(Clear is synchronous for MC14162B)

MOTOROLA CMOS LOGIC DATA MC14160B MC14161B MC14162B MC14163B

6–189
 MC14160B, MC14162B TIMING DIAGRAM

Sequence illustrated in waveforms:

1. Clear outputs to zero.
2. Preset to BCD seven.
3. Count to eight, nine, zero, one, two, and three.
4. Inhibit.

MC14160B MC14161B MC14162B MC14163B MOTOROLA CMOS LOGIC DATA

6–190
 MC14161B, MC14163B LOGIC DIAGRAM
(Clear is synchronous for MC14163B)

MOTOROLA CMOS LOGIC DATA MC14160B MC14161B MC14162B MC14163B

6–191
 MC14161B, MC14163B TIMING DIAGRAM
Sequence illustrated in waveforms:
1. Clear outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit.

MC14160B MC14161B MC14162B MC14163B MOTOROLA CMOS LOGIC DATA

6–192
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14174B
Hex Type D Flip-Flop
The MC14174B hex type D flip–flop is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic structure. L SUFFIX
Data on the D inputs which meets the setup time requirements is transferred CERAMIC
CASE 620
to the Q outputs on the positive edge of the clock pulse. All six flip–flops
share common clock and reset inputs. The reset is active low, and
independent of the clock.
P SUFFIX
• Static Operation
PLASTIC
• All Inputs and Outputs Buffered CASE 648
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–Power TTL Loads or One Low–Power D SUFFIX
Schottky TTL Load over the Rated Temperature Range SOIC
• Functional Equivalent to TTL 74174 CASE 751B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
MC14XXXBCP Plastic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit
MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C
BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
9 CLOCK Q0 2
TL Lead Temperature (8–Second Soldering) 260 _C
1 RESET
* Maximum Ratings are those values beyond which damage to the device may occur. Q1 5
†Temperature Derating: 3 D0
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 4 D1 Q2 7
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
6 D2 Q3 10
TRUTH TABLE 11 D3
(Positive Logic) Q4 12
13 D4
Inputs Output 14 D5 Q5 15
Clock Data Reset Q
0 1 0 VDD = PIN 16
1 1 1 VSS = PIN 8
No
X 1 Q
Change
X X 0 0
X = Don’t Care

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA MC14174B

6–193
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (1.1 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.3 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (3.7 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.

MC14174B MOTOROLA CMOS LOGIC DATA

6–194
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ VDD All Types

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, tTHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns 5.0 — 100 200
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time — Clock to Q tPLH, tPHL ns
tPLH, tPHL = (0.9 ns/pF) CL + 165 ns 5.0 — 210 400

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 64 ns 10 — 85 160

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 52 ns 15 — 65 120

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time — Reset to Q tPHL ns
tPHL = (0.9 ns/pF) CL + 205 ns 5.0 — 250 500

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.36 ns/pF) CL + 79 ns 10 — 100 200
tPHL = (0.26 ns/pF) CL + 62 ns 15 — 75 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 150 75 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 90 45 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 70 35 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWL 5.0 200 100 — ns
10 100 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 80 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 7.0 2.0 mHz
10 — 12 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 15.5 6.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 — — 15 ms

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — — 5.0
15 — — 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data Setup Time tsu 5.0 40 20 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 20 10 —
15 15 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data Hold Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th 5.0 80 40 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 40 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 30 15 —
Reset Removal Time trem 5.0 250 125 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
* The formulas given are for the typical characteristics only at 25_C.
10
15
100
80
50
40
—
—

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

PIN ASSIGNMENT
R 1 16 VDD
Q0 2 15 Q5
D0 3 14 D5
D1 4 13 D4
Q1 5 12 Q4
D2 6 11 D3
Q2 7 10 Q3
VSS 8 9 C

MOTOROLA CMOS LOGIC DATA MC14174B

6–195
 TIMING DIAGRAM

FUNCTIONAL BLOCK DIAGRAM

MC14174B MOTOROLA CMOS LOGIC DATA

6–196
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14175B
Quad Type D Flip-Flop
The MC14175B quad type D flip–flop is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic structure. L SUFFIX
Each of the four flip–flops is positive–edge triggered by a common clock CERAMIC
CASE 620
input (C). An active–low reset input (R) asynchronously resets all flip–flops.
Each flip–flop has independent Data (D) inputs and complementary outputs
(Q and Q). These devices may be used as shift register elements or as type
T flip–flops for counter and toggle applications. P SUFFIX
PLASTIC
• Complementary Outputs CASE 648
• Static Operation
• All Inputs and Outputs Buffered
• Diode Protection on All Inputs D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
• Output Compatible with Two Low–Power TTL Loads or One Low–Power CASE 751B
Schottky TTL Load
ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Functional Equivalent to TTL 74175
MC14XXXBCP Plastic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBD SOIC
Symbol Parameter Value Unit
TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VDD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin, Iout
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input or Output Current (DC or Transient),

ÎÎÎÎÎÎ
ÎÎÎ
per Pin
± 10 mA BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW 9 CLOCK Q0 2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C Q0 3
1 RESET

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C Q1 7
4 D0 Q1 6
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: 10
5 D1 Q2
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Q2 11
12 D2
Q3 15
TRUTH TABLE
13 D3 Q3 14
Inputs Outputs
Clock Data Reset Q Q VDD = PIN 16
VSS = PIN 8
0 1 0 1
1 1 1 0
No
X 1 Q Q
Change
X X 0 0 1
X = Don’t Care

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA MC14175B

6–197
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (1.7 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.4 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (5.0 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

PIN ASSIGNMENT
R 1 16 VDD
Q0 2 15 Q3
Q0 3 14 Q3
D0 4 13 D3
D1 5 12 D2
Q1 6 11 Q2
Q1 7 10 Q2
VSS 8 9 C

MC14175B MOTOROLA CMOS LOGIC DATA

6–198
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ VDD All Types

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, tTHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns 5.0 — 100 200
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time — Clock to Q, Q tPLH, tPHL ns
tPLH, tPHL = (0.9 ns/pF) CL + 175 ns 5.0 — 220 400

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 72 ns 10 — 90 160

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 57 ns 15 — 70 120

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time — Reset to Q, Q tPHL, tPLH ns
tPHL = (0.9 ns/pF) CL + 280 ns 5.0 — 325 500

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.36 ns/pF) CL + 112 ns 10 — 130 200
tPHL = (0.26 ns/pF) CL + 87 ns 15 — 100 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 250 110 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 45 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 75 35 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWL 5.0 200 100 — ns
10 80 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 60 30 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 4.5 2.0 mHz
10 — 11 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 14 6.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 — — 15 ms

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — — 5.0
15 — — 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data Setup Time tsu 5.0 120 60 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 50 25 —
15 40 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data Hold Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th 5.0 80 40 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 40 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 30 15 —
Reset Removal Time trem 5.0 250 125 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
* The formulas given are for the typical characteristics only at 25_C.
10
15
100
80
50
40
—
—

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14175B

6–199
 TIMING DIAGRAM

FUNCTIONAL BLOCK DIAGRAM

MC14175B MOTOROLA CMOS LOGIC DATA

6–200
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14194B
4-Bit Bidirectional Universal
Shift Register L SUFFIX
CERAMIC
The MC14194B is a 4–bit static shift register capable of operating in the CASE 620
parallel load, serial shift left, serial shift right, or hold mode. The
asynchronous Reset input, when at a low level, overrides all other inputs,
resets all stages, and forces all outputs low. When Reset is at a logic 1 level, P SUFFIX
the two mode control inputs, S0 and S1, control the operating mode as PLASTIC
shown in the truth table. Both serial and parallel operation are triggered on CASE 648
the positive–going transition of the Clock input. The Parallel Data, Data Shift,
and mode control inputs must be stable for the specified setup and hold
times before and after the positive–going Clock transition. D SUFFIX
SOIC
• Synchronous Right/Left Serial Operation
CASE 751B
• Synchronous Parallel Load
• Asynchronous Hold (Do Nothing) Mode ORDERING INFORMATION
• Functional Pin for Pin Equivalent of LS194

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Power Dissipation, per Package† 500 mW
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

LOGIC DIAGRAM
3 4 5 6
DP0 DP1 DP2 DP3
S1 10

S0 9

DSR 2 7
DSL

VDD = PIN 16
VSS = PIN 8
DQ D Q D Q D Q
CR CR CR CR
CLOCK 11
RESET 1
Q0 Q1 Q2 Q3
15 14 13 12

MOTOROLA CMOS LOGIC DATA MC14194B

6–201
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.95 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.90 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (2.90 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must R 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and DSR 2 15 Q0
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. DP0 3 14 Q1
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. DP1 4 13 Q2
DP2 5 12 Q3
DP3 6 11 C
DSL 7 10 S1
VSS 8 9 S0

MC14194B MOTOROLA CMOS LOGIC DATA

6–202
 TRUTH TABLE
Inputs Outputs
p g
Operating (Reset = 1) (@ tn+1)
Mode S1 S0 DSR DSL DP0–3 Q0 Q1 Q2 Q3
Hold 0 0 X X X Q0 Q1 Q2 Q3
1 0 X 0 X Q1 Q2 Q3 0
Shift Left
1 0 X 1 X Q1 Q2 Q3 1
0 1 0 X X 0 Q0 Q1 Q2
Shift Right
0 1 1 X X 1 Q0 Q1 Q2
1 1 X X 0 0 0 0 0
Parallel
1 1 X X 1 1 1 1 1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
X = Don’t Care
tn+1 = State after the next positive–going transition of the clock.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol
VDD
Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, tTHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns 5.0 — 100 200
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH,tPHL ns
Clock to Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.9 ns/pF) CL + 230 ns 5.0 — 275 550

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 92 ns 10 — 110 220
tPLH, tPHL = (0.26 ns/pF) CL + 72 ns 15 — 85 170

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
tPHL = (0.9 ns/pF) CL + 305 ns
tPHL
5.0 — 350 700
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.36 ns/pF) CL + 122 ns 10 — 140 280
tPHL = (0.26 ns/pF) CL + 97 ns 15 — 110 220

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 280 140 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 110 55 —
15 85 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWH 5.0 180 90 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 70 35 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 50 26 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 3.6 1.8 MHz
(Shift Right or Left Mode) 10 — 9.0 4.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 12 6.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 — — 15 µs
10 — — 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — — 4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time tsu ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data to Clock 5.0 10 – 8.0 —
10 20 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 40 9.0 —
M d C
Mode Controll (S) to Clock
Cl k

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5.0 200 100 — ns
10 75 36 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 55 27 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Time th ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data to Clock 5.0 180 90 —
10 50 25 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 35 10 —
M d C
Mode Controll (S) to Clock
Cl k

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5.0 0 – 40 — ns
10 0 – 27 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 0 – 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Removal Time trem 5.0 300 150 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 110 55 —
15 80 40 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14194B

6–203
 Parallel Load Serial Load
VDD VDD
16 16
3 15 3 15
DP0 Q0 DP0 Q0
4 CL 4 CL
DP1 DP1
5 5
DP2 14 DP2 14
6 Q1 6 Q1
DP3 CL DP3 CL
11 11
PULSE CLOCK PULSE CLOCK
2 13 2 13
GENERATOR DSR Q2 GENERATOR DSR Q2
7 7
DSL CL DSL CL
9 9
S0 S0
10 12 10 12
S1 Q3 S1 Q3
R CL R CL
1 8 VSS 1 8 VSS

NOTE: Interchange DSR with DSL and S0 with

S1 for testing shift left.
20 ns 20 ns
DPn VDD
DSR 90%
50%
DSL 10% VSS
th th
tsu tsu
VDD
CLOCK 50%
VSS
tWH(cl) 1/fcl
tPLH tPHL
VOH
Qn 90%
50%
10% VOL
tTLH tTHL
tPHL trem
VDD
RESET 50%
VSS
tWL

Figure 1. Switching Time Test Circuits and Waveforms

VDD
16
3 15
DP0 Q0
4 CL
DP1
5
DP2 14
6 Q1 20 ns 20 ns
DP3 CL
11 VDD
PULSE CLOCK CLOCK 90%
2 13 50% 10%
GENERATOR DSR Q2 VSS
7 1/f VDD
DSL CL
9 DSR
S0 VSS
10 12
S1 Q3 VOH
R CL Qn
VOL
1 8 VSS

ID 500 µF

Figure 2. Dynamic Power Dissipation Test Circuit and Waveforms

MC14194B MOTOROLA CMOS LOGIC DATA

6–204
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14415

Quad Precision Timer/Driver

MC14415 quad timer/driver is constructed with complementary MOS L SUFFIX

CERAMIC
enhancement mode devices. The output pulse width of each digital timer is
CASE 620
a function of the input clock frequency. Once the proper input sequence is
detected the output buffer is set (turned on), and after 100 clock pulses are
counted, the output buffer is reset (turned off).
The MC14415 was designed specifically for application in high speed line P SUFFIX
printers to provide the critical timing of the hammer drivers, but may be used PLASTIC
CASE 648
in many applications requiring precision pulse widths.
• Four Precision Digital Time Delays
• Schmitt Trigger Clock Conditioning DW SUFFIX
• NPN Bipolar Output Drivers SOIC
• Timing Disable Capability Using Inhibit Output CASE 751G
• Positive or Negative Edge Strobing on the Inputs
• Synchronous Polynomial Counters Used for Delay Counting ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14415FP (3.0 V–18 V) Plastic
MC14415VP (3.0 V–6.0 V) Plastic

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14415FL (3.0 V–18 V) Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Rating Symbol Value Unit MC14415VL (3.0 V–6.0 V) Ceramic
MC14415DW (3.0 V–18 V) SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage MC14415FL, FP,DW VDD – 0.5 to + 18.0 V
MC14415VL, VP – 0.5 to + 6.0 TA = – 55° to 125°C for all packages.

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
Input or Output Voltage (DC or Transient)

ÎÎÎÎÎÎ
ÎÎÎ
Input Current (DC or Transient), per Pin
Vin, Vout
Iin
– 0.5 to VDD + 0.5
± 10
V
mA

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Output Current (DC or Transient), per Pin Iout ± 20 mA PIN ASSIGNMENT

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Power Dissipation, per Package† PD 500 mW CLOCK 1 16 VDD

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
SET 2 15 INH
Storage Temperature Tstg – 65 to + 150 _C

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
SET A 3 14 OUT A
Lead Temperature (8–Second Soldering) TL 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur. SET B 4 13 OUT B
†Temperature Derating: SET C 5 12 OUT C
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
SET D 6 11 OUT D
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
ST 1 7 10 DIS
VSS 8 9 ST2
BLOCK DIAGRAM

SET A 3 14 OUTPUT A
SET B 4 DIVIDE–BY– 13 OUTPUT B
INPUT OUTPUT
100
SET C 5 LOGIC BUFFERS 12 OUTPUT C
COUNTERS
SET D 6 11 OUTPUT D

STROBE 2 9
CLOCK
STROBE 1 7 COMMON VDD = PIN 16
CONDITIONING
INPUT DISABLE 10 LOGIC VSS = PIN 8
CIRCUIT
OUTPUT SET 2

CLOCK 1
OUTPUT INHIBIT 15

MOTOROLA CMOS LOGIC DATA MC14415

6–205
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ
(No Load) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.01
0.01
—
—
0
0
0.01
0.01
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — — — — — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 — — 3.0 4.14 — — — Vdc
10 — — 8.0 9.09 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — — — 14.12 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Noise Immunity VNL Vdc
v
(∆Vout 1.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5

ÎÎÎÎ
2.25

ÎÎÎ
—

ÎÎÎÎ
1.4

ÎÎÎ
—
v
(∆Vout
v
ÎÎÎÎÎÎÎÎÎÎ
(∆Vout
v
3.0 Vdc)

ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
4.5 Vdc)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
3.0
—
—
—
3.0
—
4.50
6.75
—
—
2.9
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(∆Vout 1.5 Vdc) VNH 5.0 1.4 — 1.5 2.25 — 1.5 — Vdc
v
(∆Vout 3.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
2.9

ÎÎÎÎ
—

ÎÎÎ
3.0

ÎÎÎÎ
4.50

ÎÎÎ
—

ÎÎÎÎ
3.0

ÎÎÎ
—
v
(∆Vout

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
4.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Voltage (NPN Driver) VOH
15 — — — 6.75 — — —

Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(IOH = 0 mA) Source 5.0 — — 3.0 4.14 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(IOH = 5.0 mA) — — 2.7 3.44 — — —
(IOH = 10 mA) — — 2.5 3.30 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(IOH = 15 mA) — — 2.2 3.08 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(IOH = 0 mA) 10 — — 8.0 9.09 — — — Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(IOH = 5.0 mA) — — 7.7 8.45 — — —
(IOH = 10 mA) — — 7.5 8.30 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(IOH = 15 mA) — — 7.1 8.14 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(IOH = 0 mA) 15 — — — 14.12 — — — Vdc
(IOH = 5.0 mA)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
— — — 13.81 — — —
(IOH = 10 mA) — — — 13.70 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(IOH = 15 mA) — — — 13.61 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOL mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink 5.0 0.23 — 0.2 0.78 — 0.16 —
(VOL = 0.5 Vdc) 10 0.60 — 0.5 2.0 — 0.40 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 — — — 7.8 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Leakage Current Iin 15 — ± 0.3 — ± 0.00001 ± 0.3 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 — — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Dissipation PQ 5.0 — 0.25 — 0.00005 0.25 — 3.5 mW
10 — 1.0 — 0.00022 1.0 — 14

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — — — 0.00050 — — —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Power Dissipation** PD 5.0 PD (56 mW/MHz) f + PQ mW

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(Dynamic plus Quiescent) 10 PD (225 mW/MHz) f + PQ
(CL = 15 pF) 15 PD (510 mW/MHz) f + PQ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14415 MOTOROLA CMOS LOGIC DATA

6–206
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 15 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (2.0 ns/pF) CL + 10 ns 5.0 — 40 85
tTLH = (1.25 ns/pF) CL + 6 ns 10 — 25 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.10 ns/pF) CL + 3 ns 15 — 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (1.5 ns/pF) CL + 47 ns

ÎÎÎÎÎ
5.0

ÎÎÎÎ
—

ÎÎÎÎ
70

ÎÎÎÎ
150
tTHL = (0.75 ns/pF) CL + 24 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
tTHL = (0.55 ns/pF) CL + 17 ns

ÎÎÎ
10
15
—
—
35
25
80
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Turn–Off Delay Time tPLH ns
tPLH = (2.7 ns/pF) CL + 560 ns 5.0 — 600 1200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (1.2 ns/pF) CL + 282 ns
ÎÎÎ 10 — 300 600

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.91 ns/pF) CL + 286 ns 15 — 150 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Turn–On Delay Time tPHL ns
tPHL = (2.4 ns/pF) CL + 564 ns 5.0 — 600 1200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (1.0 ns/pF) CL + 285 ns 10 — 300 600

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.75 ns/pF) CL + 289 ns 15 — 150 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Turn–On Delay Time (Inhibit to Output) tPHL ns
5.0 — 300 550

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 225 425

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 110 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Turn–Off Delay Time (Inhibit to Output) tPLH ns
5.0 — 300 550

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 225 425

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 110 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Pulse Coincidence (Figure 3) PCmin ns
5.0 500 450 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 450 350 —
15 — — —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Pulse Width (Figure 1)

ÎÎÎÎ ÎÎÎÎÎÎÎ tWH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
5.0
10
15
500
450
—
450
350
—
—
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Input Clock Frequency

ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
fcl
5.0 — 0.7 —
MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 1.0 —
15 — 1.5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Input Rise and Fall Times (Figure 1) tTLH, tTHL 5.0 — — 15 µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — — 5.0
15 — — 4.0
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns
90% VDD
INPUT 50%
10% VSS
tPLH tWH
90% VOH
OUTPUT 50%
10%
VOL
tTLH tTHL

VDD
CLOCK 1 2 100 50%
VSS
tPHL

VOH
OUTPUT VOL

Figure 1. Switching Characteristics — Waveform Relationships

MOTOROLA CMOS LOGIC DATA MC14415

6–207
INPUT DISABLE INPUT DISABLE

STROBE 2
STROBE 2
STROBE 1
STROBE 1 MINIMUM COINCIDENCE =
MINIMUM COINCIDENCE = 500 ns @ VDD = 4.75 Vdc
500 ns @ VDD = 4.75 Vdc SET A 50%
SET A 50%
OUTPUT SET 50% OUTPUT SET

OUTPUT INHIBIT
OUTPUT INHIBIT
CLOCK 1 2 100
CLOCK 1 2 100
OUTPUT A 50%
OUTPUT A 50%

tPLH tPHL tPLH tPHL

Mode 1: OUTPUT SET Initiates Time Delay Mode 2: Set A Initiates Time Delay

INPUT DISABLE

STROBE 2 INPUT DISABLE

STROBE 1 STROBE 2 50%

SET A 50% STROBE 1 MINIMUM COINCIDENCE =

500 ns @ VDD = 4.75 Vdc
OUTPUT SET SET A

OUTPUT INHIBIT 50% OUTPUT SET

CLOCK 1 2 100 CLOCK 1 100

OUTPUT A 50% OUTPUT A 50%

tPLH tPHL tPLH tPHL tPLH tPHL

Mode 3: OUTPUT INHIBIT Disables Time Delay Mode 4: Positive–Edge Strobe (ST2)
Initiates Time Delay

Figure 2. Typical Operation Modes and Functional Timing Diagram

MC14415 MOTOROLA CMOS LOGIC DATA

6–208
 C2 DIVIDE–BY–100
C1 SYNCHRONOUS
S COUNTER VDD
Q ENABLE
R
SET A 3

14 OUTPUT A
C2 DIVIDE–BY–100
C1 SYNCHRONOUS
COUNTER

MOTOROLA CMOS LOGIC DATA

S VSS
Q ENABLE
R VDD
SET B 4

13 OUTPUT B
C2 DIVIDE–BY–100
C1 SYNCHRONOUS
S COUNTER VSS
Q
R ENABLE
VDD
SET C 5
LOGIC DIAGRAM

12 OUTPUT C
C2 DIVIDE–BY–100
C1 SYNCHRONOUS
S COUNTER VSS
Q
R ENABLE
VDD
SET D 6

11 OUTPUT D
OUTPUT SET 2

STROBE 2 9 C2 VSS
SCHMITT CLOCK
STROBE 1 7 CONDITIONING
CIRCUIT C1
INPUT DISABLE 10

15
CLOCK 1
OUTPUT INHIBIT

6–209
MC14415
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14490
Hex Contact Bounce Eliminator
The MC14490 is constructed with complementary MOS enhancement L SUFFIX
CERAMIC
mode devices, and is used for the elimination of extraneous level changes
CASE 620
that result when interfacing with mechanical contacts. The digital contact
bounce eliminator circuit takes an input signal from a bouncing contact and
generates a clean digital signal four clock periods after the input has
stabilized. The bounce eliminator circuit will remove bounce on both the P SUFFIX
“make” and the “break” of a contact closure. The clock for operation of the PLASTIC
CASE 648
MC14490 is derived from an internal R–C oscillator which requires only an
external capacitor to adjust for the desired operating frequency (bounce
delay). The clock may also be driven from an external clock source or the
oscillator of another MC14490 (see Figure 5). DW SUFFIX
NOTE: Immediately after power–up, the outputs of the MC14490 are in SOIC
indeterminate states. CASE 751G

• Diode Protection on All Inputs ORDERING INFORMATION

• Six Debouncers Per Package MC14490P Plastic
• Internal Pullups on All Data Inputs MC14490L Ceramic
• Can Be Used as a Digital Integrator, System Synchronizer, or Delay MC14490DW SOIC
Line TA = – 55° to 125°C for all packages.
• Internal Oscillator (R–C), or External Clock Source
• TTL Compatible Data Inputs/Outputs
• Single Line Input, Debounces Both “Make” and “Break” Contacts
• Does Not Require “Form C” (Single Pole Double Throw) Input Signal
• Cascadable for Longer Time Delays
• Schmitt Trigger on Clock Input (Pin 7)
• Supply Voltage Range = 3.0 V to 18 V
• Chip Complexity: 546 FETs or 136.5 Equivalent Gates

BLOCK DIAGRAM

+VDD

DATA 15 Aout
1/2–BIT
Ain 1 4–BIT STATIC SHIFT REGISTER
DELAY
SHIFT LOAD

OSCILLATOR VDD = PIN 16

OSCin 7 φ1 φ1 φ2
AND φ1 φ2 VSS = PIN 8
TWO–PHASE
OSCout 9 CLOCK GENERATOR φ2
φ1 φ2
Bin 14 IDENTICAL TO ABOVE STAGE 2 Bout
φ1 φ2
Cin 3 IDENTICAL TO ABOVE STAGE 13 Cout
φ1 φ2
Din 12 IDENTICAL TO ABOVE STAGE 4 Dout
φ1 φ2
Ein 5 IDENTICAL TO ABOVE STAGE 11 Eout
φ1 φ2
Fin 10 IDENTICAL TO ABOVE STAGE 6 Fout

MC14490 MOTOROLA CMOS LOGIC DATA

6–210
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit PIN ASSIGNMENT

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
VDD

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
Ain
Bout
1
2
16
15
VDD
Aout

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
Iin Input Current (DC or Transient), per Pin ± 10 mA Cin 3 14 Bin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW Dout 4 13 Cout

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C Ein 5 12 Din

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
Fout 6 11 Eout
* Maximum Ratings are those values beyond which damage to the device may occur.
OSCin 7 10 Fin
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 MW/_C From 65_C To 125_C VSS 8 9 OSCout
Ceramic “L” Packages: – 12 mW/_C From 100_C to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎ
ÎÎÎ
Î
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Vin = VDD or 0
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
(VO = 9.0 or 1.0 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VO = 13.5 or 1.5 Vdc)
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1 Level” VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Oscillator Output Source
(VOH = 2.5 V) 5.0 – 0.6 — – 0.5 – 1.5 — – 0.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 V) 5.0 – 0.12 — – 0.1 – 0.3 — – 0.08 —
(VOH = 9.5 V) 10 – 0.23 — – 0.2 – 0.8 — – 0.16 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 V) 15 – 1.4 — – 1.2 – 3.0 — – 1.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Debounce Outputs

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 V) 5.0 – 0.9 — – 0.75 – 2.2 — – 0.6 —
(VOH = 4.6 V) 5.0 – 0.19 — – 0.16 – 0.46 — – 0.12 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 V) 10 – 0.6 — – 0.5 – 1.2 — – 0.4 —
(VOH = 13.5 V) 15 1.8 — – 1.5 – 4.5 — – 1.2 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Oscillator Output

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
(VOL = 0.4 V) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL
5.0 0.36 — 0.3 0.9 — 0.24 —
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 V) 10 0.9 — 0.75 2.3 — 0.6 —
(VOL = 1.5 V) 15 4.2 — 3.5 10 — 2.8 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Debounce Outputs

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
(VOL = 0.4 V) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0 2.6 — 2.2 4.0 — 1.8 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 V) 10 4.0 — 3.3 9.0 — 2.7 —
(VOL = 1.5 V) 15 12 — 10 35 — 8.1 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Input Current

ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Debounce Inputs (Vin = VDD)
ÎÎÎ
ÎÎÎ
ÎÎÎ
IIH 15 — 2.0

± 620
— 0.2

± 255
2.0

± 400
— 11

± 250
µAdc

µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Oscillator — Pin 7 Iin 15 — — —
(Vin = VSS or VDD)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
(Vin = VSS)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Debounce Inputs ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Pullup Resistor Source Current

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IIL 5.0
10
15
175
340
505
375
740
1100
140
280
415
190
380
570
255
500
750
70
145
215
225
440
660
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Input Capacitance
ÎÎÎÎ
ÎÎÎ
Quiescent Current ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin
ISS
—
5.0
—
—
—
150
—
—
5.0
40
7.5
100
—
—
—
90
pF
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = VSS or VDD, Iout = 0 µA) 10 — 280 — 90 225 — 180
15 — 840 — 225 650 — 550
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14490

6–211
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol
VDD
Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH 5.0 — 180 360 ns
All Outputs 10 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 65 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time Oscillator Output 5.0 — 100 200 ns
tTHL 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
Debounce Outputs tTHL
15
5.0
—
—
40
60
80
120

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 30 60
15 — 20 40

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Oscillator Input to Debounce Outputs 5.0 — 285 570
10 — 120 240

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 95 190

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH 5.0 — 370 740
10 — 160 320

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Frequency (50% Duly Cycle) fcl
15
5.0
—
—
120
2.8
240
1.4 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(External Clock) 10 — 6 3.0
15 — 9 4.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time (See Figure 1)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ tsu 5.0 100 50 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 80 40 —
15 60 30 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum External Clock Input tr, tf 5.0 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Rise and Fall Time 10 No Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Oscillator Input 15
Oscillator Frequency fosc, typ Hz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
1.5
OSCout 5.0 Cext (in µF)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Cext ≥ 100 pF* 4.5
10 Cext (in µF)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Note: These equations are intended to be a design guide.
Laboratory experimentation may be required. Formulas 6.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15
are typically ± 15% of actual frequencies. Cext (in µF)

* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

*POWER–DOWN CONSIDERATIONS
Large values of Cext may cause problems when powering down the MC14490 because of the amount of energy stored in the
capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection
diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the
turn–off time of the power supply must not be faster than t = (VDD – VSS)  Cext / (10 mA). For example, If VDD – VSS = 15 V and
Cext = 1 µF, the power supply must turn off no faster than t = (15 V)  (1 µF) / 10 mA = 1.5 ms. This is usually not a problem
because power supplies are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid this possi-
bility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.
VDD
OSCin 50%
0V
tPLH
50% 90%
Aout D1 Cext D2
10%
tr VDD VDD
tPHL
7 9
90% 50%
Aout OSCin OSCout
10%
tf
VDD
OSCin 50%
0V MC14490
tsu
VDD
Ain 50%
0V

Figure 1. Switching Waveforms Figure 2. Discharge Protection During Power Down

MC14490 MOTOROLA CMOS LOGIC DATA

6–212
 THEORY OF OPERATION
The MC14490 Hex Contact Bounce Eliminator is basically
a digital integrator. The circuit can integrate both up and
down. This enables the circuit to eliminate bounce on both
the leading and trailing edges of the signal, shown in the tim-
ing diagram of Figure 3.
Each of the six Bounce Eliminators is composed of a
4–1/2–bit register (the integrator) and logic to compare the
input with the contents of the shift register, as shown in Fig-
ure 4. The shift register requires a series of timing pulses in
order to shift the input signal into each shift register location.
These timing pulses (the clock signal) are represented in the
upper waveform of Figure 3. Each of the six Bounce Elimi-
nator circuits has an internal resistor as shown in Figure 4. A
pullup resistor was incorporated rather than a pulldown resis-
tor in order to implement switched ground input signals, such
as those coming from relay contacts and push buttons. By
switching ground, rather than a power supply lead, system
faults (such as shorts to ground on the signal input leads) will
not cause excessive currents in the wiring and contacts. Sig-
nal lead shorts to ground are much more probable than
shorts to a power supply lead.
When the relay contact is closed, (see Figure 4) the low
level is inverted, and the shift register is loaded with a high on
each positive edge of the clock signal. To understand the op-
eration, we assume all bits of the shift register are loaded
with lows and the output is at a high level.
At clock edge 1 (Figure 3) the input has gone low and a
high has been loaded into the first bit or storage location of
the shift register. Just after the positive edge of clock 1, the
input signal has bounced back to a high. This causes the
shift register to be reset to lows in all four bits — thus starting
the timing sequence over again.
During clock edges 3 to 6 the input signal has stayed low.
Thus, a high has been shifted into all four shift register bits
and, as shown, the output goes low during the positive edge
of clock pulse 6.
It should be noted that there is a 3–1/2 to 4–1/2 clock peri-
od delay between the clean input signal and output signal. In
this example there is a delay of 3.8 clock periods from the
beginning of the clean input signal.
1 2 3 4 5 6
OSCin OR OSCout
INPUT
OUTPUT
CONTACT CONTACT CLOSED
OPEN (VALID TRUE SIGNAL)
CONTACT
BOUNCING
Figure 3. Timing Diagram
MOTOROLA CMOS LOGIC DATA
After some time period of N clock periods, the contact is
opened and at N + 1 a low is loaded into the first bit. Just after
N + 1, when the input bounces low, all bits are set to a high. At
N + 2 nothing happens because the input and output are low
and all bits of the shift register are high. At time N + 3 and
thereafter the input signal is a high, clean signal. At the posi-
tive edge of N + 6 the output goes high as a result of four lows
being shifted into the shift register.
Assuming the input signal is long enough to be clocked
through the Bounce Eliminator, the output signal will be no
longer or shorter than the clean input signal plus or minus
one clock period.
The amount of time distortion between the input and output
signals is a function of the difference in bounce characteris-
tics on the edges of the input signal and the clock frequency.
Since most relay contacts have more bounce when making
as compared to breaking, the overall delay, counting bounce
period, will be greater on the leading edge of the input signal
than on the trailing edge. Thus, the output signal will be
shorter than the input signal — if the leading edge bounce is
included in the overall timing calculation.
The only requirement on the clock frequency in order to
obtain a bounce free output signal is that four clock periods
do not occur while the input signal is in a false state. Refer-
ring to Figure 3, a false state is seen to occur three times at
the beginning of the input signal. The input signal goes low
three times before it finally settles down to a valid low state.
The first three low pulses are referred to as false states.
If the user has an available clock signal of the proper fre-
quency, it may be used by connecting it to the oscillator input
(pin 7). However, if an external clock is not available the user
can place a small capacitor across the oscillator input and
output pins in order to start up an internal clock source (as
shown in Figure 4). The clock signal at the oscillator output
pin may then be used to clock other MC14490 Bounce Elimi-
nator packages. With the use of the MC14490, a large num-
ber of signals can be cleaned up, with the requirement of
only one small capacitor external to the Hex Bounce Elimina-
tor packages.
N+1 N+3 N+5 N+7
CONTACT OPEN
CONTACT
BOUNCING
MC14490
6–213
 +VDD
PULLUP RESISTOR
(INTERNAL) DATA
Ain 1/2 BIT 15
1 4–BIT STATIC SHIFT REGISTER Aout
DELAY
“FORM A” SHIFT LOAD
CONTACT
OSCin 7 OSCILLATOR φ1 φ2
φ1 φ1 φ2
AND
Cext 9 TWO–PHASE
CLOCK GENERATOR φ2
OSCout

Figure 4. Typical “Form A” Contact Debounce Circuit

(Only One Debouncer Shown)

OPERATING CHARACTERISTICS

The single most important characteristic of the MC14490
is that it works with a single signal lead as an input, making
it directly compatible with mechanical contacts (Form A
and B).
The circuit has a built–in pullup resistor on each input. The
worst case value of the pullup resistor (determined from the
Electrical Characteristics table) is used to calculate the con-
tact wetting current. If more contact current is required, an
external resistor may be connected between VDD and the
input.
Because of the built–in pullup resistors, the inputs cannot
be driven with a single standard CMOS gate when VDD is be-
low 5 V. At this voltage, the input should be driven with paral-
leled standard gates or by the MC14049 or MC14050
buffers.
The clock input circuit (pin 7) has Schmitt trigger shaping
such that proper clocking will occur even with very slow clock
edges, eliminating any need for clock preshaping. In addi-
tion, other MC14490 oscillator inputs can be driven from a
single oscillator output buffered by an MC14050 (see Fig-
ure 5). Up to six MC14490s may be driven by a single buffer.
The MC14490 is TTL compatible on both the inputs and
the outputs. When VDD is at 4.5 V, the buffered outputs can
sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as a
result of the internal input pullup resistors.

NO CONNECTION
OSCin 7 9 OSCout
Cext 1/6 MC14050

FROM TO SYSTEM
MC14490
OSCin 7 9 OSCout CONTACTS LOGIC

TO SYSTEM
FROM CONTACTS MC14490 NO CONNECTION
LOGIC
OSCin 7 9 OSCout

TO SYSTEM
FROM CONTACTS MC14490
LOGIC

Figure 5. Typical Single Oscillator Debounce System

MC14490 MOTOROLA CMOS LOGIC DATA

6–214
 TYPICAL APPLICATIONS

ASYMMETRICAL TIMING MULTIPLE TIMING SIGNALS

In applications where different leading and trailing edge
delays are required (such as a fast attack/slow release
timer.) Clocks of different frequencies can be gated into the
MC14490 as shown in Figure 6. In order to produce a slow
attack/fast release circuit leads A and B should be inter-
changed. The clock out lead can then be used to feed clock
signals to the other MC14490 packages where the asym-
metrical input/output timing is required.
IN OUT
MC14490 OSCout
OSCin
MC14011B
As shown in Figure 8, the Bounce Eliminator circuits can
be connected in series. In this configuration each output is
delayed by four clock periods relative to its respective input.
This configuration may be used to generate multiple timing
signals such as a delay line, for programming other timing
operations.
One application of the above is shown in Figure 9, where it
is required to have a single pulse output for a single opera-
tion (make) of the push button or relay contact. This only
requires the series connection of two Bounce Eliminator cir-
cuits, one inverter, and one NOR gate in order to generate
the signal AB as shown in Figures 9 and 10. The signal AB is
four clock periods in length. If the inverter is switched to the A
output, the pulse AB will be generated upon release or break
of the contact. With the use of a few additional parts many
different pulses and waveshapes may be generated.

1 15
A B B.E. 1 Aout
Ain
EXTERNAL fC
÷N fC/N
CLOCK
14 2
B.E. 2 Bout
Bin
Figure 6. Fast Attack/Slow Release Circuit

3 13
LATCHED OUTPUT B.E. 3 Cout
Cin
The contents of the Bounce Eliminator can be latched by
using several extra gates as shown in Figure 7. If the latch
lead is high the clock will be stopped when the output goes 12 4
low. This will hold the output low even though the input has B.E. 4 Dout
Din
returned to the high state. Any time the clock is stopped the
outputs will be representative of the input signal four clock
periods earlier. 5 11
B.E. 5 Eout
Ein
IN OUT

10 6
MC14490 B.E. 6 Fout
OSCin Fin
OSCout

MC14011B

CLOCK 7 9
OSCin CLOCK OSCout
LATCH = 1
UNLATCH = 0
Figure 8. Multiple Timing Circuit Connections
Figure 7. Latched Output Circuit

MOTOROLA CMOS LOGIC DATA MC14490

6–215
 IN OUT
BE 1
A A

AB
IN OUT B
BE 2
B
A ≡ ACTIVE LOW
B ≡ ACTIVE LOW

Figure 9. Single Pulse Output Circuit

OSCin OR
OSCout

INPUT

AB

AB

Figure 10. Multiple Output Signal Timing Diagram

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14490 MOTOROLA CMOS LOGIC DATA

6–216
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14500B
Industrial Control Unit
The MC14500B Industrial Control Unit (ICU) is a single–bit CMOS L SUFFIX
CERAMIC
processor. The ICU is designed for use in systems requiring decisions based
CASE 620
on successive single–bit information. An external ROM stores the control
program. With a program counter (and output latches and input multiplexers,
if required) the ICU in a system forms a stored–program controller that
replaces combinatorial logic. Applications include relay logic processing, P SUFFIX
serial data manipulation and control. The ICU also may control an MPU or be PLASTIC
CASE 648
controlled by an MPU.
• 16 Instructions
• DC to 1.0 MHz Operation at VDD = 5 V DW SUFFIX
• On–Chip Clock (Oscillator) SOIC
• Executes One Instruction per Clock Cycle CASE 751G
• 3 to 18 V Operation
• Low Quiescent Current Characteristic of CMOS Devices ORDERING INFORMATION
• Capable of Driving One Low–Power Schottky Load or Two Low–Power MC14XXXBCP Plastic
TTL Loads over Full Temperature Range MC14XXXBCL Ceramic
MC14XXXBDW SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM

3 PIN ASSIGNMENT
DATA D 2
WRITE
C RST 1 16 VDD
D 16
+V VDD WRITE 2 15 RR
C OEN
IEN STO 8 DATA 3 14 X1
VSS
14 LU STOC
X1 I3 4 13 X2
OSC MUX
13
X2 I2 5 12 JMP
D
7
I0 15 I1 6 11 RTN
C RR
6
I1 INST RESULT 12 I0 7 10 FLAG O
JMP
5 REG REG. (RR)
I2 11
RTN
VSS 8 9 FLAG F
4
I3 10
FLAG O
1 9
RST FLAG F

X1 — OSCILLATOR OUTPUT
X2 — OSCILLATOR INPUT

MOTOROLA CMOS LOGIC DATA MC14500B

6–217
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit This device contains protection circuitry to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VDD

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ ± 10
Iin, Iout Input or Output Current (DC or Transient), mA any voltage higher than maximum rated volt-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW to the range VSS (Vin or Vout) VDD.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C or VDD). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ VDD – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input Voltage

ÎÎÎÎ
RST, D, X2 ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
VIL Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Input Voltage # “0” Level VIL Vdc
I0, I1, I2, I3

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 0.8 — 1.1 0.8 — 0.8

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 1.6 — 2.2 1.6 — 1.6
(VO = 13.5 or 1.5 Vdc) 15 — 2.4 — 3.4 2.4 — 2.4

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level

ÎÎÎ
VIH
5.0
10
2.0
6.0
—
—
2.0
6.0
1.9
3.1
—
—
2.0
6.0
—
—
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 10 — 10 4.3 — 10 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Data, Write
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Output Drive Current

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 4.6 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Source

ÎÎÎ
IOH

5.0 – 1.2 — – 1.0 – 2.0 — – 0.7 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOH = 9.5 Vdc) 10 – 3.6 — – 3.0 – 6.0 — – 2.1 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOH = 13.5 Vdc) 15 – 7.2 — – 6.0 – 12 — – 4.2 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 1.9 — 1.6 3.2 — 1.1 — mAdc
(VOL = 0.5 Vdc) 10 3.6 — 3.0 6.0 — 2.1 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOL = 1.5 Vdc) 15 7.2 — 6.0 12 — 4.2 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Output Drive Current Source IOH mAdc
Other Outputs

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOH = 2.5 Vdc) 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.5 Vdc)

ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14500B MOTOROLA CMOS LOGIC DATA

6–218
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ VDD –55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current, RST Iin 15 25 — — 150 — — 250 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance (Data) Cin — — — — 15 — — — pF
Input Capacitance (All Other Inputs) Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
Quiescent Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Per Package) Iout = 0 µA,

ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD 15 — 20 — 0.015 20 — 600
**Total Supply Current at an IT — IT = (1.5 µA/kHz) f + IDD µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
External Load Capacitance (CL)
on All Outputs
** The formulas given are for the typical characteristics only at 25_C.
IT = (3.0 µA/kHz) f + IDD
IT = (4.5 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (TA = 25_C; tr = tf = 20 ns for X and I inputs; CL = 50 pF for JMP, X1, RR, Flag O, Flag F;
CL = 130 pF + 1 TTL load for Data and Write.)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Characteristic Symbol
VDD
Vdc Min
All Types
Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time, X1 to RR tPLH, 5.0 — 250 500 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL 10 — 125 250
15 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
X1 to Flag F, Flag O, RTN, JMP 5.0 — 200 400

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 100 200
15 — 85 170

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
X1 to Write 5.0 — 225 450

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 125 250
15 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
X1 to Data 5.0 — 250 500

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 120 240
15 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RST to RR 5.0 — 250 500

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 125 250
15 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RST to X1 5.0 — 450 Note 1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 200
15 — 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RST to Flag F, Flag O, RTN, JMP 5.0 — 400 800

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 200 400
15 — 150 300

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RST to Write, Data 5.0 — 450 900

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 225 450
15 — 175 350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width, X1 tW(cl) 5.0 400 200 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 200 100 —
15 180 90 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Rent Pulse Width, RST
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tW(R) 5.0 500 250 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 250 125 —
15 200 100 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time — Instruction tsu(l) 5.0 400 200 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 250 125 —
15 180 90 —
Data
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu(D) 5.0 200 100 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50 —
15 80 40 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Hold Time — Instruction
ÎÎÎÎÎÎÎÎÎÎÎ th(l) 5.0 100 0 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 50 0 —
15 50 0 —
Data
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th(D) 5.0 200 100 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50 —
15 100 50 —
NOTE 1. Maximum Reset Delay may extend to one–half clock period.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14500B

6–219
 ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ Pin No. Function Symbols
f Clk , CLOCK FREQUENCY (Hz)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
1
2
Chip Reset
Write Pulse
RST
Write

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ

3 Data In/Out Data
1M
4 MSB Instruction Word I3

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ

5 Bit 2 Instruction Word I2

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ

6 Bit 1 Instruction Word I1
7 LSB Instruction Word I0

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ

100 k 8 Negative Supply (Ground) VSS

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ

9 Flag on NOP F Flag F
10 Flag on NOP O Flag O

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ

11 Subroutine Return Flag RTN

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ

12 Jump Instruction Flag JMP
10 k 13 Oscillator Input X2

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ

10 kΩ 100 kΩ 1 MΩ 14 Oscillator Output X1
15 Result Register RR

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ

RC, CLOCK FREQUENCY RESISTOR
16 Positive Supply VDD
Figure 1. Typical Clock Frequency
versus Resistor (RC)

ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Table 1. MC14500B Instruction Set

ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Instruction Code

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
0000
³
³ ³
Mnemonic
NOPO No change in registers. RR
Action
RR, Flag O

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1 0001 LD Load result register. Data RR
³
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
2 0010 LDC Load complement. Data RR
3 ³
0011 AND Logical AND. RR  Data RR
³
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
4 0100 ANDC Logical AND complement. RR  Data RR
³
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5 0101 OR Logical OR. RR + Data RR
6 0110 ³ ORC Logical OR complement. RR + Data RR
³
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
7 0111 XNOR Exclusive NOR. If RR = Data, RR 1
8 ³ 1000 ³ STO Store. RR Data Pin, Write

ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
9
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
A
B
³
³
1001

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1010
³
1011
³ STOC
IEN
OEN
Store complement. RR
Input enable. Data
Output enable. Data
Data Pin, Write
IEN Register
OEN Register
³
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
C
D
E
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
³
1100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1101
1110
³ ³
JMP
RTN
SKZ
Jump. JMP Flag
Return. RTN Flag and skip next instruction
Skip next instruction if RR = 0

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
F 1111 NOPF No change in registers. RR RR, Flag F

ADDITIONAL
OUTPUT DEVICES

I/O ADDRESS MC14599B

8–BIT ADDRESSABLE LATCH 8
MEMORY OUTPUTS
WITH BIDIRECTIONAL DATA
TO PERIPHERAL
MC14512 DEVICES
4 BIT OP CODE

8–CHANNEL 8
INPUTS
DATA SELECTOR
DATA BUS
ADDRESS
MEMORY

ADDITIONAL
INPUT DEVICES
I0, I1, I2, I3

MC14500B
PROGRAM CLOCK ICU
COUNTER DATA

Figure 2. Outline of a Typical Organization for a MC14500B–Based System

MC14500B MOTOROLA CMOS LOGIC DATA

6–220
 TIMING WAVEFORMS

Instructions NOPO, NOPF

Instructions RR, IEN, OEN remain unaffected

X1

RST

tW(R) tPHL
(RESET TO XI)
IEN
REGISTER

OEN
REGISTER

RR
tPHL (RESET TO RR)
4–BIT
INSTRUCTION
NOP0 NOPF NOPO

FLAG 0
tPLH tPHL
FLAG F (DATA TO FLAG)

Instructions SKZ, JMP, RTN

Instructions RR, IEN, OEN remain unaffected

X1

tW(cl)
4–BIT
INSTRUCTION
SKZ * JMP RTN * JMP
RST

RR

JMP FLAG
tPHL
RTN FLAG (RESET TO JUMP)

SKP F/F
INTERNAL

* Instructions Ignored.

MOTOROLA CMOS LOGIC DATA MC14500B

6–221
 TIMING WAVEFORMS

Instructions STO, STOC, OEN

X1

4–BIT
INSTRUCTION STO STO NOP OEN STO
STOC STOC STOC

ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
DATA 1

RR

tPLH, tPHL (X1 TO DATA)

OEN REGISTER
(INTERNAL)

WRITE

tPHL tPLH VALID WHEN RST = L

NOTE 1. Valid output data.

Instructions LD, LDC, AND, ANDC

Instructions OR, ORC, XNOR, IEN

X1

LD, etc.
4–BIT
INSTRUCTION
NOP IEN LD, etc.
tsu(I)
th(I)

DATA

tsu(D)
th(D)

RR

tPLH, tPHL (X1 TO RR)

IEN REGISTER
(INTERNAL)
VALID WHEN RST = L

MC14500B MOTOROLA CMOS LOGIC DATA

6–222
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14501UB
Triple Gate
Dual 4–Input “NAND” Gate L SUFFIX
CERAMIC
2–Input “NOR/OR” Gate CASE 620
8–Input “AND/NAND” Gate
The MC14501UB is constructed with MOS P–channel and N–channel P SUFFIX
enhancement mode devices in a single monolithic structure. These PLASTIC
complementary MOS logic gates find primary use where low power CASE 648
dissipation and/or high noise immunity is desired. Additional characteristics
can be found on the Family Data Sheet.
• Diode Protection on All Inputs D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
• Logic Swing Independent of Fanout CASE 751B
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
ORDERING INFORMATION
Schottky TTL Load Over the Rated Temperature Range

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
± 10 LOGIC DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin, Iout Input or Output Current (DC or Transient), mA
per Pin (POSITIVE LOGIC)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C
1
2
13

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
3
4
TL Lead Temperature (8–Second Soldering) 260 _C 11
14 AND
* Maximum Ratings are those values beyond which damage to the device may occur. 12
†Temperature Derating: 5 15 NAND
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 6
10
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 7
9
VDD = PIN 16
VSS = PIN 8

CIRCUIT SCHEMATIC Use Dotted Connection Externally to

Obtain 8–Input AND/NAND
VDD 16 VDD
NOTE: Pin 14 must not be used as an input
NOTE: to the inverter.
11
13 (10)
12
(6) 1
14
(7) 2
VSS 15
(9) 3

(5) 4
VSS 8 VSS

Numbers in parenthesis are for second 4–input gate.

MOTOROLA CMOS LOGIC DATA MC14501UB

6–223
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 3.6 or 1.4 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.4
(VO = 7.2 or 2.8 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 11.5 or 3.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
3.75
—
—
4.50
6.75
3.0
3.75
—
—
2.9
3.6

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.4 or 3.6 Vdc) “1” Level VIH 5.0 3.6 — 3.5 2.75 — 3.5 — Vdc
(VO = 2.8 or 7.2 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.1

ÎÎÎÎ
—

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ
—

ÎÎÎÎ
7.0

ÎÎÎ
—
(VO = 3.5 or 11.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11.4 — 11.25 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) NAND* 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) NOR 5.0 – 2.1 — – 1.75 – 3.0 — – 1.22 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.42 — – 0.35 – 0.63 — – 0.24 —
(VOH = 9.5 Vdc 10 – 1.06 — – 0.88 – 1.58 — – 0.62 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 3.1 — – 2.63 – 6.12 — – 1.84 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) NOR– 5.0 – 3.6 — – 3.0 – 5.1 — – 2.1 — mAdc
(VOH = 4.6 Vdc) 5.0 – 0.72 — – 0.6 – 1.08 — – 0.42 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Inverter

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
– 1.8
– 5.4
—
—
– 1.5
– 4.5
– 2.7
– 10.5
—
—
– 1.05
– 3.15
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) NAND* 10 1.6 — 1.3 2.25 — 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
NOR

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
0.92
2.34
6.12
—
—
—
0.77
1.95
5.1
1.32
3.37
13.2
—
—
—
0.54
1.36
3.57
—
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
NOR–

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Inverter
5.0
10
1.54
3.90
—
—
1.28
3.25
2.2
5.63
—
—
0.90
2.27
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 10.2 — 8.5 22 — 5.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
Quiescent Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Per Package)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 µAdc
(Dynamic plus Quiescent, 10 IT = (1.2 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Per Package) 15 IT = (2.4 µA/kHz) f + IDD
IT = (3.6 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

MC14501UB MOTOROLA CMOS LOGIC DATA

6–224
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS** (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Figure Symbol VDD Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NAND, NOR 2, 3 tTLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 180 360

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.5 ns/pF) CL + 15 ns 10 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 65 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NAND, NOR 2, 3 tTHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ NOR–Inverter 3 tTLH
15 40 80
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.35 ns/pF) CL + 32.5 ns 5.0 100 200
tTLH = (0.60 ns/pF) CL + 20 ns 10 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
Output Fall Time ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
tTLH = (0.40 ns/pF) CL + 17 ns

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ NOR–Inverter 3 tTHL
15 40 80
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.67 ns/pF) CL + 26.5 ns 5.0 60 120
tTHL = (0.45 ns/pF) CL + 17.5 ns 10 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.37 ns/pF) CL + 11.5 ns 15 30 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time NAND 2 tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 45 ns tPHL 50 130 260
tPLH, tPHL = (0.66 ns/pF) CL + 37 ns 10 70 140

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 30 ns NOR 3 tPLH 5.0 115 230 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 32 ns tPHL 10 65 130
tPLH, tPHL = (0.5 ns/pF) CL + 20 ns 15 45 90

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 45 ns NOR–Inverter 3 tPLH, 5.0 130 260 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 37 ns tPHL 10 70 140

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 50 100
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14501UB

6–225
 0.01 µF CERAMIC

VDD 16

CL PIN ASSIGNMENT
Vin
IN 1A 1 16 VDD
CL CL
CL IN 2A 2 15 OUTB
8
IN 3A 3 14 OUTB
IDD 500 µF 50% DUTY CYCLE
IN 4A 4 13 OUTA
IN 1C 5 12 IN 2B
20 ns IN 2C 6 11 IN 1B
VDD
90% 90%
IN 3C 7 10 OUTC
Vin 10% 10% VSS VSS 8 9 IN 4C
20 ns

Figure 1. Power Dissipation Test Circuit

and Waveform

VDD 20 ns 20 ns
90% 90% VDD
16 INPUT (A) 50% 50%
OUTPUT 10% 10% VSS
PULSE
(B)
GENERATOR INPUT tPHL tPLH
CL
(A) 8 VSS
90% 90% VOH
OUTPUT (B) 50% 50%
10% 10% VOL
tTHL tTLH

Figure 2. Input “NAND” Gate Switching Time Test Circuit and Waveforms

20 ns
VDD
90%
INPUT (A) 50%
OUTPUT (B) 10% VSS
INPUT (A) tPHL tPLH
PULSE OUTPUT (C) 90% VOH
GENERATOR OUTPUT (B) 50%
10%
CL CL tTHL VOL
tTLH
tPLH tPHL
VOH
90%
50%
OUTPUT (C) 10%
Output (B) = “NOR” All unused inputs VOL
Output (C) = “NOR–Inverter” connected to ground. tTLH tTHL

Figure 3. “NOR” Gate and “NOR–Inverter” Switching Time Test Circuit and Waveforms

MC14501UB MOTOROLA CMOS LOGIC DATA

6–226
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14502B

Strobed Hex Inverter/Buffer

The MC14502B is a strobed hex buffer/inverter with 3–state outputs, an L SUFFIX

CERAMIC
inhibit control, and guaranteed TTL drive over the temperature range. The
CASE 620
3–state output simplifies design by allowing a common bus.
• Separate Output Disable Control
• 3–State Output P SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc PLASTIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Capable of Driving 4LSTTL Loads Over the Rated Temperature Range CASE 648

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit DW SUFFIX

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
SOIC
VDD DC Supply Voltage – 0.5 to + 18.0 V CASE 751G

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Vin, Vout
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Iin ÎÎÎ
Input or Output Voltage (DC or Transient)

ÎÎÎÎÎÎ
ÎÎÎ
Input Current (DC or Transient), per Pin
– 0.5 to VDD + 0.5
± 10
V
mA
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCP Plastic
Iout Output Current (DC or Transient), per Pin + 30 mA MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBDW SOIC
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C

LOGIC DIAGRAM
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 3–STATE
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C OUTPUT
4
DISABLE
CIRCUIT DIAGRAM INHIBIT 12
5 Q1
D1 3
DISABLE
VDD 7 Q2
D2 6

2 Q3
INHIBIT D3 1

9 Q4
D4 10

D1
11 Q5
D5 13
Q1

Other five buffers are identical 14 Q6

D6 15

VDD = PIN 16
VSS VSS = PIN 8

TRUTH TABLE
Dn Inhibit Disable Qn
0 0 0 1
1 0 0 0
X 1 0 0
X X 1 High
Impedance
X = Don’t Care

MOTOROLA CMOS LOGIC DATA MC14502B

6–227
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0”’ Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ
—

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ
—

ÎÎÎÎ
– 1.7

ÎÎÎ
—
(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
3.5
7.8
—
—
2.8
6.3
6.6
17
—
—
2.0
4.4
—
—
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 29 — 24 66 — 16 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
1.0
2.0
—
—
0.002
0.004
1.0
2.0
—
—
30
60
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 4.0 — 0.006 4.0 — 120

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (2.7 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (5.3 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (8.0 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Three–State Leakage Current
ÎÎÎ
ÎÎÎ ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 —
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
± 3.0 µAdc

** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must D3 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q3 2 15 D6
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. D1 3 14 Q6
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. DISABLE 4 13 D5
Q1 5 12 INH
D2 6 11 Q5
Q2 7 10 D4
VSS 8 9 Q4

MC14502B MOTOROLA CMOS LOGIC DATA

6–228
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ All Types

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol VDD Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH 5.0
10
—
—
100
50
200
100
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL 5.0 — 40 80 ns
10 — 20 40

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 15 30

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time Data to Q tPHL 5.0 — 135 270 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
10

ÎÎÎÎ
—

ÎÎÎÎ
55

ÎÎÎÎ
110

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time, Inhibit to Q tPHL
15
5.0
—
—
40
335
80
670 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 145 290
15 — 95 190

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time Data to Q, Inhibit to Q

ÎÎÎÎ
tPLH 5.0 — 295 590 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
10
15
—
—
130
95
260
190

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Propagation Delay, Output “1” to High Impedance tPHZ 5.0 — 65 130 ns
10 — 30 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Propagation Delay, High Impedance to “1” Level tPZH
15
5.0
—
—
25
260
50
520 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 105 210
15 — 80 160

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Propagation Delay, Output “0” to High Impedance

ÎÎÎÎ
tPLZ 5.0 — 150 300 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
10
15
—
—
70
55
140
110

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Propagation Delay, High Impedance to “0” Level tPZL 5.0 — 160 320 ns
10 — 65 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 50 100

* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

16 + VDD
16 + VDD

DIS VOH Vout DIS VOL Vout

INH Q1 IOH INH Q1 IOL
D1 Q2 D1 Q2
D2 Q3 D2 Q3
D3 Q4 D3 Q4
D4 Q5 D4 Q5
D5 Q6 D5 Q6
D6 VGS = – VDD D6 VDS = VOL
VDS = VOH – VDD VGS = VDD
8 8
VSS
VSS

Figure 1. Typical Output Source Figure 2. Typical Output Sink

Current Test Circuit (IOH) Current Test Circuit (IOL)

MOTOROLA CMOS LOGIC DATA MC14502B

6–229
 VDD

ID

DIS
INH Q1
D1 Q2 CL
CL
D2 Q3
D3 Q4 CL
PULSE CL
D4 Q5
GENERATOR D5 Q6 CL
D6 CL

20 ns 20 ns 50%
90% VDD
50% DUTY
Vin
10% VSS CYCLE

Figure 3. Power Dissipation Test Circuit and Waveform

Switch Positions for 3–State Test

Test S1 S2 S3 S4
tPHZ Open Closed Closed Open
16 VDD tPLZ Closed Open Open Closed
DISABLE tPZL Closed Open Open Closed
tPZH Open Closed Closed Open
INHIBIT Q1
PULSE D1 Q2 CL
GENERATOR D2 Q3 16 VDD
D3 Q4 PULSE VDD
DISABLE
D4 Q5 GENERATOR
INHIBIT Q1
D5 Q6 CL
VDD D1 Q2
D6
D2 Q3 1k
8 D3 Q4 S1
VSS D4 Q5
S4
D5 Q6 S2
D6
S3
8
VSS
For all tTLH, tTHL, tPHL, and tPLH measurements Vin
may be applied to any other Dn input or to inhibit.
20 ns 20 ns
VDD
20 ns 20 ns 90%
50%
VDD DISABLE 10%
90% VSS
INPUT 50% tPLZ tPZL
10%
VSS VOH
90%
tPHL tPLH
10% ≈ 0.5 V @ VDD = 5 V,
VOH
90% 10 V, AND 15 V
OUTPUT 50% Q OUTPUTS tPHZ tPZH
10% ≈ 2 V @ VDD = 5 V
(TESTS 1 AND 2) VOL
90% ≈ 6 V @ VDD = 10 V
tTHL tTLH
≈ 10 V @ VDD = 15 V
10%
VOL

Figure 4. AC Test Circuit and Waveforms Figure 5. 3–State AC Test Circuit and Waveforms
(tTLH, tTHL, TPLH, and tPHL) (tPHZ, tPLZ, tPZH, tPZL)

MC14502B MOTOROLA CMOS LOGIC DATA

6–230
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14503B
Hex Non-Inverting 3-State
Buffer L SUFFIX
CERAMIC
The MC14503B is a hex non–inverting buffer with 3–state outputs, and a
CASE 620
high current source and sink capability. The 3–state outputs make it useful in
common bussing applications. Two disable controls are provided. A high
level on the Disable A input causes the outputs of buffers 1 through 4 to go
into a high impedance state and a high level on the Disable B input causes P SUFFIX
PLASTIC
the outputs of buffers 5 and 6 to go into a high impedance state.
CASE 648
• 3–State Outputs
• TTL Compatible — Will Drive One TTL Load Over Full Temperature
Range D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
• Two Disable Controls for Added Versatility CASE 751B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Pin for Pin Replacement for MM80C97 and 340097

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
Symbol Parameter Value Unit MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
Î
ÎÎÎÎÎÎÎÎÎÎÎ
Iout ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Input Current (DC or Transient), per Pin

ÎÎÎ
Output Current (DC or Transient), per Pin
± 10
± 25
mA
mA
TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
PD Power Dissipation, per Package† 500 mW
Appropriate

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C Disable

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C Inn Input Outn
* Maximum Ratings are those values beyond which damage to the device may occur. 0 0 0
†Temperature Derating: 1 0 1
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C X 1 High
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Impedance
CIRCUIT DIAGRAM X = Don’t Care
ONE OF TWO/FOUR BUFFERS

VDD

LOGIC DIAGRAM

* INn 15
OUTn DISABLE B
12 11
IN 5 OUT 5
14 13
* DISABLE IN 6 OUT 6
* INPUT 2 3
VSS IN 1 OUT 1
TO OTHER BUFFERS 4 5
IN 2 OUT 2
* Diode protection on all inputs (not shown) 6 7
IN 3 OUT 3

This device contains protection circuitry to guard against damage 10 9

IN 4 OUT 4
due to high static voltages or electric fields. However, precautions must
1
be taken to avoid applications of any voltage higher than maximum rated DISABLE A
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. VDD = PIN 16
Unused inputs must always be tied to an appropriate logic voltage VSS = PIN 8
level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA MC14503B

6–231
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = 0 ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 3.6 or 1.4 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
—

ÎÎÎÎ
1.5

ÎÎÎ
—

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ
—

ÎÎÎ
1.5
(VO = 7.2 or 2.8 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 11.5 or 3.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
3.0
4.0
—
—
4.50
6.75
3.0
4.0
—
—
3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 1.4 or 3.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ
—

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ
—

ÎÎÎÎ
3.5

ÎÎÎ
—
(VO = 2.8 or 7.2 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 3.5 or 11.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
4.5

ÎÎÎ
– 4.3

ÎÎÎÎ
—

ÎÎÎ
– 3.6

ÎÎÎÎ
– 5.0

ÎÎÎ
—

ÎÎÎÎ
– 2.5

ÎÎÎ
—
(VOH = 2.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
5.0
10
– 5.8
– 1.2
– 3.1
—
—
—
– 4.8
– 1.02
– 2.6
– 6.1
– 1.4
– 3.7
—
—
—
– 3.0
– 0.7
– 1.8
—
—
—

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VOH = 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎSink IOL
15

4.5
– 8.2

2.2
—

—
– 6.8

1.8
– 14.1

2.1
—

—
– 4.8

1.2
—

— mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) 5.0 2.6 — 2.1 2.3 — 1.3 —
(VOL = 0.5 Vdc) 10 6.5 — 5.5 6.2 — 3.8 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Input Current ÎÎÎÎ
(VOL = 1.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ

ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ Iin
15

15
19.2

—
—

± 0.1
16.1

—
25

± 0.00001
—

± 0.1
11.2

—
—

± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IQ 5.0 — 1.0 — 0.002 1.0 — 30 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 2.0 — 0.004 2.0 — 60
15 — 4.0 — 0.006 4.0 — 120

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (2.5 µA/kHz) f + IDD
IT = (6.0 µA/kHz) f + IDD
IT = (10 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(CL = 50 pF on all outputs)

ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(All outputs switching,
50% Duty Cycle)
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
Current ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Three–State Output Leakage

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 —

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
± 3.0 µAdc

** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006.

MC14503B MOTOROLA CMOS LOGIC DATA

6–232
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Characteristic Symbol
VDD
VCC Typ #
All Types
Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Output Rise Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tTLH = (0.5 ns/pF) CL + 20 ns
tTLH
5.0 45 90
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tTLH = (0.3 ns/pF) CL + 8.0 ns 10 23 45
tTLH = (0.2 ns/pF) CL + 8.0 ns 15 18 35

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Output Fall Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tTHL = (0.5 ns/pF) CL + 20 ns
tTHL = (0.3 ns/pF) CL + 8.0 ns
tTHL
5.0
10
45
23
90
45
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tTHL = (0.2 ns/pF) CL + 8.0 ns 15 18 35

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Turn–Off Delay Time, all Outputs

ÎÎÎÎ
ÎÎÎÎ
tPLH = (0.3 ns/pF) CL + 60 ns
tPLH = (0.15 ns/pF) CL + 27 ns
tPLH
5.0
10
75
35
150
70
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
tPLH = (0.1 ns/pF) CL + 20 ns

ÎÎÎÎ
ÎÎÎÎ
Turn–On Delay Time, all Outputs tPHL
15 25 50
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tPHL = (0.3 ns/pF) CL + 60 ns 5.0 75 150
tPHL = (0.15 ns/pF) CL + 27 ns 10 35 70

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tPHL = (0.1 ns/pF) CL + 20 ns 15 25 50

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
3–State Propagation Delay Time tPHZ 5.0 75 150 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Output “1” to High Impedance 10 40 80
15 35 70

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Output “0” to High Impedance

ÎÎÎÎ
ÎÎÎÎ
tPLZ 5.0
10
80
40
160
80
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
15 35 70

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
High Impedance to “1” Level tPZH 5.0 65 130 ns
10 25 50

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
15 20 40

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
High Impedance to “0” Level tPZL 5.0 100 200 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
10 35 70
15 25 50
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

PIN ASSIGNMENT

DIS A 1 16 VDD
IN 1 2 15 DIS B

OUT 1 3 14 IN 6
IN 2 4 13 OUT 6
OUT 2 5 12 IN 5
IN 3 6 11 OUT 5
OUT 3 7 10 IN 4
VSS 8 9 OUT 4

MOTOROLA CMOS LOGIC DATA MC14503B

6–233
 DISABLE 20 ns 20 ns
INPUT VDD
VDD 90%
INPUT 50%
16 10%
VSS
INPUT tPLH tPHL
PULSE
OUTPUT VOH
GENERATOR 90%
OUTPUT 50%
VSS CL 10%
VOL
tTLH tTHL

tPLH tPHL

Figure 1. Switching Time Test Circuit and Waveforms

(tTLH, tTHL, tPHL, and tPLH)

DISABLE INPUT DISABLE INPUT

PULSE PULSE tPLZ, tPZL CIRCUIT
GENERATOR GENERATOR
VDD VDD

tPHZ, tPZH CIRCUIT 16

16 1k
INPUT OUTPUT INPUT OUTPUT
1k CL
VSS CL
8 8 VSS

20 ns 20 ns
VDD
90%
50%
10%
DISABLE INPUT VSS
tPLZ tPZL
VOH
90%
10%
OUTPUT FOR tPZH, tPZL CIRCUIT ≈ VOL + 0.05 V
tPHZ tPZH
OUTPUT FOR tPHZ, tPLZ CIRCUIT 90% ≈ VOH – 0.15 V

10%
VOL

Figure 2. 3–State AC Test Circuit and Waveforms

(tPLZ, tPHZ, tPZH, tPZL)

MC14503B MOTOROLA CMOS LOGIC DATA

6–234
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS L SUFFIX
CERAMIC
The MC14504B is a hex non–inverting level shifter using CMOS CASE 620
technology. The level shifter will shift a TTL signal to CMOS logic levels for
any CMOS supply voltage between 5 and 15 volts. A control input also
allows interface from CMOS to CMOS at one logic level to another logic P SUFFIX
level: Either up or down level translating is accomplished by selection of PLASTIC
power supply levels VDD and VCC. The VCC level sets the input signal levels CASE 648
while VDD selects the output voltage levels.
• UP Translates from a Low to a High Voltage or DOWN Translates from
a High to a Low Voltage D SUFFIX
SOIC
• Input Threshold Can Be Shifted for TTL Compatibility CASE 751B
• No Sequencing Required on Power Supplies or Inputs for Power Up or
Power Down ORDERING INFORMATION
• 3 to 18 Vdc Operation for VDD and VCC MC14XXXBCP Plastic
• Diode Protected Inputs to VSS MC14XXXBCL Ceramic
• Capable of Driving Two Low–Power TTL Loads or One Low–Power MC14XXXBD SOIC
Schottky TTL Load Over the Rated Temperature Range TA = – 55° to 125°C for all packages.

LOGIC DIAGRAM
PIN ASSIGNMENT
VCC VDD VCC 1 16 VDD
Aout 2 15 Fout

LEVEL Ain 3 14 Fin

INPUT OUTPUT
SHIFTER Bout 4 13 MODE
Bin 5 12 Eout
Cout 6 11 Ein
TTL/CMOS Cin 7 10 Dout
MODE
MODE SELECT
VSS 8 9 Din

Input Logic Output Logic

Mode Select Levels Levels
1 (VCC) TTL CMOS This device contains circuitry to protect
the inputs against damage due to high static
0 (VSS) CMOS CMOS voltages or electric fields referenced to the
VSS pin, only. Extra precautions must be
1/6 of package shown. taken to avoid applications of any voltage
higher than maximum rated voltages to this
high–impedance circuit. For proper opera-
v v
tion, the ranges VSS Vin 18 V and VSS
v Vout v VDD are recommended.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VDD). Unused outputs must be left
open.

MOTOROLA CMOS LOGIC DATA MC14504B

6–235
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VDD ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage
– 0.5 to 18.0
– 0.5 to + 18.0
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Vin
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vout ÎÎÎ
Input Voltage (DC or Transient)

ÎÎÎÎÎÎ
ÎÎÎ
Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Iin, Iout

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input or output Current (DC or Transient),

ÎÎÎÎÎÎ
ÎÎÎ
per Pin
± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package* 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
– 55_C 25_C 125_C
VCC VDD

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Voltage “0” Level VOL — 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = 0 V — 10 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Vin = VCC ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level
VOH
—
—
15
5.0
—
4.95
0.05
—
—
4.95
0
5.0
0.05
—
—
4.95
0.05
— Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
— 10 9.95 — 9.95 10 — 9.95 —
— 15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Voltage

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(VOL = 1.0 Vdc) TTL–CMOS ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VIL
5.0 10 — 0.8 — 1.3 0.8 — 0.8
Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) TTL–CMOS 5.0 15 — 0.8 — 1.3 0.8 — 0.8
(VOL = 1.0 Vdc) CMOS–CMOS 5.0 10 — 1.5 — 2.25 1.5 — 1.4

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) CMOS–CMOS 5.0 15 — 1.5 — 2.25 1.5 — 1.5
(VOL = 1.5 Vdc) CMOS–CMOS 10 15 — 3.0 — 4.5 3.0 — 2.9

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Voltage

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(VOH = 9.0 Vdc) TTL–CMOS ÎÎÎ
“1” Level

ÎÎÎ
ÎÎÎ
VIH
5.0 10 2.0 — 2.0 1.5 — 2.0 —
Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) TTL–CMOS 5.0 15 2.0 — 2.0 1.5 — 2.0 —
(VOH = 9.0 Vdc) CMOS–CMOS 5.0 10 3.6 — 3.5 2.75 — 3.5 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) CMOS–CMOS 5.0 15 3.6 — 3.5 2.75 — 3.5 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) CMOS–CMOS 10 15 7.1 — 7.0 5.5 — 7.0 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source — 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) — 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) — 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) — 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL — 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) — 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) — 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input Current

ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Input Capacitance (Vin = 0)
ÎÎÎ
ÎÎÎ
ÎÎÎ
Iin
Cin
—
—
15
—
—
—
± 0.1
—
—
—
± 0.00001
5.0
± 0.1
7.5
—
—
± 1.0
—
µAdc
pF

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Quiescent Current

ÎÎÎ
(Per Package) ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD or
ICC
—
—
5.0
10
—
—
0.05
0.10
—
—
0.0005
0.0010
0.05
0.10
—
—
1.5
3.0
µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
CMOS–CMOS Mode — 15 — 0.20 — 0.0015 0.20 — 6.0

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 5.0 — 0.5 — 0.0005 0.5 — 3.8 µAdc
(Per Package) 5.0 10 — 1.0 — 0.0010 1.0 — 7.5

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
TTL–CMOS Mode 5.0 15 — 2.0 — 0.0015 2.0 — 15

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current ICC 5.0 5.0 — 5.0 — 2.5 5.0 — 6.0 mAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 5.0 10 — 5.0 — 2.5 5.0 — 6.0
TTL–CMOS Mode 5.0 15 — 5.0 — 2.5 5.0 — 6.0
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14504B MOTOROLA CMOS LOGIC DATA

6–236
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ VCC VDD Limits

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Symbol Shifting Mode Vdc Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Propagation Delay, High to Low tPHL TTL – CMOS 5.0 10 — 140 280 ns
VDD > VCC 5.0 15 — 140 280

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
CMOS – CMOS
VDD > VCC
5.0
5.0
10
15
—
—
120
120
240
240

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 15 — 70 140
CMOS – CMOS 10 5.0 — 185 370

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VCC > VDD 15 5.0 — 185 370

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 10 — 175 350
Propagation Delay, Low to High tPLH TTL – CMOS 5.0 10 — 170 340 ns

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VDD > VCC
CMOS – CMOS
5.0
5.0
15
10
—
—
160
170
320
340

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD > VCC 5.0 15 — 170 340
10 15 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
CMOS – CMOS
VCC > VDD
10
15
15
5.0
5.0
10
—
—
—
275
275
145
550
550
290

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Output Rise and Fall Time

ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
tTLH, tTHL ALL —
—
—
5.0
10
15
—
—
—
100
50
40
200
100
80
ns

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

7 7
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)

VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)

6 6
VCC = 10 V
5 5

4 4

3 VCC = 5 V 3

2 2 VCC = 5 V

1 1

0 0
0 5 10 15 20 0 5 10 15 20
VDD, SUPPLY VOLTAGE (Vdc) VDD, SUPPLY VOLTAGE (Vdc)
Figure 1. Input Switchpoint CMOS to CMOS Mode Figure 2. Input Switchpoint TTL to CMOS Mode

ÉÉÉÉÉÉÉÉÉ ÉÉ
20 20

ÉÉÉÉÉÉÉÉÉ ÉÉ
ÉÉÉÉÉÉÉÉÉ ÉÉ
ÉÉÉÉÉÉÉÉÉ ÉÉ
15 15
VDD, SUPPLY VOLTAGE (Vdc)

VDD, SUPPLY VOLTAGE (Vdc)

ÉÉÉÉÉÉÉÉÉ ÉÉ
ÉÉÉÉÉÉÉÉÉ ÉÉ
ÉÉÉÉÉÉÉÉÉ ÉÉ
10 10

ÉÉÉÉÉÉÉÉÉ ÉÉ
5
ÉÉÉÉÉÉÉÉÉ 5
ÉÉ
ÉÉÉÉÉÉÉÉÉ
0 0
0 5 10 15 20 0 5 10 15 20
VCC, SUPPLY VOLTAGE (Vdc) VCC, SUPPLY VOLTAGE (Vdc)
Figure 3. Operating Boundary CMOS to CMOS Mode Figure 4. Operating Boundary TTL to CMOS Mode

MOTOROLA CMOS LOGIC DATA MC14504B

6–237
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14506UB

Dual 2-Wide, 2-Input

Expandable AND-OR-INVERT L SUFFIX
CERAMIC
Gate CASE 620

The MC14506UB is an expandable AND–OR–INVERT gate with inhibit

and 3–state output. The expand option allows cascading with any other gate, P SUFFIX
which may be carried as far as desired as long as the propagation delay PLASTIC
added with each gate is considered. For example, the second AOI gate in CASE 648
this device may be used to expand the first gate, giving an expanded 4–wide,
2–input AOI gate. This device is useful in data control and digital multiplexing
applications. D SUFFIX
• 3–State Output SOIC
CASE 751B
• Separate Inhibit Line
• Diode Protection on All Inputs ORDERING INFORMATION
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
MC14XXXUBCP Plastic
• Capable of Driving Two Low–Power TTL Loads or One Low–Power MC14XXXUBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range MC14XXXUBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V This device contains protection circuitry to
guard against damage due to high static
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
voltages or electric fields. However, pre-
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA cautions must be taken to avoid applications of
per Pin any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
PD Power Dissipation, per Package† 500 mW operation, Vin and Vout should be constrained
Tstg Storage Temperature – 65 to + 150 _C to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an
TL Lead Temperature (8–Second Soldering) 260 _C appropriate logic voltage level (e.g., either VSS
* Maximum Ratings are those values beyond which damage to the device may occur. or VDD). Unused outputs must be left open.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C TRUTH TABLE
A B C D E Inhibit Disable Z
LOGIC DIAGRAM 0 0 0 0 1 0 0 1
0 X 0 X 1 0 0 1
AA 1 0 X X 0 1 0 0 1
BA 2 X 0 0 X 1 0 0 1
CA 3 15 ZA X 0 X 0 1 0 0 1
DA 4 1 1 X X X X 0 0
EA 5 X X 1 1 X X 0 0
X X X X 0 X 0 0
VDD = PIN 16
INH 6 X X X X X 1 0 0
VSS = PIN 8
X X X X X X 1 High
3–STATE Impedance
DIS 14
OUTPUT DISABLE
X = Don’t Care
EB 13 7 ZB
DB 12
CB 11
BB 10
AB 9 Z = (AB + CD + E + I)

MC14506UB MOTOROLA CMOS LOGIC DATA

6–238
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.0 — 2.25 1.0 — 1.0
(VO = 9.0 or 1.0 Vdc) 10 — 2.0 — 4.50 2.0 — 2.0
(VO = 13.5 or 1.5 Vdc) 15 — 2.5 — 6.75 2.5 — 2.5
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 4.0 — 4.0 2.75 — 4.0 —
(VO = 1.0 or 9.0 Vdc) 10 8.0 — 8.0 5.50 — 8.0 —
(VO = 1.5 or 13.5 Vdc) 15 12.5 — 12.5 8.25 — 12.5 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 1.0 — 0.002 1.0 — 30 µAdc
(Per Package) 10 — 2.0 — 0.004 2.0 — 60
15 — 4.0 — 0.006 4.0 — 120
Total Supply Current**† IT 5.0 IT = (0.6 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.1 µA/kHz) f + IDD
Per Package) 15 IT = (1.7 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT

AA 1 16 VDD
BA 2 15 ZA
CA 3 14 DISABLE
DA 4 13 EB
EA 5 12 DB
INH 6 11 CB
ZB 7 10 BB
VSS 8 9 AB

MOTOROLA CMOS LOGIC DATA MC14506UB

6–239
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, tTHL ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Data Propagation Delay Time tPLH ns
tPLH = (1.7 ns/pF) CL + 210 ns 5.0 — 295 580
tPLH = (0.66 ns/pF) CL + 77 ns 10 — 110 225
tPLH = (0.5 ns/pF) CL + 50 ns 15 — 75 180
tPHL = (1.7 ns/pF) CL + 185 ns tPHL 5.0 — 270 480 ns
tPHL = (0.66 ns/pF) CL + 62 ns 10 — 95 175
tPHL = (0.5 ns/pF) CL + 40 ns 15 — 65 140
Expand Propagation Delay Time tPLH ns
tPLH = (1.7 ns/pF) CL + 95 ns 5.0 — 180 430
tPLH = (0.66 ns/pF) CL + 42 ns 10 — 75 160
tPLH = (0.5 ns/pF) CL + 25 ns 15 — 50 125
tPHL = (1.7 ns/pF) CL + 115 ns tPHL 5.0 — 200 330 ns
tPHL = (0.66 ns/pF) CL + 47 ns 10 — 80 110
tPHL = (0.5 ns/pF) CL + 30 ns 15 — 55 90
Inhibit Propagation Delay Time tPLH ns
tPLH = (1.7 ns/pF) CL + 135 ns 5.0 — 220 500
tPLH = (0.66 ns/pF) CL + 67 ns 10 — 100 225
tPLH = (0.5 ns/pF) CL + 40 ns 15 — 65 160
tPHL = (1.7 ns/pF) CL + 145 ns tPHL 5.0 — 230 400 ns
tPHL = (0.66 ns/pF) CL + 62 ns 10 — 95 175
tPHL = (0.5 ns/pF) CL + 35 ns 15 — 60 150
3–State Propagation Delay Time tPHZ ns
“1” to High Impedance 5.0 — 60 150
10 — 45 110
15 — 35 90
“0” to High Impedance tPLZ 5.0 — 90 225 ns
10 — 55 140
15 — 40 100
High Impedance to “1” tPZH 5.0 — 110 300 ns
10 — 50 125
15 — 40 100
High Impedance to “0” tPZL 5.0 — 170 425 ns
10 — 70 175
15 — 50 125
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” Is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

16 16

14 VDD = 15 Vdc 14 VDD = 15 Vdc a TA = + 125°C

a
b a b TA = + 25°C
Vout , OUTPUT VOLTAGE (Vdc)

Vout , OUTPUT VOLTAGE (Vdc)

12 c 12 b c TA = – 55°C
c
10 Vdc 10 Vdc
10 a 10
b a
8.0 UNUSED INPUTS 8.0 b
c
CONNECTED TO c A AND B CONNECTED TO Vin
6.0 5.0 Vdc VSS 6.0 5.0 Vdc ENABLE INPUT CONNECTED TO
a VDD. OTHER INPUTS CONNECTED
4.0 b 4.0 a
a TA = + 125°C b TO VSS.
c b TA = + 25°C c
2.0 2.0
c TA = – 55°C
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 2.0 4.0 6.0 8.0 10 12 14 16
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)
(a) Expand Inputs (b) Data Inputs

Figure 1. Typical Voltage Transfer Characteristics

MC14506UB MOTOROLA CMOS LOGIC DATA

6–240
 VDD VDD
16 16

VOH VOL
INH ZA INH ZA
AA AA
BA IOH BA IOL
CA CA
DA DA
EA EA
AB EXTERNAL AB EXTERNAL
BB POWER BB POWER
SUPPLY SUPPLY
CB CB
DB DB
EB EB
DIS ZB DIS ZB

8 VSS 8 VSS

Figure 2. Typical Output Source Figure 3. Typical Output Sink

Characteristics Test Circuit Characteristics Test Circuit

0.01 µF
CERAMIC
VDD

VDD 16

VDD INH ZA
16
AA
INH ZA BA
CA
AA PULSE B
BA DA
GENERATOR EA
CA ITL
DA 50% DUTY CYCLE A AB
EA BB
CB
AB
DB
BB
CB EB
DB DIS ZB
EB
DIS ZB 8 VSS
CL CL
8 VSS 500 µF IDD

Figure 4. 3–State Leakage Current Figure 5. Typical Power Dissipation

Test Circuit Test Circuit

MOTOROLA CMOS LOGIC DATA MC14506UB

6–241
 VDD
16

INH ZA
AA 20 ns 20 ns
BA
PULSE CA VDD
GENERATOR DA 90%
INPUT 50%
EA 10% VSS
AB
tPHL tPLH
BB
CB 90% VOH
DB OUTPUT 50%
10%
EB VOL
DIS ZB

CL CL tTHL tTLH
8 VSS

Figure 6. Switching Time Test Circuit and Waveforms

(Data Inputs)

VDD Vout VDD

16

INH ZA
AA 20 ns
BA 20 ns
CA CL 1k DISABLE 90%
50%
DA INPUT 10%
B S1
EA S2 A
A AB tPLZ tPZL
BB B VOH
90%
CB 10% ≈ 2.5 V @ VDD = 5 V,
DB 10 V AND 15 V
EB OUTPUT tPHZ ≈ 2 V @ VDD = 5 V
tPZH
PULSE DIS ZB ≈ 6 V @ VDD = 10 V
GENERATOR 90% ≈ 10 V @ VDD = 15 V
10%
VOL
8 VSS
* To test other side of circuit connect to this output and
change switch (S1) to other expand input (E).

SWITCH POSITIONS
TEST S1 S2
tPLZ A A
tPHZ B B
tPZL A A
tPZH B B

Figure 7. Switching Time Test Circuit and Waveforms

(For 3–State Output)

MC14506UB MOTOROLA CMOS LOGIC DATA

6–242
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14508B
Dual 4-Bit Latch
The MC14508B dual 4–bit latch is constructed with MOS P–channel and L SUFFIX
N–channel enhancement mode devices in a single monolithic structure. The CERAMIC
part consists of two identical, independent 4–bit latches with separate Strobe CASE 623
(ST) and Master Reset (MR) controls. Separate Disable inputs force the
outputs to a high impedance state and allow the devices to be used in time
sharing bus line applications. P SUFFIX
These complementary MOS latches find primary use in buffer storage, PLASTIC
holding register, or general digital logic functions where low power CASE 709
dissipation and/or high noise immunity is desired.
• 3–State Output
• Supply Voltage Range = 3.0 Vdc to 18 Vdc DW SUFFIX
• Capable–of Driving Two Low–power TTL Loads or One Low–power SOIC
CASE 751E

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to VSS) ORDERING INFORMATION
Symbol Parameter Value Unit MC14XXXBCP Plastic
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBCL Ceramic
MC14XXXBDW SOIC
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
TA = – 55° to 125°C for all packages.
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C BLOCK DIAGRAM
TL Lead Temperature (8–Second Soldering) 260 _C
1 MR Q0 5
* Maximum Ratings are those values beyond which damage to the device may occur. 2 ST
†Temperature Derating: 3 DIS Q1 7
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 4 D0
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 6 D1 Q2 9
TRUTH TABLE 8 D2
10 D3 Q3 11
MR ST Disable D3 D2 D1 D0 Q3 Q2 Q1 Q0
0 1 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 1 0 0 0 1
13 MR Q0 17
0 1 0 0 0 1 0 0 0 1 0 14 ST
0 1 0 0 1 0 0 0 1 0 0 15 DIS Q1 19
0 1 0 1 0 0 0 1 0 0 0 16 D0
18 D1 Q2 21
0 0 0 X X X X Latched 20 D2
22 D3 Q3 23
1 X 0 X X X X 0 0 0 0
X X 1 X X X X High Impedance
X = Don’t Care VDD = PIN 24
VSS = PIN 12
CIRCUIT DIAGRAM
DIS VDD

MR

ST

Dn Qn

(TO OTHER THREE LATCHES)

VSS

MOTOROLA CMOS LOGIC DATA MC14508B

6–243
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.46 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.91 µA/kHz) f + IDD
Per Package) 15 IT = (4.37 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.008.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14508B MOTOROLA CMOS LOGIC DATA

6–244
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
All Types
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, tTHL ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time, Dn or MR to Q tPLH, tPHL ns
tPLH, tPHL = (1.7 ns/pF) CL + 135 ns 5.0 — 220 440
tPLH, tPHL = (0.66 ns/pF) CL + 57 ns 10 — 90 180
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns 15 — 60 120
Master Reset Pulse Width tWH(R) 5.0 200 100 — ns
10 100 50 —
15 70 35 —
Master Reset Removal Time trem 5.0 30 – 15 — ns
10 25 0 —
15 20 0 —
Strobe Pulse Width tWH(S) 5.0 140 70 — ns
10 70 35 —
15 40 20 —
Setup Time tsu 5.0 50 25 — ns
Data to Strobe 10 20 10 —
15 10 5.0 —
Hold Time th 5.0 50 20 — ns
Strobe to Data 10 35 10 —
15 35 10 —
3–State Propagation Delay Time tPHZ ns
Output “1” to High Impedance 5.0 — 55 170
10 — 35 100
15 — 30 70
Output “0” to High Impedance tPLZ 5.0 — 75 170
10 — 40 100
15 — 35 70
High Impedance to “1” Level tPZH 5.0 — 80 170
10 — 35 100
15 — 30 70
High Impedance to “0” Level tPZL 5.0 — 105 210
10 — 50 100
15 — 35 70
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

PIN ASSIGNMENT

MRA 1 24 VDD
STA 2 23 Q3B
DISA 3 22 D3B
D0A 4 21 Q2B
Q0A 5 20 D2B
D1A 6 19 Q1B
Q1A 7 18 D1B
D2A 8 17 Q0B
Q2A 9 16 D0B
D3A 10 15 DISB
Q3A 11 14 STB
VSS 12 13 MRB

MOTOROLA CMOS LOGIC DATA MC14508B

6–245
 tWH(S)
STROBE
INPUT 50% 50%
tsu tWH(R)
th VDD
MASTER RESET
Dn INPUT 50%
50% INPUT
VSS
VOH
tPLH tPHL Qn OUTPUT
90%
Qn OUTPUT 50% VOL
10%
tTLH tTHL

Figure 1. AC Waveforms

VDD

VDD Test ST1 ST2 ST3 ST4

PULSE MR Q0
ST tPHZ Open Close Close Open
GENERATOR ST1
VDD DISABLE Q1 tPLZ Close Open Open Close
D0
D1 Q2 tPZL Close Open Open Close
1.0 k
ST3 D2 tPZH Open Close Close Open
D3 Q3
1.0 k
ST4
VSS CL
ST2

20 ns 20 ns
VDD
90%
50%
10%
DISABLE VSS
tPLZ tPZL
VOH
90%
10% ≈ 2.5 V @ VDD = 5 V,
Q3 OUTPUT tPHZ tPZH 10 V, AND 15 V
≈ 2 V @ VDD = 5 V
90% ≈ 6 V @ VDD = 10 V
≈ 10 V @ VDD = 15 V
10%
VOL

Figure 2. 3–State AC Test Circuit and Waveforms

MC14508B MOTOROLA CMOS LOGIC DATA

6–246
 3–STATE MODE OF OPERATION IOD

The MC14508B can be used in bussed systems as shown.

The output terminals of N 4–bit latches can be directly wired SELECTED AS 1/2
to a bus line, and to one of the 4–bit latches selected. The DRIVING DEVICE MC14508B
selected latch controls the logic state of the bus line and the
remaining (N–1) 4–bit latches are disabled into a high imped-
ance “off” state. The number of latches, N, which may be IOD
connected to a bus line is determined from the output drive
current, IOD, the 3–state or disabled output leakage current,
ITL
ITL, and the load current, IL, required to drive the bus line (in-
1/2
cluding fanout to other device inputs) and can be calculated DISABLED
MC14508B
by the following:
IOD – IL
N= +1
ITL ITL

N must be calculated for both high and low logic states of the
bus line. ITL
1/2
DISABLED
MC14508B

IL
ITL
IL
BUS LINES

TYPICAL 3–STATE APPLICATIONS

EXAMPLE 1

RESET
CLOCK
MC14015B
4–BIT SHIFT 4–BIT SHIFT
SERIAL REGISTER REGISTER
DATA

STROBE
MC
QUAD LATCH 14508B QUAD LATCH
DISABLE (3–STATE) (3–STATE)

DISABLE

4–LINE DATA BUS

EXAMPLE 2
DATA BUS

3–STATE 3–STATE
4–BIT LATCH 4–BIT LATCH
MC MC
14508B 14508B
4–LINE DATA BUS
MC14519B
4–LINE DATA BUS

A
B
3–STATE 3–STATE
4–BIT LATCH 4–BIT LATCH

MOTOROLA CMOS LOGIC DATA MC14508B

6–247
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14510B

BCD Up/Down Counter

The MC14510B synchronous up/down BCD counter is constructed with
L SUFFIX
MOS P–channel and N–channel enhancement mode devices in a monolithic
CERAMIC
structure. The counter consists of type D flip–flop stages with a gating
CASE 620
structure to provide type T flip–flop capability.
This counter can be preset by applying the desired value in BCD to the
Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up P SUFFIX
counting) or a low (for down counting) to the UP/DOWN input. The state of PLASTIC
the counter changes on the positive transition of the clock input. CASE 648
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the D SUFFIX
Reset (R) pin. SOIC
This CMOS counter finds primary use in up/down and difference counting. CASE 751B
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analog–to– ORDERING INFORMATION
digital and digital–to–analog conversions, and (3) Magnitude and sign MC14XXXBCP Plastic
generation. MC14XXXBCL Ceramic
• Diode Protection on All Inputs MC14XXXBD SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc TA = – 55° to 125°C for all packages.
• Internally Synchronous for High Speed
• Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock
BLOCK DIAGRAM
• Asynchronous Preset Enable Operation
• Capable of Driving Two Low–power TTL Loads or One Low–power

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1 PE Q1 6
Schottky TTL Load Over the Rated Temperature Range.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5 CARRY IN
MAXIMUM RATINGS* (Voltages Referenced to VSS) 9 R Q2 11
Symbol Parameter Value Unit 10 UP/DOWN
15 CLOCK Q3 14
VDD DC Supply Voltage – 0.5 to + 18.0 V
4 P1
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V 12 P2 Q4 2
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA 13 P3
CARRY
per Pin 3 P4 7
OUT
PD Power Dissipation, per Package† 500 mW
VDD = PIN 16
Tstg Storage Temperature – 65 to + 150 _C VSS = PIN 8
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the may occur.
†Temperature Derating: This device contains protection circuitry to
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C guard against damage due to high static
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C voltages or electric fields. However, pre-
TRUTH TABLE cautions must be taken to avoid applications of
Preset any voltage higher than maximum rated volt-
Enable ages to this high–impedance circuit. For proper
Carry In Up/Down Reset Clock Action
operation, Vin and Vout should be constrained
1 X 0 0 X No Count to the range VSS v (Vin or Vout) v VDD.
0 1 0 0 Count Up Unused inputs must always be tied to an
0 0 0 0 Count Down appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
X X 1 0 X Preset
X X X 1 X Reset
X = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high, and is low only
when Q1 and Q4 are high and Carry In is low. When counting down, Carry
Out is low only when Q1 through Q4 and Carry In are low.

MC14510B MOTOROLA CMOS LOGIC DATA

6–248
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.58 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.20 µA/kHz) f + IDD
Per Package) 15 IT = (1.70 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT

PE 1 16 VDD
Q4 2 15 C
P4 3 14 Q3
P1 4 13 P3
CARRY IN 5 12 P2
Q1 6 11 Q2
CARRY OUT 7 10 U/D
VSS 8 9 R

MOTOROLA CMOS LOGIC DATA MC14510B

6–249
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C, See Figure 2)

Characteristic Symbol VDD Min

All Types
Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Clock to Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns 5.0 — 315 630
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 200
Clock to Carry Out tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPHL 5.0 — 315 630
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 200
Carry In to Carry Out tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPHL 5.0 — 180 360
tPLH, tPHL = (0.66 ns/pF) CL + 47 ns 10 — 80 160
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns 15 — 60 120
Preset or Reset to Q tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPHL 5.0 — 315 630
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 200
Preset or Reset to Carry Out tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPHL 5.0 — 550 1100
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns 10 — 225 450
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns 15 — 150 300
Reset Pulse Width tw(H) 5.0 360 180 — ns
10 210 105 —
15 160 80 —
Clock Pulse Width tw(H) 5.0 350 200 — ns
10 170 100 —
15 140 75 —
Clock Pulse Frequency fcl 5.0 — 3.0 1.5 MHz
10 — 6.0 3.0
15 — 8.0 4.0
Preset or Reset Removal Time trem 5.0 650 325 — ns
The Preset or Reset Signal must be low prior to a 10 230 115 —
positive–going transition of the clock. 15 180 90 —
Clock Rise and Fall Time tTLH, 5.0 — — 15 µs
tTHL 10 — — 5
15 — — 4
Setup Time tsu 5.0 260 130 — ns
Carry In to Clock 10 120 60 —
15 100 50 —
Hold Time th 5.0 0 – 50 — ns
Clock to Carry In 10 10 – 15 —
15 10 –5 —
Setup Time tsu 5.0 500 250 — ns
Up/Down to Clock 10 200 100 —
15 175 75 —
Hold Time th 5.0 – 70 – 140 — ns
Clock to Up/Down 10 – 30 – 80 —
15 – 20 – 50 —
Setup Time tsu 5.0 – 50 – 100 — ns
Pn to PE 10 – 30 – 65 —
15 – 25 – 55 —
Hold Time th 5.0 480 240 — ns
PE to Pn 10 410 205 —
15 410 205 —
Preset Enable Pulse Width tWH 5.0 200 100 — ns
10 100 50 —
15 80 40 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14510B MOTOROLA CMOS LOGIC DATA

6–250
 VDD

500 pF ID 0.01 µF
CERAMIC

PE Q1
CARRY IN
R Q2
PULSE UP/DOWN
GENERATOR CLOCK Q3
CL
P1
P2 Q4 CL
P3 CL
CARRY
P4 OUT CL
CL

20 ns 20 ns
VDD
90%
CLOCK 50%
10%
VARIABLE VSS
WIDTH

Figure 1. Power Dissipation Test Circuit and Waveform

VDD

PE Q1
PROGRAMMABLE CARRY IN
PULSE R Q2
GENERATOR UP/DOWN
CLOCK Q3
CL
P1
P2 Q4 CL
P3 CL
CARRY
P4 OUT CL
CL
VSS

tsu trem
1
fcl
CARRY IN OR VDD
50%
UP/DOWN VSS
VDD
CLOCK 50%
VSS
tw(H) tw(H)
VDD
PRESET ENABLE
VSS
20 ns
tTLH
CARRY OUT ONLY
90% VOH
Q1 OR CARRY OUT 90%
10% 10%
VOL
tPHL

tTHL tPLH tPLH

trem
VDD
RESET VSS
tw(H)

Figure 2. Switching Time Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14510B

6–251
 LOGIC DIAGRAM

P1 Q1 P2 Q2 P3 Q3 P4 Q4
4 6 12 11 13 14 3 2

RESET

PRESET ENABLE

CLOCK P P P P
PE Q PE Q PE Q PE Q
CARRY OUT C C C C
D Q D Q D Q D Q

CARRY IN

UP/DOWN

STATE DIAGRAM FOR UP COUNTING STATE DIAGRAM FOR DOWN COUNTING

0 1 2 3 4 0 1 2 3 4

15 5 15 5

14 6 14 6

13 7 13 7

12 11 10 9 8 12 11 10 9 8

MC14510B MOTOROLA CMOS LOGIC DATA

6–252
 PIN DESCRIPTIONS

INPUTS synchronous output is active low and may also be used to

P1, P2, P3, P4, Preset Inputs (Pins 4, 12, 13, 3) — Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) — Active–low input used when cascading
stages. Usually connected to Carry Out of the previous
stage. While high, clock is inhibited.
Clock, (Pin 15) — BCD data is incremented or de-
cremented, depending on the direction of count, on the posi-
tive transition of this signal.
OUTPUTS
Q1, Q2, Q3, Q4, BCD outputs (Pins 6, 11, 14, 2) — BCD
data is present on these outputs with Q1 corresponding to
the least significant bit.
Carry Out, (Pin 7) — Used when cascading stages, this
pin is usually connected to Carry In of the next stage. This
indicate terminal count.
CONTROLS
PE, Preset Enable (Pin 1) — Asynchronously loads data
on the Preset Inputs. This pin is active high and will inhibit the
clock when high.
R, Reset, (Pin 9) — Asynchronously resets the Q outputs
to a low state. This pin is active high and will inhibit the clock
when high.
Up/Down, (Pin 10) — Controls the direction of count: high
for up count, low for down count.
SUPPLY PINS
VSS, Negative Supply Voltage, (Pin 8) — This pin is
usually connected to ground.
VDD, Positive Supply Voltage, (Pin 16) — This pin is con-
nected to a positive supply voltage ranging from 3.0 Vdc to
18.0 Vdc.

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
PRESET
ENABLE
0 = COUNT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PE PE TERMINAL
1 = PRESET
Cin Cout Cin Cout COUNT
L.S.D. CLOCK M.S.D. INDICATOR
CLOCK
1 = UP MC14510B MC14510B
U/D U/D
0 = DOWN
R R
P1 P2 P3 P4 P1 P2 P3 P4

P1 P2 P3 P4 P5 P6 P7 P8

+ VDD + VDD
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
RESISTORS = 10 kΩ
CLOCK
RESET
+ VDD
OPEN = COUNT

Note: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) does not change while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 9
(count up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one
count. The L.S.D. now counts through another cycle (10 clock pulses) and the above cycle is repeated.

Figure 3. Presettable Cascaded 8–Bit Up/Down Counter

MOTOROLA CMOS LOGIC DATA MC14510B

6–253
 TIMING DIAGRAM FOR THE PRESETTABLE
CASCADED 8–BIT UP/DOWN COUNTER

CLOCK

UP/DOWN

CARRY IN
(MSD)
PE

P8

P7

P6

P5

P4

P3

P2

P1

CARRY OUT
(MSD)
Q8

Q7

Q6

Q5

Q4
Q3

Q2

Q1

CARRY OUT
(LSD)
RESET

COUNT MSD 6 6 6 7 7 7 7 7 7 7 6 6 6 6 9 9 9 9 9 0 0 0 0 0 0 0 0
COUNT LSD 7 8 9 0 1 2 3 2 1 0 9 8 7 6 6 6 7 8 9 0 1 2 1 0 1 0 0

PRESET ENABLE PRESET RESET

ENABLE DOWN
COUNT
UP COUNT DOWN COUNT UP COUNT UP COUNT

MC14510B MOTOROLA CMOS LOGIC DATA

6–254
 fout

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 BUFFER

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PE PE
Cin Cout Cin Cout
CLOCK L.S.D. CLOCK M.S.D.
MC14510B MC14510B
U/D U/D
R R
P1 P2 P3 P4 P1 P2 P3 P4

P0 P1 P2 P3 P4 P5 P6 P7

+ VDD + VDD
THUMBWHEEL SWITCHES
(OPEN FOR “0”) RESISTORS = 10 kΩ
CLOCK (fin) f
RESET fout = in
+ VDD n
OPEN = COUNT

Note: The programmable frequency divider can be set by applying the desired divide ratio, in BCD, to the preset inputs. For
example, the maximum divide ratio of 99 may be obtained by applying a 10011001 to the preset inputs P0 to P7. For this divide
operation, both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and
should be avoided.

Figure 4. Programmable Cascaded Frequency Divider

MOTOROLA CMOS LOGIC DATA MC14510B

6–255
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14511B
BCD-To-Seven Segment
Latch/Decoder/Driver L SUFFIX
CERAMIC
The MC14511B BCD–to–seven segment latch/decoder/driver is CASE 620
constructed with complementary MOS (CMOS) enhancement mode devices
and NPN bipolar output drivers in a single monolithic structure. The circuit
P SUFFIX
provides the functions of a 4–bit storage latch, an 8421 BCD–to–seven PLASTIC
segment decoder, and an output drive capability. Lamp test (LT), blanking CASE 648
(BI), and latch enable (LE) inputs are used to test the display, to turn–off or
pulse modulate the brightness of the display, and to store a BCD code,
respectively. It can be used with seven–segment light–emitting diodes D SUFFIX
SOIC
(LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts
CASE 751B
either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display driver,
computer/calculator display driver, cockpit display driver, and various clock, DW SUFFIX
SOIC
watch, and timer uses.
CASE 751G
• Low Logic Circuit Power Dissipation
• High–Current Sourcing Outputs (Up to 25 mA) ORDERING INFORMATION
• Latch Storage of Code MC14XXXBCP Plastic
MC14XXXBCL Ceramic
• Blanking Input MC14XXXBDW SOIC
• Lamp Test Provision MC14XXXBD SOIC
• Readout Blanking on all Illegal Input Combinations TA = – 55° to 125°C for all packages.
• Lamp Intensity Modulation Capability
• Time Share (Multiplexing) Facility
PIN ASSIGNMENT
• Supply Voltage Range = 3.0 V to 18 V
• Capable of Driving Two Low–power TTL Loads, One Low–power B 1 16 VDD
Schottky TTL Load or Two HTL Loads Over the Rated Temperature C 2 15 f
Range a
LT 3 14 g
• Chip Complexity: 216 FETs or 54 Equivalent Gates f g b
BI 4 13 a
• Triple Diode Protection on all Inputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
e c
LE 5 12 b
MAXIMUM RATINGS* (Voltages Referenced to VSS) d
D 6 11 c
Rating Symbol Value Unit
A 7 10 d
DC Supply Voltage VDD – 0.5 to + 18 V
VSS 8 9 e
Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 V
DISPLAY
DC Current Drain per Input Pin I 10 mA
Operating Temperature Range TA – 55 to + 125 _C
0 1 2 3 4 5 6 7 8 9
Power Dissipation per Package† PD 500 mW
TRUTH TABLE
Storage Temperature Range Tstg – 65 to + 150 _C
Inputs Outputs

Maximum Output Drive Current IOHmax 25 mA LE BI LT D C B A a b c d e f g Display

X X 0 X X X X 1 1 1 1 1 1 1 8
(Source) per Output
X 0 1 X X X X 0 0 0 0 0 0 0 Blank
0 1 1 0 0 0 0 1 1 1 1 1 1 0 0
Maximum Continuous Output Power POHmax 50 mW 0 1 1 0 0 0 1 0 1 1 0 0 0 0 1
0 1 1 0 0 1 1 1 1 1 1 0 0 1 2
(Source) per Output ‡ 0 1 1 0 0 1 1 1 1 1 1 0 0 1 3
0 1 1 0 1 0 0 0 1 1 0 0 1 1 4
‡POHmax = IOH (VDD – VOH) 0 1 1 0 1 0 1 1 0 1 1 0 1 1 5
0 1 1 0 1 1 0 0 0 1 1 1 1 1 6
* Maximum Ratings are those values beyond which damage to the device may occur. 0 1 1 0 1 1 1 1 1 1 0 0 0 0 7

†Temperature Derating: 0 1 1 1 0 0 0 1 1 1 1 1 1 1 8
0 1 1 1 0 0 1 1 1 1 0 0 1 1 9
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 0 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 1 0 0 0 0 0 0 0 Blank
1 1 1 X X X X * *
X = Don’t Care
* Depends upon the BCD code previously applied when LE = 0

MC14511B MOTOROLA CMOS LOGIC DATA

6–256
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.1 — 4.1 4.57 — 4.1 — Vdc
Vin = 0 or VDD 10 9.1 — 9.1 9.58 — 9.1 —
15 14.1 — 14.1 14.59 — 14.1 —
Input Voltage # “0” Level VIL Vdc
(VO = 3.8 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 8.8 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.8 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 3.8 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 8.8 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.8 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Voltage VOH Vdc
(IOH = 0 mA) Source 5.0 4.1 — 4.1 4.57 — 4.1 —
(IOH = 5.0 mA) — — — 4.24 — — —
(IOH = 10 mA) 3.9 — 3.9 4.12 — 3.5 —
(IOH = 15 mA) — — — 3.94 — — —
(IOH = 20 mA) 3.4 — 3.4 3.70 — 3.0 —
(IOH = 25 mA) — — — 3.54 — — —
(IOH = 0 mA) 10 9.1 — 9.1 9.58 — 9.1 — Vdc
(IOH = 5.0 mA) — — — 9.26 — — —
(IOH = 10 mA) 9.0 — 9.0 9.17 — 8.6 —
(IOH = 15 mA) — — — 9.04 — — —
(IOH = 20 mA) 8.6 — 8.6 8.90 — 8.2 —
(IOH = 25 mA) — — — 8.70 — — —
(IOH = 0 mA) 15 14.1 — 14.1 14.59 — 14.1 — Vdc
(IOH = 5.0 mA) — — — 14.27 — — —
(IOH = 10 mA) 14 — 14 14.18 — 13.6 —
(IOH = 15 mA) — — — 14.07 — — —
(IOH = 20 mA) 13.6 — 13.6 13.95 — 13.2 —
(IOH = 25 mA) — — — 13.70 — — —
Output Drive Current IOL mAdc
(VOL = 0.4 V) Sink 5.0 0.64 — 0.51 0.88 — 0.36 —
(VOL = 0.5 V) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 V) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) Vin = 0 or VDD, 10 — 10 — 0.010 10 — 300
Iout = 0 µA 15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.9 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.8 µA/kHz) f + IDD
Per Package) 15 IT = (5.7 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.

MOTOROLA CMOS LOGIC DATA MC14511B

6–257
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Characteristic Symbol
VDD
Vdc Min Typ Max Unit
Output Rise Time tTLH ns
tTLH = (0.40 ns/pF) CL + 20 ns 5.0 — 40 80
tTLH = (0.25 ns/pF) CL + 17.5 ns 10 — 30 60
tTLH = (0.20 ns/pF) CL + 15 ns 15 — 25 50
Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 50 ns 5.0 — 125 250
tTHL = (0.75 ns/pF) CL + 37.5 ns 10 — 75 150
tTHL = (0.55 ns/pF) CL + 37.5 ns 15 — 65 130
Data Propagation Delay Time tPLH ns
tPLH = (0.40 ns/pF) CL + 620 ns 5.0 — 640 1280
tPLH = (0.25 ns/pF) CL + 237.5 ns 10 — 250 500
tPLH = (0.20 ns/pF) CL + 165 ns 15 — 175 350
tPHL = (1.3 ns/pF) CL + 655 ns tPHL 5.0 — 720 1440
tPHL = (0.60 ns/pF) CL + 260 ns 10 — 290 580
tPHL = (0.35 ns/pF) CL + 182.5 ns 15 — 200 400

Blank Propagation Delay Time tPLH ns

tPLH = (0.30 ns/pF) CL + 585 ns 5.0 — 600 750
tPLH = (0.25 ns/pF) CL + 187.5 ns I0 — 200 300
tPLH = (0.15 ns/pF) CL + 142.5 ns 15 — 150 220

tPHL = (0.85 ns/pF) CL + 442.5 ns tPHL 5.0 — 485 970

tPHL = (0.45 ns/pF) CL + 177.5 ns 10 — 200 400
tPHL = (0.35 ns/pF) CL + 142.5 ns 15 — 160 320

Lamp Test Propagation Delay Time tPLH ns

tPLH = (0.45 ns/pF) CL + 290.5 ns 5.0 — 313 625
tPLH = (0.25 ns/pF) CL + 112.5 ns 10 — 125 250
tPLH = (0.20 ns/pF) CL + 80 ns 15 — 90 180

tPHL = (1.3 ns/pF) CL + 248 ns tPHL 5.0 — 313 625

tPHL = (0.45 ns/pF) CL + 102.5 ns 10 — 125 250
tPHL = (0.35 ns/pF) CL + 72.5 ns 15 — 90 180

Setup Time tsu 5.0 100 — — ns

10 40 — —
15 30 — —
Hold Time th 5.0 60 — — ns
10 40 — —
15 30 — —
Latch Enable Pulse Width tWL 5.0 520 260 — ns
10 220 110 —
15 130 65 —
* The formulas given are for the typical characteristics only.

This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; how-
ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit. A destructive high current mode may occur if Vin and Vout are not constrained to the range VSS ≤ (Vin or
Vout) ≤ VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to
VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).

MC14511B MOTOROLA CMOS LOGIC DATA

6–258
 Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective CL loads.

20 ns 20 ns
VDD
90%
A, B, AND C 50%
1 10% VSS
2f
50% DUTY CYCLE
VOH
50%
ANY OUTPUT
VOL

Figure 1. Dynamic Power Dissipation Signal Waveforms

20 ns 20 ns
90% VDD
INPUT C 50%
10%
VSS
tPLH tPHL
VOH
90%
OUTPUT g 50%
10% VOL

tTLH tTHL

(a) Inputs D and LE low, and Inputs A, B, BI and LT high.

20 ns
VDD
90%
50%
LE 10%
VSS
th
tsu
VDD

INPUT C 50%
VSS

VOH
OUTPUT g

VOL
(b) Input D low, Inputs A, B, BI and LT high.

20 ns
20 ns
VDD
90%
LE 50%
10% VSS
tWL

(c) Data DCBA strobed into latches.

Figure 2. Dynamic Signal Waveforms

MOTOROLA CMOS LOGIC DATA MC14511B

6–259
 CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIGHT EMITTING DIODE (LED) READOUT

VDD VDD

COMMON
ANODE LED
COMMON ≈ 1.7 V
CATHODE LED

≈ 1.7 V

VSS
VSS

INCANDESCENT READOUT FLUORESCENT READOUT

VDD VDD VDD

** DIRECT
(LOW BRIGHTNESS)

FILAMENT
SUPPLY
VSS
VSS VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
(CAUTION: Maximum working voltage = 18.0 V)

GAS DISCHARGE READOUT LIQUID CRYSTAL (LCD) READOUT

EXCITATION
APPROPRIATE (SQUARE WAVE,
VDD VOLTAGE VDD VSS TO VDD)

1/4 OF MC14070B

VSS VSS

** A filament pre–warm resistor is recommended to reduce filament Direct dc drive of LCD’s not recommended for life of
thermal shock and increase the effective cold resistance of the LCD readouts.
filament.

MC14511B MOTOROLA CMOS LOGIC DATA

6–260
 LOGIC DIAGRAM

BI 4

13 a

A 7
12 b

11 c

B 1
10 d

9 e

15 f
C 2

14 g
LT 3

D 6

VDD = PIN 16
LE 5 VSS = PIN 8

MOTOROLA CMOS LOGIC DATA MC14511B

6–261
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14512B
8-Channel Data Selector
The MC14512B is an 8–channel data selector constructed with MOS L SUFFIX
CERAMIC
P–channel and N–channel enhancement mode devices in a single
CASE 620
monolithic structure. This data selector finds primary application in signal
multiplexing functions. It may also be used for data routing, digital signal
switching, signal gating, and number sequence generation.
P SUFFIX
• Diode Protection on All Inputs PLASTIC
• Single Supply Operation CASE 648
• 3–State Output (Logic “1”, Logic “0”, High Impedance)
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power D SUFFIX
SOIC
Schottky TTL Load Over the Rated Temperature Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CASE 751B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
ORDERING INFORMATION
MC14XXXBCP Plastic
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBCL Ceramic
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package† 500 mW
PIN ASSIGNMENT
Tstg Storage Temperature – 65 to + 150 _C
X0 1 16 VDD
TL Lead Temperature (8–Second Soldering) 260 _C
X1 2 15 DIS
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: X2 3 14 Z
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
X3 4 13 C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
X4 5 12 B
TRUTH TABLE X5 6 11 A
C B A Inhibit Disable Z X6 7 10 INH
0 0 0 0 0 X0 VSS 8 9 X7
0 0 1 0 0 X1
0 1 0 0 0 X2
0 1 1 0 0 X3
1 0 0 0 0 X4 This device contains protection circuitry to
1 0 1 0 0 X5 guard against damage due to high static
1 1 0 0 0 X6 voltages or electric fields. However, pre-
1 1 1 0 0 X7 cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
X X X 1 0 0
ages to this high–impedance circuit. For proper
X X X X 1 High
operation, Vin and Vout should be constrained
Impedance
to the range VSS v (Vin or Vout) vVDD.
X = Don’t Care Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.

MC14512B MOTOROLA CMOS LOGIC DATA

6–262
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.8 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.6 µA/kHz) f + IDD
Per Package) 15 IT = (2.4 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MOTOROLA CMOS LOGIC DATA MC14512B

6–263
 SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C, See Figure 1)
All Types
Characteristic Symbol VDD Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 40 80
Propagation Delay Time (Figure 2) tPLH ns
Inhibit, Control, or Data to Z 5.0 330 650
10 125 250
15 85 170
Propagation Delay Time (Figure 2) tPHL ns
Inhibit, Control, or Data to Z 5.0 330 650
10 125 250
15 85 170
3–State Output Delay Times (Figure 3) tPHZ, tPLZ, 5.0 60 150 ns
“1” or “0” to High Z, and tPZH, tPZL 10 35 100
High Z to “1” or “0” 15 30 75
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

ID VDD

DISABLE
INHIBIT Z
A CL
B
C
X0
X1
PULSE X2
Vin 50% GENERATOR
50% X3
DUTY X4
CYCLE X5
X6
X7
VSS

Figure 1. Power Dissipation Test Circuit and Waveform

VDD
20 ns 20 ns
90% VDD
DISABLE DATA 50%
INHIBIT Z 10% VSS
A tPLH tPHL
CL 90% VOH
B 50%
C Z 10%
VOL
X0 tTLH tTHL
PULSE X1
GENERATOR TEST CONDITIONS:
X2 INHIBIT = VSS
X3 A, B, C = VSS
X4
X5 20 ns 20 ns
X6 INHIBIT, VDD
90%
X7 A, B, OR C 50%
10% VSS
tPHL tPLH
VSS Parameter Test Conditions 90% VOH
50%
Inhibit to Z A, B, C = VSS, XO = VDD Z 10% VOL
A, B, C to Z Inh = VSS, XO = VDD tTHL tTLH

Figure 2. AC Test Circuit and Waveforms

MC14512B MOTOROLA CMOS LOGIC DATA

6–264
 VDD
PULSE 20 ns
VDD 20 ns
GENERATOR VDD
DISABLE 90%
VDD 50%
INHIBIT Z DISABLE 10%
CL VSS
A INPUT
B 1k S1 tPZL
S3 tPLZ
C VOH
90%
X0 S2 OUTPUT 10% ≈ 2.5 V @ VDD = 5 V,
VOL
S4 X1 10 V, AND 15 V
tPHZ tPZH
X2 ≈ 2 V @ VDD = 5 V
X3 VSS OUTPUT VOH ≈ 6 V @ VDD = 10 V
90%
VSS X4 10% ≈ 10 V @ VDD = 15 V
VOL
X5
X6 Switch Positions for 3–State Test
X7 Test S1 S2 S3 S4
tPHZ Open Closed Closed Open
VSS
tPLZ Closed Open Open Closed
tPZL Closed Open Open Closed
tPZH Open Closed Closed Open

Figure 3. 3–State AC Test Circuit and Waveform

LOGIC DIAGRAM
13
C
12
B 15
11 DISABLE
A
1 10 DATA
X0 SELECTED
BUS
INHIBIT DEVICE
2 VDD IOD
X1
MC14512B
3 IL
X2
14 LOAD
Z ITL
4
X3 MC14512B

5
X4
ITL
6 MC14512B
X5

7 VSS
X6

9
X7 1 1
OUT
IN IN OUT

2 2
TRANSMISSION
GATE

3–STATE MODE OF OPERATION

Output terminals of several MC14512B 8–Bit Data Selec- and the load current, IL, required to drive the bus line (includ-
tors can be connected to a single date bus as shown. One ing fanout to other device inputs), and can be calculated by:
MC14512B is selected by the 3–state control, and the re- IOD – IL
maining devices are disabled into a high–impedance “off” N= +1
ITL
state. The number of 8–bit data selectors, N, that may be
connected to a bus line is determined from the output drive N must be calculated for both high and low logic state of the
current, IOD, 3–state or disable output leakage current, ITL, bus line.

MOTOROLA CMOS LOGIC DATA MC14512B

6–265
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14513B
BCD-To-Seven Segment
Latch/Decoder/Driver L SUFFIX
CERAMIC
CMOS MSI (Low–Power Complementary MOS) CASE 726

The MC14513B BCD–to–seven segment latch/decoder/driver is

constructed with complementary MOS (CMOS) enhancement mode devices P SUFFIX
and NPN bipolar output drivers in a single monolithic structure. The circuit PLASTIC
provides the functions of a 4–bit storage latch, an 8421 BCD–to–seven CASE 707
segment decoder, and has output drive capability. Lamp test (LT), blanking
(BI), and latch enable (LE) inputs are used to test the display, to turn–off or ORDERING INFORMATION
pulse modulate the brightness of the display, and to store a BCD code, MC14XXXBCP Plastic
respectively. The Ripple Blanking Input (RBI) and Ripple Blanking Output MC14XXXBCL Ceramic
(RBO) can be used to suppress either leading or trailing zeroes. It can be
TA = – 55° to 125°C for all packages.
used with seven–segment light emitting diodes (LED), incandescent,
fluorescent, gas discharge, or liquid crystal readouts either directly or
indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display driver, PIN ASSIGNMENT
computer/calculator display driver, cockpit display driver, and various clock, B 1 18 VDD
watch, and timer uses.
C 2 17 f
• Low Logic Circuit Power Dissipation
LT 3 16 g
• High–current Sourcing Outputs (Up to 25 mA) a
• Latch Storage of Binary Input BI 4 15 a f g b
• Blanking Input LE 5 14 b e c
• Lamp Test Provision D 6 13 c d
• Readout Blanking on all Illegal Input Combinations
A 7 12 d
• Lamp Intensity Modulation Capability
• Time Share (Multiplexing) Capability RBI 8 11 e
• Adds Ripple Blanking In, Ripple Blanking Out to MC14511B VSS 9 10 RBO
• Supply Voltage Range = 3.0 V to 18 V
• Capable of Driving Two Low–Power TTL Loads, One Low–power DISPLAY
Schottky TTL Load to Two HTL Loads Over the Rated Temperature

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Range.
0 1 2 3 4 5 6 7 8 9

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Rating Symbol Value Unit Inputs
TRUTH TABLE
Outputs

DC Supply Voltage VDD – 0.5 to + 18 V RBI LE BI LT D C B A RBO a b c d e f g Display

X X X 0 X X X X + 1 1 1 1 1 1 1 8
Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 V X X 0 1 X X X X + 0 0 0 0 0 0 0 Blank
1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 Blank
DC Current Drain per Input Pin I 10 mA
0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0
Operating Temperature Range TA – 55 to + 125 °C X 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 1
X 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 2
Power Dissipation, per Package† PD 500 mW X 0 1 1 0 0 1 1 0 1 1 1 1 0 0 1 3
X 0 1 1 0 1 0 0 0 0 1 1 0 0 1 1 4
Storage Temperature Range Tstg – 65 to + 150 _C X 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 5
X 0 1 1 0 1 1 0 0 0 1 0 1 1 1 1 6
Maximum Continuous Output Drive Current IOHmax 25 mA X 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 7
(Source) per Output X 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 8
X 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 9
X 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 Blank
Maximum Continuous Output Power POHmax 50 mW
X 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 Blank
(Source) per Output ‡ X 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
‡POHmax = IOH (VDD – VOH) X 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
* Maximum Ratings are those values beyond which damage to the device may occur. X 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
†Temperature Derating: X 1 1 1 X X X X † * *
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C X = Don’t Care
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C †RBO = RBI (D C B A), indicated by other rows of table
*Depends upon the BCD code previously applied when LE = 0

MC14513B MOTOROLA CMOS LOGIC DATA

6–266
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage — Segment Outputs VOL Vdc
“0” Level 5.0 — 0.05 — 0 0.05 — 0.05
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.1 — 4.1 5.0 — 4.1 — Vdc
Vin = 0 or VDD 10 9.1 — 9.1 10 — 9.1 —
15 14.1 — 14.1 15 — 14.1 —
Output Voltage — RBO Output VOL Vdc
“0” Level 5.0 — 0.05 — 0 0.05 — 0.05
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage # “0” Level VIL Vdc
(VO = 3.8 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 8.8 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.8 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 3.8 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 8.8 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.8 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Voltage — Segments VOH Vdc

(IOH = 0 mA) Source 5.0 4.1 — 4.1 4.57 — 4.1 —
(IOH = 5.0 mA) — — — 4.24 — — —
(IOH = 10 mA) 3.9 — 3.9 4.12 — 3.5 —
(IOH = 15 mA) — — — 3.94 — — —
(IOH = 20 mA) 3.4 — 3.4 3.70 — 3.0 —
(IOH = 25 mA) — — — 3.54 — — —
(IOH = 0 mA) 10 9.1 — 9.1 9.58 — 9.1 — Vdc
(IOH = 5.0 mA) — — — 9.26 — — —
(IOH = 10 mA) 9.0 — 9.0 9.17 — 8.6 —
(IOH = 15 mA) — — — 9.04 — — —
(IOH = 20 mA) 8.6 — 8.6 8.90 — 8.2 —
(IOH = 25 mA) — — — 8.75 — — —
(IOH = 0 mA) 15 14.1 — 14.1 14.59 — 14.1 — Vdc
(IOH = 5.0 mA) — — — 14.27 — — —
(IOH = 10 mA) 14 — 14 14.18 — 13.6 —
(IOH = 15 mA) — — — 14.07 — — —
(IOH = 20 mA) 13.6 — 13.6 13.95 — 13.2 —
(IOH = 25 mA) — — — 13.80 — — —
(continued)

This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; how-
ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit. A destructive high current mode may occur if Vin and Vout is not constrained to the range VSS ≤ (Vin or
Vout) ≤ VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to
VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).

MOTOROLA CMOS LOGIC DATA MC14513B

6–267
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Drive Current — RBO Output IOH mAdc
(VOH = 2.5 V) Source 5.0 – 0.40 — – 0.32 – 0.64 — – 0.22 —
(VOH = 9.5 V) 10 – 0.21 — – 0.17 – 0.34 — – 0.12 —
(VOH = 13.5 V) 15 – 0.81 — – 0.66 – 1.30 — – 0.46 —
(VOL = 0.4 V) Sink IOL 5.0 0.18 — 0.15 0.29 — 0.10 — mAdc
(VOL = 0.5 V) 10 0.47 — 0.38 0.75 — 0.26 —
(VOL = 1.5 V) 15 1.80 — 1.50 2.90 — 1.0 —

Output Drive Current — Segments IOL mAdc

(VOL = 0.4 V) Sink 5.0 0.64 — 0.51 0.88 — 0.36 —
(VOL = 0.5 V) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 V) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) Vin = 0 or VDD, 10 — 10 — 0.010 10 — 300
Iout = 0 µA 15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.9 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.8 µA/kHz) f + IDD
Per Package) 15 IT = (5.7 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.

Input LE and RBI low, and Inputs D, BI and LT high.

f in respect to a system clock.
All outputs connected to respective CL loads.
20 ns 20 ns
VDD
90%
A, B, AND C 50%
1 10% VSS
2f
50% DUTY CYCLE
VOH
ANY OUTPUT 50%
VOL

Figure 1. Dynamic Power Dissipation Signal Waveforms

MC14513B MOTOROLA CMOS LOGIC DATA

6–268
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

VDD
All Types
Characteristic Symbol Vdc Min Typ Max Unit
Output Rise Time — Segment Outputs tTLH ns
5.0 — 40 80
10 — 30 60
15 — 25 50
Output Rise Time — RBO Output tTLH ns
5.0 — 480 960
10 — 240 480
15 — 190 380
Output Fall Time — Segment Outputs* tTHL ns
tTHL = (1.5 ns/pF) CL + 50 ns 5.0 — 125 250
tTHL = (0.75 ns/pF) CL + 37.5 ns 10 — 75 150
tTHL = (0.55 ns/pF) CL + 37.5 ns 15 — 65 130
Output Fall Time — RBO Outputs tTHL ns
tTHL = (3.25 ns/pF) CL + 107.5 ns 5.0 — 270 540
tTHL = (1.35 ns/pF) CL + 67.5 ns 10 — 135 270
tTHL = (0.95 ns/pF) CL + 62.5 ns 15 — 110 220
Propagation Delay Time — A, B, C, D Inputs* tPLH ns
tPLH = (0.40 ns/pF) CL + 620 ns 5.0 — 640 1280
tPLH = (0.25 ns/pF) CL + 237.5 ns 10 — 250 500
tPLH = (0.20 ns/pF) CL + 165 ns 15 — 175 350
tPHL = (1.3 ns/pF) CL + 655 ns tPHL 5.0 — 720 1440 ns
tPHL = (0.60 ns/pF) CL + 260 ns 10 — 290 580
tPHL = (0.35 ns/pF) CL + 182.5 ns 15 — 200 400

Propagation Delay Time — RBI and BI Inputs* tPLH ns

tPLH = (1.05 ns/pF) CL + 547.5 ns 5.0 — 600 750
tPLH = (0.45 ns/pF) CL + 177.5 ns 10 — 200 300
tPLH = (0.30 ns/pF) CL + 135 ns 15 — 150 220

tPHL = (0.85 ns/pF) CL + 442.5 ns tPHL 5.0 — 485 970 ns

tPHL = (0.45 ns/pF) CL + 177.5 ns 10 — 200 400
tPHL = (0.35 ns/pF) CL + 142.5 ns 15 — 160 320

Propagation Delay Time — LT Input* tPLH ns

tPLH = (0.45 ns/pF) CL + 290.5 ns 5.0 — 313 625
tPLH = (0.25 ns/pF) CL + 112.5 ns 10 — 125 250
tPLH = (0.20 ns/pF) CL + 80 ns 15 — 90 180

tPHL = (1.3 ns/pF) CL + 248 ns tPHL 5.0 — 313 625 ns

tPHL = (0.45 ns/pF) CL + 102.5 ns 10 — 125 250
tPHL = (0.35 ns/pF) CL + 72.5 ns 15 — 90 180

Setup Time tsu 5.0 100 — — ns

10 40 — —
15 30 — —
Hold Time th 5.0 60 — — ns
10 40 — —
15 30 — —
Latch Enable Pulse Width tWL(LE) 5.0 520 260 — ns
10 220 110 —
15 130 65 —
* The formulas given are for the typical characteristics only.

MOTOROLA CMOS LOGIC DATA MC14513B

6–269
 20 ns 20 ns
90% VDD

INPUT C 50%
10% VSS
tPLH tPHL
VOH
OUTPUT g
VOL
tTLH tTHL

a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high.

20 ns 20 ns
90% VDD
INPUT C 50%
10% VSS
tPLH tPHL
VOH
90%
OUTPUT RBO 50%
10% VOL
tTLH tTHL

b. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high.

20 ns
VDD
90%
LE 50%
10% VSS
th
tsu
VDD

INPUT C 50%
VSS

VOH
OUTPUT g
VOL

c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high.

20 ns
20 ns
VDD
90%
50%
10%
LE VSS
tWL(LE)

d. Pulse Width: Data DCBA strobed into latches.

Figure 2. Dynamic Signal Waveforms

MC14513B MOTOROLA CMOS LOGIC DATA

6–270
 CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIGHT EMITTING DIODE (LED) READOUT

VDD VDD

COMMON
COMMON ANODE LED
CATHODE LED ≈ 1.7 V

≈ 1.7 V

VSS
VSS

INCANDESCENT READOUT FLUORESCENT READOUT

VDD VDD VDD

**
DIRECT
(LOW BRIGHTNESS)

FILAMENT
(SUPPLY)
VSS VSS VSS OR APPROPRIATE
VOLTAGE BELOW VSS.

GAS DISCHARGE READOUT LIQUID CRYSTAL (LC) READOUT

EXCITATION
APPROPRIATE (SQUARE WAVE,
VDD VOLTAGE VDD VSS TO VDD)

1/4 OF MC14070B

VSS VSS

** A filament pre–warm resistor is recommended to reduce

Direct dc drive of LC’s not recommended for life of LC readouts.
filament thermal shock and increase the effective cold
resistance of the filament.

MOTOROLA CMOS LOGIC DATA MC14513B

6–271
 LOGIC DIAGRAM

BI 4

15 a

A 7
14 b

13 c

B 1 12 d

11 e

17 f
C 2
16 g
LT 30
RBI 8 10 RBO
D 6

LE 5

TYPICAL APPLICATIONS FOR RIPPLE BLANKING

LEADING EDGE ZERO SUPPRESSION

DISPLAYS

a –– – –– g a–– – –– g a–– – –– g a–– – –– g a–– – –– g a–– – – –g

CONNECT TO
RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO
VDD (1) D C B A 1 D C B A 1 D C B A 0 D C B A 0 D C B A 0 D C B A 0

MC14513B MC14513B MC14513B MC14513B MC14513B MC14513B

INPUT 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1
CODE (0) (0) (5) (0) (1) (3)

MC14513B MOTOROLA CMOS LOGIC DATA

6–272
 TYPICAL APPLICATIONS FOR RIPPLE BLANKING (Cont)

TRAILING EDGE ZERO SUPPRESSION

DISPLAYS

a–– – –– g a –– – –– g a –– – ––g a–– – –– g a –– – ––g a –– – ––g CONNECT TO

0
RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI
D C B A 0 D C B A 0 D C B A 0 D C B A 1 D C B A 1 D C B A VDD (1)

MC14513B MC14513B MC14513B MC14513B MC14513B MC14513B

0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0
(5) (0) (1) (3) (0) (0) INPUT CODE

MOTOROLA CMOS LOGIC DATA MC14513B

6–273
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14514B
MC14515B
4-Bit Transparent
Latch/4-to-16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16 line L SUFFIX
decoder with latched inputs. The MC14514B (output active high option) CERAMIC
presents a logical “1” at the selected output, whereas the MC14515B (output CASE 623
active low option) presents a logical “0” at the selected output. The latches
are R–S type flip–flops which hold the last input data presented prior to the
strobe transition from “1” to “0”. These high and low options of a 4–bit latch/4 P SUFFIX
to 16 line decoder are constructed with N–channel and P–channel PLASTIC
enhancement mode devices in a single monolithic structure. The latches are CASE 709
R–S type flip–flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding applications DW SUFFIX
where low power dissipation and/or high noise immunity is desired. SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 751E
• Capable of Driving Two Low–power TTL Loads or One Low–power
ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range
MC14XXXBCP Plastic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBCL Ceramic
MC14XXXBDW SOIC
Symbol Parameter Value Unit
TA = – 55° to 125°C for all packages.
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C
DECODE TRUTH TABLE (Strobe = 1)*
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: Data Inputs Selected Output
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14514 = Logic “1”
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Inhibit D C B A MC14515 = Logic “0”
0 0 0 0 0 S0
0 0 0 0 1 S1
BLOCK DIAGRAM 11
S0 ABCD 0 0 0 1 0 S2
9 0 0 0 1 1 S3
S1 ABCD
VDD = PIN 24 S2 10 ABCD 0 0 1 0 0 S4
8 0 0 1 0 1 S5
VSS = PIN 12 S3 ABCD 0 0 1 1 0 S6
S4 7 ABCD 0 0 1 1 1 S7
2 A 6
DATA 1 S5 ABCD 0 1 0 0 0 S8
5 0 1 0 0 1 S9
S6 ABCD
3 B 4 0 1 0 1 0 S10
DATA 2 S7 ABCD
TRANSPARENT 4 TO 16 18 0 1 0 1 1 S11
21 LATCH C DECODER S8 ABCD
DATA 3 17 0 1 1 0 0 S12
S9 ABCD
22 D 20 0 1 1 0 1 S13
DATA 4 S10 ABCD 0 1 1 1 0 S14
19 0 1 1 1 1 S15
S11 ABCD
S12 14 ABCD 1 X X X X All Outputs = 0, MC14514
1
STROBE 13 All Outputs = 1, MC14515
S13 ABCD
S14 16 ABCD X = Don’t Care
15 *Strobe = 0, Data is latched
S15 ABCD

23
INHIBIT

MC14514B MC14515B MOTOROLA CMOS LOGIC DATA

6–274
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† ITL 5.0 IT = (1.35 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.70 µA/kHz) f + IDD
Per Package) 15 IT = (4.05 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14514B MC14515B

6–275
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
All Types
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise Time tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130
Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time; Data, Strobe to S tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPHL 5.0 — 550 1100
tPLH, tPHL = (0.86 ns/pF) CL + 192 ns 10 — 225 450
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns 15 — 150 300
Inhibit Propagation Delay Times tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPHL 5.0 — 400 800
tPLH, tPHL = (0.66 ns/pF) CL + 117 ns 10 — 150 300
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 200
Setup Time tsu ns
Data to Strobe 5.0 250 125 —
10 100 50 —
15 75 38 —
Hold Time th 5.0 – 20 – 100 — ns
Strobe to Data 10 0 – 40 —
15 10 – 30 —
Strobe Pulse Width tWH ns
5.0 350 175 —
10 100 50 —
15 75 38 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD

VDS
S0
STROBE S1
S2 For MC14515B
S3 1. For P–channel: Inhibit = VDD
INHIBIT S4 2. For N–channel: Inhibit = VSS
For MC14514B S5 2. and D1–D4 constitute binary
1. For P–channel: Inhibit = VSS D1 S6 2. code for “output under test.”
1. and D1–D4 constitute S7
1. binary code for “output S8
D2 S9
1. under test.” ID
S10
2. For N–channel: Inhibit = VDD D3 S11
S12
S13 EXTERNAL
D4 S14 POWER SUPPLY
S15

VSS

Figure 1. Drain Characteristics Test Circuit

MC14514B MC14515B MOTOROLA CMOS LOGIC DATA

6–276
 VDD

0.01 µF
ID
500 CERAMIC
µF
24 VDD
20 ns 20 ns
PULSE VDD
D1 S0 90%
GENERATOR
D2 CL Vin
D3 10% VSS
D4
STROBE
INHIBIT S15

12 CL
VSS

Figure 2. Dynamic Power Dissipation Test Circuit and Waveform

VDD

STROBE OUTPUT S0
S0
S1 OUTPUT S1 tTLH tTHL
INHIBIT 20 ns
CL CL
VDD
90%
D1 INPUT 50%
PROGRAMMABLE 10%
PULSE VSS
GENERATOR tPLH tPHL
D2
VDD
OUTPUT 90%
50%
D3 10% VSS

S15 OUTPUT S15

D4 tTLH tTHL
VSS CL

Figure 3. Switching Time Test Circuit and Waveforms

PIN ASSIGNMENT
ST 1 24 VDD
D1 2 23 INH
D2 3 22 D4
S7 4 21 D3
S6 5 20 S10
S5 6 19 S11
S4 7 18 S8
S3 8 17 S9
S1 9 16 S14
S2 10 15 S15
S0 11 14 S12
VSS 12 13 S13

MOTOROLA CMOS LOGIC DATA MC14514B MC14515B

6–277
6–278
MC14514B MC14515B

LOGIC DIAGRAM

AB CD
11 S0

AB CD
9 S1

AB CD
10 S2

AB CD
DATA 1 2 A 8 S3
S Q
AB CD
7 S4

R Q AB CD
6 S5
DATA 2 3 B
S Q AB CD
5 S6

AB CD
4 S7
R Q
AB CD
DATA 3 21 C 18 S8
S Q
AB CD
17 S9

R Q AB CD
20 S10
DATA 4 22 D AB CD
S Q 19 S11

AB CD
MOTOROLA CMOS LOGIC DATA

14 S12
R Q
STROBE 1 AB CD
13 S13

AB CD
16 S14
INHIBIT 23
AB CD
15 S15

IN MC14515B ONLY
 COMPLEX DATA ROUTING

Two MC14512 eight–channel data selectors are used here
with the MC14514B four–bit latch/decoder to effect a com-
plex data routing system. A total of 16 inputs from data regis-
ters are selected and transferred via a 3–state data bus to a
data distributor for rearrangement and entry into 16 output
registers. In this way sequential data can be re–routed or
intermixed according to patterns determined by data select
and distribution inputs.
Data is placed into the routing scheme via the eight inputs
on both MC14512 data selectors. One register is assigned to
each input. The signals on A0, A1, and A2 choose one of
eight inputs for transfer out to the 3–state data bus. A fourth
signal, labelled Dis, disables one of the MC14512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1 thru 16, the rate
of transfer of the sequential information can also be varied.
That is, if the MC14512 were addressed at a rate that is eight
times faster then the shift frequency of the input registers, the
most significant bit (MSB) from each register could be se-
lected for transfer to the data bus. Therefore, all of the most
significant bits from all of the registers can be transferred to
the data bus before the next most significant bit is presented
for transfer by the input registers.
Information from the 3–state bus is redistributed by the
MC14514B four–bit latch/decoder. Using the four–bit ad-
dress, D1 thru D4, the information on the inhibit line can be
transferred to the addressed output line to the desired output
registers, A thru P. This distribution of data bits to the output
registers can be made in many complex patterns. For exam-
ple, all of the most significant bits from the input registers can
be routed into output register A, all of the next most signifi-
cant bits into register B, etc. In this way horizontal, vertical, or
other methods of data slicing can be implemented.

DATA ROUTING SYSTEM

INPUT DATA 3–STATE DATA OUTPUT

REGISTERS TRANSFER DATA BUS DISTRIBUTION REGISTERS

DIS
REGISTER 1 D0 Q
D1
D2
D1 D2 D3 D4
MC14512

D3
S0 REGISTER A
D4
STROBE S1
D5
S2
D6
S3
REGISTER 8 D7 S4
A0 A1 A2
S5
S6
MC14514B

DATA S7
SELECT S8
S9
S10
A0 A1 A2
D0 Q S11
REGISTER 9
D1 S12
D2 S13
MC14512

INHIBIT S14
D3
D4 S15 REGISTER P
D5
D6
REGISTER 16 D7
DIS

MOTOROLA CMOS LOGIC DATA MC14514B MC14515B

6–279
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14516B

Binary Up/Down Counter

The MC14516B synchronous up/down binary counter is constructed with L SUFFIX
MOS P–channel and N–channel enhancement mode devices in a monolithic CERAMIC
structure. CASE 620
This counter can be preset by applying the desired value, in binary, to the
Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up P SUFFIX
counting) or a low (for down counting) to the UP/DOWN input. The state of PLASTIC
the counter changes on the positive transition of the clock input. CASE 648
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the D SUFFIX
reset (R) pin. SOIC
This CMOS counter finds primary use in up/down and difference counting. CASE 751B
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analog–to– ORDERING INFORMATION
digital and digital–to–analog conversions, and (3) Magnitude and sign MC14XXXBCP Plastic
generation. MC14XXXBCL Ceramic
• Diode Protection on All Inputs MC14XXXBD SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc TA = – 55° to 125°C for all packages.
• Internally Synchronous for High Speed
• Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock BLOCK DIAGRAM
• Single Pin Reset
• Asynchronous Preset Enable Operation PE
1 Q0 6
• Capable of Driving Two Low–Power TTL Loads or One Low–Power

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky Load Over the Rated Temperature Range 5 CARRY IN

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) 9 RESET Q1 11

Symbol Parameter Value Unit 10 UP/DOWN

VDD DC Supply Voltage – 0.5 to + 18.0 V 15 CLOCK Q2 14

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V 4 P0
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA 12 P1 Q3 2
per Pin P2
13
PD Power Dissipation, per Package† 500 mW CARRY
3 P3 7
OUT
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C VDD = PIN 16
VSS = PIN 8
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C This device contains protection circuitry to
TRUTH TABLE guard against damage due to high static
voltages or electric fields. However, pre-
Preset
cautions must be taken to avoid applications of
Carry In Up/Down Enable Reset Clock Action any voltage higher than maximum rated volt-
1 X 0 0 X No Count ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
0
0
1
0
0
0
0
0
Count Up
Count Down
to the range VSS v (Vin or Vout) vVDD.
Unused inputs must always be tied to an
X X 1 0 X Preset appropriate logic voltage level (e.g., either VSS
X X X 1 X Reset or VDD). Unused outputs must be left open.

X = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high and is low only
when Q0 through Q3 are high and Carry In is low. When counting down,
Carry Out is low only when Q0 through Q3 and Carry In are low.

MC14516B MOTOROLA CMOS LOGIC DATA

6–280
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.58 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.20 µA/kHz) f + IDD
Per Package) 15 IT = (1.70 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT
PE 1 16 VDD
Q3 2 15 C
P3 3 14 Q2
P0 4 13 P2
CARRY IN 5 12 P1
Q0 6 11 Q1
CARRY OUT 7 10 U/D
VSS 8 9 R

MOTOROLA CMOS LOGIC DATA MC14516B

6–281
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Characteristic Symbol VDD

All Types
Unit
Min Typ # Max
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Clock to Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns 5.0 — 315 630
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 200
Clock to Carry Out tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPHL 5.0 — 315 630
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 200
Carry In to Carry Out tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPHL 5.0 — 180 360
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 80 160
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 60 120
Preset or Reset to Q tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPHL 5.0 — 315 630
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 360
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 200
Preset or Reset to Carry Out tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPHL 5.0 — 550 1100
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns 10 — 225 450
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns 15 — 150 300
Reset Pulse Width tw 5.0 380 190 — ns
10 200 100 —
15 160 80 —
Clock Pulse Width tWH 5.0 350 200 — ns
10 170 100 —
15 140 75 —
Clock Pulse Frequency fcl 5.0 — 3.0 1.5 MHz
10 — 6.0 3.0
15 — 8.0 4.0
Preset or Reset Removal Time trem 5.0 650 325 — ns
The Preset or Reset signal must be low prior to a 10 230 115
positive–going transition of the clock. 15 180 90 —
Clock Rise and Fall Time tTLH, 5.0 — — 15 µs
tTHL 10 — — 5
15 — — 4
Setup Time tsu 5.0 260 130 — ns
Carry In to Clock 10 120 60 —
15 100 50 —
Hold Time th 5.0 0 – 60 — ns
Clock to Carry In 10 20 – 20 —
15 20 0 —
Setup Time tsu 5.0 500 250 — ns
Up/Down to Clock 10 200 100 —
15 150 75 —
Hold Time th 5.0 – 70 – 160 — ns
Clock to Up/Down 10 – 10 – 60 —
15 0 – 40 —
Setup Time tsu 5.0 – 40 – 120 — ns
Pn to PE 10 – 30 – 70 —
15 – 25 – 50 —
Hold Time th 5.0 480 240 — ns
PE to Pn 10 420 210 —
15 420 210 —
Preset Enable Pulse Width tWH 5.0 200 100 — ns
10 100 50 —
15 80 40 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.

MC14516B MOTOROLA CMOS LOGIC DATA

6–282
 VDD

500 pF ID 0.01 µF
CERAMIC

PE Q0
CARRY IN
20 ns 20 ns
R Q1 VDD
UP/DOWN 90%
CL CLOCK 50%
PULSE CLOCK Q2 10% VSS
GENERATOR CL VARIABLE
P0 WIDTH
P1 Q3
CL
P2
CARRY
P3 CL
OUT
CL

Figure 1. Power Dissipation Test Circuit and Waveform

LOGIC DIAGRAM

P0 Q0 P1 Q1 P2 Q2 P3 Q3
4 6 12 11 13 14 3 2

RESET 9

PRESET
1
ENABLE
CLOCK 15 P P P P
PE Q PE Q PE Q PE Q
C C C C
CARRY OUT 7 T Q T Q T Q T Q

CARRY IN 5

UP/DOWN 10

TOGGLE FLIP–FLOP FLIP–FLOP FUNCTIONAL TRUTH TABLE

PARALLEL IN Preset
Enable Clock T Qn+1
P
PE Q 1 X X Parallel In
C 0 0 Qn
T Q 0 1 Qn
0 X Qn
X = Don’t Care

MOTOROLA CMOS LOGIC DATA MC14516B

6–283
 tsu trem
1
th fcl
CARRY IN OR VDD
UP/DOWN 50%
VSS
VDD
50%
CLOCK VSS
tw(H) tw(H)
VDD
PRESET ENABLE VSS
tTLH
CARRY OUT ONLY
Q0 OR CARRY OUT VOH
90% 90%
10% 10% VOL

tPHL
tTHL tPLH tPLH
trem
VDD
50%
RESET VSS
tw

Figure 2. Switching Time Waveforms

PIN DESCRIPTIONS

INPUTS synchronous output is active low and may also be used to

P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) — This active–low input is used when
Cascading stages. Carry In is usually connected to Carry
Out of the previous stage. While high, Clock is inhibited.
Clock, (Pin 15) — Binary data is incremented or decrem-
ented, depending on the direction of count, on the positive
transition of this input.
OUTPUTS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) —
Binary data is present on these outputs with Q0 correspond-
ing to the least significant bit.
Carry Out, (Pin 7) — Used when cascading stages, Carry
Out is usually connected to Carry In of the next stage. This
indicate terminal count.
CONTROLS
PE, Preset Enable, (Pin 1) — Asynchronously loads data
on the Preset Inputs. This pin is active high and inhibits the
clock when high.
R, Reset, (Pin 9) — Asynchronously resets the Q out–
puts to a low state. This pin is active high and inhibits the
clock when high.
Up/Down, (Pin 10) — Controls the direction of count, high
for up count, low for down count.
SUPPLY PINS
VSS, Negative Supply Voltage, (Pin 8) — This pin is
usually connected to ground.
VDD, Positive Supply Voltage, (Pin 16) — This pin is
connected to a positive supply voltage ranging from 3.0 volts
to 18.0 volts.

MC14516B MOTOROLA CMOS LOGIC DATA

6–284
 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
PRESET
ENABLE
0 = COUNT Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
PE PE
1 = PRESET TERMINAL COUNT
Cin Cout Cin Cout
L.S.D. M.S.D. INDICATOR
CLOCK CLOCK
1 = UP MC14516B MC14516B
U/D U/D
0 = DOWN R R
P0 P1 P2 P3 P0 P1 P2 P3

P0 P1 P2 P3 P4 P5 P6 P7

+VDD +VDD
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
CLOCK RESISTORS = 10 kW

RESET
+VDD
OPEN = COUNT

NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.

Figure 3. Presettable Cascaded 8–Bit Up/Down Counter

MOTOROLA CMOS LOGIC DATA MC14516B

6–285
6–286
MC14516B

CLOCK

UP/DOWN
CARRY IN

TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8–BIT UP/DOWN COUNTER

(MSD)

PE

P7

P6

P5

P4

P3

P2

P1

P0
CARRY OUT
(MSD)
Q7

Q6

Q5

Q4

Q3

Q2
MOTOROLA CMOS LOGIC DATA

Q1

Q0
CARRY OUT
(LSD)

RESET

COUNT 13 14 15 16 17 18 19 18 17 16 15 14 13 251 252 253 254 255 0 1 2 3 2 1 0 1 2

PRESET RESET
PRESET ENABLE ENABLE
UP COUNT DOWN COUNT UP COUNT DOWN UP COUNT
COUNT
 fout

BUFFER
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
PE PE
Cin Cout Cin Cout
CLOCK L.S.D. CLOCK M.S.D.
MC14516B MC14516B
U/D U/D
R R
P0 P1 P2 P3 P0 P1 P2 P3

P0 P1 P2 P3 P4 P5 P6 P7

+VDD +VDD
THUMBWHEEL SWITCHES
CLOCK (fin) (OPEN FOR “0”) RESISTORS = 10 kW

RESET f
+VDD fout = in
n
OPEN = COUNT

NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.

Figure 4. Programmable Cascaded Frequency Divider

MOTOROLA CMOS LOGIC DATA MC14516B

6–287
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14517B
Dual 64-Bit Static Shift Register
The MC14517B dual 64–bit static shift register consists of two identical,
independent, 64–bit registers. Each register has separate clock and write L SUFFIX
enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data CERAMIC
CASE 620
input is entered by clocking, regardless of the state of the write enable input.
An output is disabled (open circuited) when the write enable input is high.
During this time, data appearing at the data input as well as the 16–bit,
32–bit, and 48–bit taps may be entered into the device by application of a P SUFFIX
clock pulse. This feature permits the register to be loaded with 64 bits in 16 PLASTIC
clock periods, and also permits bus logic to be used. This device is useful in CASE 648
time delay circuits, temporary memory storage circuits, and other serial shift
register applications.
• Diode Protection on All Inputs DW SUFFIX
• Fully Static Operation SOIC
CASE 751G
• Output Transitions Occur on the Rising Edge of the Clock Pulse
• Exceedingly Slow Input Transition Rates May Be Applied to the Clock
ORDERING INFORMATION
Input
MC14XXXBCP Plastic
• 3–State Output at 64th–Bit Allows Use in Bus Logic Applications
MC14XXXBCL Ceramic
• Shift Registers of any Length may be Fully Loaded with 16 Clock Pulses MC14XXXBDW SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc TA = – 55° to 125°C for all packages.
• Capable of Driving Two Low–power TTL Loads or One Low–power

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS (Voltages referenced to VSS)
PIN ASSIGNMENT

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Symbol Parameter Value Unit
Q16A 1 16 VDD

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
Q48A 2 15 Q16B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
± 10 WEA 3 14 Q48B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Iin, Iout Input or Output Current (DC or Transient), mA
per Pin CA 4 13 WEB

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Î ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎ
ÎÎÎ
500 mW Q64A 5 12 CB

ÎÎÎÎÎÎ _C
Tstg Storage Temperature – 65 to + 150
Q32A 6 11 Q64B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
DA 7 10 Q32B
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: VSS 8 9 DB
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
FUNCTIONAL TRUTH TABLE (X = Don’t Care)
Write
Clock Enable Data 16–Bit Tap 32–Bit Tap 48–Bit Tap 64–Bit Tap
0 0 X Content of 16–Bit Content of 32–Bit Content of 48–Bit Content of 64–Bit
Displayed Displayed Displayed Displayed
0 1 X High Impedance High Impedance High Impedance High Impedance
1 0 X Content of 16–Bit Content of 32–Bit Content of 48–Bit Content of 64–Bit
Displayed Displayed Displayed Displayed
1 1 X High Impedance High Impedance High Impedance High Impedance
0 Data entered Content of 16–Bit Content of 32–Bit Content of 48–Bit Content of 64–Bit
into 1st Bit Displayed Displayed Displayed Displayed
1 Data entered Data at tap Data at tap Data at tap High Impedance
into 1st Bit entered into 17–Bit entered into 33–Bit entered into 49–Bit
0 X Content of 16–Bit Content of 32–Bit Content of 48–Bit Content of 64–Bit
Displayed Displayed Displayed Displayed
1 X High Impedance High Impedance High Impedance High Impedance

MC14517B MOTOROLA CMOS LOGIC DATA

6–288
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (4.2 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (8.8 µA/kHz) f + IDD
Per Package) 15 IT = (13.7 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14517B

6–289
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, tTHL ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.65 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, tPHL ns
tPLH, tPHL = (1.7 ns/pF) CL + 390 ns 5.0 — 475 770
tPLH, tPHL = (0.66 ns/pF) CL + 177 ns 10 — 210 300
tPLH, tPHL = (0.5 ns/pF) CL + 115 ns 15 — 140 215
Clock Pulse Width tWH 5.0 330 170 — ns
10 125 75 —
15 100 60 —
Clock Pulse Frequency fcl 5.0 — 3.0 1.5 MHz
10 — 6.7 4.0
15 — 8.3 5.3
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 —
10 **See Note
15
Data to Clock Setup Time tsu 5.0 0 – 40 — ns
10 10 – 15 —
15 15 0 —
Data to Clock Hold Time th 5.0 150 75 — ns
10 75 25 —
15 35 10 —
Write Enable to Clock Setup Time tsu 5.0 400 170 — ns
10 200 65 —
15 110 50 —
Write Enable to Clock Release Time trel 5.0 380 160 — ns
10 180 55 —
15 100 40 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall
time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.

VDD
CL

CL
Q16 Q32 Q48 Q64
D D
REPETITIVE WAVEFORM C C CL
VDD WE
fo
VSS CL
C
VDD D
C
D VSS
WE
(f = 1/2 fo)
Q16 Q32 Q48 Q64
VSS
50 µF CL CL CL CL
ID

Figure 1. Power Dissipation Test Circuit and Waveform

MC14517B MOTOROLA CMOS LOGIC DATA

6–290
 Vout = VOH Vout = VOL
VDD = VGS VDD = VGS

Q16 Q32 Q48 Q64 Q16 Q32 Q48 Q64

D D
C C
WE WE

D D
C C
IOH IOL
WE WE

Q16 Q32 Q48 Q64 Q16 Q32 Q48 Q64

EXTERNAL EXTERNAL
POWER POWER
SUPPLY VSS SUPPLY
VSS

(Output being tested should be in the high–logic state) (Output being tested should be in the low–logic state)

Figure 2. Typical Output Source Current Figure 3. Typical Output Sink Current
Characteristics Test Circuit Characteristics Test Circuit

tWH
tWL VDD
PIN NO’S 1 2 16 17 18 19 90% 33
50%
CLOCK 4 (12) 10% VSS
trel tsu
WRITE 3 (13) VDD
th1 th0 VSS
20 ns
tsu1 tsu0 VDD
DATA IN 7 (9) 90%
th1 50% 50%
10% VSS
tsu1 tsu0 tPHL tPLH
VOH VDD
16–BIT OUTPUT 1 (15) th0 VDD 90%
th1 10%
17–BIT INPUT V VSS
tsu1 tsu0 20 ns tPHL tTLH tTHL OL
tPLH VOH VDD
32–BIT OUTPUT 6 (10) th0 VDD 90% 50%
th1 10%
33–BIT INPUT tPHL tTLH VOL VSS
tsu1 tsu0 20 ns tTHL
tPLH VDD
VOH
48–BIT OUTPUT 2 (14) th0 VDD
49–BIT INPUT V VSS
20 ns tPHL tTLH tTHL OL
tPLH VDD
64–BIT OUTPUT 5 (11)
VSS
tTLH
tTHL

Figure 4. AC Test Waveforms

EXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)

CLOCK

DATA D Q D Q D Q D Q D Q D Q D Q D Q D
C 1 C 2 C 16 C 17 C 32 C 33 C 48 C 49 C 64 Q
3–STATE WE 3–STATE WE 3–STATE WE 3–STATE

WRITE
ENABLE
WRITE ENABLE = 0, 16–BIT OUTPUT 32–BIT OUTPUT 48–BIT OUTPUT 64–BIT OUTPUT
WRITE ENABLE = 1, 17–BIT INPUT 33–BIT INPUT 49–BIT INPUT HIGH IMPEDANCE

MOTOROLA CMOS LOGIC DATA MC14517B

6–291
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14518B
MC14520B
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary counter
are constructed with MOS P–channel and N–channel enhancement mode
devices in a single monolithic structure. Each consists of two identical, L SUFFIX
independent, internally synchronous 4–stage counters. The counter stages CERAMIC
are type D flip–flops, with interchangeable Clock and Enable lines for CASE 620
incrementing on either the positive–going or negative–going transition as
required when cascading multiple stages. Each counter can be cleared by
applying a high level on the Reset line. In addition, the MC14518B will count P SUFFIX
out of all undefined states within two clock periods. These complementary PLASTIC
MOS up counters find primary use in multi–stage synchronous or ripple CASE 648
counting applications requiring low power dissipation and/or high noise
immunity.
• Diode Protection on All Inputs DW SUFFIX
SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
CASE 751G
• Internally Synchronous for High Internal and External Speeds
• Logic Edge–Clocked Design — Incremented on Positive Transition of ORDERING INFORMATION
Clock or Negative Transition on Enable MC14XXXBCP Plastic
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14XXXBCL Ceramic
Schottky TTL Load Over the Rated Temperature Range MC14XXXBDW SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
TA = – 55° to 125°C for all packages.

VDD DC Supply Voltage – 0.5 to + 18.0 V

BLOCK DIAGRAM
Vin, Vout Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 V
CLOCK
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA Q0 3
per Pin 1
Q1 4
C
PD Power Dissipation, per Package† 500 mW 2 Q2 5
ENABLE Q3 6
Tstg Storage Temperature – 65 to + 150 _C R
TL Lead Temperature (8–Second Soldering) 260 _C 7
* Maximum Ratings are those values beyond which damage to the device may occur.
CLOCK 11
†Temperature Derating: Q0
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 9
Q1 12
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 10
C
Q2 13
ENABLE Q3 14
TRUTH TABLE R
Clock Enable Reset Action 15
VDD = PIN 16
1 0 Increment Counter VSS = PIN 8
0 0 Increment Counter
X 0 No Change
This device contains protection circuitry to
X 0 No Change
guard against damage due to high static
0 0 No Change voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
1 0 No Change any voltage higher than maximum rated volt-
X X 1 Q0 thru Q3 = 0 ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
X = Don’t Care to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.

MC14518B MC14520B MOTOROLA CMOS LOGIC DATA

6–292
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.6 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.2 µA/kHz) f + IDD
Per Package) 15 IT = (1.7 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT
CA 1 16 VDD
EA 2 15 RB
Q0A 3 14 Q3B
Q1A 4 13 Q2B
Q2A 5 12 Q1B
Q3A 6 11 Q0B
RA 7 10 EB
VSS 8 9 CB

MOTOROLA CMOS LOGIC DATA MC14518B MC14520B

6–293
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
All Types
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Clock to Q/Enable to Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns 5.0 — 280 560
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 115 230
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 80 160
Reset to Q tPHL ns
tPHL = (1.7 ns/pF) CL + 265 ns 5.0 — 330 650
tPHL = (0.66 ns/pF) CL + 117 ns 10 — 130 230
tPHL = (0.66 ns/pF) CL + 95 ns 15 — 90 170
Clock Pulse Width tw(H) 5.0 200 100 — ns
tw(L) 10 100 50 —
15 70 35 —
Clock Pulse Frequency fcl 5.0 — 2.5 1.5 MHz
10 — 6.0 3.0
15 — 8.0 4.0
Clock or Enable Rise and Fall Time tTHL, tTLH 5.0 — — 15 µs
10 — — 5
15 — — 4
Enable Pulse Width tWH(E) 5.0 440 220 — ns
10 200 100 —
15 140 70 —
Reset Pulse Width tWH(R) 5.0 280 125 — ns
10 120 55 —
15 90 40 —
Reset Removal Time trem 5.0 –5 – 45 — ns
10 15 – 15 —
15 20 –5 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD

0.01 µF
500 µF ID CERAMIC

PULSE
C Q0
GENERATOR Q1
Q2 CL
E Q3 CL
R CL
CL

VSS

20 ns 20 ns
90%
50%
10%
VSS
VARIABLE
WIDTH

Figure 1. Power Dissipation Test Circuit and Waveform

MC14518B MC14520B MOTOROLA CMOS LOGIC DATA

6–294
 VDD 20 ns 20 ns
90% VDD
CLOCK 50%
PULSE Q0 INPUT 10%
C VSS
GENERATOR tWH tWL
Q1
tPLH tPHL
Q2 CL
E CL 90%
R Q3 CL 50%
CL 10%
VSS Q
tr tf

Figure 2. Switching Time Test Circuit and Waveforms

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

CLOCK
ENABLE

RESET

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0

Q0

Q1
MC14518B

Q2

Q3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4

Q0

Q1
MC14520B

Q2

Q3

Figure 3. Timing Diagram

MOTOROLA CMOS LOGIC DATA MC14518B MC14520B

6–295
 Q0 Q1 Q2 Q3

D Q D Q D Q D Q

C Q C Q C Q C Q
R R R R
RESET

ENABLE

CLOCK

Figure 4. Decade Counter (MC14518B) Logic Diagram

(1/2 of Device Shown)

Q0 Q1 Q2 Q3

D Q D Q D Q D Q

C Q C Q C Q C Q
R R R R
RESET

ENABLE

CLOCK

Figure 5. Binary Counter (MC14520B) Logic Diagram

(1/2 of Device Shown)

MC14518B MC14520B MOTOROLA CMOS LOGIC DATA

6–296
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14519B
4-Bit AND/OR Selector or
Quad 2-Channel Data Selector L SUFFIX
CERAMIC
or Quad Exclusive NOR" Gate CASE 620

The MC14519B is constructed with MOS P–channel and N–channel

enhancement mode devices in a monolithic structure. These complementary P SUFFIX
MOS logic gates find primary use where low power dissipation and/or high PLASTIC
noise immunity is desired. CASE 648
This device provides three functions in one package; a 4–Bit AND/OR
Selector, a Quad 2–Channel Data Selector, or a Quad Exclusive NOR Gate.
• Diode Protection on All Inputs D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
CASE 751B
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range ORDERING INFORMATION
• Plug–in Replacement for CD4019 in Most Applications
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
LOGIC DIAGRAM
TA = – 55° to 125°C for all packages.
A 9
CONTROL
INPUTS
B 14 TRUTH TABLE
X0 6 10 Z0 Control Inputs Output
A B Zn
Y0 7
0 0 0
0 1 Yn
X1 4 11 Z1
1 0 Xn
Y1 5
1 1 xn ĥ Yn
DATA
INPUTS NOTE: Xn ĥYn means Xn
X2 2 12 Z2 (Exclusive–NOR) Yn

Y2 3

X3 15 13 Z3

Y3 1

VDD = PIN 16
VSS = PIN 8

MOTOROLA CMOS LOGIC DATA MC14519B

6–297
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit PIN ASSIGNMENT

VDD DC Supply Voltage – 0.5 to + 18.0 V Y3 1 16 VDD

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V X2 2 15 X3

Iin, Iout Input or Output Current (DC or Transient), ± 10 mA Y2 3 14 B

per Pin X1 4 13 Z3
PD Power Dissipation, per Package† 500 mW Y1 5 12 Z2
Tstg Storage Temperature – 65 to + 150 _C X0 6 11 Z1
TL Lead Temperature (8–Second Soldering) 260 _C Y0 7 10 Z0
* Maximum Ratings are those values beyond which damage to the device may occur. VSS 8 9 A
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.2 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.4 µA/kHz) f + IDD
Per Package) 15 IT = (3.6 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

MC14519B MOTOROLA CMOS LOGIC DATA

6–298
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 165 ns tPHL 5.0 — 250 500
tPLH, tPHL = (0.66 ns/pF) CL + 82 10 — 115 225
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns 15 — 90 165
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

+VDD

VDD
A Z0
PULSE Vin CL
GENERATOR B
X0 20 ns 20 ns
Y0 Z1 VDD
CL 90%
X1
Vin
Y1 10%
VSS
X2 Z2 50% DUTY CYCLE
CL
Y2
X3
Y3 Z3
VSS CL

ISS
500 µF

Figure 1. Dynamic Power Dissipation Test Circuit and Waveform

VDD
20 ns 20 ns
V VDD
PULSE A DD Z0 INPUT 90%
GENERATOR CL 50%
B
10% VSS
X0
Z1 tPHL tPLH
Y0
CL 90% VOH
X1
OUTPUTS 50%
Y1 OUTPUT 10%
Z2 VOL
X2
Y2 CL
tTHL tTLH
X3 tPLH tPHL
Y3 V Z3 VOH
SS CL OUTPUT 50%
VOL

Figure 2. Switching Time Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14519B

6–299
 TYPICAL CIRCUIT APPLICATIONS

DATA REGISTER SELECTION COMPARISON

DATA A MC14015B DATA B

CLOCK A 4–BIT REGISTER A DUAL 4–BIT REGISTER 4–BIT REGISTER B CLOCK B
RESET A Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RESET B

X0 X1 X2 X3 Y0 Y1 Y2 Y3
CONTROL A A MC14519B
AND/OR SELECT/EXCL NOR
CONTROL B B Z0 Z1 Z2 Z3

INVERT

MC14070B
QUAD
EXCLUSIVE OR

Q0 Q1 Q2 Q3

CONVERSION TABLE
Operation Code Output
A B INV Q0 Q1 Q2 Q3 Function
0 0 0 0 0 0 0 Inhibit, all zeros
0 0 1 1 1 1 1 Inhibit, all ones
1 0 0 X0 X1 X2 X3 Control A
1 0 1 X0 X1 X2 X3 Control A and Invert
0 1 0 Y0 Y1 Y2 Y3 Control B
0 1 1 Y0 Y1 Y2 Y3 Control B and Invert
1 1 0 X0 ĥ Y0 X1 ĥ Y1 X2 ĥ Y2 X3 ĥ Y3 Exclusive NOR
1 1 1 X0 ę Y0 X1 ę Y1 X2 ę Y2 X3 ę Y3 Exclusive OR

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14519B MOTOROLA CMOS LOGIC DATA

6–300
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14521B
24-Stage Frequency Divider
The MC14521B consists of a chain of 24 flip–flops with an input circuit that L SUFFIX
CERAMIC
allows three modes of operation. The input will function as a crystal
CASE 620
oscillator, an RC oscillator, or as an input buffer for an external oscillator.
Each flip–flop divides the frequency of the previous flip–flop by two,
consequently this part will count up to 224 = 16,777,216. The count advances
on the negative going edge of the clock. The outputs of the last P SUFFIX
seven–stages are available for added flexibility. PLASTIC
CASE 648
• All Stages are Resettable
• Reset Disables the RC Oscillator for Low Standby Power Drain
• RC and Crystal Oscillator Outputs Are Capable of Driving External D SUFFIX
Loads SOIC
• Test Mode to Reduce Test Time CASE 751B
• VDD′ and VSS′ Pins Brought Out on Crystal Oscillator Inverter to Allow
the Connection of External Resistors for Low–Power Operation ORDERING INFORMATION
• Supply Voltage Range = 3.0 Vdc to 18 Vdc MC14XXXBCP Plastic
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14XXXBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC
Schottky TTL Load over the Rated Temperature Range.

ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VDD ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage
Parameter Value
– 0.5 to + 18.0
Unit
V
PIN ASSIGNMENT

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Q24 1 16 VDD

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin RESET 2 15 Q23

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD

ÎÎÎÎÎÎÎÎÎÎÎ
Tstg ÎÎÎÎÎÎ
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C
VSS′
OUT 2
3
4
14
13
Q22
Q21

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
VDD′
IN 2
5
6
12
11
Q20
Q19

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C OUT 1 7 10 Q18
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C VSS 8 9 IN 1

BLOCK DIAGRAM
RESET
2
Output Count Capacity
Q18 218 = 262,144
Q19 219 = 524,288
STAGES STAGES
9 6 1 THRU 17 18 THRU 24 Q20 220 = 1,048,576
IN 1 IN 2 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q21 221 = 2,097,152
Q22 222 = 4,194,304
VDD = PIN 16 Q23 223 = 8,388,608
VSS = PIN 8
5 4 Q24 224 = 16,777,216
7 VDD′ 3 OUT2 10 11 12 13 14 15 1
OUT 1 VSS′

MOTOROLA CMOS LOGIC DATA MC14521B

6–301
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) Pins 4 & 7 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 — mAdc
(VOH = 4.6 Vdc) Pins 1, 10, 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 11, 12, 13, 14 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) and 15 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.42 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.85 µA/kHz) f + IDD
Per Package) 15 IT = (1.40 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14521B MOTOROLA CMOS LOGIC DATA

6–302
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Characteristic Symbol
VDD
Vdc Min Typ # Max Unit
Output Rise and Fall Time (Counter Outputs) tTLH, tTHL ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns 15 — 40 80
Propagation Delay Time tPHL, tPLH µs
Clock to Q18
tPHL, tPLH = (1.7 ns/pF) CL + 4415 ns 5.0 — 4.5 9.0
tPHL, tPLH = (0.66 ns/pF) CL + 1667 ns 10 — 1.7 3.5
tPHL, tPLH = (0.5 ns/pF) CL + 1275 ns 15 — 1.3 2.7
Clock to Q24
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns 5.0 — 6.0 12
tPHL, tPLH = (0.66 ns/pF) CL + 2167 ns 10 — 2.2 4.5
tPHL, tPLH = (0.5 ns/pF) CL + 1675 ns 15 — 1.7 3.5
Propagation Delay Time tPHL ns
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1215 ns 5.0 — 1300 2600
tPHL = (0.66 ns/pF) CL + 467 ns 10 — 500 1000
tPHL = (0.5 ns/pF) CL + 350 ns 15 — 375 750
Clock Pulse Width tWH(cl) 5.0 385 140 — ns
10 150 55 —
15 120 40 —
Clock Pulse Frequency fcl 5.0 — 3.5 2.0 MHz
10 — 9.0 5.0
15 — 12 6.5
Clock Rise and Fall Time tTLH, tTHL 5.0 — — 15 µs
10 — — 5.0
15 — — 4.0
Reset Pulse Width tWH(R) 5.0 1400 700 — ns
10 600 300 —
15 450 225 —
Reset Removal Time trem 5.0 30 – 200 — ns
10 0 – 160 —
15 – 40 – 110 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD

500 µF 0.01 µF
ID
CERAMIC

VDD VDD

Q18 20 ns 20 ns
PULSE CL VDD
IN 2 Q19 Vin 90%
GENERATOR CL 50%
Q20 10% 0V
CL
Q21 50% DUTY CYCLE
Q22 CL
Q23 CL
R
Q24 CL
CL
VSS VSS

Figure 1. Power Dissipation Test Circuit and Waveform

MOTOROLA CMOS LOGIC DATA MC14521B

6–303
 VDD

VDD VDD′
20 ns 20 ns 20 ns
IN 2
Q18
PULSE IN 2 CL 90%
GENERATOR Q19 50%
CL 10%
Q20
CL tWL tWH
Q21
Q22 CL
90%
Q23 CL 50%
R Qn
CL 10%
Q24
CL tPLH tPHL
VSS VSS′ tTLH tTHL

Figure 2. Switching Time Test Circuit and Waveforms

500 kHz 50 kHz

Characteristic Circuit Circuit Unit
Crystal Characteristics
Resonant Frequency 500 50 kHz
Equivalent Resistance, RS 1.0 6.2 kΩ
External Resistor/Capacitor Values
VDD
Ro 47 750 kΩ
Ro CT 82 82 pF
R* CS 20 20 pF
VDD VDD′
18 M Frequency Stability
IN 1 OUT 1 Frequency Change as a Function
OUT 2 of VDD (TA = 25_C)
Q18 VDD Change from 5.0 V to 10 V
Q19 + 6.0 + 2.0 ppm
VDD Change from 10 V to 15 V
IN 2 Q20 + 2.0 + 2.0 ppm
Q21 Frequency Change as a Function
Q22 of Temperature (VDD = 10 V)
– 4.0 – 2.0 ppm
Q23 TA Change from – 55_C to + 25_C
CS CT + 100 + 120 ppm
R Q24 MC14521 only
Complete Oscillator*
VSS VSS′
TA Change from + 25_C to + 125_C
R*
MC14521 only
– 2.0 – 2.0 ppm
Complete Oscillator*
– 160 – 560 ppm
* Optional for low power operation,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 kΩ ≤ R ≤ 70 kΩ. *Complete oscillator includes crystal, capacitors, and resistors.

Figure 3. Crystal Oscillator Circuit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 4. Typical Data for Crystal Oscillator Circuit

MC14521B MOTOROLA CMOS LOGIC DATA

6–304
 100
VDD = 10 V TEST CIRCUIT
50

f, OSCILLATOR FREQUENCY (kHz)

8.0 FIGURE 7
TEST CIRCUIT
VDD = 15 V 20 f AS A FUNCTION
FIGURE 7
4.0 OF RTC
FREQUENCY DEVIATION (%)

10 (C = 1000 pF)
5.0 (RS ≈ 2RTC)
0 f AS A FUNCTION
OF C
10 V 2.0 (RTC = 56 kΩ)
–4.0
1.0 (RS = 120 k)

–8.0 0.5
5.0 V
0.2
–12
RTC = 56 kΩ, RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C 0.1
C = 1000 pF
{ RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
1.0 k 10 k 100 k 1.0 m
–16 RTC, RESISTANCE (OHMS)
–55 –25 0 25 50 75 100 125 0.0001 0.001 0.01 0.1
TA, AMBIENT TEMPERATURE (°C), DEVICE ONLY C, CAPACITANCE (µF)

Figure 5. RC Oscillator Stability Figure 6. RC Oscillator Frequency as a

Function of RTC and C

RS RTC VDD VDD

C
VDD′
VDD VDD′
IN 1 Q18
IN 1 OUT 1 Q19
OUT 2 Q20
Q18 Q21
Q19 PULSE IN 2 Q22
IN 2 Q20 GENERATOR Q23
Q21 Q24
Q22 OUT 1
Q23 R OUT 2
R Q24
VSS VSS
VSS VSS′

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Figure 7. RC Oscillator Circuit Figure 8. Functional Test Circuit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ FUNCTIONAL TEST SEQUENCE

Inputs Outputs Comments
Reset In 2 Out 2 VSS′ VDD′ Q18 thru Q24 Counter is in three 8–stage
sections in parallel mode
Counter is reset.
reset In 2 and
1 0 0 VDD Gnd 0 Out 2 are connected
together

A test function (see Figure 8) has been 0 1 1 First “0” to “1” transition
included for the reduction of test time required to on In 2, Out 2 node.
exercise all 24 counter stages. This test function 0 0 255 “0” to “1” transitions
divides the counter into three 8–stage sections, 1 1 are clocked into this In 2,
and 255 counts are loaded in each of the — — Out 2 node.
8–stage sections in parallel. All flip–flops are — —
now at a logic
g “1”. The counter is now returned — —
to the normal 24–stages in series configuration. The 255th “0” to “1”
1 1 1
One more pulse is entered into Input 2 (In 2) transition.
which will cause the counter to ripple from an all 0 0 1
“1” state to an all “0” state. 0 0 1
Gnd
VDD Counter converted back to
1 0 1
24–stages in series mode.
Out 2 converts back to an
1 0 1
output.
Counter ripples from an all
0 1 0 “1” state to an all “0” stage.

MOTOROLA CMOS LOGIC DATA MC14521B

6–305
 LOGIC DIAGRAM

VDD RESET
5 2

9 STAGES
1 2 8
3 THRU 7
IN 1

6 4
IN 2 OUT 2
7 3
OUT 1 VSS

9 10 STAGES 16
11 THRU 15

17 18 19 20 21 22 23 24

10 11 12 13 14 15 1 VDD = PIN 16
Q18 Q19 Q20 Q21 Q22 Q23 Q24 VSS = PIN 8

MC14521B MOTOROLA CMOS LOGIC DATA

6–306
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14522B
Presettable 4-Bit Down Counters MC14526B
The MC14522B BCD counter and the MC14526B binary counter are
constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.
These devices are presettable, cascadable, synchronous down counters L SUFFIX
with a decoded “0” state output for divide–by–N applications. In single stage CERAMIC
applications the “0” output is applied to the Preset Enable input. The CASE 620
Cascade Feedback input allows cascade divide–by–N operation with no
additional gates required. The Inhibit input allows disabling of the pulse
counting function. Inhibit may also be used as a negative edge clock. P SUFFIX
These complementary MOS counters can be used in frequency synthesiz- PLASTIC
ers, phase–locked loops, and other frequency division applications requiring CASE 648
low power dissipation and/or high noise immunity.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
DW SUFFIX
• Logic Edge–Clocked Design — Incremented on Positive Transition of
SOIC
Clock or Negative Transition of Inhibit CASE 751G
• Asynchronous Preset Enable
• Capable of Driving Two Low–power TTL Loads or One Low–power ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range MC14XXXBCP Plastic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBCL Ceramic
MC14XXXBDW SOIC
Symbol Parameter Value Unit
TA = – 55° to 125°C for all packages.
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA PIN ASSIGNMENT
per Pin
PD Power Dissipation, per Package† 500 mW Q3 1 16 VDD

Tstg Storage Temperature – 65 to + 150 _C P3 2 15 Q2

TL Lead Temperature (8–Second Soldering) 260 _C PE 3 14 P2

* Maximum Ratings are those values beyond which damage to the device may occur. INHIBIT 4 13 CF
†Temperature Derating: P0 5 12 “0”
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C CLOCK 6 11 P1
FUNCTION TABLE Q0 7 10 RESET
Inputs Output VSS 8 9 Q1
Preset Cascade Resulting
Clock Reset Inhibit Enable Feedback “0” Function
X H X L L L Asynchronous
y reset*
X H X H L H Asynchronous reset This device contains protection circuitry to
X H X X H H A
Asynchronous
h reset guard against damage due to high static
voltages or electric fields. However, pre-
X L X H X L Asynchronous preset cautions must be taken to avoid applications of
L H L X L Decrement inhibited any voltage higher than maximum rated volt-
L L L X L Decrement inhibited ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained

H
L
L
L L
L
L
L
L
L
No change**
g (inactive
( edge)
g )
No change** (inactive edge)
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an
L L L L L D
Decrement**
** appropriate logic voltage level (e.g., either VSS
H L L L L Decrement** or VDD). Unused outputs must be left open.
X = Don’t Care
NOTES:
* Output “0” is low when reset goes high only it PE and CF are low.
** Output “0” is high when reset is low, only if CF is high and count is 0000.

MOTOROLA CMOS LOGIC DATA MC14522B MC14526B

6–307
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.7 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.4 µA/kHz) f + IDD
Per Package) 15 IT = (5.1 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14522B MC14526B MOTOROLA CMOS LOGIC DATA

6–308
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns (Figures 4, 5) 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time (Inhibit Used as Negative tPLH, ns
Edge Clock) tPHL
Clock or Inhibit to Q (Figures 4, 5, 6)
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns 5.0 — 550 1100
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns 10 — 225 450
tPLH, tPHL = (0.5 ns/pF) CL + 135 ns 15 — 160 320
Clock or Inhibit to “0”
tPLH, tPHL = (1.7 ns/pF) CL + 155 ns 5.0 — 240 480
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns 15 — 100 200

Propagation Delay Time tPLH, 5.0 — 260 520 ns

Pn to Q tPHL 10 — 120 240
(Figures 4, 7) 15 — 100 200
Propagation Delay Time tPHL 5.0 — 250 500 ns
Reset to Q 10 — 110 220
(Figure 8) 15 — 80 160
Propagation Delay Time tPHL, 5.0 — 220 440 ns
Preset Enable to “0” tPLH 10 — 100 200
(Figures 4, 9) 15 — 80 160
Clock or Inhibit Pulse Width tw 5.0 250 125 — ns
10 100 50 —
(Figures 5, 6) 15 80 40 —
Clock Pulse Frequency (with PE = low) fmax 5.0 — 2.0 1.5 MHz
10 — 5.0 3.0
(Figures 4, 5, 6) 15 — 6.6 4.0
Clock or Inhibit Rise and Fall Time tr, 5.0 — — 15 µs
tf 10 — — 5
(Figures 5, 6) 15 — — 4
Setup Time tsu 5.0 90 40 — ns
Pn to Preset Enable 10 50 15 —
(Figure 10) 15 40 10 —
Hold Time th 5.0 30 – 15 — ns
Preset Enable to Pn 10 30 –5 —
(Figure 10) 15 30 0 —
Preset Enable Pulse Width tw 5.0 250 125 — ns
10 100 50 —
(Figure 10) 15 80 40 —
Reset Pulse Width tw 5.0 350 175 — ns
10 250 125 —
(Figure 8) 15 200 100 —
Reset Removal Time trem 5.0 10 – 110 — ns
10 20 – 30 —
(Figure 8) 15 30 – 20 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14522B MC14526B

6–309
 VOH VOL
VDD = –VGS VDD = VGS

CF Q0 CF Q0
PE PE
P0 Q1 P0 Q1
P1 P1
P2 Q2 P2 Q2
P3 IOH P3 IOL
RESET Q3 RESET Q3
INHIBIT INHIBIT
CLOCK “0” CLOCK “0”
EXTERNAL EXTERNAL
VSS VSS
POWER POWER
SUPPLY SUPPLY

Figure 1. Typical Output Source Figure 2. Typical Output Sink

Characteristics Test Circuit Characteristics Test Circuit

VDD

CF Q0
PE
P0 Q1
P1
P2 Q2
P3 CL
RESET Q3 TEST POINT
CL
INHIBIT CL
CLOCK “0” Q or “0”
CL DEVICE
VSS CL UNDER
TEST CL*

PULSE
GENERATOR 20 ns 20 ns
90% VDD
CLOCK 50%
10% VSS
VARIABLE
WIDTH 50% DUTY CYCLE * Includes all probe and jig capacitance.

Figure 3. Power Dissipation Figure 4. Test Circuit

MC14522B MC14526B MOTOROLA CMOS LOGIC DATA

6–310
 SWITCHING WAVEFORMS

tr tf tf tr
VDD VDD
90% 90%
CLOCK 50% INHIBIT 50%
10% VSS 10%
VSS
tw tw

1/fmax 1/fmax
tPLH tPHL tPLH tPHL

ANY Q 90% 90%

ANY Q
OR “0” 50% OR “0” 50%
10% 10%

tTLH tTHL tTLH tTHL

Figure 5. Figure 6.

tw
VDD
RESET 50%
VSS
tr tf
tPHL
VDD
90%
ANY P 50%
10% ANY Q 50%
VSS

tPLH tPHL
trem

ANY Q VDD
50%
CLOCK
50%
VSS

Figure 7. Figure 8.

VALID
tr tf VDD
VDD ANY P 50%
PRESET 90%
ENABLE 50% VSS
10% GND
tsu th
tPHL tPLH VDD
PRESET
ENABLE 50%
“0” 50% VSS

tw

Figure 9. Figure 10.

MOTOROLA CMOS LOGIC DATA MC14522B MC14526B

6–311
 PIN DESCRIPTIONS

Preset Enable (Pin 3) — If Reset is low, a high level on
the Preset Enable input asynchronously loads the counter
with the programmed values on P0, P1, P2, and P3.
Inhibit (Pin 4) — A high level on the Inhibit input pre–
vents the Clock from decrementing the counter. With Clock
(pin 6) held high, Inhibit may be used as a negative edge
clock input.
Clock (Pin 6) — The counter decrements by one for each
rising edge of Clock. See the Function Table for level require-
ments on the other inputs.
Reset (Pin 10) — A high level on Reset asynchronously
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is
high, causes the “0” output to go high.
“0” (Pin 12) — The “0” (Zero) output issues a pulse one
clock period wide when the counter reaches terminal count
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and
Preset Enable is low. When presetting the counter to a value
other than all zeroes, the “0” output is valid after the rising
edge of Preset Enable (when Cascade Feedback is high).
See the Function Table.
Cascade Feedback (Pin 13) — If the Cascade Feedback
input is high, a high level is generated at the “0” output when
the count is all zeroes. If Cascade Feedback is low, the “0”
output depends on the Preset Enable input level. See the
Function Table.
P0, P1, P2, P3 (Pins 5, 11, 14, 2) — These are the preset
data inputs. P0 is the LSB.
Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) — These are the syn-
chronous counter outputs. Q0 is the LSB.
VSS (Pin 8) — The most negative power supply potential.
This pin is usually ground.
VDD (Pin 16) — The most positive power supply potential.
VDD may range from 3 to 18 V with respect to VSS.

STATE DIAGRAMS

MC14522B MC14526B

0 1 2 3 4 0 1 2 3 4

15 5 15 5

14 6 14 6

13 7 13 7

12 11 10 9 8 12 11 10 9 8

MC14522B MC14526B MOTOROLA CMOS LOGIC DATA

6–312
 MC14522B LOGIC DIAGRAM (BCD Down Counter)

P0 Q0 P1 Q1 P2 Q2 P3 Q3
5 7 11 9 14 15 2 1

D R D RQ D RQ D RQ
C C C C
T PE Q T PE Q T PE Q T PE Q
VSS

13
CF

3
PE
4
INHIBIT
12
“0”

CLOCK 6
10
RESET

MC14526B LOGIC DIAGRAM (Binary Down Counter)

P0 Q0 P1 Q1 P2 Q2 P3 Q3
5 7 11 9 14 15 2 1

D R D RQ D RQ D RQ
C C C C
T PE Q T PE Q T PE Q T PE Q
VDD VDD

13
CF

PE 3

INHIBIT 4

12
“0”

CLOCK 6
10
RESET

MOTOROLA CMOS LOGIC DATA MC14522B MC14526B

6–313
 APPLICATIONS INFORMATION

Divide–By–N, Single Stage The Inhibit pin may be used to stop pulse counting. When
this pin is taken high, decrementing is inhibited.

Figure 11 shows a single stage divide–by–N application. Cascaded, Presettable Divide–By–N

The MC14522B (BCD version) can accept a number greater
than 9 and count down in binary fashion. Hence, the BCD
and binary single stage divide–by–N counters (as shown in
Figure 11) function the same.
To initialize counting a number, N is set on the parallel in-
puts (P0, P1, P2, and P3) and reset is taken high asynchro-
nously. A zero is forced into the master and slave of each bit
and, at the same time, the “0” output goes high. Because
Preset Enable is tied to the “0” output, preset is enabled. Re-
set must be released while the Clock is high so the slaves of
each bit may receive N before the Clock goes low. When the
Clock goes low and Reset is low, the “0” output goes low (if
P0 through P3 are unequal to zero).
The counter downcounts with each rising edge of the
Clock. When the counter reaches the zero state, an output
pulse occurs on “0” which presets N. The propagation delays
from the Clock’s rising and falling edges to the “0” output’s
rising and falling edges are about equal, making the “0” out-
put pulse approximately equal to that of the Clock pulse.
Figure 12 shows a three stage cascade application. Taking
Reset high loads N. Only the first stage’s Reset pin (least sig-
nificant counter) must be taken high to cause the preset for
all stages, but all pins could be tied together, as shown.
When the first stage’s Reset pin goes high, the “0” output is
latched in a high state. Reset must be released while Clock is
high and time allowed for Preset Enable to load N into all
stages before Clock goes low.
When Preset Enable is high and Clock is low, time must be
allowed for the zero digits to propagate a Cascade Feedback
to the first non–zero stage. Worst case is from the most sig-
nificant bit (M.S.B.) to the L.S.B., when the L.S.B. is equal to
one (i.e. N = 1).
After N is loaded, each stage counts down to zero with
each rising edge of Clock. When any stage reaches zero and
the leading stages (more significant bits) are zero, the “0”
output goes high and feeds back to the preceding stage.
When all stages are zero, the Preset Enable automatically
loads N while the Clock is high and the cycle is renewed.

P0 Q0
P1 Q1
N
P2 Q2
P3 Q3 BUFFER
VDD fin
CF
“0” N
RESET
VSS INHIBIT
fin CLOCK

PE

Figure 11. ÷ N Counter

LSB MSB
N0 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11

VDD
P0 P1 P2 P3 Q0 Q1 Q2 Q3 P0 P1 P2 P3 Q0 Q1 Q2 Q3 P0 P1 P2 P3 Q0 Q1 Q2 Q3
fin CLOCK CLOCK CLOCK
CF CF CF
INHIBIT INHIBIT INHIBIT
VSS RESET “0” PE VSS RESET “0” PE VSS RESET “0” PE
VDD

LOAD
N BUFFER
10 KΩ
fin
VSS N

Figure 12. 3 Stages Cascaded

MC14522B MC14526B MOTOROLA CMOS LOGIC DATA

6–314
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14527B
BCD Rate Multiplier
The MC14527B BCD rate multiplier (DRM) provides an output pulse rate
based upon the BCD input number. For example, if 6 is the BCD input L SUFFIX
number, there will be six output pulses for every ten input pulses. This part CERAMIC
may be used for arithmetic operations including multiplication and division. CASE 620
Typical applications include digital filters, motor speed control and frequency
synthesizers.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc P SUFFIX
• Output Clocked on the Negative Going Edge of Clock PLASTIC
CASE 648
• Strobe for Inhibiting or Enabling Outputs
• Enable and Cascade Inputs for Cascade Operation of Two or More
DRMs
• “9” Output for the Parallel Enable Configuration and DRMs in Cascade DW SUFFIX
SOIC
• Complementary Outputs CASE 751G

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Clear and Set to Nine Inputs

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBDW SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V TA = – 55° to 125°C for all packages.
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
per Pin

ÎÎÎÎÎÎ
ÎÎÎ
Power Dissipation, per Package† 500 mW
BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C 4

* Maximum Ratings are those values beyond which damage to the device may occur. S
12 CASC Eout 7
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 11 Ein
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C RATE INPUT 9 CLOCK OUT 6
TRUTH TABLE (X = Don’t Care, *D = Most Significant Bit) 10 ST
Output 14 A
OUT 5
Logic Level 15 B
MULTIPLIER
Inputs Number of Pulses 2 C
No. of 3 D “9” 1
Clock
CLEAR
D* C B A Pulses Ein Strobe Cascade Clear Set Out Out Eout “9”
13
0 0 0 0 10 0 0 0 0 0 0 1 1 1
0 0 0 1 10 0 0 0 0 0 1 1 1 1 VDD = PIN 16
0 0 1 0 10 0 0 0 0 0 2 2 1 1 VSS = PIN 8
0 0 1 1 10 0 0 0 0 0 3 3 1 1
0 1 0 0 10 0 0 0 0 0 4 4 1 1
0 1 0 1 10 0 0 0 0 0 5 5 1 1
0 1 1 0 10 0 0 0 0 0 6 6 1 1
0 1 1 1 10 0 0 0 0 0 7 7 1 1
1 0 0 0 10 0 0 0 0 0 8 8 1 1
1 0 0 1 10 0 0 0 0 0 9 9 1 1
1 0 1 0 10 0 0 0 0 0 8 8 1 1
1 0 1 1 10 0 0 0 0 0 9 9 1 1
1 1 0 0 10 0 0 0 0 0 8 8 1 1
1 1 0 1 10 0 0 0 0 0 9 9 1 1
1 1 1 0 10 0 0 0 0 0 8 8 1 1
1 1 1 1 10 0 0 0 0 0 9 9 1 1
X X X X 10 1 0 0 0 0 — — — —
X X X X 10 0 1 0 0 0 0 1 1 1
X X X X 10 0 0 1 0 0 1 0 1 1
1 X X X 10 0 0 0 1 0 10 10 1 0
0 X X X 10 0 0 0 1 0 0 1 1 0
X X X X 10 0 0 0 0 1 0 1 0 1

MOTOROLA CMOS LOGIC DATA MC14527B

6–315
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.85 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.75 µA/kHz) f + IDD
Per Package) 15 IT = (2.60 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0012.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must “9” 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and C 2 15 B
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. D 3 14 A
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. S 4 13 CLEAR
OUT 5 12 CASC
OUT 6 11 Ein
Eout 7 10 ST
VSS 8 9 CLOCK

MC14527B MOTOROLA CMOS LOGIC DATA

6–316
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPHL, ns
Clock to Out tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 115 ns 5.0 — 200 400
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns 10 — 100 200
tPLH, tPHL = (0.5 ns/pF) CL + 45 ns 15 — 70 140
Clock to Out tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 40 ns tPHL 5.0 — 125 250
tPLH, tPHL = (0.66 ns/pF) CL + 32 ns 10 — 65 130
tPLH, tPHL = (0.5 ns/pF) CL + 20 ns 15 — 45 90
Clock to Eout tPLH. ns
tPLH, tPHL = (1.7 ns/pF) CL + 210 ns tPHL 5.0 — 295 590
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 60 ns 15 — 85 170
Clock to “9” tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPHL 5.0 — 400 800
tPLH, tPHL = (0.66 ns/pF) CL + 122 ns 10 — 155 310
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns 15 — 110 220
Set or Clear to Out tPHL ns
tPHL = (1.7 ns/pF) CL + 295 ns 5.0 — 380 760
tPHL = (0.66 ns/pF) CL + 132 ns 10 — 165 330
tPHL = (0.5 ns/pF) CL + 85 ns 15 — 110 220
Cascade to Out tPLH ns
tPHL = (1.7 ns/pF) CL + 40 ns 5.0 — 125 250
tPHL = (0.66 ns/pF) CL + 32 ns 10 — 65 130
tPHL = (0.5 ns/pF) CL + 20 ns 15 — 45 90
Strobe to Out tPLH ns
tPHL = (1.7 ns/pF) CL + 145 ns 5.0 — 230 260
tPHL = (0.66 ns/pF) CL + 72 ns 10 — 105 210
tPHL = (0.5 ns/pF) CL + 45 ns 15 — 70 140

Clock Pulse Width tWH 5.0 500 250 — ns

10 200 110 —
15 150 80 —
Clock Pulse Frequency fcl 5.0 — 2.0 1.2 MHz
10 — 4.5 2.5
15 — 6.0 3.5
Clock Pulse Rise and Fall Time tTLH, 5.0 — — 15 µs
tTHL 10 — — 5
15 — — 4
Set or Clear Pulse Width tWH 5.0 240 80 — ns
10 100 35 —
15 75 30 —
Set Removal Time trem 5.0 0 – 20 — ns
10 0 – 10 —
15 0 – 7.5 —
Enable In Setup Time tsu 5.0 400 175 — ns
10 150 60 —
15 120 45 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14527B

6–317
 0 1234 5678 90 123 4
CLOCK
VDD
Qa

Qb

S Qc
CASC Eout
Qd
Ein
PULSE R1
CLOCK
GENERATOR OUT
ST R2
A
OUT
MULTIPLIER B R3
PRESET NO. C
D “9” R4
CLEAR OUTPUT (PIN 6)
VSS A ENABLED
B ENABLED

C ENABLED

D ENABLED
Figure 1. Test Circuit and Timing Diagram
Eout
OUTPUT (PIN 6)
(PRESET NO. OF 1)
(PRESET NO. OF 2)

(PRESET NO. OF 3)

VDD (PRESET NO. OF 4)

S (PRESET NO. OF 5)
CASC Eout
Ein (PRESET NO. OF 6)
PROGRAMMABLE CLOCK
PULSE OUT (PRESET NO. OF 7)
ST
GENERATOR (PRESET NO. OF 8)
A
OUT CL
B
(PRESET NO. OF 9)
C CL
D “9”
CLEAR CL
VSS CL

20 ns 20 ns 1
tTLH tTHL fcl
CLOCK 90% 50%
10%

SET

trem

ENABLE IN 50%
tWH
tsu
SET 50%

tPHL

OUT 50% 90%

10%
tPLH tPHL tTLH tTHL

Figure 2. Switching Time Test Circuit and Waveforms

MC14527B MOTOROLA CMOS LOGIC DATA

6–318
 VDD

ID 500 0.01 µF
pF CERAMIC

VDD
S
CASC Eout
Ein 20 ns 20 ns
PULSE
CLOCK VDD
GENERATOR OUT CLOCK 90%
ST 50%
10% VSS
A
OUT CL VARIABLE WIDTH
B
C CL 50% DUTY CYCLE
D “9” CL
CLEAR
VSS CL

Figure 3. Power Dissipation Test Circuit and Waveform

LOGIC DIAGRAM

ENABLE IN D C B A STROBE CASCADE

11 3 2 15 14 10 12

T Q
C a
Q
R
R1
6 OUT

R2
T Q
9 5 OUT
CLOCK C b

R R3

R4 VDD = PIN 16
S VSS = PIN 8
T Q
C c
Q
R

1 “9”
T S Q
C d
Q
R
7 ENABLE OUT

CLEAR 13 SET TO NINE 4

MOTOROLA CMOS LOGIC DATA MC14527B

6–319
 MOST SIGNIFICANT LEAST SIGNIFICANT
DIGIT DIGIT

1 A 0 A
0 B OUT 0 B OUT
0 C 1 C
1 0 2 NOTE: More than two MC14527Bs
1 D D
Eout Eout may be cascaded using this
CLOCK CLOCK
CASC CASC configuration.
Ein “9” Ein “9”
ST ST
CLEAR S CLEAR S

CLOCK 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
CLOCK
OUT
DRM 2

One of four output pulses contributed by DRM 2 to

output for every 100 clock pulses in for preset No. of 94.

Figure 4. Two MC14527Bs in Cascade with Preset No. of 94

MC14527B MOTOROLA CMOS LOGIC DATA

6–320
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14528B
Dual Monostable Multivibrator
The MC14528B is a dual, retriggerable, resettable monostable multivibra- L SUFFIX
CERAMIC
tor. It may be triggered from either edge of an input pulse, and produces an
CASE 620
output pulse over a wide range of widths, the duration of which is determined
by the external timing components, CX and RX.
• Separate Reset Available
P SUFFIX
• Diode Protection on All Inputs PLASTIC
• Triggerable from Leading or Trailing Edge Pulse CASE 648
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range D SUFFIX

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Pin–for–Pin Replacement with the MC14538B SOIC
CASE 751B

ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCP Plastic
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW
_C BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150
TL Lead Temperature (8–Second Soldering) 260 _C CX1 RX1
VDD
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: 1 2
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 4 6
A1 Q1
5 7
B1 Q1
ONE–SHOT SELECTION GUIDE
3
RESET 1
100 ns 1 ms 10 ms 100 ms 1 ms 10 ms 100 ms 1s 10 s
MC14528B
MC14536B 23 HR CX2 RX2
MC14538B VDD
MC14541B 5 MIN.
15 14
MC4538A*
12 10
A2 Q2
*LIMITED OPERATING VOLTAGE (2–6 V) 11 9
B2 Q2

TOTAL OUTPUT PULSE WIDTH RANGE 13

RECOMMENDED PULSE WIDTH RANGE RESET 2

VDD = PIN 16
VSS = PIN 1, PIN 8, PIN 15
RX AND CX ARE EXTERNAL COMPONENTS

MOTOROLA CMOS LOGIC DATA MC14528B

6–321
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current mAdc

(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) IOH 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) IOL 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
**Total Supply Current at an IT — IT(CL, CX) = [(CL + 0.36CX)VDDf + 2x10–8 µAdc
external load Capacitance (CL) RXCX(VDD–2)2f] x 10–3
and at external timing where: IT in µA (per circuit), CL and CX in pF, RX in megohms,
capacitance (CX), use the VDD in Vdc, f in kHz is input frequency.
formula —
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must VSS 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and CX1/RX1 2 15 VSS
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. RESET 1 3 14 CX2/RX2
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. A1 4 13 RESET 2
B1 5 12 A2
Q1 6 11 B2
Q1 7 10 Q2
VSS 8 9 Q2

MC14528B MOTOROLA CMOS LOGIC DATA

6–322
SWITCHING CHARACTERISTICS** (CL = 50 pF, TA = 25_C)
CX RX VDD
Characteristic Symbol pF kΩ Vdc Min Typ # Max Unit
Output Rise and Fall Time tTLH, — — ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Turn–Off, Turn–On Delay Time — A or B to Q or Q tPLH, 15 5.0 ns
tPLH, tPHL = (1.7 ns/pF) CL + 240 ns tPHL 5.0 — 325 650
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns 10 — 120 240
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns 15 — 90 180
Turn–Off, Turn–On Delay Time — A or B to Q or Q tPLH, 1000 10 ns
tPLH, tPHL = (1.7 ns/pF) CL + 620 ns tPHL 5.0 — 705 —
tPLH, tPHL = (0.66 ns/pF) CL + 257 ns 10 — 290 —
tPLH, tPHL = (0.5 ns/pF) CL + 185 ns 15 — 210 —
Input Pulse Width — A or B tWH 15 5.0 5.0 150 70 — ns
10 75 30 —
15 55 30 —
tWL 1000 10 5.0 — 70 — ns
10 — 30 —
15 — 30 —
Output Pulse Width — Q or Q tW 15 5.0 5.0 — 550 — ns
(For CX < 0.01 µF use graph for 10 — 350 —
appropriate VDD level.) 15 — 300 —
Output Pulse Width — Q or Q tW 10,000 10 5.0 15 30 45 µs
(For CX > 0.01 µF use formula: 10 10 50 90
tW = 0.2 RX CX Ln [VDD – VSS])† 15 15 55 95
Pulse Width Match between Circuits in the same t1 – t2 10,000 10 5.0 — 6.0 25 %
package 10 — 8.0 35
15 — 8.0 35
Reset Propagation Delay — Reset to Q or Q tPLH, 15 5.0 5.0 — 325 600 ns
tPHL 10 — 90 225
15 — 60 170
1000 10 5.0 — 1000 — ns
10 — 300 —
15 — 250 —
Retrigger Time trr 15 5.0 5.0 0 — — ns
10 0 — —
15 0 — —
1000 10 5.0 0 — — ns
10 0 — —
15 0 — —
External Timing Resistance RX — — — 5.0 — 1000 kΩ
External Timing Capacitance CX — — — No Limits* µF
† RX is in Ohms, CX is in farads, VDD and VSS in volts, PWout in seconds.
* If CX > 15 µF, Use Discharge Protection Diode DX, per Fig. 9.
** The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

FUNCTION TABLE
Inputs Outputs
Reset A B Q Q
H H
H L
H L Not Triggered
H H Not Triggered
H L, H, H Not Triggered
H L L, H, Not Triggered
L X X L H
X X Not Triggered

MOTOROLA CMOS LOGIC DATA MC14528B

6–323
 VDD VDD
16 16

IOL

A Q OPEN A Q
VOL
B B
VOH
RESET Q RESET Q OPEN
IOH
8 VSS 8 VSS

Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit

VDD

0.1 mF
500 pF ID
CERAMIC

RX RX′
CX CX′
20 ns 20 ns
VDD
Vin 90%
A

B Q Vin 10% 0V
CL
RESET Q DUTY CYCLE = 50%
CL
A′ Q′
CL
B′ Q′
CL
RESET′

VSS

Figure 3. Power Dissipation Test Circuit and Waveforms

VDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
INPUT CONNECTIONS
*CX = 15 pF
RX RX′ *CL = 15 pF Characteristics Reset A B
RX = 5.0 kW
CX CX′ tPLH, tPHL, tTLH, tTHL VDD PG1 VDD
tW
tPLH, tPHL, tTLH, tTHL VDD VSS PG2
A tW
PULSE
GENERATOR tPLH(R), tPHL(R), tW PG3 PG1 PG2
B Q
CL
RESET Q
PULSE
CL
GENERATOR PG1 =
A′ Q′ * Includes capacitance of probes,
CL wiring, and fixture parasitic.
B′ Q′ PG2 =
PULSE NOTE: AC test waveforms for
CL
GENERATOR
RESET′ PG1, PG2, and PG3 on
next page. PG3 =
VSS

Figure 4. AC Test Circuit

MC14528B MOTOROLA CMOS LOGIC DATA

6–324
 90% VDD
50% 10% 50%
A VSS
tWH tTLH tTHL
tTHL tTLH
B VDD
50% 90%
10% VSS
tWL
tTHL tTLH
RESET VDD
90% 50%
10% VSS
tTHL tWL
tW
tPLH tTLH tPHL trr
90% VOH
50% 50% 50% 10% 50%
Q VOL
tTLH tTHL
tPHL tPHL tPHL
Q VOH
50% 50% 90% 50% 50%
10% VOL

Figure 5. AC Test Waveforms

1000
VDD = 15 V
10 V 15 V
5.0 V 10 V
100 5.0 V
t W, PULSE WIDTH ( m s)

RX = 100 kW
15 V
10 V
10
5.0 V
RX = 10 kW

1.0 RX = 5.0 kW
15 V
10 V
5.0 V
0.1
10 100 1000 10,000 100,000
CX, EXTERNAL CAPACITANCE (pF)

Figure 6. Pulse Width versus CX

MOTOROLA CMOS LOGIC DATA MC14528B

6–325
 TYPICAL APPLICATIONS

Cx Rx Cx Rx

VDD VDD

RISING EDGE RISING EDGE

Q A Q
TRIGGER A TRIGGER
B Q B Q
RESET RESET
VDD

VDD VDD

Cx Rx
Cx Rx
VDD
VDD

A Q
A Q
FALLING EDGE B Q
FALLING EDGE B Q TRIGGER RESET
TRIGGER RESET
VDD
VDD

Figure 7. Retriggerable Figure 8. Non–Retriggerable

Monostables Circuitry Monostables Circuitry

DX

Cx VDD
NC
Rx 1, 15 2, 14
VDD
Q NC
A
Q
B Q NC
Q RESET
RESET
VDD
VDD VDD
VDD

Figure 9. Use of a Diode to Limit Figure 10. Connection of Unused Sections

Power Down Current Surge

MC14528B MOTOROLA CMOS LOGIC DATA

6–326
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14529B
Dual 4-Channel Analog
Data Selector L SUFFIX
The MC14529B analog data selector is a dual 4–channel or single CERAMIC
8–channel device depending on the input coding. The device is suitable for CASE 620
digital as well as analog application, including various one–of–four and
one–of–eight data selector functions. Since the device has bidirectional
analog characteristics it can also be used as a dual binary to 1–of–4 or a P SUFFIX
binary to 1–of–8 decoder. PLASTIC
• Data Paths Are Bidirectional CASE 648
• 3–State Outputs
• Linear “On” Resistance
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
• Capable of Driving Two Low–power TTL Loads or One Low–power SOIC
CASE 751B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Schottky TTL Load over the Rated Temperature Range.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) ORDERING INFORMATION
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCP Plastic
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBD SOIC
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW
_C BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150
TL Lead Temperature (8–Second Soldering) 260 _C 3–STATE OUTPUT ENABLE
* Maximum Ratings are those values beyond which damage to the device may occur. STROBE X 1
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 6 A
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
7 B
TRUTH TABLE (X = Don’t Care) 2 X0
Z 9
STX STY B A Z W 3 X1
1 1 0 0 X0 Y0 4 X2
1 1 0 1 X1 Y1 Dual 4–Channel Mode 5 X3
1 1 1 0 X2 Y2 2 Outputs
1 1 1 1 X3 Y3
1 0 0 0 X0
1 0 0 1 X1
14 Y0
1 0 1 0 X2 W 10
Single 8–Channel Mode 13 Y1
1 0 1 1 X3
1 Output 12 Y2
0 1 0 0 Y0 (Z and W tied together) 11 Y3
0 1 0 1 Y1
0 1 1 0 Y2
STROBE Y 15
0 1 1 1 Y3
VDD = PIN 16
0 0 X X High VSS = PIN 8
Impedance

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA MC14529B

6–327
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
– 55_C 25_C 125_C
Characteristic Symbol VDD Test Conditions Min Max Min Typ # Max Min Max Unit
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
Power Supply Voltage VDD — VDD – 3.0 ≥ VSS ≥ 3.0 18 3.0 — 18 3.0 18 V
Range VEE
Quiescent Current Per IDD 5.0 Control Inputs: Vin = — 1.0 — 0.005 1.0 — 60 µA
Package 10 VSS or VDD, — 1.0 — 0.010 1.0 — 60
15 Switch I/O: VSS v — 2.0 — 0.015 2.0 — 120
VI/O v VDD, and
∆Vswitch v 500 mV**
Total Supply Current ID(AV) 5.0 TA = 25_C only (The (0.07 µA/kHz) f + IDD µA
(Dynamic Plus 10 channel component, Typical (0.20 µA/kHz) f + IDD
Quiescent, Per Package 15 (Vin – Vout) / Ron, is (0.36 µA/kHz) f + IDD
not included.)
CONTROL INPUTS — INHIBIT, A, B (Voltages Referenced to VSS)
Low–Level Input Voltage VIL 5.0 Ron = per spec, — 1.5 — 2.25 1.5 — 1.5 V
10 Ioff = per spec — 3.0 — 4.50 3.0 — 3.0
15 — 4.0 — 6.75 4.0 — 4.0
High–Level Input Voltage VIH 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
10 Ioff = per spec 7.0 — 7.0 5.50 — 7.0 —
15 11 — 11 8.25 — 11 —
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µA
Input Capacitance Cin — — — — 5.0 7.5 — — pF
SWITCHES IN/OUT AND COMMONS OUT/IN — W, Z (Voltages Referenced to VEE)
Recommended Peak–to– VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD Vp–p
Peak Voltage Into or
Out of the Switch
Recommended Static or ∆Vswitch — Channel On 0 600 0 — 600 0 300 mV
Dynamic Voltage
Across the Switch**
(Figure 5)
Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV
ON Resistance Ron 10 ∆Vswitch v 500 mV**, — 400 — 120 480 — 560 Ω
15 Vin = VIL or VIH — 240 — 80 270 — 350
(Control), and Vin =
0 to VDD (Switch)
∆ON Resistance Between ∆Ron 10 — — — 15 — — — Ω
Any Two Channels 15 — — — 10 — — —
in the Same Package
Off–Channel Leakage Ioff 15 Vin = VIL or VIH ± 100 — ± 0.05 ± 100 — ± 1000 nA
Current (Figure 10) (Control) Channel to
Channel or Any One
Channel
Capacitance, Switch I/O CI/O — Inhibit = VDD — — — 8.0 — — — pF
Capacitance, Common O/I CO/I — Inhibit = VDD — — — 20 — — — pF
Capacitance, Feedthrough CI/O — Pins Not Adjacent — — — 0.15 — — — pF
(Channel Off) — Pins Adjacent — — — 0.47 — — —
#Data labelled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
** For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)

MC14529B MOTOROLA CMOS LOGIC DATA

6–328
SWTCHING CHARACTERISTICS (TA = 25_C)
Characteristic Figure Symbol VSS VDD Min Typ # Max Unit
Vin to Vout Propagation Delay Time 7 tPLH, tPHL 0.0 5.0 — 20 40 ns
(CL = 50 pF, RL = 1.0 kΩ) 10 — 10 20
15 — 8.0 15
Propagation Delay Time, Control to 8 tPLZ, tPZL, 0.0 5.0 — 140 400 ns
Output, Vin = VDD or VSS tPHZ, tPZH 10 — 70 160
(CL = 50 pF, RL = 1.0 kΩ) 15 — 50 120
Crosstalk, Control to Output 9 — 0.0 5.0 — 5.0 — mV
(CL = 50 pF, RL = 1.0 kΩ 10 — 5.0
Rout = 10 kΩ) 15 — 5.0 —
Control Input Pulse Frequency 10 fin 0.0 5.0 — 5.0 2.5 MHz
(CL = 50 pF, RL = 1.0 kΩ) 10 — 10 6.2
15 — 12 8.3
Noise Voltage 11, 12 — 0.0 5.0 — 24 — nV/
(f = 100 Hz) 10 — 25 — √cycle
15 — 30 —

5.0 — 12 —
10 — 12 —
15 — 15 —

Sine Wave Distortion — — – 5.0 5.0 — 0.36 — %

(Vin = 1.77 Vdc RMS
Centered @ 0.0 Vdc,
RL = 10 kΩ, f = 1.0 kHz)
Off–Channel Leakage Current — Ioff nA
(Vin = + 5.0 Vdc, Vout = – 5.0 Vdc) – 5.0 5.0 — ± 0.001 ± 125
(Vin = – 5.0 Vdc, Vout = + 5.0 Vdc) – 5.0 5.0 — ± 0.001 ± 125
(Vin = + 7.5 Vdc, Vout = – 7.5 Vdc) – 7.5 7.5 — ± 0.0015 ± 250
(Vin = – 7.5 Vdc, Vout = + 7.5 Vdc) – 7.5 7.5 — ± 0.0015 ± 250
Insertion Loss 13 — – 5.0 5.0 dB
(Vin = 1.77 Vdc
RMS centered @ 0.0 Vdc,
f = 1.0 MHz)
Iloss = 20 Log10 (Vout / Vin)
(RL = 1.0 kΩ) — 2.0 —
(RL = 10 kΩ) — 0.8 —
(RL = 100 kΩ) — 0.25 —
(RL = 1.0 MΩ) — 0.01 —
Bandwidth (– 3 dB) — BW – 5.0 5.0 MHz
(Vin = 1.77 Vdc
RMS centered @ 0.0 Vdc)
(RL = 1.0 kΩ) — 35 —
(RL = 10 kΩ) — 28 —
(RL = 100 kΩ) — 27 —
(RL = 1.0 MΩ) — 26 —

Feedthrough and Crosstalk — — – 5.0 5.0 MHz

20 Log10 (Vout / Vin) = – 50 dB
(RL = 1.0 kΩ) — 850 —
(RL = 10 kΩ) — 100 —
(RL = 100 kΩ) — 12 —
(RL = 1.0 MΩ) — 1.5 —
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14529B

6–329
 VDD

STX
IS
STY
VN A
1k
B
X3 Z
Y3 W
VSS

Pins 2, 3, 4, 12, 13 and 14 are left open.

OUT VIL: VC is raised from VSS until VC = VIL.
VIL: at VC = VIL: IS = ± 10 µA with Vin = VSS, Vout = VDD
VSS V
VDD VIL: Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON
VSS = 0.0 V Vin VIH: specifications are met.

Figure 1. Output Voltage Figure 2. Noise Immunity

Test Circuit Test Circuit

VDD

STX = STY = VDD

ID

VDD OUT OUT

10 k RL
PULSE VSS
GENERATOR fc A0, A1 VDD

VSS Vin
PD = VDD x ID
Vin

Figure 3. Quiescent Power Dissipation Figure 4. RON Characteristics

Test Circuit Test Circuit

TYPICAL RON versus INPUT VOLTAGE

250 250

VDD = 5 V VDD = 10 V
R ON “ON” RESISTANCE (OHMS)

R ON “ON” RESISTANCE (OHMS)

200 VSS = –5 V 200

VSS = 0 V

VDD = 15 V
150 150
VDD = 7.5 V VSS = 0 V
VSS = –7.5 V
100 100

50 50

0 0
–10 –5 0 5 10 0 5 10 15 20 25
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 5. Figure 6.

MC14529B MOTOROLA CMOS LOGIC DATA

6–330
 OUT Vout
VSS RL CL STX, STY RL CL
VDD

Vin Vin VX
20 ns
VDD
90%
20 ns 20 ns STX, STY 50%
VDD 10%
V
90% tPZH tPHZ SS
50% 10% 90% Vin VDD
Vin VSS Vout 10%
tPLH tPHL Vx VSS
tPZL tPLZ
50% Vout 90% Vin VSS
Vout 10% Vx VDD

Figure 7. Propagation Delay Test Circuit Figure 8. Turn–On Delay Time Test Circuit
and Waveforms and Waveforms

X, Y VSS
VFeedthrough INPUT
OUT

A OR B CONTROL 10 k 50 pF OUT
RL VDD
LOGIC
RL
VSS VDD
Vin

1k +2.5 Vdc
Vin 0.0 Vdc
–2.5 Vdc X, Y INPUT

Figure 9. Crosstalk Test Circuit Figure 10. Frequency Response Test Circuit

35

30
NOISE VOLTAGE (nV/ CYCLE)

VDD = 15 Vdc
25
p

10 Vdc
20
5.0 Vdc
15

10
OUT QUAN–TECH
VSS VDD MODEL 5.0
2283
IN OR EQUIV 0
10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz)

Figure 11. Noise Voltage Test Circuit Figure 12. Typical Noise Characteristics

MOTOROLA CMOS LOGIC DATA MC14529B

6–331
 2.0 PIN ASSIGNMENT
RL = 1 MW AND 100 kW
0 STX 1 16 VDD
TYPICAL INSERTION LOSS (dB)
10 kW X0 2 15 STY
–2.0
1.0 kW X1 3 14 Y0
–4.0 X2 4 13 Y1
–3.0 dB (RL = 1.0 MW)
X3 5 12 Y2
–6.0 –3.0 dB (RL = 10 kW)
A 6 11 Y3
–8.0 –3.0 dB (RL = 1.0 kW)
B 7 10 W
–10 VSS 8 9 Z

–12
10 k 100 k 1.0 M 10 M 100 M
fin, INPUT FREQUENCY (Hz)

Figure 13. Typical Insertion Loss/Bandwidth

Characteristics

LOGIC DIAGRAM

B A STY STX
7 6 15 1

2
X0

3
X1
9
Z
4
X2

5
X3

14
Y0

13
Y1
10
W
12
Y2

11
Y3

VDD = PIN 16
VSS = PIN 8

MC14529B MOTOROLA CMOS LOGIC DATA

6–332
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14530B
Dual 5-Input Majority
Logic Gate L SUFFIX
CERAMIC
The MC14530B dual five–input majority logic gate is constructed with CASE 620
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Combinational and sequential logic expressions are
easily implemented with the majority logic gate, often resulting in fewer P SUFFIX
components than obtainable with the more basic gates. This device can also PLASTIC
provide numerous logic functions by using the W and some of the logic (A CASE 648
thru E) inputs as control inputs.
• Diode Protection on All Inputs
D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
SOIC
• Capable of Driving Two Low–power TTL Loads or One Low–power CASE 751B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range

ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCP Plastic
Symbol Parameter Value Unit MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD

ÎÎÎÎÎÎÎÎÎÎÎ
Tstg ÎÎÎÎÎÎ
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C 6
W
BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C 1
2
3
A
B
C M5
7
Z
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 4 D
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 5 E

LOGIC TABLE * Z = M5  W = (ABC+ABD+ABE+ACD+

Z = M5  W = (ACE+ADE+BCD+BCE+
INPUTS A B C D E W Z
Z = M5  W = (BDE+CDE)  W
For all combinations of inputs where three or 0 1
more inputs
i t are llogical
i l “0”
“0”. 9 A
1 0
10 B
For all combinations of inputs where three or 0 0 11 C M5 15
more inputs
i t are llogical
i l “1”
“1”. Z
1 1 12 D
13 E

14
W
* M5 is a logical “1” if any three or more
This device contains protection circuitry to guard against damage inputs are logical “1”.
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
  Exclusive NOR  Exclusive OR
voltages to this high-impedance circuit. For proper operation, Vin and TRUTH TABLE
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. M5 W Z
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. 0 0 1
0 1 0
1 0 0
1 1 1
VDD = PIN 16
VSS = PIN 8

MOTOROLA CMOS LOGIC DATA MC14530B

6–333
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.2 — 2.25 1.25 — 1.15
(VO = 9.0 or 1.0 Vdc) 10 — 2.5 — 4.50 2.5 — 2.4
(VO = 13.5 or 1.5 Vdc) 15 — 3.0 — 6.75 3.0 — 2.9
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.85 — 3.75 2.75 — 3.75 —
(VO = 1.0 or 9.0 Vdc) 10 7.6 — 7.5 5.50 — 7.5 —
(VO = 1.5 or 13.5 Vdc) 15 12.1 — 12 8.25 — 12

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
15 — 1.0 — 0.0015 1.0 — 30
Total Supply Current**† IT 5.0 IT = (0.75 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.50 µA/kHz) f + IDD
Per Package) 15 IT = (2.25 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
* To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT
AA 1 16 VDD
BA 2 15 ZB
CA 3 14 WB
DA 4 13 EB
EA 5 12 DB
WA 6 11 CB
ZA 7 10 BB
VSS 8 9 AB

MC14530B MOTOROLA CMOS LOGIC DATA

6–334
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH ns
A, C, W = VDD; B, E = Gnd; D = Pulse Generator
tPLH = (1.7 ns/pF) CL + 290 ns 5.0 — 375 960
tPLH = (0.66 ns/pF) CL + 127 ns 10 — 160 400
tPLH = (0.5 ns/pF) CL + 85 ns 15 — 110 300
tPHL = (1.7 ns/pF) CL + 345 ns tPHL 5.0 — 430 1200 ns
tPHL = (0.66 ns/pF) CL + 162 ns 10 — 195 540
tPHL = (0.5 ns/pF) CL + 95 ns 15 — 120 410
A, B, C, D, E = Pulse Generator; W = VDD tPLH ns
tPLH = (1.7 ns/pF) CL + 170 ns 5.0 — 255 640
tPLH = (0.66 ns/pF) CL + 87 ns 10 — 120 300
tPLH = (0.5 ns/pF) CL + 60 ns 15 — 86 210
tPHL = (1.7 ns/pF) CL + 195 ns tPHL 5.0 — 280 750 ns
tPHL = (0.66 ns/pF) CL + 92 ns 10 — 125 330
tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 250

A, B, C, D, E = Gnd; W = Pulse Generator tPLH, ns

tPHL, tPLH = (1.7 ns/pF) CL + 145 ns tPHL 5.0 — 230 575
tPHL, tPLH = (0.66 ns/pF) CL + 72 ns 10 — 105 265
tPHL, tPLH = (0.5 ns/pF) CL + 50 ns 15 — 75 190
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD
16

A
B
Z
C
D
PULSE E CL
GENERATOR
W
A
B
C Z
D
E
W CL

20 ns 20 ns 8 VSS

VDD
50%
Vin DUTY VSS
CYCLE
Figure 1. Power Dissipation Test
Circuit and Waveform

MOTOROLA CMOS LOGIC DATA MC14530B

6–335
 SEQUENTIAL LOGIC APPLICATIONS

W COINCIDENT FLIP–FLOP
1

0 A
1 B Z x y Qn+1
x C 0 0 0 A flip–flop that will change only when both inputs agree.
y D 0 1 Q
E 0 0 Q
1 1 1

ASTABLE MULTIVIBRATOR
W
0

0 A
Z x y Qn+1
1 B
x C 0 0 1 A flip–flop with three output conditions, where the third state is
y D 0 1 2τ in oscillation between “1” and “0”. The period of oscillation is
1 0 2τ twice the delay of the gate and the feedback element.
E
1 1 1
t

COINCIDENT FLIP–FLOP

W
1
tx y z Qn+1
x A
0 0 0 0 The flip–flop changes state only when all “1’s” or all “0’s” are
y B Z
0 0 1 Qn entered. This configuration may be extended by cascading M5
z C 0 1 0 Qn gates to cover n–inputs where all inputs must be “1’s” or “0’s”
D 0 1 1 Qn before the output will change. As an example, this configura-
E 1 0 0 Qn tion is useful for controlling an n–stage up/down counter that is
1 0 1 Qn to cycle from a minimum to maximum count and back again
1 1 0 Qn without flipping over (from all “1’s” to all “0’s”.)
1 1 1 1

MC14530B MOTOROLA CMOS LOGIC DATA

6–336
 BASIC COMBINATIONAL FUNCTIONS 5–INPUT MAJORITY LOGIC GATE APPLICATIONS
Each package labeled M5 is a single majority logic gate
W W
1 0 using five inputs, A thru E, and one output Z.
A A
B Z B Z
C C 1. Majority Logic Gate Array
M5 M5
D D yielding the symmetric function
E E of 1 thru 7 variables true, out
5–INPUT MAJORITY GATES of 7 input variables (X1... X7)
W W
1 0 (e.g., if any two–input variables
1 1 are true (logical “1”), Z1 and
Z Z Z2 are true (logical “1”) 0 A
0 0 B
A A 0
M3 M3 C M5 Z7
B B D
C C E
3–INPUT MAJORITY GATES
W W
1 0
1 1
1 Z 1 Z 0 A
A OR3 A NOR3 B
B B C M5 Z6
C C D
E
3–INPUT OR GATE 3–INPUT NOR GATE
W W
1 0
0 0
0 Z 0 Z 0 A
A AND3 A NAND3 0 B
B B M5 C M5 Z5
C C D
E
3–INPUT AND GATE 3–INPUT NAND GATE

DOUBLING THE WEIGHT OF INPUT VARIABLE A

BY TYING IT TO ANY TWO INPUTS 0 A
B
W M5 C M5 Z4
W D
A E
A
B
Z
(AB + AC + AD + BCD) W
C
D
0 A
0 B
CORRELATION OF MULTIPLE SAMPLES M5 M5 C M5 Z3
W D
To WITH A TEST BIT E
S0 A
S1 B Z
S2 C CORRELATION OF 60%, 80%, 100%
S3 D
S4 E The gate will have a “1” output if
the test bit To matches or corre- 0 1 1 A
1 B
lates with 3, 4 or 5 of the sample M5 M5 C M5 Z2
W bits S0–S4. D
To E
To A
S0 B Z
C CORRELATION OF 75%, 100%
S1
S2 D
S3 E 1 1 1 A
1 1 1 B
M5 M5 C M5 Z1
W D
To E
To A
To B Z X1 X3 X4 X5 X6 X7
S0 C CORRELATION OF 100% X2
S1 D
S2 E

MOTOROLA CMOS LOGIC DATA MC14530B

6–337
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14531B
12-Bit Parity Tree
The MC14531B 12–bit parity tree is constructed with MOS P–channel and L SUFFIX
CERAMIC
N–channel enhancement mode devices in a single monolithic structure. The
CASE 620
circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity
selection input (W) and an output (Q). The parity selection input can be
considered as an additional bit. Words of less than 13 bits can generate an
even or odd parity output if the remaining inputs are selected to contain an P SUFFIX
even or odd number of ones, respectively. Words of greater than 12–bits can PLASTIC
CASE 648
be accommodated by cascading other MC14531B devices by using the W
input. Applications include checking or including a redundant (parity) bit to a
word for error detection/correction systems, controller for remote digital
sensors or switches (digital event detection/correction), or as a multiple input D SUFFIX
summer without carries. SOIC
CASE 751B
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered ORDERING INFORMATION
• Capable of Driving Two Low–Power TTL Loads or One Low–Power MC14XXXBCP Plastic
Schottky TTL Load Over the Rated Temperature Range MC14XXXBCL Ceramic
• Variable Word Length MC14XXXBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Diode Protection on All Inputs TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
PD ÎÎÎ
per Pin

ÎÎÎÎÎÎ
ÎÎÎ
Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
TRUTH TABLE
* Maximum Ratings are those values beyond which damage to the device may occur.
Inputs Output
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Decimal
(Octal)
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C W D11 D10 … D2 D1 D0 Equivalent Q*
0 0 0 … 0 0 0 0 (0) 0
LOGIC DIAGRAM 0 0 0 … 0 0 1 1 (1) 1
0 0 0 … 0 1 0 2 (2) 1
0 0 0 … 0 1 1 3 (3) 0
D0 7 0 0 0 … 1 0 0 4 (4) 1
0 0 0 … 1 0 1 5 (5) 0
D1 6 0 0 0 … 1 1 0 6 (6) 0
D2 5 0 0 0 … 1 1 1 7 (7) 1
D3 4 * * * * * * * * *
* * * … * * * * *
D4 3 * * * * * * * * *
D5 2 1 1 1. … 0 0 0 8184 (17770) 0
D6 1 9 Q 1 1 1 … 0 0 1 8185 (17771) 1
1 1 1 … 0 1 0 8186 (17772) 1
D7 15 1 1 1 … 0 1 1 8187 (17773) 0
D8 14 1 1 1 … 1 0 0 8188 (17774) 1
D9 13 1 1 1 … 1 0 1 8189 (17775) 0
VDD = PIN 16 1 1 1 … 1 1 0 8190 (17776) 0
D10 12 1 1 1 … 1 1 1 8191 (17777) 1
VSS = PIN 8
D11 11 *0 = Even Parity 1 = Odd Parity
ODD/EVEN W 10 NOTE: May redefine to suit application by manipulating W and/or other
available D’s.

Q = D0  D1  D2  @@@@  D11  W

MC14531B MOTOROLA CMOS LOGIC DATA

6–338
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.25 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.50 µA/kHz) f + IDD
Per Package) 15 IT = (0.75 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must D6 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and D5 2 15 D7
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. D4 3 14 D8
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. D3 4 13 D9
D2 5 12 D10
D1 6 11 D11
D0 7 10 W
VSS 8 9 Q

MOTOROLA CMOS LOGIC DATA MC14531B

6–339
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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.6 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Data to Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 355 ns 5.0 — 440 1320
tPLH, tPHL = (0.66 ns/pF) CL + 142 ns 10 — 175 525
tPLH, tPHL = (0.5 ns/pF) CL + 95 ns 15 — 120 360
Odd/Even to Q
tPLH, tPHL = (1.7 ns/pF) CL + 165 ns 5.0 — 250 750
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns 10 — 100 300
tPLH, tPHL = (0.5 ns/pF) CL + 45 ns 15 — 70 210
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns 20 ns 20 ns
VDD VDD
90% 90%
50% 50% 10%
SIGNAL 10% VSS INPUT VSS
INPUT (D OR W) tPLH tPHL
1 VOH
DATA RATE (f) 90%
50%
10%
OUTPUT VOL
f IN RESPECT TO SYSTEM CLOCK tTLH tTHL

Figure 1. Dynamic Power Dissipation Figure 2. Dynamic Signal Waveforms

Signal Waveform

MC14531B MOTOROLA CMOS LOGIC DATA

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14532B
8-Bit Priority Encoder
The MC14532B is constructed with complementary MOS (CMOS) L SUFFIX
enhancement mode devices. The primary function of a priority encoder is to CERAMIC
provide a binary address for the active input with the highest priority. Eight CASE 620
data inputs (D0 thru D7) and an enable input (Ein) are provided. Five outputs
are available, three are address outputs (Q0 thru Q2), one group select (GS)
and one enable output (Eout). P SUFFIX
PLASTIC
• Diode Protection on All Inputs
CASE 648
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–Power

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load over the Rated Temperature Range
D SUFFIX

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SOIC
MAXIMUM RATINGS* (Voltages Referenced to VSS) CASE 751B
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
ORDERING INFORMATION
MC14XXXBCP Plastic
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
MC14XXXBCL Ceramic
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA MC14XXXBD SOIC
per Pin TA = – 55° to 125°C for all packages.
PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C PIN ASSIGNMENT
* Maximum Ratings are those values beyond which damage to the device may occur. D4 1 16 VDD
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C D5 2 15 Eout
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C D6 3 14 GS

TRUTH TABLE D7 4 13 D3

Input Output Ein 5 12 D2

Q2 6 11 D1
Ein D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 Eout
Q1 7 10 D0
0 X X X X X X X X 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 1 VSS 8 9 Q0
1 1 X X X X X X X 1 1 1 1 0
1 0 1 X X X X X X 1 1 1 0 0
1 0 0 1 X X X X X 1 1 0 1 0
1 0 0 0 1 X X X X 1 1 0 0 0
1 0 0 0 0 1 X X X 1 0 1 1 0
1 0 0 0 0 0 1 X X 1 0 1 0 0
1 0 0 0 0 0 0 1 X 1 0 0 1 0
1 0 0 0 0 0 0 0 1 1 0 0 0 0
X = Don’t Care

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA MC14532B

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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.74 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.65 µA/kHz) f + IDD
Per Package) 15 IT = (5.73 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.

MC14532B MOTOROLA CMOS LOGIC DATA

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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time — Ein to Eout tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 120 ns tPHL 5.0 — 205 410
tPLH, tPHL = (0.66 ns/pF) CL + 77 ns 10 — 110 220
tPLH, tPHL = (0.5 ns/pF) CL + 55 ns 15 — 80 160
Propagation Delay Time — Ein to GS tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns tPHL 5.0 — 175 350
tPLH, tPHL = (0.66 ns/pF) CL 57 ns 10 — 90 180
tPLH, tPHL = (0.5 ns/pF) CL + 40 ns 15 — 65 130
Propagation Delay Time — Ein to Qn tPHL, ns
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns tPLH 5.0 — 280 560
tPLH, tPHL = (0.66 ns/pF) CL + 107 ns 10 — 140 280
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 200
Propagation Delay Time — Dn to Qn tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns tPHL 5.0 — 300 600
tPLH, tPHL = (0.66 ns/pF) CL + 137 ns 10 — 170 340
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns 15 — 110 220
Propagation Delay Time — Dn to GS tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns tPHL 5.0 — 280 560
tPLH, tPHL = (0.66 ns/pF) CL + 107 ns 10 — 140 280
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 200
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Vout

Ein
D0
D1 Eout
D2 Q0
SWITCH
MATRIX D3 Q1
D4 Q2 VDD
ID
D5 GS
D6 500 µF ID 0.01 µF
D7
EXTERNAL
POWER
SUPPLY Ein Eout
D0 CL

VGS = VDD VGS = – VDD D1 Q0

VDS = Vout VDS = Vout – VDD D2 CL
Output
Sink Current Source Current D3 Q1
Under
D4 CL
Test D0 thru D7 Ein D0 thru D6 D7 Ein
D5 Q2
Eout X 0 0 0 1 CL
Q0 X 0 0 1 1 PULSE D6
Q1 X 0 0 1 1 GENERATOR D7 GS
Q2 X 0 0 1 1 (fo) CL
VSS
GS X 0 0 1 1

Figure 1. Typical Sink and Source

Current Characteristics Figure 2. Typical Power Dissipation Test Circuit

MOTOROLA CMOS LOGIC DATA MC14532B

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 VDD

Ein Eout
D0 CL
D1 Q0
PROGRAMMABLE D2 CL
PULSE D3 Q1
GENERATOR D4 CL
D5 Q2
D6 CL
D7 GS
VSS CL

NOTE: Input rise and fall times are 20 ns

PIN
NO.
50%
D0 10
50%
D1 11
50%
D2 12

50%
D3 13

50%
D4 1
50%
D5 2

50%
D6 3
50%
D7 4
50%
Ein 5
tPLH tPHL
90%
50%
Eout 15 10%
tTHL
tTLH tPLH tPHL
90%
50%
GS 14 10%
tTLH tPLH tPLH tPLH tTHL
tPLH tPHL tPHL tPHL tPHL
90%
50%
Q0 9 10%
tPLH tPLH tTLH tTHL
tPHL tPHL
90%
50%
Q1 7 10%
tTLH tTHL
tPLH tPHL
90%
50%
10%
Q2 6
tTLH tTHL

Figure 3. AC Test Circuit and Waveforms

MC14532B MOTOROLA CMOS LOGIC DATA

6–344
 LOGIC DIAGRAM
(Positive Logic)
LOGIC EQUATIONS

Eout = Ein  D0  D1  D2  D3  D4  D5  D6  D7
Q0 = Ein  (D1  D2  D4  D6 + D3  D4  D6 + D5  D6 + D7)
Q1 = Ein  (D2  D4  D5 + D3  D4  D5 + D6 + D7)
10 Q2 = Ein  (D4 + D5 + D6 + D7)
D0
GS = Ein  (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)

11
D1 9
Q0

12
D2

13
D3

1
D4
7
Q1

2
D5

3
D6

4
D7

6
5 Q2
Ein

14
GS

15
Eout

MOTOROLA CMOS LOGIC DATA MC14532B

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 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

VDD Ein Eout Ein Eout Eout = “1”

WITH Din = “0”
GS Q2 Q1 Q0 Q2 Q1 Q0

3/4 MC14071B

Q3 Q2 Q1 Q0

Figure 4. Two MC14532B’s Cascaded for 4–Bit Output

VDD VSS

CLOCK
INPUT
C E R C E R
1/2 MC14520B 1/2 MC14520B
DIGITAL TO ANALOG CONVERSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
The digital eight–bit word to be converted is applied to
the inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to
2.5 MHz (at VDD = 10 V) is applied to the MC14520B.
A compromise between I bias for the MC1710 and ∆R
between N and P–channel outputs gives a value of R of
33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms,
C [ 0.03 µF). The analog 3.0 dB bandwidth would then be D0 D1 D2 D3 D4 D5 D6 D7
DIGITAL INPUT/OUTPUT
8–BIT WORD
dc to 1.0 kHz. VDD Ein TO BE CONVERTED
Q2 Q1 Q0
ANALOG TO DIGITAL CONVERSION
X7 X6 X5 X4 X3 X2 X1 X0
An analog signal is applied to the analog input of the A
MC1710. A digital eight–bit word known to represent a digi- B MC14512
C Z
tized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is increm-
ented at rates sufficient to allow steady state to be reached MC1710 R
between incrementations (i.e. 3.0 ms). The output of the ANALOG
MC1710 will change when the digital input represents the STOP OUTPUT
first digitized level above the analog input. This word is the WORD C
digital representation of the analog word. INCREMENTATION

ANALOG
INPUT

Figure 5. Digital to Analog and Analog to Digital Converter

MC14532B MOTOROLA CMOS LOGIC DATA

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14534B
5 Cascaded BCD Counters
The MC14534B is composed of five BCD ripple counters that have their L SUFFIX
CERAMIC
respective outputs multiplexed using an internal scanner. Outputs of each
CASE 623
counter are selected by the scanner and appear on four (BCD) pins.
Selection is indicated by a logic high on the appropriate digit select pin. Both
BCD and digit select outputs have three–state controls providing an
“open–circuit” when these controls are high and allowing multiplexing. P SUFFIX
Cascading may be accomplished by using the carry–out pin. The counters PLASTIC
CASE 709
and scanner can be independently reset by applying a high to the counter
master reset (MR) and the scanner reset (SR). The MC14534B was
specifically designed for application in real time or event counters where
continual updating and multiplexed displays are used. DW SUFFIX
SOIC
• Four Operating Modes (See truth table) CASE 751E
• Input Error Detection Circuit
• Clock Conditioning Circuits for Slow Transition Inputs ORDERING INFORMATION
• Counter Sequences on Positive Transition of Clock A MC14XXXBCP Plastic
• Supply Voltage Range = 3.0 Vdc to 18 Vdc MC14XXXBCL Ceramic
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14XXXBDW SOIC
Schottky TTL Load Over the Rated Temperature Range TA = – 55° to 125°C for all packages.

BLOCK DIAGRAM

TO CAPACITORS

22 1
23 VDD = PIN 24
CLOCK B 3 VSS = PIN 12
PULSE ERROR ERROR OUT
PULSE
CLOCK A DETECTOR
4 SHAPER
TEST
CONTROL
MASTER 2
RESET
UNITS TENS HUNDREDS THOUSANDS TEN
CARRY THOUSANDS 13
C ÷ 10 Cn+4 C ÷ 10 Cn+4 C ÷ 10 Cn+4 C ÷ 10 Cn+4 C ÷ 10 Cn+4 CARRY OUT
CONTROL
Q0 Q3 Q0 Q3 Q0 Q3 Q0 Q3 Q0 Q3
5
MODE A OUTPUT MUX MUX MUX MUX 17
MODE B CONTROL Q3
6
MUX 18
Q2
BCD
OUT
SCANNER 19
Q1
RESET 9
R
20
SCANNER 10 Q0
SCANNER
CLOCK

3–STATE BCD
21
CONTROL
15 3–STATE DIGIT
7 8 14 16 11 CONTROL 3–State Control Out
DS1 DS2 DS3 DS4 DS5
NOTE:
0 Q or DS
= 3–STATE DIGIT SELECT
OUTPUT BUFFER 1 High Impedance

MOTOROLA CMOS LOGIC DATA MC14534B

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MAXIMUM RATINGS (Voltages referenced to VSS)
Symbol Parameter Value Unit This device contains protection circuitry to
VDD DC Supply Voltage – 0.5 to + 18.0 V guard against damage due to high static
voltages or electric fields. However, pre-
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V cautions must be taken to avoid applications of
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA any voltage higher than maximum rated volt-
per Pin ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
PD Power Dissipation, per Package† 500 mW to the range VSS v(Vin or Vout) v
VDD.
Unused inputs must always be tied to an
Tstg Storage Temperature – 65 to + 150 _C
appropriate logic voltage level (e.g., either VSS
TL Lead Temperature (8–Second Soldering) 260 _C or VDD). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.0 — 1.5 1.0 — 1.0
(VO = 9.0 or 1.0 Vdc) 10 — 2.0 — 3.0 2.0 — 2.0
(VO = 13.5 or 1.5 Vdc) 15 — 3.0 — 4.5 3.0 — 3.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 4.0 — 4.0 3.5 — 4.0 —
(VO = 1.0 or 9.0 Vdc) 10 8.0 — 8.0 7.0 — 8.0 —
(VO = 1.5 or 13.5 Vdc) 15 12 — 12 11 — 12 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Output Drive Current — Pins 1 and 22 IOH mAdc
(VOH = 2.5 Vdc) 5.0 – 0.31 – 0.25 – 0.8 – 0.17
(VOH = 9.5 Vdc) Source 10 – 0.31 — – 0.25 – 0.4 — – 0.17 —
(VOH = 13.5 Vdc) 15 – 0.9 — – 0.75 – 1.6 — – 0.51 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.024 — 0.02 0.03 — 0.014 — mAdc
(VOL = 0.5 Vdc) 10 0.06 — 0.05 0.09 — 0.035 —
(VOL = 1.5 Vdc) 15 1.3 — 0.25 1.63 — 0.175 —

Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. (continued)

MC14534B MOTOROLA CMOS LOGIC DATA

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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) (continued)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Quiescent Current IDD 5.0 — 5.0 — 0.010 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.020 10 — 300
15 — 20 — 0.030 20 — 600
Total Supply Current**† IT 5.0 µAdc
(Dynamic plus Quiescent, 10 IT = (0.5 µA/kHz) f + IDD Scan Oscillator
Per Package) 15 IT = (1.0 µA/kHz) f + IDD Frequency = 1.0 kHz
(CL = 50 pF on all outputs, all IT = (1.5 µA/kHz) f + IDD
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MOTOROLA CMOS LOGIC DATA MC14534B

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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C, see Figure 1)

Characteristic Symbol
VDD
Vdc Min Typ # Max Unit
Output Rise and Fall Time tTLH, 5.0 — 100 200 ns
tTHL 10 — 50 100
15 — 40 80
Propagation Delay Time, tPLH, µs
Clock to Q tPHL
tPLH, tPHL = (1.8 ns/pF) CL + 4.0 µs 5.0 — 4.0 8.0
tPLH, tPHL = (0.8 ns/pF) CL + 1.5 µs 10 — 1.5 3.0
tPLH, tPHL = (0.6 ns/pF) CL + 1.0 µs 15 — 1.0 2.25
Clock to Carry Out tPLH µs
tPLH = (1.8 ns/pF) CL + 3.3 µs 5.0 — 3.3 6.6
tPLH = (0.8 ns/pF) CL + 1.1 µs 10 — 1.1 2.2
tPLH = (0.6 ns/pF) CL + 0.8 µs 15 — 0.8 1.7
Master Reset to Q tPHL µs
tPHL = (1.8 ns/pF) CL + 1.8 µs 5.0 — 1.8 3.6
tPHL = (0.8 ns/pF) CL + 0.6 µs 10 — 0.6 1.2
tPHL = (0.6 ns/pF) CL + 0.5 µs 15 — 0.5 0.9
Master Reset to Error Out tPHL µs
tPHL = (1.8 ns/pF) CL + 0.57 µs 5.0 — 0.6 1.5
tPHL = (0.8 ns/pF) CL + 0.19 µs 10 — 0.2 .5
tPHL = (0.6 ns/pF) CL + 0.11 µs 15 — 0.12 0.38
Scanner Clock to Q tPLH, µs
tPLH, tPHL = (1.8 ns/pF) CL + 1.8 µs tPHL 5.0 — 1.8 3.6
tPLH, tPHL = (0.8 ns/pF) CL + 0.6 µs 10 — 0.6 1.2
tPLH, tPHL = (0.6 ns/pF) CL + 0.5 µs 15 — 0.5 0.9
Scanner Clock to Digit Select tPLH, µs
tPHL, tPLH = (1.8 ns/pF) CL + 1.5 µs tPLH 5.0 — 1.5 3.0
tPHL, tPLH = (0.8 ns/pF) CL + 0.5 µs 10 — 0.5 1.0
tPHL, tPLH = (0.6 ns/pF) CL + 0.4 µs 15 — 0.4 0.75
Propagation Delay Time tPHZ 5.0 — 75 150 ns
3–State Control to Q 10 — 45 90
15 — 40 80
tPZH 5.0 — 120 240 ns
10 — 55 110
15 — 40 80
tPLZ 5.0 — 120 240 ns
10 — 55 110
15 — 45 90
tPZL 5.0 — 160 320 ns
10 — 70 140
15 — 45 90
Clock Pulse Frequency fcl 5.0 — 1.0 0.5 MHz
10 — 3.0 1.0
15 — 5.0 1.2
Clock or Scanner Clock Pulse Width tWH 5.0 1000 500 — ns
10 500 190 —
15 375 125 —
Scanner Reset Pulse Width tw 5.0 320 160 — ns
10 130 65 —
15 80 40 —
Scanner Reset Removal Time trem 5.0 900 270 — ns
10 150 80 —
15 100 50 —
Master Reset Pulse Width tWH(R) 5.0 2000 900 — ns
10 600 300 —
15 450 250 —
Master Reset Removal Time trem 5.0 1060 550 — ns
10 350 205 —
15 250 140 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14534B MOTOROLA CMOS LOGIC DATA

6–350
 COUNTER TIMING DIAGRAM

1 2 3 4 5 6 7 8 9 10 102 103 104 105 106

CLOCK A

UNITS Q0

UNITS Q1

UNITS Q2

UNITS Q3

UNITS Cn + 4

TENS Q0

TENS Q3

TENS Cn + 4

HUNDREDS Q0

HUNDREDS Q3

HUNDREDS Cn + 4

THOUSANDS Q0

THOUSANDS Q3

THOUSANDS Cn + 4

TEN THOUSANDS Q0

TEN THOUSANDS Q3

CARRY OUT

MASTER RESET

MODE CONTROL TRUTH TABLE

Mode A Mode B First Stage Output Carry to Second Stage Application
0 0 Normal Count and Display At 9 to 0 transition of first stage 5–digit Counter
0 1 Inhibited Input Clock Test Mode: Clock directly into stages 1, 2, and 4.
1 1 Inhibited At 4 to 5 transition of first stage 4–digit counter with ÷ 10 and roundoff at front end.
1 0 Counts 3, 4, 5, 6, 7 = 5 At 7 to 8 transition of first stage 4–digit counter with 1/2 pence capability.
Counts 8, 9, 0, 1, 2 = 0

MOTOROLA CMOS LOGIC DATA MC14534B

6–351
 SCANNER TIMING DIAGRAM

SCANNER
CLOCK
SCANNER
RESET

DS1 UNITS

DS2 TENS

DS3
HUNDREDS

DS4 THOUSANDS

DS5 TEN
THOUSANDS

NOTE: If Mode B = 1, the first decade is inhibited and S1 will not go high, and the cycle will be
shortened to four stages.
DS5 is selected automatically when Scanner Reset goes high.

ERROR DETECTION TIMING DIAGRAM

RESET

CLOCK A
CLOCK B

ERROR ERROR
ERROR GOOD PULSE 1 2 GOOD PULSE ERROR ERROR
OUT 3 4

NOTE: Error detector looks for inverted pulse on Clock B. Whenever a positive edge at
Clock A is not accompanied by a negative pulse at Clock B (or vice–versa) within
a time period of the one–shots an error is counted. Three errors result in Error Out
to go to a “1”. If error detection is not needed, tie Clock B high or low and leave
Pins 1 and 22 unconnected.

CLOCK SKEW RANGE

1000
500
ALLOWABLE CLOCK SKEW (ns/pF)

300

100 SKEW IN THIS RANGE

RESULTS IN COUNTED NOTES:
50 ERROR. 1. The skew is the time difference between the
30 low–to–high transition of CA to the high–to–
MAX
SKEW IN THIS RANGE low transition of CB or vice–versa. Capacitors
10 MAY OR MAY NOT C1 = C22 tied from pins 1 and 22 to VSS.
RESULT IN COUNTED TYP
2. This graph is accurate for C1 = C22 ≥ 100 pF.
5.0 ERROR.
3. When the error detection circuitry in not used,
3.0 SKEW IN THIS RANGE MIN
RESULTS IN NO ERROR
pins 1 and 22 are left open.
COUNTED.
1.0
3.0 5.0 7.0 9.0 11 13 15 17
VDD (Vdc)

MC14534B MOTOROLA CMOS LOGIC DATA

6–352
 APPLICATIONS INFORMATION

VDD

En MC14534B MC14534B
1/2
Q4 CLOCK A Cout* CLOCK A
MC14518B
CLOCK C

* Carry Out is high for a single clock period when all five BCD stages go to zero.
(Carry Out also goes high when MR is applied.)

Figure 1. Cascade Operation

Q0
CLOCK CLOCK A BCD FOR
Q1
MC14534B SELECTED
Q2 STAGE
SC
Q3
DS1 DS2 DS3 DS4 DS5

When the Q outputs of a given stage are required, this configuration will
lock up the selected stage within four clock cycles. The select line feedback
may be hardwired or switched.

Figure 2. Forcing a BCD Stage to the Q Outputs

PIN ASSIGNMENT

Cext 1 24 VDD
MR 2 23 CLOCK B
Eout 3 22 Cext
CLOCK A 4 21 3–ST BCD
MODE A 5 20 Q0
MODE B 6 19 Q1
DS1 7 18 Q2
DS2 8 17 Q3
SR 9 16 DS4
SC 10 15 3–ST DIG
DS5 11 14 DS3
VSS 12 13 Cout

MOTOROLA CMOS LOGIC DATA MC14534B

6–353
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14536B
Programmable Timer
The MC14536B programmable timer is a 24–stage binary ripple counter L SUFFIX
CERAMIC
with 16 stages selectable by a binary code. Provisions for an on–chip RC
CASE 620
oscillator or an external clock are provided. An on–chip monostable circuit
incorporating a pulse–type output has been included. By selecting the
appropriate counter stage in conjunction with the appropriate input clock
frequency, a variety of timing can be achieved. P SUFFIX
PLASTIC
• 24 Flip–Flop Stages — Will Count From 20 to 224 CASE 648
• Last 16 Stages Selectable By Four–Bit Select Code
• 8–Bypass Input Allows Bypassing of First Eight Stages
• Set and Reset Inputs DW SUFFIX
• Clock Inhibit and Oscillator Inhibit Inputs SOIC
• On–Chip RC Oscillator Provisions CASE 751G
• On–Chip Monostable Output Provisions
ORDERING INFORMATION
• Clock Conditioning Circuit Permits Operation With Very Long Rise and
Fall Times MC14XXXBCP Plastic
MC14XXXBCL Ceramic
• Test Mode Allows Fast Test Sequence MC14XXXBDW SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
TA = – 55° to 125°C for all packages.
• Capable of Driving Two Low–power TTL Loads or One Low–power

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
CLOCK INH. RESET SET 8 BYPASS
7 2 1 6

OSC. INHIBIT 14

STAGES STAGES 9 THRU 24

IN1 Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
3 1 THRU 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

4 5
OUT1 OUT2 A 9
B 10
C 11 DECODER
VDD = PIN 16 D 12
VSS = PIN 8
MONOSTABLE DECODE
MONO–IN 15 13
MULTIVIBRATOR OUT

MC14536B MOTOROLA CMOS LOGIC DATA

6–354
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) Pins 4 & 5 5.0 – 0.25 — – 0.25 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 — mAdc
(VOH = 4.6 Vdc) Pin 13 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.010 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.020 10 — 300
15 — 20 — 0.030 20 — 600
Total Supply Current**† IT 5.0 IT = (1.50 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.30 µA/kHz) f + IDD
Per Package) 15 IT = (3.55 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.

MOTOROLA CMOS LOGIC DATA MC14536B

6–355
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time (Pin 13) tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Clock to Q1, 8–Bypass (Pin 6) High tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 1715 ns 5.0 — 1800 3600
tPLH, tPHL = (0.66 ns/pF) CL + 617 ns 10 — 650 1300
tPLH, tPHL = (0.5 ns/pF) CL + 425 ns 15 — 450 1000
Clock to Q1, 8–Bypass (Pin 6) Low tPLH, µs
tPLH, tPHL = (1.7 ns/pF) CL + 3715 ns tPHL 5.0 — 3.8 7.6
tPLH, tPHL = (0.66 ns/pF) CL + 1467 ns 10 — 1.5 3.0
tPLH, tPHL = (0.5 ns/pF) CL + 1075 ns 15 — 1.1 2.3
Clock to Q16 tPLH, µs
tPHL, tPLH = (1.7 ns/pF) CL + 6915 ns tPHL 5.0 — 7.0 14
tPHL, tPLH = (0.66 ns/pF) CL + 2967 ns 10 — 3.0 6.0
tPHL, tPLH = (0.5 ns/pF) CL + 2175 ns 15 — 2.2 4.5
Reset to Qn tPHL ns
tPHL = (1.7 ns/pF) CL + 1415 ns 5.0 — 1500 3000
tPHL = (0.66 ns/pF) CL + 567 ns 10 — 600 1200
tPHL = (0.5 ns/pF) CL + 425 ns 15 — 450 900
Clock Pulse Width tWH 5.0 600 300 — ns
10 200 100 —
15 170 85 —
Clock Pulse Frequency fcl 5.0 — 1.2 0.4 MHz
(50% Duty Cycle) 10 — 3.0 1.5
15 — 5.0 2.0
Clock Rise and Fall Time tTLH, 5.0 —
tTHL 10 No Limit
15
Reset Pulse Width tWH 5.0 1000 500 — ns
10 400 200 —
15 300 150 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must SET 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and RESET 2 15 MONO IN
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. IN 1 3 14 OSC INH
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. OUT 1 4 13 DECODE
OUT 2 5 12 D
8–BYPASS 6 11 C
CLOCK INH 7 10 B
VSS 8 9 A

MC14536B MOTOROLA CMOS LOGIC DATA

6–356
 PIN DESCRIPTIONS
INPUTS
SET (Pin 1) — A high on Set asynchronously forces
Decode Out to a high level. This is accomplished by setting
an output conditioning latch to a high level while at the same
time resetting the 24 flip–flop stages. After Set goes low
(inactive), the occurrence of the first negative clock transition
on IN1 causes Decode Out to go low. The counter’s flip–flop
stages begin counting on the second negative clock transi-
tion of IN1. When Set is high, the on–chip RC oscillator is
disabled. This allows for very low–power standby operation.
RESET (Pin 2) — A high on Reset asynchronously forces
Decode Out to a low level; all 24 flip–flop stages are also
reset to a low level. Like the Set input, Reset disables the
on–chip RC oscillator for standby operation.
IN1 (Pin 3) — The device’s internal counters advance on
the negative–going edge of this input. IN1 may be used as an
external clock input or used in conjunction with OUT 1 and
OUT 2 to form an RC oscillator. When an external clock is
used, both OUT 1 and OUT 2 may be left unconnected or
used to drive 1 LSTTL or several CMOS loads.
8–BYPASS (Pin 6) — A high on this input causes the first
8 flip–flop stages to be bypassed. This device essentially be-
comes a 16–stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7) — A high on this input discon-
nects the first counter stage from the clocking source. This
holds the present count and inhibits further counting. How-
ever, the clocking source may continue to run. Therefore,
when Clock Inhibit is brought low, no oscillator start–up time
is required. When Clock Inhibit is low, the counter will start
counting on the occurrence of the first negative edge of the
clocking source at IN1.
MOTOROLA CMOS LOGIC DATA
OSC INHIBIT (Pin 14) — A high level on this pin stops the
RC oscillator which allows for very low–power standby op-
eration. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONO–IN (Pin 15) — Used as the timing pin for the on–
chip monostable multivibrator. If the Mono–In input is con-
nected to V SS , the monostable circuit is disabled, and
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between Mono–In and V DD. This resistor and the device’s in-
ternal capacitance will determine the minimum output pulse
widths. With the addition of an external capacitor to V SS, the
pulse width range may be extended. For reliable operation
the resistor value should be limited to the range of 5 kΩ to
100 kΩ and the capacitor value should be limited to a maxi-
mum of 1000 pf. (See figures 3, 4, 5, and 10).
A, B, C, D (Pins 9, 10, 11, 12) — These inputs select the
flip–flop stage to be connected to Decode Out. (See the truth
tables.)
OUTPUTS
OUT1, OUT2 (Pin 4, 5) — Outputs used in conjunction with
IN1 to form an RC oscillator. These outputs are buffered and
may be used for 20 frequency division of an external clock.
DECODE OUT (Pin 13) — Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flip–flop stages
into three 8–stage sections to facilitate a fast test sequence.
The test mode is enabled when 8–Bypass, Set and Reset
are at a high level. (See Figure 8.)
MC14536B
6–357
 TRUTH TABLES

Input Input
Stage Selected Stage Selected
8–Bypass D C B A for Decode Out 8–Bypass D C B A for Decode Out

0 0 0 0 0 9 1 0 0 0 0 1
0 0 0 0 1 10 1 0 0 0 1 2
0 0 0 1 0 11 1 0 0 1 0 3
0 0 0 1 1 12 1 0 0 1 1 4
0 0 1 0 0 13 1 0 1 0 0 5
0 0 1 0 1 14 1 0 1 0 1 6
0 0 1 1 0 15 1 0 1 1 0 7
0 0 1 1 1 16 1 0 1 1 1 8
0 1 0 0 0 17 1 1 0 0 0 9
0 1 0 0 1 18 1 1 0 0 1 10
0 1 0 1 0 19 1 1 0 1 0 11
0 1 0 1 1 20 1 1 0 1 1 12
0 1 1 0 0 21 1 1 1 0 0 13
0 1 1 0 1 22 1 1 1 0 1 14
0 1 1 1 0 23 1 1 1 1 0 15
0 1 1 1 1 24 1 1 1 1 1 16

FUNCTION TABLE

Clock OSC Decode

In1 Set Reset Inh Inh Out 1 Out 2 Out
0 0 0 0 No
Change
0 0 0 0 Advance to
next state
X 1 0 0 0 0 1 1
X 0 1 0 0 0 1 0
X 0 0 1 0 — — No
Change
X 0 0 0 1 0 1 No
Change
0 0 0 0 X 0 1 No
Change
1 0 0 0 Advance to
next state
X = Don’t Care

MC14536B MOTOROLA CMOS LOGIC DATA

6–358
 RESET
2 8–BYPASS
6

MOTOROLA CMOS LOGIC DATA

OSC INHIBIT
14

3 STAGES
STAGES STAGES
T 1 8 T 9 10 THRU 16 17 18 THRU 24
2 THRU 7 15
IN1 23
4 OUT 2 5
OUT 1 A 9
S B 10
C C 11 DECODER
Q D 12
LOGIC DIAGRAM

En R

SET DECODER
1 OUT
7 13
CLOCK
INHIBIT

15 VDD = PIN 16
MONO–IN VSS = PIN 8

MC14536B
6–359
 TYPICAL RC OSCILLATOR CHARACTERISTICS
(For Circuit Diagram See Figure 11 In Application)

8.0 100
VDD = 15 V VDD = 10 V
50
f AS A FUNCTION

f, OSCILLATOR FREQUENCY (kHz)

4.0
FREQUENCY DEVIATION (%)

20 OF RTC
(C = 1000 pF)
0 10
(RS ≈ 2RTC)
10 V 5.0
– 4.0
2.0 f AS A FUNCTION
OF C
– 8.0 1.0 (RTC = 56 kΩ)
5.0 V
0.5 (RS = 120 k)
– 12
RTC = 56 kΩ, RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C 0.2
C = 1000 pF RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
– 16 0.1
– 55 – 25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 M
* Device Only. RTC, RESISTANCE (OHMS)
TA, AMBIENT TEMPERATURE (°C)*
0.0001 0.001 0.01 0.1
C, CAPACITANCE (µF)
Figure 1. RC Oscillator Stability Figure 2. RC Oscillator Frequency as a
Function of RTC and C

MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 10 In Application)
100 100
FORMULA FOR CALCULATING tW IN FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS: MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX • CX 0.85 tW = 0.00247 RX • CX 0.85
t W, PULSE WIDTH ( µs)

t W, PULSE WIDTH ( µs)

WHERE R IS IN kΩ, CX IN pF. WHERE R IS IN kΩ, CX IN pF.

10 10

RX = 100 kΩ RX = 100 kΩ
50 kΩ 50 kΩ
1.0 10 kΩ 1.0
5 kΩ 10 kΩ
TA = 25°C 5 kΩ TA = 25°C
VDD = 5 V VDD = 10 V
0.1 0.1
1.0 10 100 1000 1.0 10 100 1000
CX, EXTERNAL CAPACITANCE (pF) CX, EXTERNAL CAPACITANCE (pF)

Figure 3. Typical CX versus Pulse Width Figure 4. Typical CX versus Pulse Width
@ VDD = 5.0 V @ VDD = 10 V

100
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX • CX 0.85
WHERE R IS IN kΩ, CX IN pF.
t W, PULSE WIDTH ( µs)

10

RX = 100 kΩ
50 kΩ
1.0
10 kΩ
5 kΩ TA = 25°C
VDD = 15 V
0.1
1.0 10 100 1000
CX, EXTERNAL CAPACITANCE (pF)
Figure 5. Typical CX versus Pulse Width
@ VDD = 15 V

MC14536B MOTOROLA CMOS LOGIC DATA

6–360
 VDD

0.01 µF
500 µF ID
CERAMIC

SET 20 ns 20 ns
RESET OUT 1
8–BYPASS CL VDD
PULSE IN1 50%
IN1
GENERATOR tWL tWH
C INH SET
MONO IN OUT OUT 1
RESET 90%
OSC INH 2 OUT 50%
CL 8–BYPASS 10%
A PULSE
IN1 tPLH tPHL
B GENERATOR
C INH tTLH tTHL
C DECODE MONO IN OUT
D OUT CL 2
OSC INH
VSS A
B
C DECODE
20 ns 20 ns D OUT CL
90% VSS
50%
10%
50%
DUTY CYCLE

Figure 6. Power Dissipation Test Figure 7. Switching Time Test Circuit and Waveforms
Circuit and Waveform

FUNCTIONAL TEST SEQUENCE VDD

Test function (Figure 8) has been included for the reduc- SET
tion of test time required to exercise all 24 counter stages. PULSE RESET OUT 1
This test function divides the counter into three 8–stage GENERATOR 8–BYPASS
IN1
sections and 255 counts are loaded in each of the 8–stage
C INH
sections in parallel. All flip–flops are now at a “1”. The count- MONO IN OUT
er is now returned to the normal 24–stages in series configu- OSC INH 2
ration. One more pulse is entered into In1 which will cause A
the counter to ripple from an all “1” state to an all “0” state. B
C DECODE
D OUT

VSS

Figure 8. Functional Test Circuit

FUNCTIONAL TEST SEQUENCE

Inputs Outputs Comments
Decade Out
In1 Set Reset 8–Bypass Q1 thru Q24 g are in Reset mode.
All 24 stages
1 0 1 1 0
1 1 1 1 0 Counter is in three 8 stage sections in parallel mode.
0 1 1 1 0 First “1” to “0” transition of clock.
1
0
— 1 1 1 255 “1” to “0” transitions are clocked in the counter.
—
—
0 1 1 1 1 The 255 “1” to “0” transition.
0 0 0 0 1 Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1 0 0 0 1 In1 Switches to a “1”.
0 0 0 0 0 Counter Ripples from an all “1” state to an all “0” state.

MOTOROLA CMOS LOGIC DATA MC14536B

6–361
 +V

16
6 VDD
8–BYPASS
9 4
A OUT 1
10 B
11 C
12
D
2 OUT 2 5
RESET
14
OSC INH
15
MONO–IN
PULSE 1
SET
GEN. 7
CLOCK INH
3 DECODE OUT 13
PULSE IN1
VSS
GEN.
CLOCK 8

IN1

SET

CLOCK INH

DECODE OUT

POWER UP

NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.
On the rising edge of a Set pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because Clock Inh is held high, the clock source on
the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low
on the first negative clock transition. The output returns high depending on the 8–Bypass,
A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = the
number of stages selected from the truth table) is obtainable at Decode Out. A 20–divided
output of IN1 can be obtained at OUT1 and OUT2.

Figure 9. Time Interval Configuration Using an External Clock, Set,

and Clock Inhibit Functions
(Divide–by–2 Configured)

MC14536B MOTOROLA CMOS LOGIC DATA

6–362
 +V

16
6 VDD
8–BYPASS
RX 9 4
A OUT 1
10 B
11 C
12
D
PULSE 2 5
RESET OUT 2
GEN. 1
SET
7
CLOCK INH
15
MONO–IN
14
CLOCK INH
3 DECODE OUT 13
CLOCK IN1
VSS
CX 8

IN1

RESET

*tw ≈ .00247 • RX • CX0.85

DECODE OUT tw in µsec

RX in kΩ
CX in pF
*tw
POWER UP

NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset
input low enables the chip’s internal counters. After Reset goes low, the 2n/2 negative transition of the clock input causes
Decode Out to go high. Since the Mono–In input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock
period) intervals where n = the number of stages selected from the truth table.

Figure 10. Time Interval Configuration Using an External Clock, Reset,

and Output Monostable to Achieve a Pulse Output
(Divide–by–4 Configured)

MOTOROLA CMOS LOGIC DATA MC14536B

6–363
 +V

RS
16
6 VDD
8–BYPASS
9 4
A OUT 1
10 B C
11 C
RTC
12
D
PULSE 2 5
RESET OUT 2
GEN. 14
SET
15
CLOCK INH
1
MONO–IN
7
CLOCK INH
3 DECODE OUT 13
IN1
VSS
8

RESET

OUT 1

OUT 2

fosc ^ 2.3 R1tc C

DECODE OUT
Rs ≥ Rtc
F = Hz
tw R = Ohms
POWER UP
C = FARADS

NOTE: This circuit is designed to use the on–chip oscillation function. The oscillator frequency is deter-
mined by the external R and C components. When power is first applied to the device, Decode Out
initializes to a high state. Because this output is tied directly to the Osc–Inh input, the oscillator is
disabled. This puts the device in a low–current standby condition. The rising edge of the Reset pulse
will cause the output to go low. This in turn causes Osc–Inh to go low. However, while Reset is high,
the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains low
for 2n/2 of the oscillator’s period. After the part times out, the output again goes high.

Figure 11. Time Interval Configuration Using On–Chip RC Oscillator and

Reset Input to Initiate Time Interval
(Divide–by–2 Configured)

MC14536B MOTOROLA CMOS LOGIC DATA

6–364
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14538B

Dual Precision
Retriggerable/Resettable L SUFFIX
CERAMIC
Monostable Multivibrator CASE 620

The MC14538B is a dual, retriggerable, resettable monostable multivibra-

tor. It may be triggered from either edge of an input pulse, and produces an P SUFFIX
accurate output pulse over a wide range of widths, the duration and accuracy PLASTIC
of which are determined by the external timing components, CX and RX. CASE 648
• Unlimited Rise and Fall Time Allowed on the A Trigger Input
• Pulse Width Range = 10 µs to 10 s
• Latched Trigger Inputs DW SUFFIX
SOIC
• Separate Latched Reset Inputs CASE 751G
• 3.0 Vdc to 18 Vdc Operational Limits
• Triggerable from Positive (A Input) or Negative–Going Edge (B–Input) ORDERING INFORMATION
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14XXXBCP Plastic
Schottky TTL Load Over the Rated Temperature Range MC14XXXBCL Ceramic
• Pin–for–pin Compatible with MC14528B and CD4528B (CD4098) *MC14XXXBDW SOIC
• Use the MC54/74HC4538A for Pulse Widths Less Than 10 µs with TA = – 55° to 125°C for all packages.
Supplies Up to 6 V.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit
CX

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V RX
VDD

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
1 2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA A
per Pin 4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Q1 6
PD Power Dissipation, per Package† 500 mW B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
5 Q1 7
Tstg Storage Temperature – 65 to + 150 _C RESET

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C 3

CX RX
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C VDD
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
15 14
A
ONE–SHOT SELECTION GUIDE 12
Q2 10
B
11 Q2 9
100 ns 1 µs 10 µs 100 µs 1 ms 10 ms 100 ms 1s 10 s
RESET
MC14528B
MC14536B 23 HR 13
MC14538B RX AND CX ARE EXTERNAL COMPONENTS.
MC14541B 5 MIN. VDD = PIN 16
MC4538A* VSS = PIN 8, PIN 1, PIN 15

*LIMITED OPERATING VOLTAGE (2 – 6 V) * Consult factory for possible “D” suffix SOIC
Case 751B.
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE

MOTOROLA CMOS LOGIC DATA MC14538B

6–365
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current, Pin 2 or 14 Iin 15 — ± 0.05 — ± 0.00001 ± 0.05 — ± 0.5 µAdc
Input Current, Other Inputs Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance, Pin 2 or 14 Cin — — — — 25 — — — pF
Input Capacitance, Other Inputs Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
Q = Low, Q = High 15 — 20 — 0.015 20 — 600
Quiescent Current, Active State IDD 5.0 — 2.0 — 0.04 0.20 — 2.0 mAdc
(Both) (Per Package) 10 — 2.0 — 0.08 0.45 — 2.0
Q = High, Q = Low 15 — 2.0 — 0.13 0.70 — 2.0
**Total Supply Current at an IT 5.0 IT = (3.5 x 10–2) RXCXf + 4CXf + 1 x 10–5 CLf µAdc
external load capacitance (CL) and 10 IT = (8.0 x 10–2) RXCXf + 9CXf + 2 x 10–5 CLf
at external timing network (RX, CX) IT = (1.25 x 10–1) RXCXf + 12CXf + 3 x 10–5 CLf
where: IT in µA (one monostable switching only),
where: CX in µF, CL in pF, RX in k ohms, and
where: f in Hz is the input frequency.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14538B MOTOROLA CMOS LOGIC DATA

6–366
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

VDD
All Types
Characteristic Symbol Vdc Min Typ # Max Unit
Output Rise Time tTLH ns
tTLH = (1.35 ns/pF) CL + 33 ns 5.0 — 100 200
tTLH = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTLH = (0.40 ns/pF) CL + 20 ns 15 — 40 80
Output Fall Time tTHL ns
tTHL = (1.35 ns/pF) CL + 33 ns 5.0 — 100 200
tTHL = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTHL = (0.40 ns/pF) CL + 20 ns 15 — 40 80
Propagation Delay Time tPLH, ns
A or B to Q or Q tPHL
tPLH, tPHL = (0.90 ns/pF) CL + 255 ns 5.0 — 300 600
tPLH, tPHL = (0.36 ns/pF) CL + 132 ns 10 — 150 300
tPLH, tPHL = (0.26 ns/pF) CL + 87 ns 15 — 100 220
Reset to Q or Q ns
tPLH, tPHL = (0.90 ns/pF) CL + 205 ns 5.0 — 250 500
tPLH, tPHL = (0.36 ns/pF) CL + 107 ns 10 — 125 250
tPLH, tPHL = (0.26 ns/pF) CL + 82 ns 15 — 95 190
Input Rise and Fall Times tr, tf 5 — — 15 µs
Reset 10 — — 5
15 — — 4
B Input 5 — 300 1.0 ms
10 — 1.2 0.1
15 — 0.4 0.05
A Input 5 —
10 No Limit
15
Input Pulse Width tWH, 5.0 170 85 — ns
A, B, or Reset tWL 10 90 45 —
15 80 40 —
Retrigger Time trr 5.0 0 — — ns
10 0 — —
15 0 — —
Output Pulse Width — Q or Q T µs
Refer to Figures 8 and 9
CX = 0.002 µF, RX = 100 kΩ 5.0 198 210 230
10 200 212 232
15 202 214 234
CX = 0.1 µF, RX = 100 kΩ 5.0 9.3 9.86 10.5 ms
10 9.4 10 10.6
15 9.5 10.14 10.7
CX = 10 µF, RX = 100 kΩ 5.0 0.91 0.965 1.03 s
10 0.92 0.98 1.04
15 0.93 0.99 1.06
Pulse Width Match between circuits in 100 5.0 — ± 1.0 ± 5.0 %
the same package. [(T1 – T2)/T1] 10 — ± 1.0 ± 5.0
CX = 0.1 µF, RX = 100 kΩ 15 — ± 1.0 ± 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
OPERATING CONDITIONS
External Timing Resistance RX — 5.0 — kΩ
External Timing Capacitance CX — 0 — No µF
Limit†
* The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board layout
and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 MΩ..
†If CX > 15 µF, use discharge protection diode per Fig. 11.

MOTOROLA CMOS LOGIC DATA MC14538B

6–367
 VDD VDD

P1
RX
2 (14) ENABLE
+ +
C1 C2
CX Vref1 – Vref2 – R Q 6 (10)
ENABLE OUTPUT
1 (15) LATCH
N1 S Q 7 (9)

VSS CONTROL
4 (12)
A
5 (11)
B
QR QR NOTE: Pins 1, 8 and 15 must
3 (13)
RESET S RESET LATCH R be externally grounded

Figure 1. Logic Diagram

(1/2 of DevIce Shown)

VDD

0.1 µF
500 pF ID
CERAMIC

RX RX′
VSS CX CX′
VSS
Vin CX/RX
A

B Q
CL 20 ns 20 ns
RESET Q VDD
CL 90%
A′ Q′
CL 10%
B′ Q′ Vin 0V
CL
RESET′

VSS

Figure 2. Power Dissipation Test Circuit and Waveforms

VDD
INPUT CONNECTIONS
RX RX′ * CL = 50 pF Characteristics Reset A B
CX CX′ tPLH, tPHL, tTLH, tTHL, VDD PG1 VDD
VSS VSS T, tWH, tWL
CX/RX tPLH, tPHL, tTLH, tTHL, VDD VSS PG2
PULSE A
T, tWH, tWL
GENERATOR B Q tPLH(R), tPHL(R), PG3 PG1 PG2
CL tWH, tWL
PULSE RESET Q
GENERATOR CL
A′ Q′ * Includes capacitance of probes, PG1 =
CL wiring, and fixture parasitic.
PULSE B′ Q′
CL NOTE: Switching test waveforms PG2 =
GENERATOR RESET′ for PG1, PG2, PG3 are shown
VSS In Figure 4. PG3 =

Figure 3. Switching Test Circuit

MC14538B MOTOROLA CMOS LOGIC DATA

6–368
 90%
50% 10% 50% VDD
A
tWH tTLH tTHL
tTHL tTLH
B
50% 90% VDD
10%
tWL
tTHL tPHL
RESET
90% VDD
50%
10%
tWL
tPLH tTHL tTLH
T
tPLH tPHL trr
90%
50% 50% 50% 10% 50%
Q
tTLH tTHL
tPHL tPHL tPLH
Q 90%
50% 50% 50% 50%
10%

Figure 4. Switching Test Waveforms

WITH RESPECT TO VALUE AT VDD = 10 V (%)

RELATIVE FREQUENCY OF OCCURRENCE

TA = 25°C
RX = 100 kΩ 0% POINT PULSE WIDTH NORMALIZED PULSE WIDTH CHANGE
RX = 100 kΩ
CX = 0.1 µF VDD = 5.0 V, T = 9.8 ms CX = 0.1 µF
1.0 VDD = 10 V, T = 10 ms 2
VDD = 15 V, T = 10.2 ms
0.8 1
0
0.6 1

0.4 2

0.2

0
–4 –2 0 2 4 5 6 7 8 9 10 11 12 13 14 15
T, OUTPUT PULSE WIDTH (%) VDD, SUPPLY VOLTAGE (VOLTS)

Figure 5. Typical Normalized Distribution Figure 6. Typical Pulse Width Variation as

of Units for Output Pulse Width a Function of Supply Voltage VDD

1000 FUNCTION TABLE

Inputs Outputs
TOTAL SUPPLY CURRENT ( µA)

RX = 100 kΩ, CL = 50 pF
ONE MONOSTABLE SWITCHING ONLY Reset A B Q Q
100
H H
H L
VDD = 15 V
10 5.0 V H L Not Triggered
10 V H H Not Triggered
H L, H, H Not Triggered
H L L, H, Not Triggered
1.0
L X X L H
X X Not Triggered
0.1
0.001 0.1 1.0 10 100
OUTPUT DUTY CYCLE (%)

Figure 7. Typical Total Supply Current

versus Output Duty Cycle

MOTOROLA CMOS LOGIC DATA MC14538B

6–369
WITH RESPECT TO 25°C VALUE AT VDD = 10 V (%)

WITH RESPECT TO 25°C VALUE AT VDD = 10 V (%)

RX = 100 kΩ
CX = .002 µF
RX = 100 kΩ 3.0
TYPICAL NORMALIZED ERROR

TYPICAL NORMALIZED ERROR

CX = 0.1 µF VDD = 15 V
2 2.0
1 1.0 VDD = 15 V
VDD = 10 V
0 0
VDD = 5 V VDD = 10 V
–1 – 1.0
–2 – 2.0
VDD = 5.0 V
– 3.0

– 60 – 40 – 20 0 20 40 60 80 100 120 140 – 60 – 40 – 20 0 20 40 60 80 100 120 140

TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 8. Typical Error of Pulse Width Figure 9. Typical Error of Pulse Width
Equation versus Temperature Equation versus Temperature

THEORY OF OPERATION

1 3 4

A
2

RESET

Vref 2 Vref 2 Vref 2 Vref 2

CX/RX Vref 1 Vref 1 Vref 1 Vref 1

T T T

1 Positive edge trigger 4 Positive edge re–trigger (pulse lengthening)

2 Negative edge trigger 5 Positive edge re–trigger (pulse lengthening)
3 Positive edge trigger

Figure 10. Timing Operation

TRIGGER OPERATION comparator C2 turns on. With transistor N1 off, the capacitor
CX begins to charge through the timing resistor, RX, toward
The block diagram of the MC14538B is shown in Figure 1, V DD. When the voltage across CX equals Vref 2, comparator
with circuit operation following. C2 changes state, causing the output latch to reset (Q goes
As shown in Figure 1 and 10, before an input trigger low) while at the same time disabling comparator C2 ➁. This
occurs, the monostable is in the quiescent state with the Q ends at the timing cycle with the monostable in the quiescent
output low, and the timing capacitor CX completely charged state, waiting for the next trigger.
to V DD. When the trigger input A goes from V SS to V DD In the quiescent state, CX is fully charged to VDD causing
(while inputs B and Reset are held to V DD) a valid trigger is the current through resistor RX to be zero. Both comparators
recognized, which turns on comparator C1 and N–channel are “off” with total device current due only to reverse junction
transistor N1 ➀. At the same time the output latch is set. With leakages. An added feature of the MC14538B is that the out-
transistor N1 on, the capacitor CX rapidly discharges toward put latch is set via the input trigger without regard to the
V SS until V ref1 is reached. At this point the output of capacitor voltage. Thus, propagation delay from trigger to Q
comparator C1 changes state and transistor N1 turns off. is independent of the value of CX, RX, or the duty cycle of the
Comparator C1 then turns off while at the same time input waveform.

MC14538B MOTOROLA CMOS LOGIC DATA

6–370
RETRIGGER OPERATION
The MC14538B is retriggered if a valid trigger occurs ➂ fol-
lowed by another valid trigger ➃ before the Q output has
returned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at pin 2 or 14 has begun to rise from
Vref 1, but has not yet reached Vref 2, will cause an increase
in output pulse width T. When a valid retrigger is initiated ➃,
the voltage at C X /R X will again drop to V ref 1 before
progressing along the RC charging curve toward VDD. The Q
output will remain high until time T, after the last valid retrig-
ger.
RESET OPERATION
The MC14538B may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on Reset sets the reset latch and causes the capacitor to be
fast charged to VDD by turning on transistor P1 ➄. When the
voltage on the capacitor reaches Vref 2, the reset latch will
clear, and will then be ready to accept another pulse. It the
Reset input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change. Since the Q output is reset when an input low level is
detected on the Reset input, the output pulse T can be made
significantly shorter than the minimum pulse width specifi-
cation.
POWER–DOWN CONSIDERATIONS
Large capacitance values can cause problems due to the
large amount of energy stored. When a system containing
the MC14538B is powered down, the capacitor voltage may
discharge from V DD through the standard protection diodes
at pin 2 or 14. Current through the protection diodes should
be limited to 10 mA and therefore the discharge time of the
V DD supply must not be faster than (V DD). (C) / (10 mA). For
example, if V DD = 10 V and CX = 10 µF, the V DD supply
should discharge no faster than (10 V) x (10 µF) / (10 mA) =
10 ms. This is normally not a problem since power supplies
are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of V DD to zero volts occurs,
the MC14538B can sustain damage. To avoid this possibility
use an external clamping diode, DX, connected as shown in
Fig. 11.

Dx
PIN ASSIGNMENT
Cx Rx VDD
VSS VSS 1 16 VDD
CX/RXA 2 15 VSS
VDD
RESET A 3 14 CX/RXB
Q AA 4 13 RESET B
BA 5 12 AB
Q
QA 6 11 BB
RESET
QA 7 10 QB
VSS 8 9 QB

Figure 11. Use of a Diode to Limit

Power Down Current Surge

MOTOROLA CMOS LOGIC DATA MC14538B

6–371
 TYPICAL APPLICATIONS

CX RX

CX RX
VDD

VDD RISING–EDGE Q
A
TRIGGER
RISING–EDGE Q B
A Q
TRIGGER
B Q
B = VDD RESET = VDD

RESET = VDD CX RX

CX RX VDD

A = VSS VDD A Q

B Q
Q FALLING–EDGE
TRIGGER
B Q
FALLING–EDGE RESET = VDD
TRIGGER
RESET = VDD

Figure 12. Retriggerable Figure 13. Non–Retriggerable

Monostables Circuitry Monostables Circuitry

NC

Q NC
A
B Q NC
CD

VDD
VDD

Figure 14. Connection of Unused Sections

MC14538B MOTOROLA CMOS LOGIC DATA

6–372
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14539B
Dual 4-Channel Data
Selector/Multiplexer L SUFFIX
CERAMIC
The MC14539B data selector/multiplexer is constructed with MOS CASE 620
P–channel and N–channel enhancement mode devices in a single
monolithic structure. The circuit consists of two sections of four inputs each.
One input from each section is selected by the address inputs A and B. A P SUFFIX
“high” on the Strobe input will cause the output to remain “low”. PLASTIC
This device finds primary application in signal multiplexing functions. It CASE 648
permits multiplexing from N–lines to I–line, and can also perform parallel–to–
serial conversion. The Strobe input allows cascading of n–lines to n–lines.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
SOIC
• Capable of Driving Two Low–Power TTL Loads or One Low–Power CASE 751B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCP Plastic
Symbol Parameter Value Unit MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBD SOIC
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Iin, Iout

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input or Output Current (DC or Transient),

ÎÎÎÎÎÎ
ÎÎÎ
per Pin
± 10 mA

BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C 14 A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
2 B Z 7
TL Lead Temperature (8–Second Soldering) 260 _C
1 ST
* Maximum Ratings are those values beyond which damage to the device may occur. 6 X0
†Temperature Derating:
5 X1
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 4 X2
3 X3
TRUTH TABLE
Address A
Inputs Data Inputs B W 9
X3 X2 X1 X0 Outputs 15 ST′
B A Y3 Y2 Y1 Y0 ST, ST′ Z, W 10 Y0
11 Y1
X X X X X X 1 0
12 Y2
0 0 X X X 0 0 0
13 Y3
0 0 X X X 1 0 1
0 1 X X 0 X 0 0 VDD = PIN 16
0 1 X X 1 X 0 1 VSS = PIN 8
1 0 X 0 X X 0 0
1 0 X 1 X X 0 1
1 1 0 X X X 0 0
1 1 1 X X X 0 1
X = Don’t Care

MOTOROLA CMOS LOGIC DATA MC14539B

6–373
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.85 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.70 µA/kHz) f + IDD
Per Package) 15 IT = (2.60 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14539B MOTOROLA CMOS LOGIC DATA

6–374
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
X, Y Input to Output tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 125 ns 5.0 — 210 420
tPLH, tPHL = (0.66 ns/pF) CL + 57 ns 10 — 90 180
tPLH, tPHL = (0.55 ns/pF) CL + 45 ns 15 — 70 140
A Input to Output tPLH ns
tPLH = (1.7 ns/pF) CL + 140 ns 5.0 — 225 450
tPLH = (0.66 ns/pF) CL + 77 ns 10 — 110 220
tPLH = (0.5 ns/pF) CL + 60 ns 15 — 85 170
tPHL = (1.7 ns/pF) CL + 160 ns tPHL 5.0 — 245 490 ns
tPHL = (0.66 ns/pF) CL + 82 ns 10 — 115 230
tPHL = (0.5 ns/pF) CL + 65 ns 15 — 90 180
Strobe Input to Output tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 60 ns tPHL 5.0 — 145 290
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 — 75 150
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns 15 — 60 120
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD

20 ns 20 ns
A
B
PULSE ST Z
GENERATOR X0 INPUT
X1 CL
X2
X3
OUTPUT
ST′
(TEST 1) tTLH tTHL
Y0 tPLH tPHL
Y1 W OUTPUT
Y2 (TESTS 2 AND 3)
Y3
tTHL tTLH
VSS tPHL tPLH

INPUT CONNECTIONS FOR tTLH, tTHL, tPHL, tPLH

Test Strobe A X0
1 Gnd Gnd P.G.
2 P.G. Gnd VDD
3 Gnd P.G. VDD

Figure 1. AC Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14539B

6–375
 VDD

0.01 µF
500 µF ID CERAMIC

A
B
ST Z 20 ns 20 ns
PULSE X0 VDD
GENERATOR 90%
X1 50%
X2 Vin 10% VSS
X3 CL
ST′ 50% DUTY CYCLE
Y0
Y1 W
Y2
Y3 CL

VSS

Figure 2. Power Dissipation Test Circuit and Waveform

LOGIC DIAGRAM
2
B
14
A

6 ST
X0 1 PIN ASSIGNMENT
ST 1 16 VDD
5
X1 7 B 2 15 ST′
Z
X3 3 14 A
4
X2 X2 4 13 Y3
X1 5 12 Y2
3
X3 X0 6 11 Y1
Z 7 10 Y0

10 VSS 8 9 W
Y0

11
Y1
9
W
12
Y2

15
13 ST′
Y3

MC14539B MOTOROLA CMOS LOGIC DATA

6–376
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14541B
Programmable Timer
The MC14541B programmable timer consists of a 16–stage binary L SUFFIX
CERAMIC
counter, an integrated oscillator for use with an external capacitor and two
CASE 620
resistors, an automatic power–on reset circuit, and output control logic.
Timing is initialized by turning on power, whereupon the power–on reset is
enabled and initializes the counter, within the specified VDD range. With the
power already on, an external reset pulse can be applied. Upon release of P SUFFIX
the initial reset command, the oscillator will oscillate with a frequency PLASTIC
CASE 648
determined by the external RC network. The 16–stage counter divides the
oscillator frequency (fosc) with the nth stage frequency being fosc/2n.
• Available Outputs 28, 210, 213 or 216
D SUFFIX
• Increments on Positive Edge Clock Transitions SOIC
• Built–in Low Power RC Oscillator (± 2% accuracy over temperature CASE 751B
range and ± 20% supply and ± 3% over processing at < 10 kHz)
• Oscillator May Be Bypassed if External Clock Is Available (Apply ORDERING INFORMATION
external clock to Pin 3) MC14XXXBCP Plastic
• External Master Reset Totally Independent of Automatic Reset MC14XXXBCL Ceramic
Operation MC14XXXBD SOIC
• Operates as 2n Frequency Divider or Single Transition Timer TA = – 55° to 125°C for all packages.
• Q/Q Select Provides Output Logic Level Flexibility
• Reset (auto or master) Disables Oscillator During Resetting to Provide
No Active Power Dissipation PIN ASSIGNMENT
• Clock Conditioning Circuit Permits Operation with Very Slow Clock Rise
and Fall Times Rtc 1 14 VDD
• Automatic Reset Initializes All Counters On Power Up Ctc 2 13 B
• Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset RS 3 12 A
Disabled (Pin 5 = VDD)
= 8.5 Vdc to 18 Vdc with Auto Reset NC 4 11 NC
Enabled (Pin 5 = VSS) AR 5 10 MODE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MR 6 9 Q/Q SEL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
VSS 7 8 Q

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V NC = NO CONNECTION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin Input Current (DC or Transient), per Pin ± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iout Output Current (DC or Transient), per Pin ± 45 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MOTOROLA CMOS LOGIC DATA MC14541B

6–377
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 7.96 — – 6.42 – 12.83 — – 4.49 —
(VOH = 9.5 Vdc) 10 – 4.19 — – 3.38 – 6.75 — – 2.37 —
(VOH = 13.5 Vdc) 15 – 16.3 — – 13.2 – 26.33 — – 9.24 —
(VOL = 0.4 Vdc) Sink IOL 5.0 1.93 — 1.56 3.12 — 1.09 — mAdc
(VOL = 0.5 Vdc) 10 4.96 — 4.0 8.0 — 2.8 —
(VOL = 1.5 Vdc) 15 19.3 — 15.6 31.2 — 10.9 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Pin 5 is High) 10 — 10 — 0.010 10 — 300
Auto Reset Disabled 15 — 20 — 0.015 20 — 600
Auto Reset Quiescent Current IDDR 10 — 250 — 30 250 — 1500 µAdc
(Pin 5 is low) 15 — 500 — 82 500 — 2000
Supply Current**† ID 5.0 ID = (0.4 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent) 10 ID = (0.8 µA/kHz) f + IDD
15 ID = (1.2 µA/kHz) f + IDD
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†When using the on chip oscillator the total supply current (in µAdc) becomes: IT = ID + 2 Ctc VDD f x 10–3 where ID is in µA, Ctc is in pF,
VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power–on with automatic reset enabled is typically 50 µA @ VDD = 10 Vdc.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14541B MOTOROLA CMOS LOGIC DATA

6–378
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay, Clock to Q (28 Output) tPLH µs
tPLH, tPHL = (1.7 ns/pF) CL + 3415 ns tPHL 5.0 — 3.5 10.5
tPLH, tPHL = (0.66 ns/pF) CL + 1217 ns 10 — 1.25 3.8
tPLH, tPHL = (0.5 ns/pF) CL + 875 ns 15 — 0.9 2.9
Propagation Delay, Clock to Q (216 Output) tPHL µs
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns tPLH 5.0 — 6.0 18
tPHL, tPLH = (0.66 ns/pF) CL + 3467 ns 10 — 3.5 10
tPHL, tPLH = (0.5 ns/pF) CL + 2475 ns 15 — 2.5 7.5
Clock Pulse Width tWH(cl) 5.0 900 300 — ns
10 300 100 —
15 225 85 —
Clock Pulse Frequency (50% Duty Cycle) fcl 5.0 — 1.5 0.75 MHz
10 — 4.0 2.0
15 — 6.0 3.0
MR Pulse Width tWH(R) 5.0 900 300 — ns
10 300 100 —
15 225 85 —
Master Reset Removal Time trem 5.0 420 210 — ns
10 200 100 —
15 200 100 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD VDD

PULSE PULSE
RS RS
GENERATOR GENERATOR
AR AR
Q/Q SELECT Q/Q SELECT
MODE Q MODE Q
A CL A CL
B B
MR MR

VSS VSS

(Rtc AND Ctc OUTPUTS ARE LEFT OPEN) 20 ns 20 ns

90% 50%
50%
20 ns 20 ns RS 10%
tPLH tPHL
90% 50%
10% 50% 90%
50%
50% Q 10%
DUTY CYCLE tTLH tTHL

Figure 1. Power Dissipation Test Circuit Figure 2. Switching Time Test Circuit
and Waveform and Waveforms

MOTOROLA CMOS LOGIC DATA MC14541B

6–379
 EXPANDED BLOCK DIAGRAM

A 12
B 13

1 OF 4
MUX
8 Q
Rtc 1 210 213 216
8–STAGE 8
Ctc 2 OSC C 2 C 8–STAGE
COUNTER
RS 3 RESET COUNTER
RESET RESET

AUTO RESET POWER–ON

5
RESET

6 10 9
MASTER RESET MODE Q/Q
SELECT
VDD = PIN 14
VSS = PIN 7

FREQUENCY SELECTION TABLE TRUTH TABLE

Number of State
Counter Stages Count
Pin 0 1
A B n 2n
Auto Reset, 5 Auto Reset Operating Auto Reset Disabled
0 0 13 8192
Master Reset, 6 Timer Operational Master Reset On
0 1 10 1024
Q / Q, 9 Output Initially Low Output Initially High
1 0 8 256 After Reset After Reset
1 1 16 65536 Mode, 10 Single Cycle Mode Recycle Mode

3
TO CLOCK
CIRCUIT

INTERNAL
RESET
2 1
Ctc

RS RTC

Figure 3. Oscillator Circuit Using RC Configuration

MC14541B MOTOROLA CMOS LOGIC DATA

6–380
 TYPICAL RC OSCILLATOR CHARACTERISTICS

8.0 100
VDD = 10 V
VDD = 15 V 50
4.0
f AS A FUNCTION

f, OSCILLATOR FREQUENCY (kHz)

20
FREQUENCY DEVIATION (%)

OF RTC
0 10 (C = 1000 pF)
(RS ≈ 2RTC)
10 V 5.0
– 4.0 f AS A FUNCTION
2.0 OF C
– 8.0 (RTC = 56 kΩ)
5.0 V 1.0
(RS = 120 kΩ)
0.5
– 12
RTC = 56 kΩ, RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C 0.2
C = 1000 pF RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
– 16 0.1
– 55 – 25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 m
TA, AMBIENT TEMPERATURE (°C) RTC, RESISTANCE (OHMS)
0.0001 0.001 0.01 0.1
Figure 4. RC Oscillator Stability C, CAPACITANCE (µF)

Figure 5. RC Oscillator Frequency as a

Function of Rtc and Ctc

OPERATING CHARACTERISTICS

With Auto Reset pin set to a “0” the counter circuit is initial- when B is “0”, normal counting is interrupted and the 9th
ized by turning on power. Or with power already on, the counter stage receives its clock directly from the oscillator
counter circuit is reset when the Master Reset pin is set to a (i.e., effectively outputting 28).
“1”. Both types of reset will result in synchronously resetting The Q/Q select output control pin provides for a choice of
all counter stages independent of counter state. Auto Reset output level. When the counter is in a reset condition and
pin when set to a “1” provides a low power operation. Q/Q select pin is set to a “0” the Q output is a “0”, corre-
The RC oscillator as shown in Figure 3 will oscillate with a spondingly when Q/Q select pin is set to a “1” the Q output is
frequency determined by the external RC network i.e., a “1”.

f=
1
2.3 RtcCtc
if (1 kHz v f v 100 kHz) When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with mode
pin “0” and after a reset condition the RS flip–flop (see Ex-
and RS ≈ 2 Rtc where RS ≥ 10 kΩ panded Block Diagram) resets, counting commences, and
The time select inputs (A and B) provide a two–bit address after 2n–1 counts the RS flip–flop sets which causes the out-
to output any one of four counter stages (28, 210, 213 and put to change state. Hence, after another 2n–1 counts the
216). The 2n counts as shown in the Frequency Selection output will not change. Thus, a Master Reset pulse must be
Table represents the Q output of the Nth stage of the counter. applied or a change in the mode pin level is required to reset
When A is “1”, 216 is selected for both states of B. However, the single cycle operation.

DIGITAL TIMER APPLICATION

Rtc When Master Reset (MR) receives a positive pulse, the in-
1 14 VDD ternal counters and latch are reset. The Q output goes high
Ctc and remains high until the selected (via A and B) number of
2 13 B
3 12 A
clock pulses are counted, the Q output then goes low and re-
RS mains low until another input pulse is received.
NC 4 11 N.C.
AR MODE
This “one shot” is fully retriggerable and as accurate as the
5 10 input frequency. An external clock can be used (pin 3 is the
MR Q/Q clock input, pins 1 and 2 are outputs) if additional accuracy is
6 9 VDD
INPUT needed.
7 8
OUTPUT Notice that a setup time equal to the desired pulse width
tMR output is required immediately following initial power up, dur-
ing which time Q output will be high.

t + tMR

MOTOROLA CMOS LOGIC DATA MC14541B

6–381
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14543B
BCD-to-Seven Segment
Latch/Decoder/Driver for L SUFFIX
CERAMIC
Liquid Crystals CASE 620

The MC14543B BCD–to–seven segment latch/decoder/driver is designed

for use with liquid crystal readouts, and is constructed with complementary
P SUFFIX
MOS (CMOS) enhancement mode devices. The circuit provides the PLASTIC
functions of a 4–bit storage latch and an 8421 BCD–to–seven segment CASE 648
decoder and driver. The device has the capability to invert the logic levels of
the output combination. The phase (Ph), blanking (BI), and latch disable (LD)
inputs are used to reverse the truth table phase, blank the display, and store
D SUFFIX
a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is
SOIC
applied to the Ph input of the circuit and the electrically common backplane CASE 751B
of the display. The outputs of the circuit are connected directly to the
segments of the LC readout. For other types of readouts, such as ORDERING INFORMATION
light–emitting diode (LED), incandescent, gas discharge, and fluorescent
MC14XXXBCP Plastic
readouts, connection diagrams are given on this data sheet. MC14XXXBCL Ceramic
Applications include instrument (e.g., counter, DVM etc.) display driver, MC14XXXBD SOIC
computer/calculator display driver, cockpit display driver, and various clock,
TA = – 55° to 125°C for all packages.
watch, and timer uses.
• Latch Storage of Code
• Blanking Input
• Readout Blanking on All Illegal Input Combinations TRUTH TABLE
Inputs Outputs
• Direct LED (Common Anode or Cathode) Driving Capability
LD BI Ph* D C B A a b c d e f g Display
• Supply Voltage Range = 3.0 V to 18 V
X 1 0 X X X X 0 0 0 0 0 0 0 Blank
• Capable of Driving Two Low–power TTL Loads, One Low–power 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0
Schottky TTL Load or Two HTL Loads Over the Rated Temperature 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1
Range 1 0 0 0 0 1 0 1 1 0 1 1 0 1 2
1 0 0 0 0 1 1 1 1 1 1 0 0 1 3
• Pin–for–Pin Replacement for CD4056A (with Pin 7 Tied to VSS).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1 0 0 0 1 0 0 0 1 1 0 0 1 1 4
• Chip Complexity: 207 FETs or 52 Equivalent Gates 1 0 0 0 1 0 1 1 0 1 1 0 1 1 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1 0 0 0 1 1 0 1 0 1 1 1 1 1 6
1 0 0 0 1 1 1 1 1 1 0 0 0 0 7
MAXIMUM RATINGS* (Voltages referenced to VSS)
1 0 0 1 0 0 0 1 1 1 1 1 1 1 8
Rating Symbol Value Unit 1 0 0 1 0 0 1 1 1 1 1 0 1 1 9
1 0 0 1 0 1 0 0 0 0 0 0 0 0 Blank
DC Supply Voltage VDD – 0.5 to + 18 V 1 0 0 1 0 1 1 0 0 0 0 0 0 0 Blank

Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 V 1 0 0 1 1 0 0 0 0 0 0 0 0 0 Blank

1 0 0 1 1 0 1 0 0 0 0 0 0 0 Blank
DC Input Current per Pin Iin ± 10 mA 1 0 0 1 1 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 1 1 0 0 0 0 0 0 0 Blank
Operating Temperature Range TA – 55 to + 125 _C 0 0 0 X X X X ** **

Power Dissipation, per Package† PD 500 mW † † † † Inverse of Output Display

Combinations as above
Storage Temperature Range Tstg – 65 to + 150 _C Above

X = Don’t care
Maximum Continuous Output Drive IOHmax 10 mA
† = Above Combinations
Current (Source or Sink) per Output IOLmax * = For liquid crystal readouts, apply a square wave to Ph
For common cathode LED readouts, select Ph = 0
Maximum Continuous Output Power* POHmax 70 mW For common anode LED readouts, select Ph = 1
(Source or Sink) per Output POLmax ** = Depends upon the BCD code previously applied when
LD = 1
* POHmax = IOH (VOH – VDD) and POLmax = IOL (VOL – VSS)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MC14543B MOTOROLA CMOS LOGIC DATA

6–382
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 0.5 Vdc) 10 — — — – 10.1 — — —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 9.5 Vdc) 10 — — — 10.1 — — —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) Vin = 0 or VDD, 10 — 10 — 0.010 10 — 300
Iout = 0 µA 15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.6 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.1 µA/kHz) f + IDD
Per Package) 15 IT = (4.7 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.
** The formulas given are for the typical characteristics only at 25_C.

MOTOROLA CMOS LOGIC DATA MC14543B

6–383
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ Max Unit
Output Rise Time tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 100 200
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 50 100
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 40 80
Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 12.5 ns 15 — 40 80
Turn–Off Delay Time tPLH ns
tPLH = (1.7 ns/pF) CL + 520 ns 5.0 — 605 1210
tPLH = (0.66 ns/pF) CL + 217 ns 10 — 250 500
tPLH = (0.5 ns/pF) CL + 160 ns 15 — 185 370
Turn–On Delay Time tPHL ns
tPHL = (1.7 ns/pF) CL + 420 ns 5.0 — 505 1650
tPHL = (0.66 ns/pF) CL + 172 ns 10 — 205 660
tPHL = (0.5 ns/pF) CL + 130 ns 15 — 155 495
Setup Time tsu 5.0 350 — ns
10 450 —
15 500 —
Hold Time th 5.0 40 — ns
10 30 —
15 20 —
Latch Disable Pulse Width (Strobing Data) tWH 5.0 250 125 — ns
10 100 50 —
15 80 40 —
* The formulas given are for the typical characteristics only.

LOGIC DIAGRAM

BI 7
VDD = PIN 16
VSS = PIN 8

9 a
A 5

10 b

B 3 11 c

12 d

13 e
C 2

15 f

14 g
D 4

LD 1 PHASE 6

MC14543B MOTOROLA CMOS LOGIC DATA

6–384
 0 24

VDD = 5.0 Vdc VDD = 15 Vdc

POHmax = 70 mWdc
IOH, SOURCE CURRENT (mAdc)

IOL , SINK CURRENT (mAdc)

– 6.0 18

VDD = 10 Vdc VDD = 10 Vdc

– 12 12

– 18 6.0
VDD = 15 Vdc VDD = 5.0 Vdc POLmax = 70 mWdc
VSS = 0 Vdc VSS = 0 Vdc
– 24 0
– 16 – 12 – 8.0 – 4.0 0 0 4.0 8.0 12 16
(VOH – VDD), SOURCE DEVICE VOLTAGE (Vdc) (VOL – VSS), SINK DEVICE VOLTAGE (Vdc)

Figure 1. Typical Output Source Figure 2. Typical Output Sink

Characteristics Characteristics

(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.

20 ns 20 ns
VDD
C 90%
50%
10% VSS
tPHL tPLH
VOH
90% 50%
g 10% VOL
tTHL tTLH

(b) Inputs D, Ph, and BI low, and Inputs A and B high.

20 ns
VDD
LD 90%
50%
10% VSS
tsu
Inputs BI and Ph low, and Inputs D and LD high. th
VDD
f in respect to a system clock. C 50% 50%
VSS
All outputs connected to respective CL loads.
VOH
20 ns 20 ns g
VDD VOL
A, B, AND C 90% 50%
10% 1 VSS
2f (c) Data DCBA strobed into latches
50% DUTY CYCLE
VDD
VOH LD 50%
ANY OUTPUT VSS
VOL tWH

Figure 3. Dynamic Power Dissipation Figure 4. Dynamic Signal Waveforms

Signal Waveforms

MOTOROLA CMOS LOGIC DATA MC14543B

6–385
 CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIQUID CRYSTAL (LC) READOUT INCANDESCENT READOUT

APPROPRIATE
MC14543B ONE OF SEVEN SEGMENTS VOLTAGE
OUTPUT
Ph COMMON
BACKPLANE

MC14543B
SQUARE WAVE OUTPUT
(VSS TO VDD) Ph

VSS

LIGHT EMITTING DIODE (LED) READOUT GAS DISCHARGE READOUT

APPROPRIATE
VDD VOLTAGE
COMMON COMMON
CATHODE LED ANODE LED
MC14543B
OUTPUT
Ph
MC14543B
OUTPUT
MC14543B
Ph
VSS OUTPUT
Ph
VDD
NOTE: Bipolar transistors may be added for gain (for VDD v 10 V or Iout ≥ 10 mA). VSS

PIN ASSIGNMENT CONNECTIONS TO SEGMENTS

a
LD 1 16 VDD
f g b
C 2 15 f
e c
B 3 14 g d
D 4 13 e
A 5 12 d VDD = PIN 16
VSS = PIN 8
PH 6 11 c
BI 7 10 b
DISPLAY
VSS 8 9 a

0 1 2 3 4 5 6 7 8 9

MC14543B MOTOROLA CMOS LOGIC DATA

6–386
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14544B
BCD-to-Seven Segment
Latch/Decoder/Driver for
Liquid Crystals
L SUFFIX
CERAMIC
CASE 726
CMOS MSI (Low–Power Complementary MOS)
The MC14544B BCD–to–seven segment latch/decoder/driver is designed
for use with liquid crystal readouts, and is constructed with complementary
MOS (CMOS) enhancement mode devices. The circuit provides the P SUFFIX
functions of a 4–bit storage latch and an 8421 BCD–to–seven segment PLASTIC
decoder and driver. The device has the capability to invert the logic levels of CASE 707
the output combination. The phase (Ph), blanking (BI), and latch disable (LD)
inputs are used to reverse the truth table phase, blank the display, and store
a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is
applied to the Ph input of the circuit and the electrically common backplane ORDERING INFORMATION
of the display. The outputs of the circuit are connected directly to the MC14XXXBCP Plastic
segments of the LC readout. The Ripple Blanking Input (RBI) and the Ripple MC14XXXBCL Ceramic
Blanking Output (RBO) can be used to suppress either leading or trailing TA = – 55° to 125°C for all packages.
zeroes.
For other types of readouts, such as light–emitting diode (LED),
incandescent, gas discharge, and fluorescent readouts, connection dia-
grams are given on this data sheet. PIN ASSIGNMENT
Applications include instrument (e.g., counter, DVM etc.) display driver,
LD 1 18 VDD
computer/calculator display driver, cockpit display driver, and various clock,
watch, and timer uses. C 2 17 f
a
• Latch Storage of Code B 3 16 g
f g b
• Blanking Input D 4 15 e
• Readout Blanking on All Illegal Input Combinations e c
A 5 14 d
• Direct LED (Common Anode or Cathode) Driving Capability d
• Supply Voltage Range = 3.0 V to 18 V PH 6 13 c
• Capability for Suppression of Non–significant zero BI 7 12 b
• Capable of Driving Two Low–power TTL Loads, One Low–power RBO 8 11 a
Schottky TTL Load or Two HTL Loads Over the Rated Temperature

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VSS 9 10 RBI
Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages referenced to VSS)

DC Supply Voltage
Rating Symbol
VDD
Value
– 0.5 to + 18
Unit
V
DISPLAY

0 1 2 3 4 5 6 7 8 9
Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 V
DC Input Current per Pin Iin ± 10 mAdc
Operating Temperature Range TA – 55 to + 125 _C This device contains protection circuitry to
guard against damage due to high static
Power Dissipation, per Package† PD 500 mW
voltages or electric fields. However, pre-
Storage Temperature Range Tstg – 65 to + 150 _C cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
Maximum Continuous Output Drive IOHmax 10 mAdc
ages to this high–impedance circuit. For proper
Current (Source or Sink) per Output IOLmax
operation, Vin and Vout should be constrained
Maximum Continuous Output Power* POHmax 70 mW to the range VSS v
(Vin or Vout) VDD. v
(Source or Sink) per Output POLmax Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
* POHmax = IOH (VOH – VDD) and POLmax = IOL (VOL – VSS)
or VDD). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MOTOROLA CMOS LOGIC DATA MC14544B

6–387
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage # “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 0.5 Vdc) 10 — — — – 10.1 — — —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 9.5 Vdc) 10 — — — 10.1 — — —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) Vin = 0 or VDD, 10 — 10 — 0.010 10 — 300
Iout = 0 µA 15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.6 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.1 µA/kHz) f + IDD
Per Package) 15 IT = (4.7 µA/kHz )f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.
* The formulas given are for the typical characteristics only at 25_C.

MC14544B MOTOROLA CMOS LOGIC DATA

6–388
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ Max Unit
Output Rise Time tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 100 200
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 50 100
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 40 80
Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 12.5 ns 15 — 40 80
Turn–Off Delay Time tPLH ns
tPLH = (1.7 ns/pF) CL + 520 ns 5.0 — 605 1210
tPLH = (0.66 ns/pF) CL + 217 ns 10 — 250 500
tPLH = (0.5 ns/pF) CL + 160 ns 15 — 185 370
Turn–On Delay Time tPHL ns
tPHL = (1.7 ns/pF) CL + 420 ns 5.0 — 505 1650
tPHL = (0.66 ns/pF) CL + 172 ns 10 — 205 660
tPHL = (0.5 ns/pF) CL + 130 ns 15 — 155 495
Setup Time tsu 5.0 0 – 40 — ns
10 0 – 15 —
15 0 – 10 —
Hold Time th 5.0 80 40 — ns
10 30 15 —
15 20 10 —
Latch Disable Pulse Width (Strobing Data) tWH 5.0 250 125 — ns
10 100 50 —
15 80 40 —
* The formulas given are for the typical characteristics only.

LOGIC DIAGRAM

BI 7
VDD = PIN 18
VSS = PIN 9

11 a
A 5

12 b

B 3 13 c

14 d

15 e
C 2

17 f

16 g
D 4

LD 1 6
PHASE
8 RBO
RBI 10

MOTOROLA CMOS LOGIC DATA MC14544B

6–389
 CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIQUID CRYSTAL (LC) READOUT INCANDESCENT READOUT

APPROPRIATE
MC14544B ONE OF SEVEN SEGMENTS VOLTAGE
OUTPUT
Ph COMMON
BACKPLANE

SQUARE WAVE MC14544B

(VSS TO VDD) OUTPUT
Ph

VSS

LIGHT EMITTING DIODE (LED) READOUT GAS DISCHARGE READOUT

APPROPRIATE
VDD VOLTAGE
COMMON COMMON
CATHODE LED ANODE LED
MC14544B
OUTPUT
Ph
MC14544B
OUTPUT
MC14544B
Ph
VSS OUTPUT
Ph
VDD
NOTE: Bipolar transistors may be added for gain (for VDD v 10 V or Iout ≥ 10 mA). VSS

TRUTH TABLE
Inputs Outputs X = Don’t Care
†Above Combinations
RBI LD BI Ph* D C B A RBO a b c d e f g Display
* For liquid crystal readouts, apply a square wave
X X 1 0 X X X X # 0 0 0 0 0 0 0 Blank to Ph. For common cathode LED readouts, select
1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Blank Ph = 0. For common anode LED readouts, select
0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 Ph = 1.
X 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 ** Depends upon the BCD Code previously applied
X 1 0 0 0 0 1 0 0 1 1 0 1 1 0 1 2 when LD = 1.
X 1 0 0 0 0 1 1 0 1 1 1 1 0 0 1 3
# RBO = RBI  (A B C D)
X 1 0 0 0 1 0 0 0 0 1 1 0 0 1 1 4
X 1 0 0 0 1 0 1 0 1 0 1 1 0 1 1 5

X 1 0 0 0 1 1 0 0 1 0 1 1 1 1 1 6
X 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 7
X 1 0 0 1 0 0 0 0 1 1 1 1 1 1 1 8
X 1 0 0 1 0 0 1 0 1 1 1 1 0 1 1 9
X 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 Blank

X 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 Blank
X 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Blank
X 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Blank
X 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 Blank
Bl k
X 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Blank

X 0 0 0 X X X X # ** **
† † † 1 † † Inverse of Output Display
Combinations Above as above

MC14544B MOTOROLA CMOS LOGIC DATA

6–390
 0 24

VDD = 5.0 Vdc VDD = 15 Vdc

POHmax = 70 mWdc
IOH, SOURCE CURRENT (mAdc)

IOL , SINK CURRENT (mAdc)

– 6.0 18

VDD = 10 Vdc VDD = 10 Vdc

– 12 12

– 18 6.0
VDD = 15 Vdc VDD = 5.0 Vdc POLmax = 70 mWdc
VSS = 0 Vdc VSS = 0 Vdc
– 24 0
– 16 – 12 – 8.0 – 4.0 0 0 4.0 8.0 12 16
(VOH – VDD), SOURCE DEVICE VOLTAGE (Vdc) (VOL – VSS), SINK DEVICE VOLTAGE (Vdc)

Figure 1. Typical Output Source Figure 2. Typical Output Sink

Characteristics Characteristics

(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.

20 ns 20 ns
VDD
C 90%
50%
10% VSS
tPHL tPLH
VOH
90% 50%
g 10% VOL
tTHL tTLH

(b) Inputs D, Ph, and BI low, and Inputs A and B high.

20 ns
VDD
LD 90%
50%
10% VSS
tsu
th
Inputs BI and Ph low, and Inputs D and LD high. VDD
f in respect to a system clock. C 50% 50%
VSS
All outputs connected to respective CL loads.
VOH
20 ns 20 ns g
VDD VOL
A, B, AND C 90% 50%
10% 1 VSS
2f (c) Data DCBA strobed into latches
50% DUTY CYCLE VDD
VOH LD 50%
ANY OUTPUT VSS
VOL tWH

Figure 3. Dynamic Power Dissipation Figure 4. Dynamic Signal Waveforms

Signal Waveforms

MOTOROLA CMOS LOGIC DATA MC14544B

6–391
 TYPICAL APPLICATIONS FOR RIPPLE BLANKING

LEADING EDGE ZERO SUPPRESSION

DISPLAYS

CONNECT TO a–– –––g a–– –––g a–– –––g a–– –––g a–– –––g a–– –––g
RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO
VDD (1) D C B A 1 D C B A 1 D C B A 0 D C B A 0 D C B A 0 D C B A 0

MC14544B MC14544B MC14544B MC14544B MC14544B MC14544B

INPUT 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1
CODE (0) (0) (5) (0) (1) (3)

TRAILING EDGE ZERO SUPPRESSION

DISPLAYS

a–– –––g a–– –––g a–– –––g a–– –––g a–– –––g a – – – – – g CONNECT TO
0
RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO
D C B A 0 D C B A 0 D C B A 0 D C B A 1 D C B A 1 D C B A VDD (1)

MC14544B MC14544B MC14544B MC14544B MC14544B MC14544B

INPUT 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 INPUT
CODE (5) (0) (1) (3) (0) (0) CODE

MC14544B MOTOROLA CMOS LOGIC DATA

6–392
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14547B
High Current BCD-to-Seven
Segment Decoder/Driver L SUFFIX
CERAMIC
The MC14547 BCD–to–seven segment decoder/driver is constructed with CASE 620
complementary MOS (CMOS) enhancement mode devices and NPN bipolar
output drivers in a single monolithic structure. The circuit provides the
functions of an 8421 BCD–to–seven segment decoder with high output drive P SUFFIX
PLASTIC
capability. Blanking (BI), can be used to turn off or pulse modulate the
CASE 648
brightness of the display. The MC14547 can drive seven–segment
light–emitting diodes (LED), incandescent, fluorescent or gas discharge
readouts either directly or indirectly. DW SUFFIX
Applications include instrument (e.g., counter, DVM, etc.) display driver, SOIC
computer/calculator display driver, cockpit display driver, and various clock, CASE 751G
watch, and timer uses.
• High Current Sourcing Outputs (Up to 65 mA) ORDERING INFORMATION
• Low Logic Circuit Power Dissipation MC14XXXBCP Plastic
MC14XXXBCL Ceramic
• Supply Voltage Range = + 3.0 V to + 18 V MC14XXXBDW SOIC
• Blanking Input
TA = – 55° to 125°C for all packages.
• Readout Blanking on All Illegal Combinations
• Lamp Intensity Modulation Capability
• Multiplexing Capability
• Capable of Driving Two Low–Power TTL Loads, One Low–Power B 1 16 VDD
Schottky TTL Load or Two HTL Loads over the Rated Temperature C 2 15 f
Range
NC 3 14 g

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
a
• Use MC14511B for Applications Requiring Data Latches
BI 4 13 a f g b

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages referenced to VSS, Pin 8)
Rating Symbol Value Unit
NC
D
5
6
12
11
b
c
e
d
c

DC Supply Voltage VDD – 0.5 to + 18 V A 7 10 d

Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 V VSS 8 9 e
Operating Temperature Range TA – 55 to + 125 _C
DISPLAY
Storage Temperature Range Tstg – 65 to + 150 _C
Maximum Continuous Output Drive IOHmax 65 mA
Current (Source) per Output 0 1 2 3 4 5 6 7 8 9

Maximum Continuous Power Dissipation PD 1200* mW

TRUTH TABLE
* Maximum Ratings are those values beyond which damage to the device may occur.
Inputs Outputs
* See Power Derating Curve Figure 1.
BI D C B A a b c d e f g Display
0 X X X X 0 0 0 0 0 0 0 Blank
This device contains circuitry to protect the inputs against damage
1 0 0 0 0 1 1 1 1 1 1 0 0
due to high static voltages or electric fields; however, it is advised that 1 0 0 0 1 0 1 1 0 0 0 0 1
normal precautions be taken to avoid application of any voltage higher 1 0 0 1 0 1 1 0 1 1 0 1 2
than maximum rated voltages to this high-impedance circuit. A destruc- 1 0 0 1 1 1 1 1 1 0 0 1 3
tive high current mode may occur if Vin and Vout is not constrained to 1 0 1 0 0 0 1 1 0 0 1 1 4
the range VSS ≤ (Vin or Vout) ≤ VDD. 1 0 1 0 1 1 0 1 1 0 1 1 5
1 0 1 1 0 0 0 1 1 1 1 1 6
Due to the sourcing capability of this circuit, damage can occur to the 1 0 1 1 1 1 1 1 0 0 0 0 7
device if VDD is applied, and the outputs are shorted to VSS and are at a 1 1 0 0 0 1 1 1 1 1 1 1 8
logical 1 (See Maximum Ratings). 1 1 0 0 1 1 1 1 0 0 1 1 9
Unused inputs must always be tied to an appropriate logic voltage 1 1 0 1 0 0 0 0 0 0 0 0 Blank
1 1 0 1 1 0 0 0 0 0 0 0 Blank
level (e.g., either VSS or VDD).
1 1 1 0 0 0 0 0 0 0 0 0 Blank
1 1 1 0 1 0 0 0 0 0 0 0 Blank
1 1 1 1 0 0 0 0 0 0 0 0 Blank
1 1 1 1 1 0 0 0 0 0 0 0 Blank
X = Don’t care

MOTOROLA CMOS LOGIC DATA MC14547B

6–393
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.1 — 4.4 4.6 — 4.3 — Vdc
Vin = 0 or VDD 10 9.1 — 9.4 9.6 — 9.3 —
15 14.1 — 14.4 14.6 — 14.4 —
Input Voltage # “0” Level VIL Vdc
(VO = 3.8 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 8.8 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.8 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 3.8 Vdc) VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 8.8 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.8 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Voltage VOH Vdc
(IOH = 5.0 mA) Source 5.0 4.0 — 4.2 4.3 — 4.3 —
(IOH = 10 mA) — — 4.1 4.3 — — —
(IOH = 20 mA) 3.8 3.9 4.2 — 4.0 —
(IOH = 40 mA) — — 3.7 4.0 — — —
(IOH = 65 mA) 3.1 — 3.2 3.7 — 3.0 —
(IOH = 5.0 mA) 10 9.1 — 9.2 9.3 — 9.3 — Vdc
(IOH = 10 mA) — — 9.1 9.3 — — —
(IOH = 20 mA) 8.8 — 9.0 9.2 — 9.2 —
(IOH = 40 mA) — — 8.9 9.0 — — —
(IOH = 65 mA) 8.4 — 8.5 8.8 — 8.1 —
(IOH = 5.0 mA) 15 14 — 14.2 14.3 — 14.4 — Vdc
(IOH = 10 mA) — — 14.1 14.3 — — —
(IOH = 20 mA) 13.8 — 14.0 14.2 — 14.2 —
(IOH = 40 mA) — — 13.8 14.0 — — —
(IOH = 65 mA) 13.5 — 13.5 13.7 — 13.3 —
Output Drive Current IOL mAdc
(VOL = 0.4 Vdc) Sink 5.0 0.32 — 0.26 0.44 — 0.18 —
(VOL = 0.5 Vdc) 10 0.80 — 0.65 1.13 — 0.45 —
(VOL = 1.5 Vdc) 15 2.10 — 1.7 4.4 — 1.2 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) Vin = 0 or VDD, 10 — 10 — 0.010 10 — 300
Iout = 0 µA 15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.9 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.8 µA/kHz) f + IDD
Per Package) 15 IT = (5.7 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Noise immunity specified for worst input combination.
Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.
** The formulas given are for the typical characteristics only at 25_C.

MC14547B MOTOROLA CMOS LOGIC DATA

6–394
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

Characteristic Symbol
VDD
Vdc Min Typ Max Unit
Output Rise Time tTLH 5.0 — 40 80 ns
10 — 40 80
15 — 40 80
Output Fall Time tTHL 5.0 — 125 250 ns
10 — 75 150
15 — 70 140
Data Propagation Delay Time tPLH 5.0 — 750 1500 ns
10 — 300 600
15 — 200 400
tPHL 5.0 — 750 1500
10 — 300 600
15 — 200 400
Blank Propagation Delay Time tPLH 5.0 — 750 1500 ns
10 — 300 600
15 — 200 400
tPHL 5.0 — 500 1000
10 — 250 500
15 — 170 340

MOTOROLA CMOS LOGIC DATA MC14547B

6–395
 LOGIC DIAGRAM

BI 4

A 7

13 a

12 b

B 1
11 c

10 d

C 2
9 e

15 f

D 6
14 g

1200
PD, MAXIMUM POWER DISSIPATION (mW)

1000

800 (L) CERAMIC

PER PACKAGE

600 (P) PDIP

400 410 mW (L)

(D) SOIC
230 mW (P)
200
150 mW (D)

0
25 50 75 100 125 150 175
TA, AMBIENT TEMPERATURE (0°C)

Figure 1. Ambient Temperature Power Derating

MC14547B MOTOROLA CMOS LOGIC DATA

6–396
 CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIGHT EMITTING DIODE (LED) READOUT

VDD VDD

COMMON
ANODE LED ≈ 1.7 V
COMMON
CATHODE LED

≈ 1.7 V

VSS VSS

INCANDESCENT READOUT LIGHT–EMITTING DIODE (LED) READOUT

USING A ZENER DIODE TO REPLACE DROPPING RESISTORS
VDD VDD
VDD

**

COMMON
CATHODE LED

VSS
VSS
VZD*

GAS DISCHARGE READOUT VSS

APPROPRIATE
VDD VOLTAGE
FLUORESCENT READOUT
VDD

DIRECT
(LOW BRIGHTNESS)

VSS
FILAMENT
SUPPLY
* VZD should be set at VDD – 1.3 V – VLED. Wattage of zener diode VSS
must be calculated for number of segments and worst–case VSS OR APPROPRIATE
conditions. VOLTAGE BELOW VSS.
** A filament pre–warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the (Caution: Absolute maximum
filament. working voltage = 18.0 V)

MOTOROLA CMOS LOGIC DATA MC14547B

6–397
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14549B
Successive Approximation MC14559B
Registers
The MC14549B and MC14559B successive approximation registers are
8–bit registers providing all the digital control and storage necessary for L SUFFIX
successive approximation analog–to–digital conversion systems. These CERAMIC
parts differ in only one control input. The Master Reset (MR) on the CASE 620
MC14549B is required in the cascaded mode when more than 8 bits are
desired. The Feed Forward (FF) of the MC14559B is used for register
shortening where End–of–Conversion (EOC) is required after less than eight
P SUFFIX
cycles. PLASTIC
Applications for the MC14549B and MC14559B include analog–to–digital CASE 648
conversion, with serial and parallel outputs.
• Totally Synchronous Operation
• All Outputs Buffered DW SUFFIX
• Single Supply Operation SOIC
• Serial Output CASE 751G
• Retriggerable
• Compatible with a Variety of Digital and Analog Systems such as the ORDERING INFORMATION
MC1408 8–Bit D/A Converter MC14XXXBCP Plastic
• All Control Inputs Positive–Edge Triggered MC14XXXBCL Ceramic
MC14XXXBDW SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
TA = – 55° to 125°C for all packages.
• Capable of Driving Two Low–Power TTL Loads, One Low–Power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Chip Complexity: 488 FETs or 122 Equivalent Gates PIN ASSIGNMENT
MAXIMUM RATINGS* (Voltages referenced to VSS)
Q4 1 16 VDD
Rating Symbol Value Unit
Q5 2 15 Q3
DC Supply Voltage VDD – 0.5 to + 18 Vdc
Q6 3 14 Q2
Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 Vdc
Q7 4 13 Q1
DC Input Current, per Pin Iin ± 10 mAdc
Sout 5 12 Q0
Power Dissipation, per Package† PD 500 mW
D 6 11 EOC
Operating Temperature Range TA – 55 to + 125 _C
Storage Temperature Range Tstg – 65 to + 150 _C C 7 10 *
* Maximum Ratings are those values beyond which damage to the device may occur. VSS 8 9 SC
†Temperature Derating:
“P and D/DW” Packages: – 7.0 mW/C From 65_C To 125_C Ceramic * For MC14549B Pin 10 is MR input.
“L” Packages: – 12 mW/_C From 100_C To 125_C For MC14559B Pin 10 is FF input.
TRUTH TABLES
MC14549B MC14559B
SC SC(t–1) MR MR(t–1) Clock Action SC SC(t–1) EOC Clock Action
X X X X None X X X None
X X 1 X Reset 1 0 0 Start
1 0 0 0 Start Conversion
Conversion X 1 0 Continue
1 X 0 1 Start Conversion
Conversion 0 0 0 Continue
1 1 0 0 Continue Conversion
Conversion 0 X 1 Retain
0 X 0 X Continue Conversion
Previous Result
Operation 1 X 1 Start
X = Don’t Care t–1 = State at Previous Clock Conversion

MC14549B MC14559B MOTOROLA CMOS LOGIC DATA

6–398
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage # “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOL = 0.4 Vdc) Sink IOL 5.0 1.28 — 1.02 1.76 — 0.72 — mAdc
(VOL = 0.5 Vdc) Q Outputs 10 3.2 — 2.6 4.5 — 1.8 —
(VOL = 1.5 Vdc) 15 8.4 — 6.8 17.6 — 4.8 —
(VOL = 0.4 Vdc) Sink 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) Pin 5, 11 only 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
(Clock = 0 V, 15 — 20 — 0.015 20 — 600
Other Inputs = VDD
or 0 V, Iout = 0 µA)
Total Supply Current**† IT 5.0 IT = (0.8 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.6 µA/kHz) f + IDD
Per Package) 15 IT = (2.4 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL = 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.
** The formulas given are for the typical characteristics only at 25_C.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it
is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or v
Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).

MOTOROLA CMOS LOGIC DATA MC14549B MC14559B

6–399
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ Max Unit
Output Rise Time tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130
Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Clock to Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns 5.0 — 500 1000
tPLH, tPHL = (0.66 ns/pF) CL + 177 ns 10 — 210 420
tPLH, tPHL = (0.5 ns/pF) CL + 130 ns 15 — 155 310
Clock to Sout
tPLH, tPHL = (1.7 ns/pF) CL + 665 ns 5.0 — 750 1500
tPLH, tPHL = (0.66 ns/pF) CL + 277 ns 10 310 620
tPLH, tPHL = (0.5 ns/pF) CL + 195 ns 15 — 220 440
Clock to EOC
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns 5.0 — 300 600
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 — 100 200
SC, D, FF or MR Setup Time tsu 5.0 250 125 — ns
10 100 50 —
15 80 40 —
Clock Pulse Width tWH(cl) 5.0 700 350 — ns
10 270 135 —
15 200 100 —
Pulse Width — D, SC, FF or MR tWH 5.0 500 250 — ns
10 200 100 —
15 160 80 —
Clock Rise and Fall Time tTLH, 5.0 — 15 µs
tTHL 10 — 1.0
15 — — 0.5
Clock Pulse Frequency fcl 5.0 — 1.5 0.8 MHz
10 — 3.0 1.5
15 — 4.0 2.0
* The formulas given are for the typical characteristics only.

MC14549B MC14559B MOTOROLA CMOS LOGIC DATA

6–400
 SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

VDD

Q7
Q6
C CL
Q5
CL
Q4
SC CL
PROGRAMMABLE Q3
PULSE CL
Q2
GENERATOR FF(MR) CL
Q1
CL
Q0 CL
D
EOC
CL
Sout CL
CL 1
VSS fcl
tWH(cl)
50%
C
tsu
50%
SC
tsu tsu tWH(D)
D
50%
tPLH tPHL
50% 90% 10%
Q7
tTLH tTHL tPLH
50% 90%
Sout 10%
tTLH
NOTE: Pin 10 = VSS

TIMING DIAGRAM

CLOCK
SC

ÉÉÉ
D

ÉÉÉ
Q7

ÉÉÉ
Q6

ÉÉÉ
Q5

ÉÉÉ
Q4

ÉÉÉ
Q3

ÉÉÉ
Q2

ÉÉÉ
Q1

ÉÉÉ
Q0

ÉÉÉ
EOC

ÉÉÉ
Sout INH Q7 Q6 INH Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q8* INH

ÉÉÉ
— Don’t care condition
INH — Indicates Serial Out is inhibited low.
* — Q8 is ninth–bit of serial information available from 8–bit register.
NOTE: Pin 10 = VSS

MOTOROLA CMOS LOGIC DATA MC14549B MC14559B

6–401
 OPERATING CHARACTERISTICS

Both the MC14549B and MC14559B can be operated in
either the “free run” or “strobed operation” mode for conver-
sion schemes with any number of bits. Reliable cascading
and/or recirculating operation can be achieved if the End of
Convert (EOC) output is used as the controlling function,
since with EOC = 0 (and with SC = 1 for MC14549B but
either 1 or 0 for MC14559B) no stable state exists under con-
tinual clocked operation. The MC14559B will automatically
recirculate after EOC = 1 during externally strobed operation,
provided SC = 1.
All data and control inputs for these devices are triggered
into the circuit on the positive edge of the clock pulse.
Operation of the various terminals is as follows:
C = Clock — A positive–going transition of the Clock is
required for data on any input to be strobed into the circuit.
SC = Start Convert — A conversion sequence is initiated
on the positive–going transition of the SC input on succeed-
ing clock cycles.
D = Data in — Data on this input (usually from a compara-
tor in A/D applications) is also entered into the circuit on a
positive–going transition of the clock. This input is Schmitt
triggered and synchronized to allow fast response and guar-
anteed quality of serial and parallel data.
MR = Master Reset (MC14549B Only) — Resets all out-
put to 0 on positive–going transitions of the clock. If removed
while SC = 0, the circuit will remain reset until SC = 1. This
allows easy cascading of circuits.
FF = Feed Forward (MC14559B Only) — Provides regis-
ter shortening by removing unwanted bits from a system.
For operation with less than 8 bits, tie the output following
the least significant bit of the circuit to EOC. E.g., for a 6–bit
conversion, tie Q1 to FF; the part will respond as shown in
the timing diagram less two bit times. Not that Q1 and Q0 will
still operate and must be disregarded.
For 8–bit operation, FF is tied to VSS.
For applications with more than 8 but less than 16 bits, use
the basic connections shown in Figure 1. The FF input of the
MC14559B is used to shorten the setup. Tying FF directly to
the least significant bit used in the MC14559B allows EOC to
provide the cascading signal, and results in smooth transition
of serial information from the MC14559B to the MC14549B.
The Serial Out (S out) inhibit structure of the MC14559B
remains inactive one cycle after EOC goes high, while Sout of
the MC14549B remains inhibited until the second clock cycle
of its operation.
Qn = Data Outputs — After a conversion is initiated the
Q’s on succeeding cycles go high and are then conditionally
reset dependent upon the state of the D input. Once condi-
tionally reset they remain in the proper state until the circuit is
either reset or reinitiated.
EOC = End of Convert — This output goes high on the
negative–going transition of the clock following FF = 1 (for
the MC14559B) or the conditional reset of Q0. This allows
settling of the digital circuitry prior to the End of Conversion
indication. Therefore either level or edge triggering can indi-
cate complete conversion.
Sout = Serial Out — Transmits conversion in serial fash-
ion. Serial data occurs during the clock period when the cor-
responding parallel data bit is conditionally reset. Serial Out
is inhibited on the initial period of a cycle, when the circuit is
reset, and on the second cycle after EOC goes high. This
provides efficient operation when cascaded.

FROM A/D EXTERNAL 1/4 MC14001

COMPARATOR CLOCK

SERIAL OUT
(CONTINUAL
UPDATE EVERY
D Sout D Sout
C C 13 CLOCK CYCLES)
SC MC14559B SC MC14549B
* FF MR
Q7 Q6 Q5 Q4 •• Q0 EOC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
** {

NC
MSB LSB
TO D/A AND PARALLEL DATA
TO D/A AND
PARALLEL DATA

FREE RUN MODE

EXTERNAL STROBE
* FF allows EOC to activate as if in 4–stage register.
** Cascading using EOC guaranteed; no stable unfunctional state.
†Completion of conversion automatically re–initiates cycle in free run mode.

Figure 1. 12–Bit Conversion Scheme

MC14549B MC14559B MOTOROLA CMOS LOGIC DATA

6–402
 TYPICAL APPLICATIONS

Externally Controlled 6–Bit ADC (Figure 2)
Several features are shown in this application:
• Shortening of the register to six bits by feeding the seventh
output bit into the FF input.
• Continuous conversion, if a continuous signal is applied to
SC.
• Externally controlled updating (the start pulse must be
shorter than the conversion cycle).
• The EOC output indicating that the parallel data are valid
and that the serial output is complete.
Continuously Cycling 8–Bit ADC (Figure 3)
This ADC is running continuously because the EOC signal
is fed back to the SC input, immediately initiating a new cycle
on the next clock pulse.
Continuously Cycling 12–Bit ADC (Figure 4)
Because each successive approximation register (SAR)
has a capability of handling only an eight–bit word, two must
be cascaded to make an ADC with more than eight bits.
When it is necessary to cascade two SAR’s, the second
SAR must have a stable resettable state to remain in while
awaiting a subsequent start signal. However, the first stage
must not have a stable resettable state while recycling, be-
cause during switch–on or due to outside influences, the first
stage has entered a reset state, the entire ADC will remain in
a stable non–functional condition.
This 12–bit ADC is continuously recycling. The serial as
well as the parallel outputs are updated every thirteenth
clock pulse. The EOC pulse indicates the completion of

C
SC
MC14559B Sout

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC

TO DAC

Figure 2. Externally Controlled 6–Bit ADC

C
SC
MC14559B Sout

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC

TO DAC

Figure 3. Continuously Cycling 8–Bit ADC

MOTOROLA CMOS LOGIC DATA MC14549B MC14559B

6–403
 Sout

C Sout C
SC SC Sout
MC14559B MC14549B
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC

TO DAC TO DAC

EOC

Figure 4. Continuously Cycling 12–Bit ADC

the 12–bit conversion cycle, the end of the serial output Additional Motorola Parts for Successive
word, and the validity of the parallel data output. Approximation ADC

Externally Controlled 12–Bit ADC (Figure 5) Monolithic digital–to–analog converters — The

In this circuit the external pulse starts the first SAR and
simultaneously resets the cascaded second SAR. When Q4
of the first SAR goes high, the second SAR starts conver-
sion, and the first one stops conversion. EOC indicates that
the parallel data are valid and that the serial output is com-
plete. Updating the output data is started with every external
control pulse.
MC1408/1508 converter has eight–bit resolution and is avail-
able with 6, 7, and 8–bit accuracy. The amplifier–compara-
tor block — The MC1407/1507 contains a high speed
operational amplifier and a high speed comparator with ad-
justable window.
With these two linear parts it is possible to construct SA–
ADCs with an accuracy of up to eight bits, using as the regis-
ter one MC14549B or one MC14559B. An additional CMOS
block will be necessary to generate the clock frequency.
Additional information on successive approximation ADC
is found in Motorola Application Note AN–716.

C Sout C
SC SC Sout
MC14559B MC14549B
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC

TO DAC TO DAC
EOC Sout

Figure 5. Externally Controlled 12–Bit ADC

MC14549B MC14559B MOTOROLA CMOS LOGIC DATA

6–404
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14551B
Quad 2-Channel Analog
Multiplexer/Demultiplexer L SUFFIX
CERAMIC
The MC14551B is a digitally–controlled analog switch. This device CASE 620
implements a 4PDT solid state switch with low ON impedance and very low
OFF Leakage current. Control of analog signals up to the complete supply
voltage range can be achieved. P SUFFIX
• Triple Diode Protection on All Control Inputs PLASTIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 648
• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V
Note: VEE must be v
VSS
• Linearized Transfer Characteristics D SUFFIX
SOIC
• Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical
CASE 751B
• For Low RON, Use The HC4051, HC4052, or HC4053 High–Speed
CMOS Devices ORDERING INFORMATION
• Switch Function is Break Before Make

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* MC14XXXBD SOIC
Symbol Parameter Value Unit TA = – 55° to 125°C for all packages.

VDD DC Supply Voltage (Referenced to VEE, – 0.5 to + 18.0 V

VSS ≥ VEE)
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
(Referenced to VSS for Control Input &
VEE for Switch I/O)
Iin Input Current (DC or Transient), per ± 10 mA
Control Pin
Isw Switch Through Current ± 25 mA
PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages – 12 mW/_C From 100_C To 125_C

PIN ASSIGNMENT
W1 1 16 VDD
9 CONTROL
W 14 Control ON X0 2 15 W0
15 W0 0 W0 X0 Y0 Z0 X1 3 14 W
1 W1 X 4
1 W1 X1 Y1 Z1 X 4 13 Z
2 X0 COMMONS
SWITCHES 3 X1 OUT/IN VDD = Pin 16 Y 5 12 Z1
IN/OUT 6 Y0 Y 5
VSS = Pin 8 Y0 6 11 Z0
10 Y1
VEE = Pin 7 VEE 7 10 Y1
11 Z0 Z 13
12 Z1 VSS 8 9 CONTROL

NOTE: Control Input referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be v VSS.

MOTOROLA CMOS LOGIC DATA MC14551B

6–405
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
– 55_C 25_C 125_C
Characteristic Symbol VDD Test Conditions Min Max Min Typ # Max Min Max Unit

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage VDD — VDD – 3.0 ≥ VSS ≥ 3.0 18 3.0 — 18 3.0 18 V
Range VEE
Quiescent Current Per IDD 5.0 Control Inputs: Vin = — 5.0 — 0.005 5.0 — 150 µA
Package 10 VSS or VDD, — 10 — 0.010 10 — 300
15 v
Switch I/O: VEE VI/O — 20 — 0.015 20 — 600
v VDD, and ∆Vswitch
v 500 mV**
Total Supply Current ID(AV) 5.0 TA = 25_C only (The µA
(0.07 µA/kHz) f + IDD
(Dynamic Plus 10 channel component,
Typical (0.20 µA/kHz) f + IDD
Quiescent, Per Package) 15 (Vin – Vout)/Ron, is
(0.36 µA/kHz) f + IDD
not included.)
CONTROL INPUT (Voltages Referenced to VSS)
Low–Level Input Voltage VIL 5.0 Ron = per spec, — 1.5 — 2.25 1.5 — 1.5 V
10 Ioff = per spec — 3.0 — 4.50 3.0 — 3.0
15 — 4.0 — 6.75 4.0 — 4.0
High–Level Input Voltage VIH 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
10 Ioff = per spec 7.0 — 7.0 5.50 — 7.0 —
15 11 — 11 8.25 — 11 —
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µA
Input Capacitance Cin — — — — 5.0 7.5 — — pF
SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to VEE)
Recommended Peak–to– VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD Vp–p
Peak Voltage Into or Out
of the Switch
Recommended Static or ∆Vswitch — Channel On 0 600 0 — 600 0 300 mV
Dynamic Voltage Across
the Switch** (Figure 3)
Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV
ON Resistance Ron 5.0 ∆Vswitch v 500 mV**, — 800 — 250 1050 — 1200 Ω
10 Vin = VIL or VIH — 400 — 120 500 — 520
15 (Control), and Vin = 220 — 80 280 — 300
0 to VDD (Switch)
∆ON Resistance Between ∆Ron 5.0 — 70 — 25 70 — 135 Ω
Any Two Channels 10 — 50 — 10 50 — 95
in the Same Package 15 — 45 — 10 45 — 65
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — ± 100 — ± 0.05 ± 100 — ± 1000 nA
Current (Figure 8) (Control) Channel to
Channel or Any One
Channel
Capacitance, Switch I/O CI/O — Switch Off — — — 10 — — — pF
Capacitance, Common O/I CO/I — — — — 17 — — — pF
Capacitance, Feedthrough CI/O — Pins Not Adjacent — — — 0.15 — — — pF
(Channel Off) — Pins Adjacent — — — 0.47 — — —
#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
** For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
** current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
** Ratings are exceeded. (See first page of this data sheet.)

MC14551B MOTOROLA CMOS LOGIC DATA

6–406
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C, VEE

Characteristic Symbol
VSS)
VDD – VEE
Vdc Min Typ # Max Unit
Propagation Delay Times tPLH, tPHL ns
Switch Input to Switch Output (RL = 10 kΩ)
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns 5.0 — 35 90
tPLH, tPHL = (0.08 ns/pF) CL + 11 ns 10 — 15 40
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns 15 — 12 30
Control Input to Output (RL = 10 kΩ) tPLH, tPHL ns
VEE = VSS (Figure 4) 5.0 — 350 875
10 — 140 350
15 — 100 250
Second Harmonic Distortion — 10 — 0.07 — %
RL = 10 kΩ, f = 1 kHz, Vin = 5 Vp–p
Bandwidth (Figure 5) BW 10 — 17 — MHz
RL = 1 kΩ, Vin = 1/2 (VDD – VEE) p–p,
20 Log (Vout / Vin) = – 3 dB, CL = 50 pF
Off Channel Feedthrough Attenuation, Figure 5 — 10 — – 50 — dB
RL = 1 kΩ, Vin = 1/2 (VDD – VEE) p–p,
fin = 55 MHz
Channel Separation (Figure 6) — 10 — – 50 — dB
RL = 1 kΩ, Vin = 1/2 (VDD – VEE) p–p,
fin = 3 MHz
Crosstalk, Control Input to Common O/I, Figure 7 — 10 — 75 — mV
R1 = 1 kΩ, RL = 10 kΩ,
Control tr = tf = 20 ns
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD for control inputs and VEE ≤
(Vin or Vout) ≤ VDD for Switch I/O.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14551B

6–407
 VDD
VDD VDD

IN/OUT OUT/IN

VEE

VDD

LEVEL
CONVERTED
IN/OUT OUT/IN
CONTROL

CONTROL
VEE

Figure 1. Switch Circuit Schematic

16 VDD

CONTROL 9 LEVEL
CONTROL
CONVERTER

8 VSS 7 VEE
W0 15
14 W
W1 1

X0 2
4 X
X1 3

Y0 6
5 Y
Y1 10

Z0 11
13 Z
Z1 12

Figure 2. MC14551B Functional Diagram

MC14551B MOTOROLA CMOS LOGIC DATA

6–408
 TEST CIRCUITS

ON SWITCH
CONTROL
PULSE
SECTION
GENERATOR
OF IC CONTROL Vout
LOAD
V RL CL

SOURCE
VDD VEE VEE VDD

Figure 3. ∆V Across Switch Figure 4. Propagation Delay Times,

Control to Output

Control input used to turn ON or OFF

the switch under test.
RL
ON
CONTROL Vout CONTROL

RL CL = 50 pF OFF
Vout
RL CL = 50 pF
Vin
VDD – VEE VDD – VEE Vin
2 2

Figure 5. Bandwidth and Off–Channel Figure 6. Channel Separation

Feedthrough Attenuation (Adjacent Channels Used for Setup)

OFF CHANNEL UNDER TEST

VDD
VEE
CONTROL
SECTION OTHER
CONTROL Vout
OF IC CHANNEL(S) VEE
RL CL = 50 pF VDD
R1
VEE
VDD

Figure 7. Crosstalk, Control Input Figure 8. Off Channel Leakage

to Common O/I

MOTOROLA CMOS LOGIC DATA MC14551B

6–409
 VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kΩ
VDD RANGE X/Y
PLOTTER
VEE = VSS

Figure 9. Channel Resistance (RON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTICS

350 350

300 300
RON, “ON” RESISTANCE (OHMS)

RON, “ON” RESISTANCE (OHMS)

250 250

200 200

150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C
50 – 55°C 50

0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)

Figure 10. VDD @ 7.5 V, VEE @ – 7.5 V Figure 11. VDD @ 5.0 V, VEE @ – 5.0 V

700 350
TA = 25°C
600 300
RON, “ON” RESISTANCE (OHMS)

RON, “ON” RESISTANCE (OHMS)

500 250 VDD = 2.5 V

400 200

300 150
5.0 V
TA = 125°C
200 100 7.5 V
25°C
100 – 55°C 50

0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)

Figure 12. VDD @ 2.5 V, VEE @ – 2.5 V Figure 13. Comparison at 25_C, VDD @ – VEE

MC14551B MOTOROLA CMOS LOGIC DATA

6–410
 APPLICATIONS INFORMATION

Figure A illustrates use of the on–chip level converter
detailed in Figure 2. The 0–to–5 volt Digital Control signal is
used to directly control a 9 Vp–p analog signal.
The digital control logic levels are determined by V DD and
V SS. The V DD voltage is the logic high voltage; the V SS volt-
age is logic low. For the example, V DD = + 5 V = logic high at
the control inputs; V SS = GND = 0 V = logic low.
The maximum analog signal level is determined by V DD
and V EE. The V DD voltage determines the maximum recom-
mended peak above V SS. The V EE voltage determines the
maximum swing below V SS. For the example, V DD – V SS
= 5 volt maximum swing above V SS; VSS – VEE = 5 volt
maximum swing below VSS. The example shows a ± 4.5 volt
signal which allows a 1/2 volt margin at each peak. If voltage
transients above V DD and/or below V EE are anticipated on
the analog channels, external diodes (Dx) are recommended
as shown in Figure B. These diodes should be small signal
types able to absorb the maximum anticipated current
surges during clipping.
The absolute maximum potential difference between V DD
and V EE is 18.0 volts. Most parameters are specified up to
15 volts which is the recommended maximum difference be-
tween V DD and V EE.
Balanced supplies are not required. However, V SS must
be greater than or equal to V EE . For example, V DD =
+ 10 volts, V SS = + 5 volts, and V EE = – 3 volts is acceptable.
See the table below.

+5 V –5 V

VDD VSS VEE

+ 4.5 V
+5 V 9 Vp–p SWITCH
ANALOG SIGNAL I/O 9 Vp–p
COMMON
GND
O/I ANALOG SIGNAL
EXTERNAL MC14551B
CMOS 0–TO–5 V DIGITAL
CONTROL – 4.5 V
DIGITAL CONTROL SIGNAL
CIRCUITRY

Figure A. Application Example

VDD VDD

Dx Dx
SWITCH COMMON
I/O O/I
Dx Dx

VEE VEE

Figure B. External Schottky or Germanium Clipping Diodes

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
POSSIBLE SUPPLY CONNECTIONS

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Control Inputs

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
VDD VSS VEE Logic High/Logic Low Maximum Analog Signal Range
In Volts In Volts In Volts In Volts In Volts

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
+8
ÎÎÎÎ
ÎÎÎÎ
+5
ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
0

ÎÎÎÎÎÎÎÎÎÎ
0
–8

– 12
+ 8/0

+ 5/0
+ 8 to – 8 = 16 Vp–p

+ 5 to – 12 = 17 Vp–p

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
+5 0 0 + 5/0 + 5 to 0 = 5 Vp–p

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
+5 0 –5 + 5/0 + 5 to – 5 = 10 Vp–p

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
+ 10 –5 + 10/ + 5 + 10 to – 5 = 15 Vp–p

MOTOROLA CMOS LOGIC DATA MC14551B

6–411
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14553B
3-Digit BCD Counter
L SUFFIX
The MC14553B 3–digit BCD counter consists of 3 negative edge triggered CERAMIC
BCD counters that are cascaded synchronously. A quad latch at the output CASE 620
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible. P SUFFIX
An on–chip oscillator provides the low–frequency scanning clock which PLASTIC
drives the multiplexer output selector. CASE 648
This device is used in instrumentation counters, clock displays, digital
panel meters, and as a building block for general logic applications.
DW SUFFIX
• TTL Compatible Outputs SOIC
• On–Chip Oscillator CASE 751G
• Cascadable
• Clock Disable Input ORDERING INFORMATION
• Pulse Shaping Permits Very Slow Rise Times on Input Clock MC14XXXBCP Plastic
• Output Latches MC14XXXBCL Ceramic
MC14XXXBDW SOIC
• Master Reset

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
BLOCK DIAGRAM

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V 4 3

Iin Input Current (DC or Transient), per Pin ± 10 mA

CIA CIB Q0 9
Iout Output Current (DC or Transient), per Pin + 20 mA
12 CLOCK Q1 7
PD Power Dissipation, per Package† 500 mW
Q2 6
Tstg Storage Temperature – 65 to + 150 _C 10 LE
Q3 5
TL Lead Temperature (8–Second Soldering) 260 _C O.F. 14
11 DIS
* Maximum Ratings are those values beyond which damage to the device may occur. DS1 2
†Temperature Derating: DS2 1
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 13 MR
DS3 15
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
VDD = PIN 16
TRUTH TABLE VSS = PIN 8

Inputs
Master
Reset This device contains protection circuitry to
Clock Disable LE Outputs
guard against damage due to high static
0 0 0 No Change voltages or electric fields. However, pre-
0 0 0 Advance cautions must be taken to avoid applications of
0 X 1 X No Change any voltage higher than maximum rated volt-
0 1 0 Advance ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
v v
0 1 0 No Change
0 0 X X No Change to the range VSS (Vin or Vout) VDD.
0 X X Latched Unused inputs must always be tied to an
0 X X 1 Latched appropriate logic voltage level (e.g., either VSS
1 X X 0 Q0 = Q1 = Q2 = Q3 = 0 or VDD). Unused outputs must be left open.

X = Don’t Care

MC14553B MOTOROLA CMOS LOGIC DATA

6–412
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 4.6 Vdc) Source — 5.0 – 0.25 — – 0.2 – 0.36 — 0.14 —
(VOH = 9.5 Vdc) Pin 3 10 – 0.62 — – 0.5 – 0.9 — 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — 1.1 —
(VOH = 4.6 Vdc) Source — 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 — mAdc
(VOH = 9.5 Vdc) Other 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) Outputs 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink — IOL 5.0 0.5 — 0.4 0.88 — 0.28 — mAdc
(VOL = 0.5 Vdc) Pin 3 10 1.1 — 0.9 2.25 — 0.65 —
(VOL = 1.5 Vdc) 15 1.8 — 1.5 8.8 — 1.20 —
(VOL = 0.4 Vdc) Sink — Other 5.0 3.0 — 2.5 4.0 — 1.6 — mAdc
(VOL = 0.5 Vdc) Outputs 10 6.0 — 5.0 8.0 — 3.5 —
(VOL = 1.5 Vdc) 15 18 — 15 20 — 10 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.010 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.020 10 — 300
MR = VDD 15 — 20 — 0.030 20 — 600
Total Supply Current**† IT 5.0 IT = (0.35 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.85 µA/kHz) f + IDD
Per Package) 15 IT = (1.50 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

MOTOROLA CMOS LOGIC DATA MC14553B

6–413
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic Figure Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time 2a tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Clock to BCD Out 2a tPLH, 5.0 — 900 1800 ns
tPHL 10 — 500 1000
15 — 200 400
Clock to Overflow 2a tPHL 5.0 — 600 1200 ns
10 — 400 800
15 — 200 400
Reset to BCD Out 2b tPHL 5.0 — 900 1800 ns
10 — 500 1000
15 — 300 600
Clock to Latch Enable Setup Time 2b tsu 5.0 600 300 — ns
Master Reset to Latch Enable Setup Time 10 400 200 —
15 200 100 —
Removal Time 2b trem 5.0 – 80 – 200 — ns
Latch Enable to Clock 10 – 10 – 70 —
15 0 – 50 —
Clock Pulse Width 2a tWH(cl) 5.0 550 275 — ns
10 200 100 —
15 150 75 —
Reset Pulse Width 2b tWH(R) 5.0 1200 600 — ns
10 600 300 —
15 450 225 —
Reset Removal Time — trem 5.0 – 80 – 180 — ns
10 0 – 50 —
15 20 – 30 —
Input Clock Frequency 2a fcl 5.0 — 1.5 0.9 MHz
10 — 5.0 2.5
15 — 7.0 3.5
Input Clock Rise Time 2b tTLH 5.0 No ns
10 Limit
15
Disable, MR, Latch Enable — tTLH, 5.0 — — 15 µs
Rise and Fall Times tTHL 10 — — 5.0
15 — — 4.0
Scan Oscillator Frequency 1 fosc 5.0 — 1.5/C1 — Hz
(C1 measured in µF) 10 — 4.2/C1 —
15 — 7.0/C1 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14553B MOTOROLA CMOS LOGIC DATA

6–414
 1000
100
101

899
900
901
990
991
992
993
994
995
996
997
998
999
10

12
13
14
15
16
17

86
87
88
89
90
91
92
93
94
95
96
97
98
99
11
1
2
3
4
5
6
7
8
9
UNITS CLOCK

UNITS Q0

UNITS Q1

UNITS Q2

UNITS Q3

TENS CLOCK

TENS Q0

TENS Q3
UP AT 80 UP AT 980
HUNDREDS
CLOCK
HUNDREDS Q0

HUNDREDS Q3
UP AT 800
DISABLE (DISABLES CLOCK WHEN HIGH)

OVERFLOW
MASTER
RESET
SCAN
OSCILLATOR
DIGIT SELECT 1
UNITS
DIGIT SELECT 2 TENS
DIGIT SELECT 3 HUNDREDS

Figure 1. 3–Digit Counter Timing Diagram (Reference Figure 3)

16 VDD
(a)
PULSE Q3 20 ns

1000
C tWL(cl)

999
GENERATOR Q2 CL 20 ns
90%
Q1 CL CLOCK 50%
10%
LE Q0 CL tPLH
O.F. CL tPHL 1/fcl
DIS DS1 CL BCD OUT 10% 90% 50% tPHL
DS2 tTLH tTHL
MR DS3 OVERFLOW 50%

8 VSS

tTLH
90%
VDD CLOCK 50%
(b) 10%
GENERATOR Q3 tsu trem
C
1 Q2 CL
Q1 CL LATCH 50%
GENERATOR
LE Q0 CL ENABLE
2 tPHL, tPLH
O.F. CL tsu
GENERATOR MR DS1 CL
3 BCD OUT 50%
DS2
DIS DS3
tPHL
VSS
MASTER RESET 50%

tWH(R)
Figure 2. Switching Time Test Circuits and Waveforms

MOTOROLA CMOS LOGIC DATA MC14553B

6–415
 OPERATING CHARACTERISTICS

The MC14553B three–digit counter, shown in Figure 3,
consists of three negative edge–triggered BCD counters
which are cascaded in a synchronous fashion. A quad latch
at the output of each of the three BCD counters permits stor-
age of any given count. The three sets of BCD outputs
(active high), after going through the latches, are time divi-
sion multiplexed, providing one BCD number or digit at a
time. Digit select outputs (active low) are provided for display
control. All outputs are TTL compatible.
An on–chip oscillator provides the low frequency scanning
clock which drives the multiplexer output selector. The fre-
quency of the oscillator can be controlled externally by a
capacitor between pins 3 and 4, or it can be overridden and
driven with an external clock at pin 4. Multiple devices can be
cascaded using the overflow output, which provides one
pulse for every 1000 counts.
The Master Reset input, when taken high, initializes the
three BCD counters and the multiplexer scanning circuit.
While Master Reset is high the digit scanner is set to digit
one; but all three digit select outputs are disabled to prolong
display life, and the scan oscillator is inhibited. The Disable
input, when high, prevents the input clock from reaching the
counters, while still retaining the last count. A pulse shaping
circuit at the clock input permits the counters to continue op-
erating on input pulses with very slow rise times. Information
present in the counters when the latch input goes high, will
be stored in the latches and will be retained while the latch
input is high, independent of other inputs. Information can be
recovered from the latches after the counters have been re-
set if Latch Enable remains high during the entire reset cycle.

C1A
LATCH ENABLE 4
10 SCAN PULSE
R C1
OSCILLATOR 3 GENERATOR
C1B
CLOCK
12 R SCANNER

Q0
PULSE C Q1 QUAD
SHAPER Q2 LATCH
R ÷ 10
Q3 9
UNITS Q0
11
DISABLE
(ACTIVE
HIGH) MULTIPLEXER
7
Q1
Q0
C BCD
Q1 QUAD OUTPUTS
Q2 LATCH (ACTIVE
R ÷ 10
Q3 HIGH)
TENS
6
Q2

5
Q0 Q3
C
Q1 QUAD
Q2 LATCH
R
÷ 10 Q3
HUNDREDS

13 14 2 1 15
MR OVERFLOW DS1 DS2 DS3
(ACTIVE HIGH) (LSD) DIGIT SELECT (MSD)
(ACTIVE LOW)

Figure 3. Expanded Block Diagram

MC14553B MOTOROLA CMOS LOGIC DATA

6–416
 MOTOROLA CMOS LOGIC DATA

STROBE
RESET

10 13 10 13
LE MR 4 LE MR 4
12 C1A 0.001 12 C1 A
CLOCK CLK CLK 3
INPUT 3 µF
C1B MC14553B C1 B
11 MC14553B 11 14
DIS 14 DIS
O.F. O.F.
Q3 Q2 Q1 Q0 DS3 DS2 DS1 Q3 Q2 Q1 Q0 DS3 DS2 DS1
5 6 7 9 15 1 2 5 6 7 9 15 1 2
5 9
A a
Figure 4. Six–Digit Display

3 10
B b
2 11
VDD C c
4 12
D MC14543B d
6 13
Ph e
VDD 1 15
LD f
7 g 14
BI

5 9
A a
3
B b 10
2 11
C c
4 12
D MC14543B d
6 13
Ph e
1 15
VDD LD f
7 14
BI g

LSD DISPLAYS ARE LOW CURRENT LEDs MSD

(I peak < 10 mA PER SEGMENT)
MC14553B
6–417
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14554B
2-Bit by 2-Bit Parallel
Binary Multiplier L SUFFIX
CERAMIC
The MC14554B 2 x 2–bit parallel binary multiplier is constructed with CASE 620
complementary MOS (CMOS) enhancement mode devices. The multiplier
can perform the multiplication of two binary numbers and simultaneously add
two other binary numbers to the product. The MC14554B has two P SUFFIX
multiplicand inputs (X0 and X1), two multiplier inputs (Y0 and Y1), five PLASTIC
cascading or adding inputs (K0, K1, M0, M1, and M2), and five sum and CASE 648
carry outputs (S0, S1, S2, C1 [S3], and C0). The basic multiplier can be
expanded into a straightforward m–bit by n–bit parallel multiplier without D SUFFIX
additional logic elements. SOIC
Application areas include arithmetic processing (multiplying/adding, CASE 751B
obtaining square roots, polynomial evaluation, obtaining reciprocals, and
dividing), Fast Fourier Transform processing, digital filtering, communica- ORDERING INFORMATION
tions (convolution and correlation), and process and machine controls. MC14XXXBCP Plastic
• Diode Protection on All Inputs MC14XXXBCL Ceramic
• All Outputs Buffered MC14XXXBD SOIC
• Straight–forward m–Bit By n–Bit Expansion TA = – 55° to 125°C for all packages.
• No Additional Logic Elements Needed for Expansion
• Multiplies and Adds Simultaneously
• Positive Logic Design This device contains protection circuitry to
• Supply Voltage Range = 3.0 Vdc to 18 Vdc guard against damage due to high static
voltages or electric fields. However, pre-
• Capable of Driving Two Low–Power TTL Loads or One Low–Power cautions must be taken to avoid applications of

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range any voltage higher than maximum rated volt-

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ages to this high–impedance circuit. For proper
MAXIMUM RATINGS* (Voltages Referenced to VSS)
operation, Vin and Vout should be constrained
Symbol Parameter Value Unit to the range VSS v (Vin or Vout)v VDD.
VDD DC Supply Voltage – 0.5 to + 18.0 V Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V or VDD). Unused outputs must be left open.
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package† 500 mW EQUATIONS
Tstg Storage Temperature – 65 to + 150 _C S = (X x Y) + K + M
Where:
TL Lead Temperature (8–Second Soldering) 260 _C x Means Arithmetic Times.
* Maximum Ratings are those values beyond which damage to the device may occur. + Means Arithmetic Plus.
†Temperature Derating: S = S3 S2 S1 S0, X = X1X0, Y = Y1Y0,
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C K = K1 K0, M = M1 M0 (Binary Numbers).
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Example:
Given: X = 2(1), Y = 3(11)
PIN ASSIGNMENT K = 1(01), M = 2(10)

Y1 1 16 VDD Then: S = (2 x 3) + 1 + 2 = 9
S = (10 x 11) + 01 + 10 = 1001
M0 2 15 Y0
M1 3 14 X0 NOTE: C0 connected to M2 for this size
multiplier. See general expansion
C0 4 13 X1 diagram for other size multipliers.
M2 5 12 K0
C1 (S3) 6 11 S0
S2 7 10 K1
VSS 8 9 S1

MC14554B MOTOROLA CMOS LOGIC DATA

6–418
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.0 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.0 µA/kHz) f + IDD
Per Package) 15 IT = (3.0 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0035.

MOTOROLA CMOS LOGIC DATA MC14554B

6–419
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
K0 to C0 tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 185 ns 5.0 — 270 675
tPLH, tPHL = (0.66 ns/pF) CL + 82 ns 10 — 115 290
tPLH, tPHL = (0.5 ns/pF) CL + 60 ns 15 — 85 215
M0 to S2
tPLH, tPHL = (1.7 ns/pF) CL + 595 ns 5.0 — 680 1700
tPLH, tPHL = (0.66 ns/pF) CL + 247 ns 10 — 280 750
tPLH, tPHL = (0.5 ns/pF) CL + 185 ns 15 — 210 570
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns

VDD
90%
50%
INPUT 10% VSS
20 ns 20 ns tPLH tPHL
K0 OR M0
VOH
90%
VDD 50%
90% 10% VOL
50% OUTPUT
ALL INPUTS 10% VSS C0 OR S2
(50% DUTY CYCLE) tTLH tTHL
1
2f For K0 to C0:
VOH
Inputs X0, X1, Y0, Y1, K1, and M2 low, and inputs
M0 and M1 high.
ANY OUTPUT VOL
(50% DUTY CYCLE) For M0 to S2:
All outputs connected to respective Inputs X1, Y1, and K0 low, and inputs X0, Y0,
CL loads. f = system clock frequency K1, M1, and M2 high.

Figure 1. Dynamic Power Dissipation Figure 2. Dynamic Signal Waveforms

Waveforms

LOGIC DIAGRAM

M1 Y1 M0 Y0

3 1 2 15
M Y M Y 14
X X0
MULTIPLIER MULTIPLIER X
4 CELL CELL 12
C0 C K C K K0 MULTIPLIER CELL
S S

5 S
M2 M
Y
M Y M Y 13 L
X1 X
X
MULTIPLIER MULTIPLIER X K C
CELL CELL 10
C K C K K1
S S

6 7 9 11
C1(S3) S2 S1 S0

MC14554B MOTOROLA CMOS LOGIC DATA

6–420
 EXPANSION DIAGRAM
m–Bit by n–Bit Parallel Binary Multiplier (Top View)

Y AND M

Y(n–1) Y3 Y1 Y1 VDD
M(n–2) Y(n–2) M2 Y2 M0 M0 Y0 Y0
M(n–1) X0 M3 X0 M1 M1 X0 X0
X1 X1 C0 X1 X1
M2 K0 K0
C1 S0
S2 K1 K1
VSS S1

Y(n–1) Y3 Y1
Y(n–2) Y2 Y0 X AND K
X2 X2 X2
X3 X3 X3
K2

K3

Y(n–1) Y3 Y1
Y(n–2) Y2 Y0
X(m–2) X(m–2) X(m–2)
X(m–1) X(m–1) X(m–1)
K(m–2)

K(m–1)

S(m + n–1) S(m + n–2) S(m + n–3) S(m+2) S(m+1) S(m) S(m–1) S3 S1
S(m–2) S2 S0
S = (X x Y) + K + M Where: x means Arithmetic Times.
S = (X x Y) + K + M Where: + means Arithmetic Plus.
S = S(m + n–1) S(m + n–2) … S2 S1 S0
X = X(m–1) X (m–2) … X2 X1 X0, Y = Y(n–1) Y(n–2) … Y2 Y1 Y0
K = K(m–1) K(m–2) … K2 K1 K0 and M = M(n–1) M(n–2) … M2 M1 M0
(Binary Numbers).
Number of output binary digits = m + n
Number of packages = mxn/4 (For m or n of both odd select next highest even number.)

MOTOROLA CMOS LOGIC DATA MC14554B

6–421
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14555B
MC14556B
Dual Binary to 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with complementary
L SUFFIX
MOS (CMOS) enhancement mode devices. Each Decoder/Demultiplexer
CERAMIC
has two select inputs (A and B), an active low Enable input (E), and four
CASE 620
mutually exclusive outputs (Q0, Q1, Q2, Q3). The MC14555B has the
selected output go to the “high” state, and the MC14556B has the selected
output go to the “low” state. Expanded decoding such as binary–to–hexade-
cimal (1–of–16), etc., can be achieved by using other MC14555B or P SUFFIX
PLASTIC
MC14556B devices.
CASE 648
Applications include code conversion, address decoding, memory selec-
tion control, and demultiplexing (using the Enable input as a data input) in
digital data transmission systems.
D SUFFIX
• Diode Protection on All Inputs SOIC
• Active High or Active Low Outputs CASE 751B
• Expandable
• Supply Voltage Range = 3.0 Vdc to 18 Vdc ORDERING INFORMATION
• All Outputs Buffered MC14XXXBCP Plastic
• Capable of Driving Two Low–Power TTL Loads or One Low–Power MC14XXXBCL Ceramic
MC14XXXBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range
TA = – 55° to 125°C for all packages.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit TRUTH TABLE
VDD DC Supply Voltage – 0.5 to + 18.0 V Inputs Outputs
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Enable Select MC14555B MC14556B

Iin, Iout Input or Output Current (DC or Transient), ± 10 mA E B A Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

per Pin 0 0 0 0 0 0 1 1 1 1 0
0 0 1 0 0 1 0 1 1 0 1
PD Power Dissipation, per Package† 500 mW 0 1 0 0 1 0 0 1 0 1 1
0 1 1 1 0 0 0 0 1 1 1
Tstg Storage Temperature – 65 to + 150 _C
1 X X 0 0 0 0 1 1 1 1
TL Lead Temperature (8–Second Soldering) 260 _C
X = Don’t Care
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: This device contains protection circuitry to
“P and D/DW” Packages: – 7.0 mW/C From 65_C To 125_C Ceramic guard against damage due to high static
“L” Packages: – 12 mW/_C From 100_C To 125_C voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
BLOCK DIAGRAM any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
MC14555B MC14556B
operation, Vin and Vout should be constrained

Q0 4 Q0 4
to the range VSS v
(Vin or Vout) VDD.v
2 A 2 A Unused inputs must always be tied to an
Q1 5 Q1 5 appropriate logic voltage level (e.g., either VSS
3 B 3 B
Q2 6 Q2 6 or VDD). Unused outputs must be left open.
1 E 1 E
Q3 7 Q3 7

14 A Q0 12 14 A Q0 12
Q1 11 Q1 11
13 B 13 B
Q2 10 Q2 10
15 E 15 E
Q3 9 Q3 9
VDD = PIN 16
VSS = PIN 8

MC14555B MC14556B MOTOROLA CMOS LOGIC DATA

6–422
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.85 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.70 µA/kHz) f + IDD
Per Package) 15 IT = (2.60 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENTS
MC14555B MC14556B
EA 1 16 VDD EA 1 16 VDD
AA 2 15 EB AA 2 15 EB
BA 3 14 AB BA 3 14 AB
Q0A 4 13 BB Q0A 4 13 BB
Q1A 5 12 Q0B Q1A 5 12 Q0B
Q2A 6 11 Q1B Q2A 6 11 Q1B
Q3A 7 10 Q2B Q3A 7 10 Q2B
VSS 8 9 Q3B VSS 8 9 Q3B

MOTOROLA CMOS LOGIC DATA MC14555B MC14556B

6–423
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time — A, B to Output tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPHL 5.0 — 220 440
tPLH, tPHL = (0.66 ns/pF) CL + 62 ns 10 — 95 190
tPLH, tPHL = (0.5 ns/pF) CL + 45 ns 15 — 70 140
Propagation Delay Time — E to Output tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 115 ns tPHL 5.0 — 200 400
tPLH, tPHL = (0.66 ns/pF) CL + 52 ns 10 — 85 170
tPLH, tPHL = (0.5 ns/pF) CL + 40 ns 15 — 65 130
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

INPUT E LOW
20 ns 20 ns INPUT A HIGH, INPUT E LOW
20 ns 20 ns
VDD
90%
50% VDD
90%
A INPUTS 10% VSS INPUT B 50%
1
(50% DUTY CYCLE) 10% VSS
2f VDD tPHL tPLH
90% VOH
OUTPUT Q3 50%
B INPUTS VSS
MC14556B 10%
(50% DUTY CYCLE) V
VOH tTHL tTLH OL
tPLH tPHL
VOH
OUTPUT Q1 VOL OUTPUT Q3 90%
50%
MC14555B 10% VOL
All 8 outputs connect to respective CL loads.
f in respect to a system clock. tTLH tTHL

Figure 1. Dynamic Power Dissipation Signal Waveforms Figure 2. Dynamic Signal Waveforms

LOGIC DIAGRAM
(1/2 of Dual)

* Q0

*
Q1

* Q2

* Q3

* Eliminated for MC14555B

MC14555B MC14556B MOTOROLA CMOS LOGIC DATA

6–424
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14557B
1-to-64 Bit Variable Length
Shift Register L SUFFIX
CERAMIC
The MC14557B is a static clocked serial shift register whose length may
CASE 620
be programmed to be any number of bits between 1 and 64. The number of
bits selected is equal to the sum of the subscripts of the enabled Length
Control inputs (L1, L2, L4, L8, L16, and L32) plus one. Serial data may be
P SUFFIX
selected from the A or B data inputs with the A/B select input. This feature is PLASTIC
useful for recirculation purposes. A Clock Enable (CE) input is provided to CASE 648
allow gating of the clock or negative edge clocking capability.
The device can be effectively used for variable digital delay lines or simply
to implement odd length shift registers. DW SUFFIX
SOIC
• 1–64 Bit Programmable Length CASE 751G
• Q and Q Serial Buffered Outputs
• Asynchronous Master Reset ORDERING INFORMATION
• All Inputs Buffered MC14XXXBCP Plastic
• No Limit On Clock Rise and Fall Times MC14XXXBCL Ceramic
• Supply Voltage Range = 3.0 Vdc to 18 Vdc MC14XXXBDW SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Capable of Driving Two Low–power TTL Loads or one Low–power TA = – 55° to 125°C for all packages.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit BLOCK DIAGRAM
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V 3 RESET
4 CLOCK
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
5 CE
per Pin 6 B Q 10
PD Power Dissipation, per Package† 500 mW 7 A
9 A/B SELECT
Tstg Storage Temperature – 65 to + 150 _C 2 L1
1 L2
TL Lead Temperature (8–Second Soldering) 260 _C 15 L4 Q 11
* Maximum Ratings are those values beyond which damage to the device may occur. 14 L8
13 L16
†Temperature Derating:
12 L32
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
VDD = PIN 16
LENGTH SELECT TRUTH TABLE VSS = PIN 8
L32 L16 L8 L4 L2 L1 Register Length
0 0 0 0 0 0 1 Bit TRUTH TABLE
0 0 0 0 0 1 2 Bits
Bit Inputs Output
0 0 0 0 1 0 3 Bits
0 0 0 0 1 1 4 Bits Rst A/B Clock CE Q
0 0 0 1 0 0 5 Bits 0 0 0 B
0 0 0 1 0 1 6 Bits 0 1 0 A
      
       0 0 1 B
      
0 1 1 A
1 0 0 0 0 0 Bit
33 Bits
1 0 0 0 0 1 34 Bits 1 X X X 0
       Q is the output of the first selected shift
      
       register stage.
1 1 1 1 0 0 61 Bits
X = Don’t Care
1 1 1 1 1 1 62 Bits
1 1 1 1 1 0 63 Bits
1 1 1 1 0 1 64 Bit
Bits
NOTE: Length equals the sum of the binary length control
subscripts plus one.

MOTOROLA CMOS LOGIC DATA MC14557B

6–425
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.010 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.020 10 — 300
15 — 20 — 0.030 20 — 600
Total Supply Current**† IT 5.0 IT = (1.75 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.50 µA/kHz) f + IDD
Per Package) 15 IT = (5.25 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14557B MOTOROLA CMOS LOGIC DATA

6–426
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Rise and Fall Time, Q or Q Output
Symbol
tTLH,
VDD Min Typ # Max Unit
ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay, Clock or CE to Q or Q tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPHL 5 — 300 600
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns 15 — 90 180
Propagation Delay, Reset to Q or Q tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPHL 5 — 300 600
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 70 ns 15 — 95 190
Pulse Width, Clock tWH(cl) 5 200 95 — ns
10 100 45 —
15 75 35 —
Pulse Width, Reset tWH(rst) 5 300 150 — ns
10 140 70 —
15 100 50 —
Clock Frequency (50% Duty Cycle) fcl 5 — 3.0 1.7 MHz
10 — 7.5 5.0
15 — 13.0 6.7
Setup Time, A or B to Clock or CE tsu ns
Worst case condition: L1 = L2 = L4 = L8 = 5 700 350 —
L16 = L32 = VSS (Register Length = 1) 10 290 130 —
15 145 85 —
Best case condition: L32 = VDD, L1 through L16 = 5 400 45 —
Don’t Care (Any register length from 33 to 64) 10 165 5 —
15 60 0 —
Hold Time, Clock or CE to A or B th ns
Best case condition: L1 = L2 = L4 = L8 = L16 = 5 200 – 150 —
L32 = VSS (Register Length = 1) 10 100 – 60 —
15 10 – 50 —
Worst case condition: L32 = VDD, L1 through L16 = 5 400 50 —
Don’t Care (Any register length from 33 to 64) 10 185 25 —
15 85 22 —
Rise and Fall Time, Clock tr, 5 —
tf 10 No Limit
15
Rise and Fall Time, Reset or CE tr, 5 — — 15 µs
tf 10 — — 5
15 — — 4
Removal Time, Reset to Clock or CE trem 5 160 80 — ns
10 80 40 —
15 70 35 —
* The formulas given are for the typical characteristics only at 25_C.
# Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
TIMING DIAGRAM
VDD
50%
CLOCK tWH(cl) VSS
1/fcl VDD
50%
A INPUT trem VSS
tsu
VDD
th 50%
RESET VSS
tTLH tTHL PWR
1–bit length: VOH
90%
CE = 0 50%
A/B = 1 Q 10% VOL
L1 = L2 = L4 = L8 = L16 = L32 = 0 tPLH tPHL tPHL

MOTOROLA CMOS LOGIC DATA MC14557B

6–427
6–428
MC14557B

5
CE
4
CLOCK
3
RESET

7 C R C R C R C R
A 32 BIT 16 BIT 8 BIT 4 BIT

6
B

A/B 9 12 13 14 15
SELECT L32 L16 L8 L4

LOGIC DIAGRAM
C R C R C R 10
Q
2 BIT 1 BIT 1 BIT

11
Q

1 2 VDD = PIN 16
L2 L1 VSS = PIN 8
CLOCK
RESET
MOTOROLA CMOS LOGIC DATA

VSS

CE

L2
L1

PIN ASSIGNMENT
A
B
8
7
6
5
4
3
2
1
12
13
14
15
16
10
11
9

L4
A/B SEL
Q
Q
L32
L16
L8

VDD
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14558B
BCD-to-Seven Segment
Decoder L SUFFIX
CERAMIC
The MC14558B decodes 4–bit binary coded decimal data dependent on CASE 620
the state of auxiliary inputs, Enable and RBI, and provides an active–high
seven–segment output for a display driver.
An auxiliary input truth table is shown, in addition to the BCD to P SUFFIX
PLASTIC
seven–segment truth table, to indicate the functions available with the two
CASE 648
auxiliary inputs.
Leading Zero blanking is easily obtained with an external flip–flop in time
division multiplexed systems displaying most significant decade first. D SUFFIX
SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
CASE 751B
• Segment Blanking for All Illegal Input Combinations
• Lamp Test Function ORDERING INFORMATION
• Capability for Suppression of Non–Significant Zeros
MC14XXXBCP Plastic
• Lamp Intensity Function MC14XXXBCL Ceramic
• Capable of Driving Two Low–power TTL Loads. One Low–power MC14XXXBD SOIC
Schottky TTL Load or Two HTL Loads Over the Rated Temperature TA = – 55° to 125°C for all packages.
Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages referenced to VSS)

DC Supply Voltage
Rating Symbol
VDD
Value
– 0.5 to + 18
Unit
V
PIN ASSIGNMENT
B 1 16 VDD
C 2 15 f
Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 V
ENABLE 3 14 g a
DC Input Voltage, per Pin Iin ± 10 mAdc
RBO 4 13 a f g b
Operating Temperature Range TA – 55 to + 125 _C
RBI 5 12 b e c
Power Dissipation, per Package† PD 500 mW d
D 6 11 c
Storage Temperature Range Tstg – 65 to + 150 _C
A 7 10 d
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: VSS 8 9 e
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
DISPLAY
AUXILIARY INPUT TRUTH TABLE
BCD 0 1 2 3 4 5 6 7 8 9
Enable RBI Input RBO
Pin 3 Pin 5 Code Pin 4 Function Performed
0 0 X 0 Lamp Test
0 1 X 1 Blank Segments
1 1 0 1 Display Zero
1 0 0 0 Blank Segments
1 X 1–9 1 1–9 Displayed
X = Don’t Care
RBI = Ripple Blanking Input
RBO = Ripple Blanking Output

MOTOROLA CMOS LOGIC DATA MC14558B

6–429
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) Vin = 0 or VDD 10 — 10 — 0.010 10 — 300
Iout = 0 µA 15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.2 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.4 µA/kHz) f + IDD
Per Package) 15 IT = (3.6 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.
** The formulas given are for the typical characteristics only at 25_C.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however,
it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or
Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).

MC14558B MOTOROLA CMOS LOGIC DATA

6–430
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C; see Figure 1)
Characteristic Symbol VDD Min Typ Max Unit
Output Rise Time tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 100 200
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 50 100
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 40 80
Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH ns
tPLH = (1.7 ns/pF) CL + 495 ns 5.0 — 580 1160
tPLH = (0.66 ns/pF) CL + 187 ns 10 — 220 440
tPLH = (0.5 ns/pF) CL + 120 ns 15 — 145 230
Propagation Delay Time tPHL ns
tPHL = (1.7 ns/pF) CL + 695 ns 5.0 — 780 1560
tPHL = (0.66 ns/pF) CL + 242 ns 10 — 275 550
tPHL = (0.5 ns/pF) CL + 160 ns 15 185 370
* The formulae given are for the typical characteristics only.

TRUTH TABLE
Inputs Outputs*
Enable RBI D C B A a b c d e f g RBO
Pin 3 Pin 5 Pin 6 Pin 2 Pin 1 Pin 7 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 15 Pin 14 Pin 4 Display

1 1 0 0 0 0 1 1 1 1 1 1 0 1

1 X 0 0 0 1 0 0 0 0 1 1 0 1

1 X 0 0 1 0 1 1 0 1 1 0 1 1

1 X 0 0 1 1 1 1 1 1 0 0 1 1

1 X 0 1 0 0 0 1 1 0 0 1 1 1

1 X 0 1 0 1 1 0 1 1 0 1 1 1

1 X 0 1 1 0 0 0 1 1 1 1 1 1

1 X 0 1 1 1 1 1 1 0 0 0 0 1

1 X 1 0 0 0 1 1 1 1 1 1 1 1

1 X 1 0 0 1 1 1 1 0 0 1 1 1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 Blank

0 0 X X X X 1 1 1 1 1 1 1 0

0 1 X X X X 0 0 0 0 0 0 0 1 Blank
* All non–valid BCD input codes produce a blank display.
X = Don’t Care

20 ns 20 ns

ANY INPUT 90%

10% 50%
tPLH tPHL

50% 90%
ANY OUTPUT 10%

tTLH tTHL

Figure 1. Signal Waveforms

MOTOROLA CMOS LOGIC DATA MC14558B

6–431
 LOGIC DIAGRAM

g
c

RBO
f
13

12

10

15

14
11

4
3

6
ENABLE

RBI

D
A

MC14558B MOTOROLA CMOS LOGIC DATA

6–432
 TYPICAL APPLICATIONS

N4 N3 N2 N1 N–1 N–2 N–3

VSS RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO

En En En En En En En
VSS
LAMP TEST

Figure 2. Leading and Trailing Zero

Suppression with Lamp Test

N4 N3 N2 N1 N–1 N–2 N–3

VDD

RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO

En En En En En En En
BLANKING

Figure 3. Leading and Trailing Zero Suppression

with PWM Intensity Blanking and No Lamp Test

N4 N3 N2 N1 N–1 N–2 N–3

RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO

En En En En En En En

BLANKING

LAMP TEST

Figure 4. Zero Suppression with Lamp Test

and Intensity Blanking

MOTOROLA CMOS LOGIC DATA MC14558B

6–433
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14560B
NBCD Adder
The MC14560B adds two 4–bit numbers in NBCD (natural binary coded L SUFFIX
decimal) format, resulting in sum and carry outputs in NBCD code. CERAMIC
CASE 620
This device can also subtract when one set of inputs is complemented with
a 9’s Complementer (MC14561B).
All inputs and outputs are active high. The carry input for the least
P SUFFIX
significant digit is connected to VSS for no carry in. PLASTIC
• Diode Protection on All Inputs CASE 648
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power D SUFFIX

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range SOIC
CASE 751B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
ORDERING INFORMATION
MC14XXXBCP Plastic
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBCL Ceramic
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package† 500 mW
BLOCK DIAGRAM
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C 7 Cin S1 13
* Maximum Ratings are those values beyond which damage to the device may occur. 15 A1
†Temperature Derating: 14 B1 S2 12
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C A2
1
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C B2 S3
2 11
3 A3
TRUTH TABLE* 4 B3 S4 10
Input Output 5 A4
6 B4 Cout 9
A4 A3 A2 A1 B4 B3 B2 B1 Cin Cout S4 S3 S2 S1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
VDD = PIN 16
0 0 0 0 0 0 0 0 1 0 0 0 0 1
VSS = PIN 8
0 1 0 0 0 0 1 1 0 0 0 1 1 1
0 1 0 0 0 0 1 1 1 0 1 0 0 0
0 1 1 1 0 1 0 0 0 1 0 0 0 1
0 1 1 1 0 1 0 0 1 1 0 0 1 0
1 0 0 0 0 1 0 1 0 1 0 0 1 1
0 1 1 0 1 0 0 0 0 1 0 1 0 0
1 0 0 1 1 0 0 1 1 1 1 0 0 1
* Partial truth table to show logic operation for representative input values.

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MC14560B MOTOROLA CMOS LOGIC DATA

6–434
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.68 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.35 µA/kHz) f + IDD
Per Package) 15 IT = (5.03 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.

PIN ASSIGNMENT
A2 1 16 VDD
B2 2 15 A1
A3 3 14 B1
B3 4 13 S1
A4 5 12 S2
B4 6 11 S3
Cin 7 10 S4
VSS 8 9 Cout

MOTOROLA CMOS LOGIC DATA MC14560B

6–435
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, tTHL ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, tPHL ns
A or B to S
tPLH, tPHL = (1.7 ns/pF) CL + 665 ns 5.0 — 750 2100
tPLH, tPHL = (0.66 ns/pF) CL + 297 ns 10 — 330 900
tPLH, tPHL = (0.5 ns/pF) CL + 195 ns 15 — 220 675
A or B to Cout ns
tPLH, tPHL = (1.7 ns/pF) CL + 565 ns 5.0 — 650 1800
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns 10 — 230 600
tPLH, tPHL = (0.5 ns/pF) CL + 145 ns 15 — 170 450
Cin to Cout ns
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns 5.0 — 550 1500
tPLH, tPHL = (0.66 ns/pF) CL + 187 ns 10 — 220 600
tPLH, tPHL = (0.5 ns/pF) CL + 135 ns 15 — 160 450
Turn–Off Delay Time tPLH ns
Cin to S
tPLH = (1.7 ns/pF) CL + 715 ns 5.0 — 800 2250
tPLH = (0.66 ns/pF) CL + 197 ns 10 — 350 975
tPLH = (0.5 ns/pF) CL + 215 ns 15 — 240 750
Turn–On Delay Time tPHL ns
Cin to S
tPHL = (1.7 ns/pF) CL + 565 ns 5.0 — 650 1800
tPHL = (0.66 ns/pF) CL + 197 ns 10 — 230 600
tPHL = (0.5 ns/pF) CL + 145 ns 15 — 170 450
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns
VDD
90% 20 ns 20 ns
ALL INPUTS 50% VDD
10% VSS 90%
1 ANY INPUT 50%
2f 10% VSS

tPLH tPHL
VOH
ANY OUTPUT
VOL VOH
90%
50%
Duty Cycle = 50% ANY OUTPUT
10%
VOL
All outputs connected to respective CL loads
f = System clock frequency tTLH tTHL

Figure 1. Power Dissipation Waveforms Figure 2. Switching Time Waveforms

MC14560B MOTOROLA CMOS LOGIC DATA

6–436
 FUNCTIONAL EQUIVALENT LOGIC DIAGRAM

7
Cin
15 13
A1 S1

14
B1 12
S2
1
A2

2
B2
11
S3
3
A3

4 10
B3 S4
5
A4
9
6 Cout
B4

VDD = PIN 16
VSS = PIN 8

ADD/SUBTRACT
MC14561B
A1 F1
MC14560B
A2
A1
A3 F2 Cin S1
A4 A1
COMP F3 A2 S2
COMP A3 UNITS
ZERO Z F4 A4 S3
B1
One MC14560B and MC14561B permit a
B2 S4
BCD digit to be added to or subtracted from B1
B3
a second digit, such as in this typical config-
B4 Cout
uration. A second MC14561B permits either
digit to be added to or subtracted from the MC14561B
other, or either word to appear unmodified at
the output. A1 F1
MC14560B
A2
A10
A3 F2 Cin S1
TRUTH TABLE
A4 A1
Zero Add/Subtract Result COMP F3 A2 S2
0 0 B plus A COMP A3 TENS
Z F4 A4 S3
0 1 B minus A
B1
1 X B
B2 S4
X = Don’t Care B10 B3
B4 Cout

Figure 3. Parallel Add/Subtract Circuit

MOTOROLA CMOS LOGIC DATA MC14560B

6–437
 APPLICATIONS INFORMATION
INTRODUCTION
Frequently in small digital systems, simple decimal arith-
metic is performed. Decimal data enters and leaves the sys-
tem arithmetic unit in a binary coded decimal (BCD) format.
The adder/subtracter in the arithmetic unit may be required
to accept sign as well as magnitude, and generate sign,
magnitude, and overflow. In the past, it has been cumber-
some to build sign and magnitude adder/subtracters. Now,
using Motorola’s MSI CMOS functions, the MC14560 NBCD
Adders and MC14561 9’s Complementers, NBCD adder/
subtracters may be built economically, with surprisingly low
package count and moderate speed.
Some background information on BCD arithmetic is pres-
ented here, followed by simple circuits for unsigned adder/
subtracters. The final circuit discussed is an adder/subtracter
for signed numbers with complete overflow and sign correc-
tion logic.
DECIMAL NUMBER REPRESENTATION
Because logic elements are binary or two–state devices,
decimal digits are generally represented as a group of bits in
a weighted format. There are many possible binary codes
which can be used to represent a decimal number. One of
the most popular codes using 4 binary digits to represent 0
thru 9 is Natural Binary Coded Decimal (NBCD or 8–4–2–1
code).
NBCD is a weighted code. If a value of “0” or “1” is as-
signed to each of the bit positions, where the rightmost posi-
tion is 20 and the leftmost is 23, and the values are summed
for a given code, the result is equal to the decimal digit repre-
sented by the code. Thus, 0110 equals 0@23 + 1@22 + 1@21 +
0@20 = 4 + 2 = 6. The 1010, 1011, 1100, 1101, 1110, and 1111
binary codes are not used. Because of these illegal states,
the addition and subtraction of NBCD numbers is more com-
plex than similar calculations on straight binary numbers.
ADDITION OF UNSIGNED NBCD NUMBERS
When 2 NBCD digits, A and B, and a possible carry, C, are
added, a total of 20 digit sums (A + B + C) are possible as
shown in Table 1.
The binary representations for the digit sums 10 thru 19
are offset by 6, the number of unused binary states, and are
not correct. An algorithm for obtaining the correct sum is
shown in Figure 1. A conventional method of implementing
the BCD addition algorithm is shown in Figure 2(a). The
NBCD digits, A and B, are summed by a 4 bit binary full ad-
der. The resultant (sum and carry) is input to a binary/BCD
code converter which generates the correct BCD code and
carry.
An NBCD adder block which performs the above function
is available in a single CMOS package (MC14560).
MC14560B
6–438
Figure 2(b) shows n decades cascaded for addition of n digit
unsigned NBCD numbers. Add time is typically 0.1 + 0.2n µs
for n decades. When the carry out of the most significant de-
cade is a logical “1”, an overflow is indicated.
COMPLEMENT ARITHMETIC
Complement arithmetic is used in NBCD subtraction. That
is, the “complement” of the subtrahend is added to the minu-
end. The complementing process amounts to biasing the
subtrahend such that all possible sums are positive. Consid-
er the subtraction of the NBCD numbers, A and B:
R=A–B
where R is the result. Now bias both sides of the equation
by 10N – 1 where N is the number of digits in A and B.
R + 10N – 1 A – B + 10N – 1
Rearranging,
R + 10N – 1 A + (10N – 1 – B)
The term (10N – 1 – B), – B biased by 10N – 1, is known as
the 9’s complement of B. When A > B, R + 10N – 1 > 10N – 1;
thus R is a positive number. To obtain R, 1 is added to R +
10N – 1, and the carry term, 10N, is dropped. The addition of
1 is called End Around Carry (EAC).
When A < B, R + 10N – 1 < 10N – 1, no EAC results and R
is a negative number biased by 10N – 1; thus R + 10N – 1 is
the 9’s complement of R.
SUBTRACTION OF UNSIGNED NBCD NUMBERS
Nine’s complement arithmetic requires an element to per-
form the complementing function. An NBCD 9’s comple-
menter may be implemented using a 4 bit binary adder and 4
inverters, or with combinatorial logic. The Motorola MC14561
9’s complementer is available in a single package. It has true
and inverted complement disable, which allow straight–
through or complement modes of operation. A “zero” line
forces the output to “0”. Figure 3 shows an NBCD subtracter
block using the MC14560 and MC14561. Also shown are n
cascaded blocks for subtraction of n digit unsigned numbers.
Subtract time is 0.6 + 0.4n µs for n stages. Underflow (bor-
row) is indicated by a logical “0” on the carry output of the
most significant digit. A “0” carry also indicates that the differ-
ence is a negative number in 9’s complement form. If the re-
sult is input to a 9’s complementer, as shown, and its mode
controlled by the carry out of the most significant digit, the
output of the complementer will be the correct negative mag-
nitude. Note that the carry out of the most significant digit
(MSD) is the input to carry in of the least significant digit
(LSD). This End Around Carry is required because subtrac-
tion is done in 9’s complement arithmetic.
By controlling the complement and overflow logic with an
add/subtract line, both addition and subtraction are per-
formed using the basic subtracter blocks (Figure 4).
MOTOROLA CMOS LOGIC DATA
 Table 1. Sum = A + B + C ADDITION AND SUBTRACTION OF SIGNED NBCD
Decimal Corrected NUMBERS
Binary Sums Numbers Binary Sums
Using MC14560 NBCD Adders and MC14561 9’s Comple-
0000 0 0000
0001 1 0001
menters, a sign and magnitude adder/subtracter can be con-
0010 2 0010 figured (Figure 5). Inputs A and B are signed positive (AS, BS
0011 3 0011 = “0”) or negative (AS, BS = “1”). B is added to or subtracted
0100 4 0100 from A under control of an Add/Sub line (subtraction = “1”).
0101 5 0101 The result, R, of the operation is positive signed, positive
0110 6 0110 signed with overflow, negative signed, or negative signed
0111 7 0111 with overflow. Add/subtract time is typically 0.6 + 0.4n µs for
1000 8 1000 n decades.
1001 9 1001 An exclusive–OR of Add/Sub line and BS produces B′,
1010 10 0000 + Carry
which controls the B complementers. If BS, the sign of B, is a
1011 11 0001 + Carry
1100 Non valid 12 0010 + Carry
logical “1” (B is negative) and the Add/Sub line is a “0” (add
1101 BCD 13 0011 + Carry B to A), then the output of the exclusive–OR (BS′) is a logical
1110 representation 14 0100 + Carry “1” and B is complemented. If BS = “1” and Add/Sub = “1”, B
1111 15 0101 + Carry is not complemented since subtracting a negative number is
0000 + Carry 16 0110 + Carry the same as adding a positive number. When Add/Sub is a
0001 + Carry 17 0111 + Carry “1” and BS = “0”, BS′ is a “1” and B is complemented. The A
0010 + Carry 18 1000 + Carry complementer is controlled by the A sign bit, AS. When AS =
0011 + Carry 19 1001 + Carry “1”, A is complemented.

THOUSANDS HUNDREDS TENS UNITS

6,941 0110 1001 0100 0001
+
5,870 0101 1000 0111 0000

ADDER ADDER ADDER ADDER

1 1 0
4 BIT BINARY ADDERS Cin Cin Cin

DIGIT BINARY SUMS

1011 1 0001 1011 0001
BINARY SUMS WITH 1100 1 0010 1011 0001
CARRY FROM CONVERTERS

CODE CONVERTERS
Cout Cout Cout Cout
CORRECTED SUM
12,811
1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1

Figure 4. Unsigned NBCD Addition Algorithm

A B

A1 B1 A2 B2 An Bn

Cin 4 BIT BINARY FULL ADDER

Cin Cout Cin Cout Cin Cout

MC14560 MC14560 MC14560
BINARY TO NBCD
Cout OVERFLOW
CODE CONVERTER
R1 R2 Rn
Typical Add Time = 0.1 + 0.2n µs
where n = Number of Decades
RESULT, R
(a) MC14560 Block Diagram (b) n–Decade Adder

Figure 5. Addition of Unsigned NBCD Numbers

MOTOROLA CMOS LOGIC DATA MC14560B

6–439
 The truth table and Karnaugh maps for sign, overflow, and
End Around Carry are shown in Figures 6 and 7. Note the
use of BS′ from the exclusive–OR of Add/Sub and BS. BS′
eliminates Add/Sub as a variable in the truth table. As an ex-
ample of truth table generation, consider an n decade adder/
subtracter where AS = “0”, BS = “1”, and Add/Sub = “0”. B is
in 9’s complement form, 10N – 1 – B. Thus A + (10N – 1 – B)
= 10N – 1 + (A – B). There is no carry when A v
B, and the
sign is negative (sign = “1”). When AS and BS are opposite
states and Add/Sub is a “0” (add mode), no overflow can oc-
cur (overflow = “0”). The other output states are determined
in a similar manner (see Figure 6).
From the Karnaugh maps it is apparent that End Around
Carry is composed of the two symmetrical functions S2 and
S3 of three variables with AS BS′ Cout as the center of sym-
metry. This is the definition of the majority logic function
M3(ABC). Similarly the Sign is composed of the symmetrical
functions S2(3) and S3(3) but with the center of symmetry
translated to ASBS′ Cout. This is equivalent to the majority
function M3(ASBS′ Cout). Further evaluation of the maps and
truth table reveal that Overflow can be generated by the
exclusive–OR function of End Around Carry and Carry Out.
This analysis results in a minimum device count consisting of
one exclusive–OR package and one dual Majority Logic
package to implement BS′, EAC, Sign and Overflow. The
logic connections of these devices are shown in Figure 5.
The output sign, RS, complements the result of the add/
subtract operation when RS = “1”. This is required because
the adder performs 9’s complement arithmetic. Complement-
ing, when RS indicates the result is negative, restores sign
and magnitude convention.
Several variations of the adder/subtracter are possible.
For example, 9’s complement is available at the output of the
NBCD adders, and output complementers are eliminated if
sign and magnitude output is not required.

A B

A1 A2 A3 A4
VDD C

C MC14561

Z
F1 F2 F3 F4

A1 A2 A3 A4 B1 B2 B3 AB
Cn Cin MC14560 Cout Cn + 1
S1 S2 S3 S4

A1 A2 A3 A4
VDD C
FROM Cout
OF MOST SIGNIFICANT C MC14561
DECADE
Z
F1 F2 F3 F4

RESULT, R
(a) Basic Subtracter Block

A1 B1 A2 B2 An Bn
LEAST MOST
SIGNIFICANT SIGNIFICANT
DECADE DECADE
BASIC
Cin C Cin Cout Cin
SUBTRACT out Cout
C BLOCK C C
R1

R1 R2 Rn “0” INDICATES
UNDERFLOW
Typical Subtract Time = 0.6 + 0.4n µs where n = Number of Decades (NEGATIVE RESULT)

(b) n–Decade Subtracter

Figure 6. Subtraction of Unsigned NBCD Numbers

MC14560B MOTOROLA CMOS LOGIC DATA

6–440
SUMMARY
The concepts of binary code representations for decimal
numbers, addition, and complement subtraction were dis-
cussed in detail. Using the basic Adder and Complementer
MSI blocks, adder/subtracters for both signed and unsigned
numbers were illustrated with examples.
REFERENCES
1. Chu, Y.: Digital Computer Design Fundamentals, New
York, McGraw–Hill, 1962.
2. McMOS Handbook, Motorola Inc., 1st Edition.
3. Beuscher, H.: Electronic Switching Theory and Circuits,
New York, Van Nostrand Reinhold, 1971.
4. Garrett, L.: CMOS May Help Majority Logic Win De-
signer’s Vote, Electronics, July 19, 1973.
5. Richards, R.: Digital Design, New York, Wiley–
Interscience, 1971.

A1 B1 A2 B2 An Bn

LSD MSD
Cin BASIC Cout Cin Cout Cin
SUBTRACT Cout
C BLOCK C C

R1 R2 Rn

1/6 MC14572
ADD/SUBTRACT
(“1”/“0”) OVERFLOW = “1”

1/6 MC14572
UNDERFLOW = “1”
(NEGATIVE RESULT)

Typical Add/Subtract Time = 0.6 + 0.4 n µs

where n = Number of Decades

Figure 7. Adder/Subtracter for Unsigned NBCD Numbers

MOTOROLA CMOS LOGIC DATA MC14560B

6–441
6–442
MC14560B

A1 B1 A2 B2 An Bn

A1 A2 A3 A4 A1 A2 A3 A4
C C
C MC14561 C MC14561 MC14561 MC14561 MC14561 MC14561
Z Z
F1 F2 F3 F4 F1 F2 F3 F4
Figure 8. Sign and Magnitude Adder/Subtracter with Overflow

A1 A2 A3 A4 B1 B2 B3 B4
Cin MC14560 Cout MC14560 MC14560 Cout
S1 S2 S3 S4

A1 A2 A3 A4
C
MC14561 MC14561
C MC14561
Z
F1 F2 F3 F4

R2 Rn
R1 EAC
Cout

AS A
1/4 MC14070
1/4 MC14070 B
BS M5 Z OVERFLOW
C W
B S′
MOTOROLA CMOS LOGIC DATA

ADD/SUB
D
E

MC14530 VDD
1/4 MC14070 A
B Z
W SIGN OF RS
C M5 SIGN
VDD D
E Typical Add/Subtract Time = 0.6 + 0.4n µ s
where n = Number of Decades
 Arithmatic Expression
Inputs for R* (Result) Outputs
(N = N mber of Digits
Number Digits,
10N = Modulus End Around
AS BS′ Coutt A B,
A, B R are Positive Carry (EAC) Sign of R Overflow
“1” = Neg “1” = Neg “1” = Carry Magnitudes) “1” = EAC “1” = Negative “1” = Overflow
No EAC (“0”) Since A and B are When Cout = “0”, there
0 0 0 R=A+8 because R is correct positive signed, R is is no carry (R < 10N)
result. positive signed (“0”). and thus no overflow
(“0”).
When Cout = “1”, there
0 0 1 is a carry (R ≥ 10N)
and thus overflow
(“1”).
No EAC (“0”) A v B when Cout =
0 1 0 R=A–B because 9’s “0”; thus sign of R
= A + (10N – 1 – B) complement must be negative
= A – B + 10N – 1 expression for R is (“1”).
correct result.
EAC = “1” because A > B when Cout =
0 1 1 expression for R is in “1”; thus sign of R
error by 1. must be positive There is never an
(“0”). overflow when
No EAC (“0”) B v A when Cout = numbers of opposite
sign are added.
1 0 0 R=B–A because 9’s “0”; thus sign of R
= B + (10N – 1 – A) complement must be negative
= B – A + 10N – 1 expression for R is (“1”).
correct result.
EAC = “1” because B > A when Cout =
1 0 1 expression for R is in “1”; thus sign of R
error by 1. must be positive
(“0”).
EAC = “1” because Since A and B are When Cout = “0”, there
1 1 0 R=–A–B 9’s complement negative signed. R is is no Carry (R < 0N)
= (10N – 1 – A) + expression for R is in negative signed (“1”). and (A + B) > 10N – 1
(10N – 1 – B) error by 1. indicating overflow
= – (A + B) + 2 x (“1”).
10N – 2
When Cout = “1”, there
1 1 1 is a carry (R ≥ 10N)
and (A + B) v 10N – 1
indicating no overflow
(“0”).
* Output of Adders
Figure 9. Truth Table Generation for EAC, Sign, and Overflow Logic

MOTOROLA CMOS LOGIC DATA MC14560B

6–443
 TRUTH TABLE KARNAUGH MAPS
Inputs Outputs
End Around Carry Sign (SGN) Overflow (OVF)
AS BS′ Cout EAC SGN OVF AS AS AS
0 0 0 0 0 0 0 1 1 1 0 1
BS′ BS′ BS′
0 1 0 0 1 0 1 1 0 1 0 0
Cout Cout Cout
1 0 0 0 1 0 0 1 0* 0 1 0
0* 0 0 1 0 0
1 1 0 1 1 1
* = Center of Symmetry
0 0 1 0 0 1
EAC = S2 (ASBS′ Cout) + S3 (ASBS′ Cout)
0 1 1 1 0 0 = M3 (ASBS′ Cout)
1 0 1 1 0 0 SGN = S2 (ASBS′ Cout) + S3 (ASBS′ Cout)
= M3 (ASBS′ Cout)
1 1 1 1 1 0
BS = (Add/Sub) ę BS
AS = Sign of A (“1” = Negative) EAC ę Cout = OVF
BS = Sign of B (“1” = Negative)
Cout = Adder Carry Out 0 1 0 0 0 1
1
0
1
1
ę 1
1
1
1
=
0
1
0
0
0 0 0 0 0 0

Figure 10. Mapping of EAC, Sign and Overflow Logic

MC14560B MOTOROLA CMOS LOGIC DATA

6–444
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14561B

9's Complementer
L SUFFIX
The MC14561B 9’s complementer is a companion to the MC14560B CERAMIC
NBCD adder to allow BCD subtraction. A BCD number (8–4–2–1 code) is CASE 632
applied to the inputs (A1 = 20, A2 = 21, A3 = 22, A4 = 23). If the complement
control (Comp) is low, the BCD number appears at the outputs unmodified.
The complement disable (Comp) allows the complement control to be gated, P SUFFIX
or an inverted control signal to be used. If the complement input is high and PLASTIC
the disable input low, the 9’s complement of the number is displayed at the CASE 646
outputs. The zero control (Z), when high, forces the outputs low regardless of
the state of the other inputs.
D SUFFIX
When the MC14561B is used to perform BCD subtraction in conjunction
SOIC
with the MC14560B NBCD adder, the complement control becomes an CASE 751A
add/subtract control.
• All Inputs Buffered ORDERING INFORMATION
• Supply Voltage Range = 3.0 Vdc to 18 Vdc MC14XXXBCP Plastic
• Capable of Driving Two Low–Power TTL Loads or One Low–Power MC14XXXBCL Ceramic
Schottky TTL Load Over the Rated Temperature Range MC14XXXBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V PIN ASSIGNMENT
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V A1 1 14 VDD
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA A2 2 13 F1
per Pin A3 3 12 F2
PD Power Dissipation, per Package† 500 mW A4 4 11 F3
Tstg Storage Temperature – 65 to + 150 _C COMP 5 10 F4
TL Lead Temperature (8–Second Soldering) 260 _C COMP 6 9 Z
* Maximum Ratings are those values beyond which damage to the device may occur. VSS 7 8 NC
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C NC = NO CONNECTION
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

TRUTH TABLE
This device contains protection circuitry to
Z Comp Comp F1 F2 F3 F4 Mode guard against damage due to high static
voltages or electric fields. However, pre-
0 0 0
cautions must be taken to avoid applications of
0 0 1 A1 A2 A3 A4 Straight–through any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
0 1 1 operation, Vin and Vout should be constrained
0 1 0 A1 A2 A2A3 + A2A3 A2A3A4 Complement to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an
1 X X 0 0 0 0 Zero appropriate logic voltage level (e.g., either VSS
X = Don’t Care. or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA MC14561B

6–445
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.5 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.0 µA/kHz) f + IDD
Per Package) 15 IT = (4.5 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

MC14561B MOTOROLA CMOS LOGIC DATA

6–446
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPHL 5.0 — 400 1000
tPLH, tPHL = (0.66 ns/pF) CL + 127 ns 10 — 160 400
tPLH, tPHL = (0.5 ns/pF) CL + 95 ns 15 — 120 300
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns
VDD
90%
ANY INPUT 50%
10% VSS
tPLH tPHL
VOH
90%
50%
ANY OUTPUT 10%
VOL

tTLH tTHL

Figure 1. Switching Time Waveforms

MOTOROLA CMOS LOGIC DATA MC14561B

6–447
 LOGIC DIAGRAM

A1
F1
1
13

A2
F2
2
12

F3
11
A3
3

F4
10
A4
4

COMP
5
COMP VDD = PIN 14
6 VSS = PIN 7
Z
9

TRUTH TABLE – COMPLEMENT MODE

(Z = 0, Comp = 1, Comp = 0)
Decimal Inputs Decimal Outputs
Equivalent
Eq ivalent Equivalent
Eq ivalent
Input A4 A3 A2 A1 Output F4 F3 F2 F1
0 0 0 0 0 9 1 0 0 1
1 0 0 0 1 8 1 0 0 0
2 0 0 1 0 7 0 1 1 1
3 0 0 1 1 6 0 1 1 0
4 0 1 0 0 5 0 1 0 1
5 0 1 0 1 4 0 1 0 0
6 0 1 1 0 3 0 0 1 1
7 0 1 1 1 2 0 0 1 0
8 1 0 0 0 1 0 0 0 1
9 1 0 0 1 0 0 0 0 0
10 1 0 1 0 7 0 1 1 1
Illegal 11 1 0 1 1 6 0 1 1 0
BCD 12 1 1 0 0 5 0 1 0 1
Input 13 1 1 0 1 4 0 1 0 0
Codes 14 1 1 1 0 3 0 0 1 1
15 1 1 1 1 2 0 0 1 0

MC14561B MOTOROLA CMOS LOGIC DATA

6–448
 TYPICAL APPLICATIONS

One MC14560B and one MC14561B permit a BCD digit to MC14561B permits either digit to be added to or subtracted
be added to or subtracted from a second digit, such as in from the other, or either word to appear unmodified at the
the typical configurations in Figures 2 and 3. A second output.

ADD/SUBTRACT

MC14561B

A1 F1
MC14560B
A2
A1
A3 F2 Cin S1
A4 A1
COMP F3 A2 S2
COMP A3
UNITS
ZERO Z F4 A4 S3
B1
B2 S4
B1
B3
Cout

MC14561B

A1 F1
MC14560B
A2
A10
A3 F2 Cin S1
A4 A1
COMP F3 A2 S2

COMP A3 TENS
Z F4 A4 S3
B1
B2 S4
B10 B3
B4 Cout

TRUTH TABLE
Zero Add/Subtract Result
0 0 B plus A
0 1 B minus A
1 X B
X = Don’t Care

Figure 2. Parallel Add/Subtract Circuit (10’s Complement)

MOTOROLA CMOS LOGIC DATA MC14561B

6–449
 TYPE D
FLIP–FLOP

D Q

C
ADD/SUBTRACT
A REGISTER
MC14561B
A1 F1
MC14560B
A2
100’s 10’s 1’s A3 F2 Cin S1
A4 A1
COMP F3 A2 S2
COMP A3 RESULT
Z F4 A4 S3
CLOCK B1
B2 S4
100’s 10’s 1’s B3
B4 Cout

B REGISTER

Figure 3. Serial Add/Subtract Circuit

MC14561B MOTOROLA CMOS LOGIC DATA

6–450
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14562B
128-Bit Static Shift Register
L SUFFIX
The MC14562B is a 128–bit static shift register constructed with MOS CERAMIC
P–channel and N–channel enhancement mode devices in a single CASE 632
monolithic structure. Data is clocked in and out of the shift register on the
positive edge of the clock input. Data outputs are available every 16 bits,
from 16 through bit 128. This complementary MOS shift register is primarily P SUFFIX
used where low power dissipation and/or high noise immunity is desired. PLASTIC
• Diode Protection on All Inputs CASE 646

• Fully Static Operation

• Cascadable to Provide Longer Shift Register Lengths D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
CASE 751A
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
MAXIMUM RATINGS* (Voltages Referenced to VSS)
MC14XXXBCL Ceramic
Symbol Parameter Value Unit MC14XXXBD SOIC
VDD DC Supply Voltage – 0.5 to + 18.0 V TA = – 55° to 125°C for all packages.

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin BLOCK DIAGRAM
PD Power Dissipation, per Package† 500 mW
Q16 10
Tstg Storage Temperature – 65 to + 150 _C 12 DATA Q32 13
TL Lead Temperature (8–Second Soldering) 260 _C Q48 9
Q64 1
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: Q80 8
Q96 2
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 5 CLOCK
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Q112 6
Q128 3
LOGIC DIAGRAM
Pins 4 and 11 VDD = PIN 14
CLOCK 5 not used. VSS = PIN 7

DATA IN 12

DQ D Q DQ DQ D Q DQ D Q DQ D Q DQ
C C C C C C C C C C
1 2 3 16 17 32 33 48 49 64

10 Q16
DQ D Q DQ D Q DQ DQ D Q DQ
C C C C C C C C 13 Q32
65 80 81 96 97 112 113 128
9 Q48

1 Q64

8 Q80

2 Q96

6 Q112

3 Q128

MOTOROLA CMOS LOGIC DATA MC14562B

6–451
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 05 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.010 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.020 10 — 300
15 — 20 — 0.030 20 — 600
Total Supply Current**† IT 5.0 IT = (1.94 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.81 µA/kHz) f + IDD
Per Package) 15 IT = (5.52 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must Q64 1 14 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q96 2 13 Q32
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Q128 3 12 DATA
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. NC 4 11 NC
CLOCK 5 10 Q16
Q112 6 9 Q48
VSS 7 8 Q80

NC = NO CONNECTION

MC14562B MOTOROLA CMOS LOGIC DATA

6–452
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Clock to Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 515 ns 5.0 — 600 1200
tPLH, tPHL = (0.66 ns/pF) CL + 217 ns 10 — 250 500
tPLH, tPHL = (0.5 ns/pF) CL + 145 ns 15 — 170 340
Clock Pulse Width tWH 5.0 600 300 — ns
(50% Duty Cycle) 10 220 110 —
15 150 75 —
Clock Pulse Frequency fcl 5.0 — 1.9 1.1 MHz
10 — 5.6 3.0
15 — 8.0 4.0
Data to Clock Setup Time tsu(1) 5.0 – 20 – 170 — ns
10 – 10 – 64 —
15 0 – 60 —
tsu(0) 5.0 – 20 – 91 — ns
10 – 10 – 58 —
15 0 – 48 —
Data to Clock Hold Time th(1) 5.0 350 263 — ns
10 165 109 —
15 155 100 —
th(0) 5.0 350 267 — ns
10 200 140 —
15 140 93 —
Clock Input Rise and Fall Times tr, tf 5.0 — — 15 µs
10 — — 5
15 — — 4
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD

Q16
DATA Q32
Q48
Q64
Q80
CLOCK Q96
Q112
Q128

7 VSS CL CL CL CL CL CL CL CL

ID 500 µF
fo VDD
CLOCK
VSS

DATA VDD
(f = 1/2 fo)
VSS

Figure 1. Power Dissipation Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14562B

6–453
 TIMING DIAGRAM

PIN PULSE 1 PULSE 16 PULSE 32 PULSE 128

NO.’S

CLOCK 5

DATA IN 12

Q16 10

Q32 13

Q28 3

AC TEST WAVEFORMS

PULSE 1 PULSE 2 PULSE 16 PULSE 17

90% VDD
CLOCK 50% 50% 50% 50%
10%
VSS
tWH tr
tWL tf
VDD
DATA IN 50% 50%
VSS
tsu(0)
th(0)
VDD
50% 10% 90%
Q16
VSS
tPHL
tTHL
PULSE 1 PULSE 2 PULSE 16 PULSE 17
VDD
CLOCK 50% 50% 50% 50%
VSS
tWH
tWL
VDD
DATA IN 50% 50%
VSS
tsu(1)
th(1)
VDD
Q16 50% 90%
10%
VSS
tPLH
tTHL

NOTE: The remaining Data–Bit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80,
96, 112, 128 in the same relationship as Q16.

MC14562B MOTOROLA CMOS LOGIC DATA

6–454
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14566B
Industrial Time Base Generator
The MC14566B industrial time base generator is constructed with MOS L SUFFIX
P–channel and N–channel enhancement mode devices in a single CERAMIC
monolithic structure. This device consists of a divide–by–10 ripple counter CASE 620
and a divide–by–5 or divide–by–6 ripple counter to permit stable time
generation from a 50 or 60 Hz line. By cascading this device as divide–by–60
counters, seconds and minutes can be counted and are available in BCD P SUFFIX
PLASTIC
format at the circuit outputs. An internal monostable multivibrator is included
CASE 648
whose output can be used as a reset or clock pulse providing additional
frequency flexibility. Also a pin has been included to allow divide–by–5
counting for generating 1.0 Hz from European 50 Hz line. Pin 11 = VDD will D SUFFIX
cause ÷ 5. SOIC
CASE 751B
• Negative Edge Triggered Counters for Ease of Cascading
• Pulse Shapers on Counter Inputs Accept Slow Input Rise Times
ORDERING INFORMATION
• Monostable Multivibrator Positive or Negative Edge Triggered
MC14XXXBCP Plastic
• Diode Protection on All Inputs
MC14XXXBCL Ceramic
• Supply Voltage Range = 3.0 Vdc to 18 Vdc MC14XXXBD SOIC
• Capable of Driving Two Low–power TTL Loads or One Low–power TA = – 55° to 125°C for all packages.
Schottky TTL Load Over the Rated Temperature Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit PIN ASSIGNMENT
VDD DC Supply Voltage – 0.5 to + 18.0 V CA 1 16 VDD
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V RESET 2 15 CB
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
Q0A 3 14 Q2B
per Pin
Q1A 4 13 Q1B
PD Power Dissipation, per Package† 500 mW
Q2A 5 12 Q0B
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C
Q3A 6 11 B5/B6
* Maximum Ratings are those values beyond which damage to the device may occur. B 7 10 Qm
†Temperature Derating: VSS 8 9 A
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

BLOCK DIAGRAM
3
Q0A
4
CA 1 PULSE Q1A BCD
C 5
÷ 10 SHAPER Q2A OUT
6
Q3A
R
2
RESET
11 R 12
÷ 5/÷ 6 CONTROL Q0B
13 BCD
Q1B
OUT
CB 15 PULSE 14
C Q2B
÷ 5/÷ 6 SHAPER

7 MONO–
B STABLE 10
Qm
9 MULTI–
A VIBRATOR

MOTOROLA CMOS LOGIC DATA MC14566B

6–455
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.0 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.0 µA/kHz) f + IDD
Per Package) 15 IT = (3.0 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14566B MOTOROLA CMOS LOGIC DATA

6–456
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time, Clock to Q3A tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 1365 ns tPHL 5.0 — 1450 4500
tPLH, tPHL = (0.66 ns/pF) CL + 497 ns 10 530 1500
tPLH, tPHL = (0.5 ns/pF) CL + 295 ns 15 — 320 1000
Propagation Delay Time, Reset to Q3A tPHL ns
tPHL = (1.7 ns/pF) CL + 845 ns 5.0 — 930 3000
tPHL = (0.66 ns/pF) CL + 282 ns 10 — 315 1000
tPHL = (0.5 ns/pF) CL + 185 ns 15 — 210 750
Clock Pulse Width tWH(cl) ns
5.0 1200 400 —
10 400 125 —
15 270 90 —
Reset Pulse Width tWH(R) ns
5.0 1200 400 —
10 400 125 —
15 270 90 —
Clock Pulse Frequency fcl MHz
5.0 — 1.0 0.3
10 — 2.5 1.0
15 — 4.2 1.5
Clock Pulse Rise and Fall Time tTLH, —
tTHL 5.0
No Limit
10
15
Monostable Multivibrator Pulse Width tWH(Qm) ns
5.0 1200 2800 —
10 400 900 —
15 300 600 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD 20 ns
20 ns
VDD
90%
ID 500 µF 50%
Vin 10% VSS

VARIABLE
Vin WIDTH
PULSE
CA Q0A
GENERATOR
CB Q1A
Q2A
RESET Q3A
÷ 5/÷ 6 Q0B
CONTROL Q1B
B Q2B
A Qm

VSS CL CL CL CL CL CL CL CL

Figure 1. Power Dissipation Test Circuit and Waveform

MOTOROLA CMOS LOGIC DATA MC14566B

6–457
 VDD

CA Q0A
PROGRAMMABLE
CB Q1A
PULSE
GENERATOR Q2A
RESET Q3A
÷ 5/÷ 6 Q0B
CONTROL Q1B
B Q2B
A Qm

VSS CL CL CL CL CL CL CL CL

NOTE: Assume ÷ 10 Counter at “6” and ÷ 5/ ÷ 6 Counter at “2” at beginning of sequence.

20 ns tWH(cl)
÷ 10 OR ÷ 5/÷ 6 90% 50%
CLOCK AND B 10%

fcl 20 ns

90% 50%
10%
RESET
tPLH tWH(R)
tPHL
90%
Q3A OR 10% 50%
Q2B tTLH
tPLH
tTHL
50% 50%
Qm
tWH(Qm) t WHQm

Figure 2. Switching Time Test Circuit and Waveforms

MC14566B MOTOROLA CMOS LOGIC DATA

6–458
 TIMING DIAGRAM

Divide–By–10 Counter
0 1 2 3 4 5 6 7 8 9 0 1

CLOCK

RESET

Q0

Q1

Q2

Q3

Divide–By–5/Divide–By–6
0 1 2 3 4 5 0 1 2 3 4 0

CLOCK

RESET

CONTROL
÷ 5/÷ 6

Q0

Q1

Q2

Monostable Multivibrator

Qm

= DON’T CARE

MOTOROLA CMOS LOGIC DATA MC14566B

6–459
 APPLICATION — 12 HOUR CLOCK

÷ 5/÷ 6 ÷ 10 VDD

< 1.0 M* Q0 Q0 A
60 Hz C TENTH
C Q1 Qm
Q1 SECONDS B
> 1500 pF* Q2
Q2 Q3

÷ 10 ÷ 5/÷ 6 + VDD
Q0 A
C Q0
Q1 C Qm
Q2 Q1 B
Q3 Q2
SECONDS

÷ 10 ÷ 5/÷ 6
Q0 Q0 A
C Q1 Qm
C
Q2 Q1 B
Q3 Q2
MINUTES

A
B

C
MC14011B

÷ 10 ÷ 5/÷ 6
Q0 Q0 A
C Q1 Qm
C
Q2 Q1 B

R Q3 HOURS R Q2

÷ 5/ ÷ 6 Control not shown = VSS

Reset pins not shown = VSS
* Care must be taken in the indicated circuit to filter line
transients which may cause “false” counting.

MC14566B MOTOROLA CMOS LOGIC DATA

6–460
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14568B
Phase Comparator and
Programmable Counters L SUFFIX
CERAMIC
The MC14568B consists of a phase comparator, a divide–by–4, 16, 64 or CASE 620
100 counter and a programmable divide–by–N 4–bit binary counter (all
positive–edge triggered) constructed with MOS P–channel and N–channel
enhancement mode devices (complementary MOS) in a monolithic structure. P SUFFIX
The MC14568B has been designed for use in conjunction with a PLASTIC
programmable divide–by–N counter for frequency synthesizers and phase– CASE 648
locked loop applications requiring low power dissipation and/or high noise
immunity.
D SUFFIX
This device can be used with both counters cascaded and the output of SOIC
the second counter connected to the phase comparator (CTL high), or used CASE 751B
independently of the programmable divide–by–N counter, for example
cascaded with a MC14569B, MC14522B or MC14526B (CTL low). ORDERING INFORMATION
• Supply Voltage Range = 3.0 to 18 V MC14XXXBCP Plastic
• Capable of Driving Two Low–Power TTL Loads, One Low–Power MC14XXXBCL Ceramic
Schottky TTL Load or Two HTL Loads Over the Rated Temperature MC14XXXBD SOIC
Range. TA = – 55° to 125°C for all packages.
• Chip Complexity: 549 FETs or 137 Equivalent Gates

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages referenced to VSS)
Rating Symbol Value Unit TRUTH TABLE
DC Supply Voltage VDD – 0.5 to + 18 Vdc
F G Division Ratio
Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 Vdc Pin 10 Pin 11 of Counter D1
DC Input Current, per Pin Iin ± 10 mAdc 0 0 4
Power Dissipation, per Package† PD 500 mW 0 1 16
1 0 64
Operating Temperature Range TA – 55 to + 125 _C 1 1 100
Storage Temperature Range Tstg – 65 to + 150 _C
The divide by zero state on the pro-
* Maximum Ratings are those values beyond which damage to the device may occur. grammable divide–by–N 4–bit binary
†Temperature Derating: counter, D2, is illegal.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM

PCin 14 A PHASE 13 PCout

(REF.) COMPARATOR
B 12 LD

TG

TG CTL HIGH CTL LOW

C1 9 11 G
COUNTER D1 PCin PCout
10 F PCout PCin
P/C P/C
CTL 15 LD
LD
TG
C1
“0” 3 4–BIT D1 C1 D1
PROGRAMMABLE 1 Q1/C2
PE 2 COUNTER D2
D2 “0” D2
“0” Q1/C2 Q1/C2
VDD = PIN 16 DP3 DP0
4 5 6 7
VSS = PIN 8 DP2 DP1

MOTOROLA CMOS LOGIC DATA MC14568B

6–461
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage#‡ “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) Vin = 0 or VDD, 10 — 10 — 0.010 10 — 300
Iout = 0 µA 15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.2 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.4 µA/kHz) f + IDD
Per Package) 15 IT = (0.9 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
Pins 1, 13
#Noise immunity for worst input combination.
Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 1 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.
** The formulas given are for the typical characteristics only at 25_C.
‡Pin 15 is connected to VSS or VDD for input voltage test.

PIN ASSIGNMENT
Q1/C2 1 16 VDD
PE 2 15 CTL
“0” 3 14 PCin
DP3 4 13 PCout
DP2 5 12 LD
DP1 6 11 G
DP0 7 10 F
VSS 8 9 C1

MC14568B MOTOROLA CMOS LOGIC DATA

6–462
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

Characteristic Symbol
VDD
V Min Typ Max Unit
Output Rise Time tTLH 5.0 — 180 360 ns
10 — 90 180
15 — 65 130
Output Fall Time tTHL 5.0 — 100 200 ns
10 — 50 100
15 — 40 80
Minimum Pulse Width, C1, Q1/C2, or PCin Input tWH 5.0 — 125 250 ns
10 — 60 120
15 — 45 90
Maximum Clock Rise and Fall Time, tTLH, 5.0 15 — — µs
C1, Q1/C2, or PCin Input tTHL 10 15 — —
15 15 — —
PHASE COMPARATOR
Input Resistance Rin 5.0 to 15 — 106 — MΩ
Input Sensitivity, dc Coupled — 5.0 to 15 See Input Voltage
Turn–Off Delay Time, tPHL 5.0 — 550 1100 ns
PCout and LD Outputs 10 — 195 390
15 — 120 240
Turn–On Delay Time. tPLH 5.0 — 675 1350 ns
PCout and LD Outputs 10 — 300 600
15 — 190 380
DIVIDE–BY–4, 16, 64 OR 100 COUNTER (D1)
Maximum Clock Pulse Frequency fcl MHz
Division Ratio = 4, 64 or 100 5.0 3.0 6.0 —
10 8.0 16 —
15 10 22 —
Division Ratio = 16 5.0 1.0 2.5 —
10 3.0 6.3 —
15 50 9.7 —
Propagation Delay Time, Q1/C2 Output tPLH, ns
Division Ratio = 4, 64 or 100 tPHL 5.0 — 450 900
10 — 190 380
15 — 130 260
Division Ratio = 16 5.0 — 720 1440
10 — 300 600
15 — 200 400
PROGRAMMABLE DIVIDE–BY–N 4–BIT COUNTER (D2)
Maximum Clock Pulse Frequency fcl 5.0 1.2 1.8 — MHz
(Figure 3a) 10 3.0 8.5 —
15 4.0 12 —
Turn–On Delay Time, “0” Output tPLH 5.0 — 450 900 ns
(Figure 3a) 10 — 190 380
15 — 130 260
Turn–Off Delay Time, “0” Output tPHL 5.0 — 225 450 ns
(Figure 3a) 10 — 85 170
15 — 60 150
Minimum Preset Enable Pulse Width tWH(PE) 5.0 — 75 250 ns
10 — 40 100
15 — 30 75

MOTOROLA CMOS LOGIC DATA MC14568B

6–463
 SWITCHING TIME TEST CIRCUITS AND WAVEFORMS
VDD VDD A LAGS B, PCout IS LOW. A LEADS B, PCout IS HIGH.
2 “0”out REF 50%
10 k B
CTL 20 ns
DP0 PCout 20 ns
tW(PCin)
DP1 LD PCin 90%
DP2 CL CL PG1 50%
DP3 A 10%
PULSE tPLH
PCin tPLH tPLH
GENERATOR 1 tTHL
F Q1/C2
90%
G LD
PULSE C1 “0” 10%
GENERATOR 2 tPHL
PE
tTLH
tPHL
VOH
PCout THREE–STATE THREE–STATE 75%
VSS
25%
VOL
tPHL tPLH
Figure 1. Phase Comparator
VDD

CTL 20 ns tW(C1)
DP0 PCout 20 ns
DP1 LD 90%
C1 50% fin fmax
DP2 10%
DP3
PCin tPHL
F Q1/C2
CL 90%
G Q1/C2 50%
PULSE C1 “0” 10%
GENERATOR tTLH tTHL
PE

VSS
Figure 2. Counter D1

VDD VDD
DP0 DP0
DP1 PCout DP1 PCout
DP2 LD DP2 LD
DP3 DP3
PULSE Q1/C2 PULSE Q1/C2
GENERATOR GENERATOR 1
PCin PCin
F F
G G
“0” “0”
C1 C1
CTL CTL CL
PULSE
PE PE
GENERATOR 2
VSS
CL VSS

N PULSES*

tW(Q1/C2) 50%
20 ns 20 ns Q1/C2 = PG 1
90% 20 ns
Q1/C2 50% 20 ns
10%
90%
tPLH tPHL fin fmax PE = PG2 50%
10%
90%
“0” 50%
10% tW(PE)
tTLH tTHL “0”
* N is the value programmed on the DP Inputs.
a. b.
Figure 3. Counter D2

MC14568B MOTOROLA CMOS LOGIC DATA

6–464
 LOGIC DIAGRAM

14 A
PCin
13
PCout

B (REF.) LD

D D Q
Q Q
C
C C

COUNTER
9 D1
C1

10
F
11
G

1
Q1/C2

15
CTL

3
“0”

PE

2
PE

COUNTER C
D2
Q
D

VDD = PIN 16
VSS = PIN 8

4 5 6 7
DP3 DP2 DP1 DP0

MOTOROLA CMOS LOGIC DATA MC14568B

6–465
 Typical Maximum Frequency Divider D1 Typical Maximum Frequency Divider D1
Division ratios: 4, 64 or 100 (CL = 50 pF) Division ratio: 16 (CL = 50 pF)
28 12

26 10

f, FREQUENCY (MHz)
24 8 VDD = 15 V

22 6
VDD = 10 V
20 4
VDD = 15 V
18 2 VDD = 5 V
f, FREQUENCY (MHz)

16 0
– 40 – 20 0 + 20 + 40 + 60 + 80 + 100
T, TEMPERATURE (°C)
14

12 VDD = 10 V
Typical Maximum Frequency Divider D2
10 Division ratio: 2 (CL = 50 pF)
6
8
5
6
VDD = 5 V
f, FREQUENCY (MHz)

4
4 VDD = 15 V
3
2
VDD = 10 V
2
0
– 40 – 20 0 + 20 + 40 + 60 + 80 + 100
1 VDD = 5 V
T, TEMPERATURE (°C)

0
– 40 – 20 0 + 20 + 40 + 60 + 80 + 100
T, TEMPERATURE (°C)

MC14568B MOTOROLA CMOS LOGIC DATA

6–466
 OPERATING CHARACTERISTICS

The MC14568B contains a phase comparator, a fixed
divider (÷ 4, ÷ 16, ÷ 64, ÷ 100) and a programmable divide–
by–N 4–bit counter.
PHASE COMPARATOR
The phase comparator is a positive edge controlled logic
circuit. It essentially consists of four flip–flops and an output
pair of MOS transistors. Only one of its inputs (PCin, pin 14)
is accessible externally. The second is connected to the out-
put of one of the two counters D1 or D2 (see block diagram).
Duty cycles of both input signals (at A and B) need not be
taken into consideration since the comparator responds to
leading edges only.
If both input signals have identical frequencies but different
phases, with signal A (pin 14) leading signal B (Ref.), the
comparator output will be high for the time equal to the
phased difference.
If signal A lags signal B, the output will be low for the same
time. In between, the output will be in a three–state condition
and the voltage on the capacitor of an RC filter normally con-
nected at this point will have some intermediate value (see
Figure 4). When used in a phase locked loop, this value will
adjust the Voltage Controlled Oscillator frequency by reduc-
ing the phase difference between the reference signal and
the divided VCO frequency to zero.
VDD
A (PCin) VSS
1/f
VOH
B (REF.) VOL
VOH
LD
VOL
VOH
PCout
VOL
Figure 4. Phase Comparator Waveforms
If the input signals have different frequencies, the output
signal will be high when signal B has a lower frequency than
signal A, and low otherwise.
Under the same conditions of frequency difference, the
output will vary between VOH (or VOL) and some intermedi-
ate value until the frequencies of both signals are equal and
their phase difference equal to zero, i.e. until locked condition
is obtained.
Capture and lock range will be determined by the VCO fre-
quency range. The comparator is provided with a lock indi-
cator output, which will stay at logic 1 in locked conditions.
The state diagram (Figure 5) depicts the internal state
transitions. It assumes that only one transition on either sig-
nal occurs at any time. It shows that a change of the output
state is always associated with a positive transition of either
signal. For a negative transition, the output does not change
state. A positive transition may not cause the output to
change, this happens when the signals have different fre-
quencies.
DIVIDE BY 4, 16, 64 OR 100 COUNTER (D1)
This counter is able to work at an input frequency of 5 MHz
for a VDD value of 10 volts over the standard temperature
range when dividing by 4, 64 and 100. Programming is ac-
complished by use of inputs F and G (pins 10 and 11) ac-
cording to the truth table shown. Connecting the Control
input (CTL, pin 15), to VDD allows cascading this counter with
the programmable divide–by–N counter provided in the
same package. Independent operation is obtained when the
Control input is connected to VSS.
The different division ratios have been chosen to generate
the reference frequencies corresponding to the channel
spacings normally required in frequency synthesizer applica-
tions. For example. with the division ratio 100 and a 5 MHz
crystal stabilized source a reference frequency of 50 kHz is
supplied to the comparator. The lower division ratios permit
operation with low frequency crystals.

INPUT STATE

00 00 00

X X 01 10 10 01 01 10

11 11 11
A B

3–STATE
PCout 0 1
OUTPUT DISCONNECTED
LD
0 1 0
(LOCK DETECT)

Figure 5. Phase Comparator State Diagram

MOTOROLA CMOS LOGIC DATA MC14568B

6–467
 If used in cascade with the programmable divide–by–N
counter, practically all usual reference frequencies, or chan-
nel spacings of 25, 20, 12.5, 10, 6.25 kHz, etc. are easily
achievable.
PROGRAMMABLE DIVIDE–BY–N
4–BIT COUNTER (D2)
This counter is programmable by using inputs DP0 ... DP3
(pins 7 ... 4). The Preset Enable input enables the parallel
preset inputs DP0... DP3. The “0” output must be externally
connected to the PE input for single stage applications.
Since there is not a cascade feedback input, this counter,
when cascaded, must be used as the most significant digit.
Because of this, it can be cascaded with binary counters as
well as with BCD counters (MC14569B, MC14522B,
MC14526B).

TYPICAL APPLICATIONS

CF CF CF
fin C C Q4 C Q4 Q1/C2
MC14522B MC14522B
MC14569B OR OR MC14568B
ZERO DETECT PE MC14526B “0” PE MC14526B “0” PE “0”

DP0 – – – – – – DP3 DP0 – – – – – – DP3 DP0 – – – – – – DP3

LSD MSD fout

Figure 6. Cascading MC14568B and MC14522B or MC14526B with MC14569B

fout
(40 kHz) PCin PCout VCO
C1 G VSS (144 – 146 MHz)
MC14568B
CTI F VSS
VSS “0” Q1/C2
PE
VDD
DP0 – – – – DP3
MC14011

Q CF

MC14569B C
ZERO DETECT
MIXER
2k

2M
CRYSTAL
Frequencies shown in parenthesis are given as an example. OSCILLATOR

(143.5 MHz)
Figure 7. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer
(Channel Spacing 10 kHz)

MC14568B MOTOROLA CMOS LOGIC DATA

6–468
 fout
PCin PCout VCO
(5 MHz) C1 G VDD
MC14568B
(VDD) CTL F VDD
“0” PE

VDD Q CF C
C
VSS MC14569B
MC14522B
DP0 – – – – – DP3 ZERO DETECT
“0” PE (BCD) BINARY

DP0 – – – – – DP3

N1 N2 N3
(0 – 5) (0 – 9) (0, 4, 8, 12)
(625 kHz STEPS) (62.5 kHz STEPS) (6.25 kHz STEPS)

Divide ratio = 160N1 + 16N2 + N3 Figures shown in parenthesis refer to example.

Example: Recommended reading:

fout = N1 (MHz) + N2 (x 100 kHz) + N3 (x25 kHz) (1) AN535: “Phase–Lock Techniques”
Frequency range = 5 MHz (2) AR254: “Phase–Locked Loop Design Articles”
Channel spacing = 25 kHz
Reference frequency = 6.25 kHz

Figure 8. Frequency Synthesizer Using MC14568B, MC14569B and MC14522B

(Without Mixer)

MOTOROLA CMOS LOGIC DATA MC14568B

6–469
6–470
MC14568B

26.965–27.255
(28.605) MHz

RECEIVER RECEIVER
SECOND MIXER FIRST MIXER
10.695 MHz RF
TO 455 kHz

Figure 9. Typical 23–Channel CB Frequency Synthesizer for

IF AMP
16.270–16.560 (17.910) MHz
LOCK DETECTOR

MC14568B
Double Conversion Transceivers

REFERENCE φ LOOP LOW

÷2 ÷8 ÷64 VCO
OSCILLATOR D PASS FILTER

÷N
10 kHz
10.24 MHz
X3
.91–1.20 (2.55) MHz
N = 91–120 (255) MHz

÷N DOWN
MC14526B MIXER
NOTE:
1. 10 kHz Channel Spacing
2. Expandable to 165 Channels
(Expanded frequency range
MOTOROLA CMOS LOGIC DATA

shown in parenthesis) TRX TO TRANSMITTER

OSCILLATOR
MIXER 26.965–27.255
(TRASMIT ONLY) (28.605) MHz
VDD

RCV

10.695 MHz
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD L SUFFIX
CERAMIC
Down Counter CASE 620

The MC14569B is a programmable divide–by–N dual 4–bit binary or BCD

down counter constructed with MOS P–channel and N–channel enhance- P SUFFIX
ment mode devices (complementary MOS) in a monolithic structure. PLASTIC
CASE 648
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phase–locked loops, and
other frequency division applications requiring low power dissipation and/or DW SUFFIX
high noise immunity. SOIC
CASE 751G
• Speed–up Circuitry for Zero Detection
• Each 4–Bit Counter Can Divide Independently in BCD or Binary Mode
ORDERING INFORMATION
• Can be Cascaded With MC14568B, MC14522B or MC14526B for
Frequency Synthesizer Applications MC14XXXBCP Plastic
MC14XXXBCL Ceramic
• All Outputs are Buffered MC14XXXBDW SOIC
• Schmitt Triggered Clock Conditioning

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

BLOCK DIAGRAM

P0 P1 P2 P3 CTL1 CTL2 P4 P5 P6 P7
CTL = Low for Binary Count
3 4 5 6 2 10 11 12 13 14
CTL = High for BCD Count VDD = PIN 16
VSS = PIN 8

9 BINARY/BCD CLOCK BINARY/BCD 15

CLOCK Q
COUNTER #1 LOAD COUNTER #2

CASCADE 7 1 ZERO
FEEDBACK ZERO DETECT ENCODER
DETECT

MOTOROLA CMOS LOGIC DATA MC14569B

6–471
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.58 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.20 µA/kHz) f + IDD
Per Package) 15 IT = (1.95 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14569B MOTOROLA CMOS LOGIC DATA

6–472
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

VDD
All Types
Characteristic Symbol Vdc Min Typ # Max Unit
Output Rise Time tTLH 5.0 — 100 200 ns
10 — 50 100
15 — 40 80
Output Fall Time tTHL 5.0 — 100 200 ns
10 — 50 100
15 — 40 80
Turn–On Delay Time tPLH ns
Zero Detect Output 5.0 — 420 700
10 — 175 300
15 — 125 250
Q Output 5.0 — 675 1200 ns
10 — 285 500
15 — 200 400
Turn–Off Delay Time tPHL ns
Zero Detect Output 5.0 — 380 600
10 — 150 300
15 — 100 200
Q Output 5.0 — 530 1000 ns
10 — 225 400
15 — 155 300
Clock Pulse Width tWH 5.0 300 100 — ns
10 150 45 —
15 115 30 —
Clock Pulse Frequency fcl 5.0 — 3.5 2.1 MHz
10 — 9.5 5.1
15 — 13.0 7.8
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 NO LIMIT µs
10
15
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

SWITCHING WAVEFORMS

20 ns
20 ns
90%
CLOCK 50% fin = fmax
10%
tWH
tPLH tPHL
90%
Q 50%
10%
tTLH tTHL

Figure 1.

20 ns
20 ns
90%
CLOCK 50%
10%
tWH
tPHL
tPLH
90%
ZERO DETECT 10%
tTLH tTHL

Figure 2.

MOTOROLA CMOS LOGIC DATA MC14569B

6–473
 PIN DESCRIPTIONS

INPUTS CONTROLS

P0, P1, P2, P3 (Pins 3, 4, 5, 6) — Preset Inputs. Program-
mable inputs for the least significant counter. May be binary
or BCD depending on the control input.
P4, P5, P6, P7 (Pins 11, 12, 13, 14) — Preset Inputs. Pro-
grammable inputs for the most significant counter. May be
binary or BCD depending on the control input.
Clock (Pin 9) — Preset data is decremented by one on
each positive transition of this signal.
OUTPUTS
Cascade Feedback (Pin 7) — This pin is normally set
high. When low, loading of the preset inputs (P0 through P7)
is inhibited, i.e., P0 through P7 are “don’t cares.” Refer to
Table 1 for output characteristics.
CTL1 (Pin 2) — This pin controls the counting mode of the
least significant counter. When set high, counting mode is
BCD. When set low, counting mode is binary.
CTL2 (Pin 10) — This pin controls the counting mode of
the most significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.

Zero Detect (Pin 1) — This output is normally low and SUPPLY PINS
goes high for one clock cycle when the counter has decrem- VSS (Pin 18) — Negative Supply Voltage. This pin is usual-
ented to zero. ly connected to ground.

Q (Pin 15) — Output of the last stage of the most signifi- VDD (Pin 16) — Positive Supply Voltage. This pin is con-
cant counter. This output will be inactive unless the preset nected to a positive supply voltage ranging from 3.0 volts to
input P7 has been set high. 18.0 volts.

OPERATING CHARACTERISTICS

The MC14569B is a programmable divide–by–N dual 4–bit
down counter. This counter may be programmed (i.e., pre-
set) in BCD or binary code through inputs P0 to P7. For each
counter, the counting sequence may be chosen indepen-
dently by applying a high (for BCD count) or a low (for binary
count) to the control inputs CTL1 and CTL2.
The divide ratio N (N being the value programmed on the
preset inputs P0 to P7) is automatically loaded into the
counter as soon as the count 1 is detected. Therefore, a divi-
sion ratio of one is not possible. After N clock cycles, one
pulse appears on the Zero Detect output. (See Timing Dia-
gram.) The Q output is the output of the last stage of the most
significant counter (See Tables 1 through 5, Mode Controls.)
When cascading the MC14569B to the MC14568B,
MC14522B or the MC14526B, the Cascade Feedback input,
Q, and Zero Detect outputs must be respectively connected
to “0”, Clock, and Load of the following counter. If the
MC14569B is used alone, Cascade Feedback must be con-
nected to VDD.

18
CL = 50 pF PIN ASSIGNMENT
16
ZERO 1 16 VDD
f, FREQUENCY (MHz), TYPICAL

14 DETECT
CTL1 2 15 Q
12 VDD = 15 V
P0 3 14 P7
10
P1 4 13 P6
8.0 10 V
P2 5 12 P5
6.0
P3 6 11 P4
4.0 5.0 V CASCADE 7 10 CTL2
FEEDBACK
2.0
VSS 8 9 CLOCK
0
– 40 – 20 0 + 20 + 40 + 60 + 80 + 100
TA, AMBIENT TEMPERATURE (°C)

MC14569B MOTOROLA CMOS LOGIC DATA

6–474
 Table 1. Mode Controls (Cascade Feedback = Low)
Counter Control Values Divide Ratio
CTL1 CTL2 Zero Detect Q
0 0 256 256
0 1 160 160
1 0 160 160
1 1 100 100
NOTE: Data Preset Inputs (P0–P7) are “Don’t Cares” while Cascade Feedback is
Low.

Table 2. Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High)
Preset Inputs Divide Ratio
Zero
P7 P6 P5 P4 P3 P2 P1 P0 Detect Q Comments
0 0 0 0 0 0 0 0 256 256 Max Count
0 0 0 0 0 0 0 1 X X Illegal State
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
         X
         X
         X
0 0 0 0 1 1 1 1 15 X
0 0 0 1 0 0 0 0 16 X
         X
         X
         X
0 0 1 0 0 0 0 0 32 X
         X
         X
         X
0 1 0 0 0 0 0 0 64 X
         X
         X
         X
0 1 1 1 1 1 1 1 127 X
1 0 0 0 0 0 0 0 128 128 Q Output Active
         
         
         
1 0 0 0 1 0 0 0 136 136
         
         
         
1 1 1 1 1 1 1 1 255 255
27 26 25 24 23 22 21 20
128 64 32 16 8 4 2 1 Bit Value
Counter #2 Counter #1 Counting
Binary Binary Sequence
X = No Output (Always Low)

MOTOROLA CMOS LOGIC DATA MC14569B

6–475
 Table 3. Mode Controls (CTL1 = High, CTL2 = Low, Cascade Feedback = High)
Preset Inputs Divide Ratio
Zero
P7 P6 P5 P4 P3 P2 P1 P0 Detect Q Comments
0 0 0 0 0 0 0 0 160 160 Max Count
0 0 0 0 0 0 0 1 X X Illegal State
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
         X
         X
         X
0 0 0 0 1 0 0 1 9 X
0 0 0 1 0 0 0 0 10 X
         X
         X
         X
0 0 0 1 1 0 0 1 19 X
0 0 1 0 0 0 0 0 20 X
         X
         X
         X
0 0 1 1 0 0 0 0 30 X
         X
         X
         X
0 1 0 0 0 0 0 0 40 X
         X
         X
         X
0 1 0 1 0 0 0 0 50 X
         X
         X
         X
0 1 1 0 0 0 0 0 60 X
         X
         X
         X
0 1 1 1 0 0 0 0 70 X
         X
         X
         X
1 0 0 0 0 0 0 0 80 80 Q Output Active
         
         
         
1 0 0 1 0 0 0 0 90 90
         
         
         
1 1 1 1 0 0 0 0 150 150
         
         
         
1 1 1 1 1 0 0 1 159 159
80 40 20 10 8 4 2 1 Bit Value
Counter #2 Counter #1 Counting
Binary BCD Sequence
X = No Output (Always Low)

MC14569B MOTOROLA CMOS LOGIC DATA

6–476
 Table 4. Mode Controls (CTL1 = Low, CTL2 = High, Cascade Feedback = High)
Preset Values Divide Ratio
Zero
P7 P6 P5 P4 P3 P2 P1 P0 Detect Q Comments
0 0 0 0 0 0 0 0 160 160 Max Count
0 0 0 0 0 0 0 1 X X Illegal State
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
         X
         X
         X
0 0 0 0 1 1 1 1 15 X
0 0 0 1 0 0 0 0 16 X
         X
         X
         X
0 0 0 1 1 1 1 1 31 X
0 0 1 0 0 0 0 0 32 X
         X
         X
         X
0 0 1 1 0 0 0 0 48 X
         
         
         
0 1 0 0 0 0 0 0 64 X
         
         
         
0 1 0 1 0 0 0 0 80 X
         
         
         
0 1 1 1 0 0 0 0 112 X
         
         
         
1 0 0 0 0 0 0 0 128 128 Q Output Active
         
         
         
1 0 0 1 0 0 0 0 144 144
         
         
         
1 0 0 1 1 1 1 1 159 159
27 26 25 24 23 22 21 20
128 64 32 16 8 4 2 1 Bit Value
Counter #2 Counter #1 Counting
BCD Binary Sequence
X = No Output (Always Low)

MOTOROLA CMOS LOGIC DATA MC14569B

6–477
 Table 5. Mode Controls (CTL1 = High, CTL2 = High, Cascade Feedback = High)
Preset Values Divide Ratio
Zero
P7 P6 P5 P4 P3 P2 P1 P0 Detect Q Comments
0 0 0 0 0 0 0 0 100 100 Max Count
0 0 0 0 0 0 0 1 X X illegal state
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
         X
         X
         X
0 0 0 0 1 0 0 1 9 X
0 0 0 1 0 0 0 0 10 X
         X
         X
         X
0 0 1 1 0 0 0 0 30 X
         X
         X
         X
0 1 0 0 0 0 0 0 40 X
         X
         X
         X
0 1 0 1 0 0 0 0 50 X
         X
         X
         X
0 1 1 1 0 0 0 0 70 X
         X
         X
         X
1 0 0 0 0 0 0 0 80 80 Q Output Active
         
         
         
1 0 0 1 0 0 0 0 90 90
         
         
         
1 0 0 1 1 0 0 1 99 99
80 40 20 10 8 4 2 1 Bit Value
Counter #2 Counter #1 Counting
BCD BCD Sequence
X = No Output (Always Low)

TIMING DIAGRAM MC14569B

CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

DIVIDE
BY 2
DIVIDE
ZERO BY 3
DETECT
OUTPUT DIVIDE
BY 4

DIVIDE
BY 12

MC14569B MOTOROLA CMOS LOGIC DATA

6–478
 LOGIC DIAGRAM
2
CTL1
DP Q
PE
D C

DP Q
3 PE
P0 D C

4 DP Q
P1 PE
D C

DP Q PE

5 D C
P2
DP Q
PE
6 D C
P3
DP Q
PE
D C

DP Q
PE
D C

DP Q
PE
D C
IU

VDD

CASCADE 7
FEEDBACK VDD

9
CLOCK
1 ZERO
DETECT

11 DP D C
P4
Q PE

12 DP D C
P5
Q PE

13 DP D C
P6
Q PE

14 DP D C
P7
Q PE
10 15
CTL2

MOTOROLA CMOS LOGIC DATA MC14569B

6–479
 TYPICAL APPLICATIONS

CF CF CF
fin C Q C Q4 C Q4 Q1/C2
MC14522B MC14522B
MC14569B OR OR MC14568B
ZERO DETECT PE MC14526B “0” PE MC14526B “0” PE “0”

DP0 – – – – – – DP3 DP0 – – – – – – DP3 DP0 – – – – – – DP3

LSD MSD fout

Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B

fout
(40 kHz) PCin PCout VCO
C1 G VSS (144 – 146 MHz)
CT1 F VSS
VSS “0” Q1/C2
PE
VDD
DP0 – – – – DP3
MC14011

Q CF

MC14569B C
ZERO DETECT
MIXER
2k

2M
CRYSTAL
Frequencies shown in parenthesis are given as an example OSCILLATOR

(143.5 MHz)

Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer

(Channel Spacing 10 kHz)

MC14569B MOTOROLA CMOS LOGIC DATA

6–480
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14572UB
Hex Gate
L SUFFIX
The MC14572UB hex functional gate is constructed with MOS P–channel CERAMIC
and N–channel enhancement mode devices in a single monolithic structure. CASE 620
These complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired. The chip contains four
inverters, one NOR gate and one NAND gate. P SUFFIX
• Diode Protection on All Inputs PLASTIC
CASE 648
• Single Supply Operation
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter D SUFFIX
• NAND Input Pin Adjacent to VDD Pin to Simplify Use As An Inverter SOIC
CASE 751B
• NOR Output Pin Adjacent to Inverter Input Pin For OR Application
• NAND Output Pin Adjacent to Inverter Input Pin For AND Application
ORDERING INFORMATION
• Capable of Driving Two Low–power TTL Loads or One Low–Power
MC14XXXUBCP Plastic
Schottky TTL Load over the Rated Temperature Range
MC14XXXUBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC14XXXUBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) TA = – 55° to 125°C for all packages.
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V LOGIC DIAGRAM
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin 2 1

PD Power Dissipation, per Package† 500 mW

Tstg Storage Temperature – 65 to + 150 _C
4 3
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: 6
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 5
7
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

CIRCUIT SCHEMATIC 10 9
VDD VDD
VDD
12 11

7
2 1 13 14
13
15
6 14 VDD = PIN 16
5
VSS VSS = PIN 8

15
VSS VSS

MOTOROLA CMOS LOGIC DATA MC14572UB

6–481
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.0 — 2.25 1.0 — 1.0
(VO = 9.0 or 1.0 Vdc) 10 — 2.0 — 4.50 2.0 — 2.0
(VO = 13.5 or 1.5 Vdc) 15 — 2.5 — 6.75 2.5 — 2.5
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 4.0 — 4.0 2.75 — 4.0 —
(VO = 1.0 or 9.0 Vdc) 10 8.0 — 8.0 5.50 — 8.0 —
(VO = 1.5 or 13.5 Vdc) 15 12.5 — 12.5 8.25 — 12.5 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
15 — 1.0 — 0.0015 1.0 — 30
Total Supply Current**† IT 5.0 IT = (1.89 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.80 µA/kHz) f + IDD
Per Package) 15 IT = (5.68 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must OUTA 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and INA 2 15 IN 2F
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. OUTB 3 14 IN 1F
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. INB 4 13 OUTF
OUTC 5 12 INE
IN 1C 6 11 OUTE
IN 2C 7 10 IND
VSS 8 9 OUTD

MC14572UB MOTOROLA CMOS LOGIC DATA

6–482
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise Time tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130
Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 5 ns tPHL 5.0 — 90 180
tPLH, tPHL = (0.66 ns/pF) CL + 17 ns 10 — 50 100
tPLH, tPHL = (0.5 ns/pF) CL + 15 ns 15 — 40 80
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD VDD

INPUT
INPUT 16 16
7
2 PULSE
PULSE GENERATOR
OUTPUT 6 OUTPUT
GENERATOR 1 5
8 VSS CL 8 VSS CL

VDD
20 ns 20 ns
16 VDD
90% 90%
INPUT 14 INPUT 50% 50%
10% 10% VSS
15 OUTPUT
PULSE tPHL
13 tPLH
GENERATOR
8 VSS CL 90% 90% VOH
OUTPUT 50% 50%
10% 10%
VOL
tf tr

Figure 1. Switching Time Test Circuits and Waveforms

MOTOROLA CMOS LOGIC DATA MC14572UB

6–483
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14580B
4 x 4 Multiport Register
L SUFFIX
The MC14580B is a 4 by 4 multiport register useful in small scratch pad CERAMIC
memories, arithmetic operations when coupled with an adder, and other data CASE 623
storage applications. It allows independent reading of any two words (or the
same word at both outputs) while writing into any one of four words.
Address changing and data entry occur on the rising edge of the clock. P SUFFIX
When the write enable input is low, the contents of any word may be PLASTIC
accessed but not altered. CASE 709
• No Restrictions on Clock Input Rise or Fall Times
• 3–State Outputs DW SUFFIX
• Single Phase Clocking SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 751E
• Capable of Driving Two Low–power TTL Loads or one Low–power
Schottky TTL Load Over the Rated Temperature Range ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Pin Compatible with CD40108 MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
MC14XXXBDW SOIC
TA = – 55° to 125°C for all packages.

VDD DC Supply Voltage – 0.5 to + 18.0 V

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
PIN ASSIGNMENT
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin Q3B 1 24 VDD

PD Power Dissipation, per Package† 500 mW Q2B 2 23 Q1B

3–STATE A 3 22 Q0B
Tstg Storage Temperature – 65 to + 150 _C
Q0A 4 21 3–STATE B
TL Lead Temperature (8–Second Soldering) 260 _C
Q1A 5 20 D0
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: Q2A 6 19 D1
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Q3A 7 18 D2
WRITE 0 8 17 D3
BLOCK DIAGRAM WRITE 1 9 16 CLOCK
W0 W1 R0A R1A R0B R1B READ 1B 10 15 WE
8 9 13 14 11 10
READ 0B 11 14 READ 1A

16 VSS 12 13 READ 0A
CLOCK DECODER
3–STATE A
3

15 4
WE Q0A
5 WORD A
Q1A
6
20 Q2A OUTPUT
D0 7
19 Q3A
DATA D1 4X4
18
INPUT D2 MEMORY 22
17 Q0B
D3 23
Q1B WORD B
2 OUTPUT
Q2B
1
Q3B

21
VDD = PIN 24
3–STATE B
VSS = PIN 12

MC14580B MOTOROLA CMOS LOGIC DATA

6–484
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.010 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.020 10 — 300
15 — 20 — 0.030 20 — 600
Total Supply Current**† IT 5.0 IT = (1.18 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.91 µA/kHz) f + IDD
Per Package) 15 IT = (2.67 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14580B

6–485
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, tTHL ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns (Figures 3 and 6) 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, tPHL 5.0 — 650 1300 ns
Clock to Output (Figures 3 and 6) 10 — 250 500
15 — 170 340
Write Enable Setup Time tsu 5.0 800 400 — ns
(Enabling a Write or Read) (Figure 5) 10 300 150 —
15 200 100 —
Write Enable Removal Time trem 5.0 0 – 100 — ns
(Disabling a Write or Read) (Figure 5) 10 0 – 50 —
15 0 – 35 —
Setup Time** tsu 5.0 50 20 — ns
Address, Data to Clock (Figure 3) 10 30 0 —
15 25 0 —
Hold Time** th 5.0 480 160 — ns
Clock to Address, Data (Figure 3) 10 195 65 —
15 150 50 —
3–State Enable/Disable Delay Time tPHZ, tPLZ 5.0 — 130 260 ns
tPZH, tPZL 10 — 60 120
(Figures 4 and 7) 15 — 45 90
Clock Pulse Width tw 5.0 820 410 — ns
(Figure 3) 10 330 165 —
15 220 110 —
** When loading repetitive highs, the output may glitch low momentarily after the rising edge of Clock. However, data integrity remains unaffected
and data is valid after the propagation delays listed in the Switching Characteristics Table.

VDD Vout
WE Q0A
W0
W1 Q1A IDS
R0A Q2A Sink Current Source Current
R1A
R0B Q3A Position of S1 2 1
EXTERNAL
R1B Q0B VGS = VDD – VDD
PULSE POWER
C SUPPLY VDS = Vout Vout – VDD
GENERATOR
D0 Q1B
D1
Q2B
1 D2
VDD
D3 Q3B
2
VSS S1 VSS

Figure 1. Output Drive Current Test Circuit

MC14580B MOTOROLA CMOS LOGIC DATA

6–486
 VDD
IDD

PULSE WE Q0A
REPETITIVE WAVEFORMS
GENERATOR W0 CL
W1 Q1A
1
R0A Q2A CL
R1A P.G. 1
Q3A CL
R0B
PULSE R1B Q0B CL
GENERATOR C P.G. 2
2 D0 Q1B CL
D1 CL
Q2B
PULSE D2 P.G. 3
GENERATOR D3 Q3B CL
OUTPUT
3 Qn A, B
VSS CL

Figure 2. Power Dissipation Test Circuit and Waveforms (3–State Inputs are High)

tw(H)
tw(L)
VDD
CLOCK 50% VDD
3–STATE 50% 50%
VSS A OR B
tsu VSS
th tPHZ
VDD tPZH
ADDRESS DATA 50% 90% VOH
QA
VSS 10% VOL
tPLH, tPHL
VOH tPZL tPZL
90% VOH
Q 50% 90%
10%
VOL QB 10%
tTLH, tTHL VOL

Figure 3. Figure 4.

VDD
CLOCK 50% 50% Q
VSS DEVICE
tsu trem UNDER CL
VDD TEST
50% 50%
WE
VSS

Figure 5. Figure 6. Test Circuit

Q 1 kΩ CONNECT TO VCC WHEN TESTING tPLZ AND tPZL

DEVICE CONNECT TO GND WHEN TESTING tPHZ AND tPZH
UNDER
CL
TEST

Figure 7. Test Circuit

MOTOROLA CMOS LOGIC DATA MC14580B

6–487
 LOGIC DIAGRAM

R1A R0A R1B R0B 3–STATE A

14 13 10 11 3
16
CLOCK
C Q C Q C Q C Q
15
WE D Q D Q D Q D Q

7
C Q Q3A
D
3–STATE
6
C Q Q2A
D
3–STATE
5
C C Q Q1A
17
D3 D Q D
3–STATE
4
C Q Q0A
D
C
18 3–STATE
D2 D Q
1
C Q Q3B
D
3–STATE
C 2
19 Q C Q Q2B
D1 D
D
3–STATE
23
C Q Q1B
C D
20
D0 D Q 3–STATE
22
C Q Q0B
D
C Q 3–STATE
9
W1 D Q

C Q
8 21
W0 D Q 3–STATE B

TRUTH TABLE
Clock WE Write 1 Write 0 Read 1A Read 0A Read 1B Read 0B 3–State A 3–State B Dn QnA QnB
1 0 1 0 1 0 1 1 1 1 1 1
1 0 1 0 1 0 1 1 1 0 0 0
X X X X X X X 1 1 X No No
Change Change
X X X X X X X X 0 0 X Z Z
0 X X X X X X X 1 1 X No No
Change Change
1 X X X X X X X 1 1 X No No
Change Change
1 0 0 0 1 1 0 1 1 Dn to Contents Contents
word 0 of word 1 of word 2
displayed displayed
0 0 0 0 1 1 0 1 1 Word 0 Contents Contents
not of word 1 of word 2
altered displayed displayed
Z = High Impedance
X = Don’t Care

MC14580B MOTOROLA CMOS LOGIC DATA

6–488
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14581B
4-Bit Arithmetic Logic Unit
The MC14581B is a CMOS 4–bit ALU capable of providing 16 functions of L SUFFIX
two Boolean variables and 16 binary arithmetic operations on two 14–bit CERAMIC
words. The level of the mode control input determines whether the output CASE 623
function is logic or arithmetic. The desired logic function is selected by
applying the appropriate binary word to the select inputs (S0 thru S3) with
the mode control input high, while the desired arithmetic operation is P SUFFIX
selected by applying a low voltage to the mode control input, the required PLASTIC
CASE 709
level to carry in, and the appropriate word to the select inputs. The word
inputs and function outputs can be operated with either active high or active
low data. DW SUFFIX
Carry propagate (P) and carry generate (G) outputs are provided to allow SOIC
a full look–ahead carry scheme for fast simultaneous carry generation for the CASE 751E
four bits in the package. Fast arithmetic operations on long words are
obtainable by using the MC14582B as a second order look ahead block. An ORDERING INFORMATION
inverted ripple carry input (Cn) and a ripple carry output (Cn+4) are included MC14XXXBCP Plastic
for ripple through operation. MC14XXXBCL Ceramic
When the device is in the subtract mode (LHHL), comparison of two 4–bit MC14XXXBDW SOIC
words present at the A and B inputs is provided using the A = B output. It TA = – 55° to 125°C for all packages.
assumes a high–level state when indicating equality. Also, when the ALU is
in the subtract mode the Cn+4 output can be used to indicate relative
magnitude as shown in this table:
Data
PIN ASSIGNMENT
Level Cn Cn+4 Magnitude B0 1 24 VDD
Active H H v
A B
A0 2 23 A1
High L H A<B
H L A>B S3 3 22 B1
L L AwB
S2 4 21 A2
Active L L AvB
S1 5 20 B2
Low H L A<B
L H A>B S0 6 19 A3
H H w
A B
Cn 7 18 B3
• Functional and Pinout Equivalent to 74181.
MC 8 17 G
• Diode Protection on All Inputs
F0 9 16 Cn+4
• All Outputs Buffered
• Supply Voltage Range = 3.0 Vdc to 18 Vdc F1 10 15 P
• Capable of Driving Two Low–power TTL Loads or One Low–power F2 11 14 A=B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load over the Rated Temperature Range
VSS 12 13 F3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
– 0.5 to + 18.0
Unit
V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MOTOROLA CMOS LOGIC DATA MC14581B

6–489
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.8 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.7 µA/kHz) f + IDD
Per Package) 15 IT = (5.5 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.008.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14581B MOTOROLA CMOS LOGIC DATA

6–490
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Sum in to Sum Out tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 620 ns 5.0 — 705 1410
tPLH, tPHL = (0.66 ns/pF) CL + 217 ns 10 — 250 500
tPLH, tPHL = (0.5 ns/pF) CL + 155 ns 15 — 180 360
Sum in to Sum Out (Logic Mode) tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 520 ns tPHL 5.0 — 605 1210
tPLH, tPHL = (0.66 ns/pF) CL + 182 ns 10 — 215 430
tPLH, tPHL = (0.5 ns/pF) CL + 155 ns 15 — 180 360
Sum in to A = B tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 870 ns tPHL 5.0 — 955 1910
tPLH, tPHL = (0.66 ns/pF) CL + 297 ns 10 — 330 660
tPLH, tPHL = (0.5 ns/pF) CL + 220 ns 15 — 245 490
Sum in to P or G tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 400 ns tPHL 5.0 — 485 970
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns 10 — 180 360
tPLH, tPHL = (0.5 ns/pF) CL + 105 ns 15 — 130 260
Sum in to Cn+4 tPLH ns
tPLH, tPHL = (1.7 ns/pF) CL + 530 ns 5.0 — 615 1230
tPLH, tPHL = (0.66 ns/pF) CL + 187 ns 10 — 220 440
tPLH, tPHL = (0.5 ns/pF) CL + 135 ns 15 — 160 360
Carry in to Sum Out tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 295 ns tPHL 5.0 — 380 760
tPLH, tPHL = (0.66 ns/pF) CL + 112 ns 10 — 145 290
tPLH, tPHL = (0.5 ns/pF) CL + 80 ns 15 — 105 210
Carry in to Cn+4 tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns tPHL 5.0 — 305 610
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns 10 — 120 240
tPLH, tPHL = (0.5 ns/pF) CL + 60 ns 15 — 85 170
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

AC TEST SETUP REFERENCE TABLE

AC Paths DC Data Inputs Fig.
g 3
Test Inputs Outputs To VSS To VDD Mode Waveform
Sumin to Sumout Remaining A’s
A0 Any F All B’s Add #1
Delay Time Cn
Sumin to P Remaining A’s
A0 P All B’s Add #1
Delay Time Cn
Sumin to G All A’s
B0 G Remaining B’s Add #1
Delay Time Cn
Sumin to Cn+4 All A’s
B0 Cn+y Remaining B’s Add #2
Delay Time Cn
Cn to Sumout
Cn Any F All A’s All B’s Add #1
Delay Time
Cn to Cn+4
Cn Cn+4 All A’s All B’s Add #1
Delay Time
Sumin to A = B All B’s
A0 A=B Cn Sub #2
Delay Time Remaining A’s
Sumin to Sumout
Exclusive
Delay Time B0 Any F All A’s M #2
OR
(Logic Mode)

MOTOROLA CMOS LOGIC DATA MC14581B

6–491
 Vout = VOH Vout = VOH
VDD VDD

S0 S1 S2 S3 S0 S1 S2 S3
F0 F0
VDD A0 VDD A0
F1 F1
A1 A1
A2 F2 IOH A2 F2 IOH
A3 F3 A3 F3
B0 B0
A=B A=B
B1 B1
B2 Cn+4 B2 Cn+4
B3 G B3 G
HIGH FOR Cn HIGH FOR Cn
ALL OUTPUTS P ALL OUTPUTS P
MC MC
EXCEPT Cn+4 EXTERNAL EXCEPT Cn+4 EXTERNAL
VSS POWER VSS POWER
SUPPLY SUPPLY

Figure 1. Typical Source Current Test Circuit Figure 2. Typical Sink Current Test Circuit

LOAD A TP 20 ns
out
VDD 20 ns
VDD
90%
50 pF TPin
10% 0V
TPin tPHL
S0 S1 S2 S3 tTLH
SEE AC TEST
A0 F0 LOAD A
SETUP
PULSE F1 LOAD A #1 VOH
REFERENCE A1
GENERATOR TABLE FOR A2 F2 LOAD A TPout 10%
CONNECTIONS A3 VOL
F3 LOAD A
B0 tPLH
tTHL
B1 A=B LOAD A tTHL
B2 Cn+4 LOAD A VOH
90%
B3 #2
G LOAD A
Cn TPout 10%
P LOAD A VOL
MC tPHL tTLH
tPLH

Figure 3. Switching Time Test Circuit and Waveforms

VDD

LOAD A TPout

S0 S1 S2 S3 50 pF
F0 LOAD A
A0
TPin A1 F1 LOAD A
A2 F2 LOAD A
A3 F3 LOAD A
PULSE 20 ns
B0 20 ns
GENERATOR
B1 A=B LOAD A VDD
B2 90%
DUTY CYCLE = 50% Cn+4 LOAD A TPin 50%
B3 10%
G LOAD A 0V
Cn
P LOAD A VARIABLE
MC
WIDTH

Figure 4. Dynamic Power Dissipation Test Circuit and Waveform

MC14581B MOTOROLA CMOS LOGIC DATA

6–492
 BLOCK DIAGRAM BLOCK DIAGRAM
(ACTIVE LOW) (ACTIVE HIGH)
3 3
FUNCTION
4 4
SELECT
INPUTS 5 5
6 VDD = PIN 24 6
VSS = PIN 12
S0 S1 S2 S3 S0 S1 S2 S3
2 A0 2 A0
F0 9 F0 9
23 A1 23 A1
WORD A F1 10 OUTPUT F1 10
21 A2 FUNCTION 21 A2
F2 11 F2 11
19 A3 19 A3
F3 13 F3 13
1 B0 1 B0
22 B1 22 B1
WORD B A=B 14 COMPARISON OUTPUT A=B 14
20 B2 20 B2
Cn+4 16 RIPPLE CARRY OUTPUT Cn+4 16
18 B3 18 B3
G 17 LOOK AHEAD G 17
CARRY IN 7 Cn 7 Cn
P 15 CARRY OUTPUTS P 15
MODE CONTROL 8 MC 8 MC

TRUTH TABLE
Function Select Inputs/Outputs Active Low Inputs/Outputs Active High
Logic Arithmetic* Logic Arithmetic*
Function Function Function Function
S3 S2 S1 S0 (MC = H) (MC = L, Cn = L) (MC = H) (MC = L, Cn = H)
L L L L A A minus 1 A A
L L L H AB AB minus 1 A+B A+B
L L H L A+B AB minus 1 AB A+B
L L H H Logic “1” minus 1 Logic “0” minus 1
L H L L A+B A plus (A + B) AB A plus AB
L H L H B AB plus (A + B) B (A + B) plus AB
L H H L A ęB A minus B minus 1 A ęB A minus B minus 1
L H H H A+B A+B AB AB minus 1
H L L L AB A plus (A + B) A+B A plus AB
H L L H A ęB A plus B A ęB A plus B
H L H L B AB plus (A + B) B (A + B) plus AB
H L H H A+B A+B AB AB minus 1
H H L L Logic “0” A plus A Logic “1” A plus A
H H L H AB AB plus A A+B (A + B) plus A
H H H L AB AB plus A A+B (A + B) plus A
H H H H A A A A minus 1
* Expressed as two’s complements. For arithmetic function with Cn in the opposite state, the resulting
function is as shown plus 1.

MOTOROLA CMOS LOGIC DATA MC14581B

6–493
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14582B
Look-Ahead Carry Block
L SUFFIX
The MC14582B is a CMOS look–ahead carry generator capable of CERAMIC
anticipating a carry across four binary adders or groups of adders. The CASE 620
device is cascadable to perform full look–ahead across n–bit adders. Carry,
generate–carry, and propagate–carry functions are provided as enumerated
in the pin designation table shown below. P SUFFIX
• Expandable to any Number of Bits PLASTIC
CASE 648
• All Buffered Outputs
• Low Power Dissipation
• Diode Protection on All Inputs D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
CASE 751B
• Capable of Driving Two Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBCP Plastic
Symbol Parameter Value Unit MC14XXXBCL Ceramic
MC14XXXBD SOIC
VDD DC Supply Voltage – 0.5 to + 18.0 V
TA = – 55° to 125°C for all packages.
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PIN ASSIGNMENT
PD Power Dissipation, per Package† 500 mW
G1 1 16 VDD
Tstg Storage Temperature – 65 to + 150 _C
P1 2 15 P2
TL Lead Temperature (8–Second Soldering) 260 _C
G0 3 14 G2
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: P0 4 13 Cin
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C G3 5 12 Cn+x
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
P3 6 11 Cn+y
LOGIC EQUATIONS P 7 10 G
Cn+x = G0 + (P0  Cn)
VSS 8 9 Cn+z
Cn+y = G1 + (P1  G0) + (P1  P0  Cn)
Cn+z = G2 + (P2  G1) + (P2  P1 G0) + (P2  P1  P0  Cn)
G = G3 + (P3  G2) + (P3  P2  G1) + (P1  P2  P3  G0)
P = P3  P2  P1  P0

PIN DESIGNATIONS
Designation Pin No’s Function
G0, G1, G2, G3 3, 1, 14, 5 Active–Low
Carry–Generate Inputs
P0, P1, P2, P3 4, 2, 15, 6 Active–Low
Carry–Propagate Inputs
Cn 13 Carry Input
Cn+x, Cn+y 12, 11, 9 Carry Outputs
Cn+z
G 10 Active–Low Group
Carry–Generate Output
P 7 Active–Low Group
Carry–Propagate Output

MC14582B MOTOROLA CMOS LOGIC DATA

6–494
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.4 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.8 µA/kHz) f + IDD
Per Package) 15 IT = (4.3 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14582B

6–495
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 260 ns tPHL 5.0 — 345 690
tPLH, tPHL = (0.66 ns/pF) CL + 107 ns 10 — 140 280
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns 15 — 110 220
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD

Cin
G0
Cn+x
20 ns 20 ns G1 CL
VDD G2 Cn+y
Vin 90% CL
50% G3
PULSE Cn+z
10% V P0 CL
SS GENERATOR Vin
VARIABLE P1 P
WIDTH CL
P2
G
P3 CL

Figure 1. Dynamic Power Dissipation

Test Circuit and Waveform

Vout = VOH Vout = VOL

VDD VDD

16 16

Cin Cin
G0 G0
Cn+x Cn + x
G1 G1
G2 Cn+y G2 Cn + y
G3 G3
Cn+z IOH Cn + z IOL
P0 P0
P1 P P1 P
P2 P2
G G
P3 P3

8 VSS 8 VSS
EXTERNAL EXTERNAL
POWER POWER
SUPPLY SUPPLY

Figure 2. Source Current Test Circuit Figure 3. Sink Current Test Circuit

MC14582B MOTOROLA CMOS LOGIC DATA

6–496
 TEST TABLE
AC Paths DC Data
Input Output To VSS To VDD
P0 P Remaining G’s
VDD Vout P’s, Cn
Cin G0 G P’s, Cn Remaining
G0 Cn+x G’s
G1 Cn+y Cn Cn+x, Cn+y, P’s G’s
SEE G2 CL
PULSE Cn+z
TEST G3 Cn+z
GENERATOR
TABLE P0 20 ns 20 ns
P VDD
P1 Vin 90%
P2 G 50% 10% VSS
VSS P3 tPLH tPHL
VOH
Vout
VOL
tTLH tTHL
Figure 4. Switching Time Test Circuit and Waveforms

TYPICAL APPLICATIONS
MC14581B

Cn Cn+4 Cn Cn+4 Cn Cn+4 Cn Cn+4

16–BIT ALU, RIPPLE CARRY

MC14581B

Cn Cn Cn Cn Cn+4
G P G P G P G P

G0 P0 Cn+x G1 P1 Cn+y G2 P2 Cn+z G3 P3

Cn
MC14582B G P

16–BIT ALU, TWO LEVEL LOOK–AHEAD

MC14581B

Cn Cn Cn Cn Cn+4 Cn Cn Cn Cn Cn+4
G P G P G P G P G P G P G P G P

G0 P0 Cn+x G1 P1 Cn+y G2 P2 Cn+z G3 P3 G0 P0 Cn+x G1 P1 Cn+y G2 P2 Cn+z G3 P3

Cn MC14582B Cn MC14582B
G P G P

32–BIT ALU, TWO LEVEL LOOK–AHEAD OVER 16–BIT GROUPS

MC14581B

Cn Cn+4 Cn+4 Cn Cn Cn Cn Cn+4 Cn Cn+4 Cn Cn

G P G P G P G P G P G P

G0 P0 Cn+x G1 P1 Cn+y G2 P2 Cn+z G3 P3 G0 P0 Cn+x G1 P1 Cn+y

Cn MC14582B Cn MC14582B
G P

COMBINED TWO–LEVEL LOOK–AHEAD AND RIPPLE CARRY ALU

MC14581B

Cn Cn Cn Cn Cn Cn Cn Cn Cn+4 Cn
G P G P G P G P G P G P G P G P G P

G0 P0 Cn+x G1 P1 Cn+y G2 P2 Cn+z G3 P3 G0 P0 Cn+x G1 P1 Cn+y G2 P2 Cn+z G3 P3 G0 P0 Cn+x

Cn MC14582B Cn MC14582B Cn MC14582B
G P G P

G0 P0 Cn+x G1 P1 Cn+y
Cn MC14582B

64–BIT ALU, FULL–CARRY LOOK–AHEAD IN THREE LEVELS.

A AND B INPUTS AND F OUTPUTS ARE NOT SHOWN (MC14581B).

MOTOROLA CMOS LOGIC DATA MC14582B

6–497
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14583B
Dual Schmitt Trigger
L SUFFIX
The MC14583B is a dual Schmitt trigger constructed with complementary CERAMIC
P–channel and N–channel MOS devices on a monolithic silicon substrate. CASE 620
Each Schmitt trigger is functionally independent except for a common
3–state input and an internally–connected Exclusive OR output for use in
line receiver applications. Trigger levels are adjustable through the positive, P SUFFIX
negative, and common terminals with the use of external resistors. PLASTIC
Applications include the speed–up of a slow waveform edge in interface CASE 648
receivers, level detectors, etc.
• Diode Protection on All Inputs D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
• Single Supply Operation CASE 751B
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Resistor Adjustable Trigger Levels MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
– 0.5 to + 18.0
Unit
V
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
BLOCK DIAGRAM
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin 6 5 7
VDD = PIN 16
PD Power Dissipation, per Package† 500 mW VSS = PIN 8
Tstg Storage Temperature – 65 to + 150 _C
APos ANeg ACom
TL Lead Temperature (8–Second Soldering) 260 _C
Aout 4
* Maximum Ratings are those values beyond which damage to the device may occur. 9 Ain
Aout 11
†Temperature Derating:
13 Dis 14
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Bout 10
15 Bin
Bout 12
LOGIC DIAGRAM BPos BNeg BCom
POSITIVE A NEGATIVE A
6 5
7 COMMON A
2 3 1
Ain 9 4 Aout

TRUTH TABLE
11 Aout Inputs Outputs
3–STATE
13
A B Dis Aout Aout Bout Bout ę
OUTPUT DISABLE 0 0 0 0 Z 0 Z 0
14 EXCLUSIVE OR 0 0 1 0 1 0 1 0
0 1 0 0 Z 1 Z 1
0 1 1 0 1 1 0 1
1 0 0 1 Z 0 Z 1
Bin 15 10 Bout 1 0 1 1 0 0 1 1
1 1 0 1 Z 1 Z 0
1 1 1 1 0 1 0 0
12 Bout Z = High impedance at output

1 COMMON B VDD = PIN 16

2 3
VSS = PIN 8
POSITIVE B2 NEGATIVE B

MC14583B MOTOROLA CMOS LOGIC DATA

6–498
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 1.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
15 — 1.0 — 0.0015 1.0 — 30
Total Supply Current**† IT 5.0 IT = (1.33 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.65 µA/kHz) f + IDD
Per Package) 15 IT = (3.98 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must BCom 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and BPos 2 15 Bin
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. BNeg 3 14 
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Aout 4 13 DIS
ANeg 5 12 Bout
APos 6 11 Aout
ACom 7 10 Bout
VSS 8 9 Ain

MOTOROLA CMOS LOGIC DATA MC14583B

6–499
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise Time tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130
Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Ain, Bin to Aout, Bout tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 565 ns 5.0 — 650 1300
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns 10 — 230 460
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns 15 — 150 300
Ain, Bin to Aout, Bout tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 1015 ns tPHL 5.0 — 1100 2200
tPLH, tPHL = (0.66 ns/pF) CL + 347 ns 10 — 380 760
tPLH, tPHL = (0.5 ns/pF) CL + 235 ns 15 — 260 520
Ain, Bin to Exclusive OR tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 665 ns tPHL 5.0 — 750 1500
tPLH, tPHL = (0.66 ns/pF) CL + 257 ns 10 — 280 560
tPLH, tPHL = (0.5 ns/pF) CL + 145 ns 15 — 170 340
3–State Enable, Disable Delay Time (see figure 5) ton, ns
ton, toff = (1.7 ns/pF) CL + 140 ns toff 5.0 — 225 450
ton, toff = (0.66 ns/pF) CL + 57 ns 10 — 90 180
ton, toff = (0.5 ns/pF) CL + 30 ns 15 — 55 110
Positive Threshold Voltage VT+ 5.0 — 3.30 — Vdc
(R1, R2 = 5.0 kΩ) 10 — 5.70 —
15 — 8.20 —
Negative Threshold Voltage VT– 5.0 — 1.70 — Vdc
(R1, R2 = 5.0 kΩ) 10 — 4.30 —
15 — 6.80 —
Hysteresis Voltage VH 5.0 0.85 1.70 3.40 Vdc
(R1, R2 = 5.0 kΩ) 10 0.70 1.40 2.80
15 0.70 1.40 2.80
Threshold Voltage Variation, A to B ∆VT 5.0 — 0.1 — Vdc
(R1, R2 = 5.0 kΩ) 10 — 0.15 —
15 — 0.20 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14583B MOTOROLA CMOS LOGIC DATA

6–500
VDD Vout
Output Source Output Sink
Characteristics Characteristics
VDD
Test
1 NJ VGS = – VDD Test
NJ VGS = VDD
Value VDS = Vout – VDD Value VDS = Vout
VSS Ain Aout Output Switch Position Switch Position
SW1 Under Test SW1 SW2 SW1 SW2
Aout

2
DIS Aout, Bout 1 1 2 2
2
Bout Aout, Bout 2 2 1 1
Bin Bout IO Exclusive OR 1 2 1 1
SW2
1 VSS EXTERNAL
POWER
SUPPLY

Figure 1. Typical Output Source and Sink Characteristics Test Circuit

VDD

500 µF ID 0.01 µF
CERAMIC

PULSE
GENERATOR 1 Ain Aout
fout, Ain
Aout

CL fout, Bin
DIS
CL
Bout
PULSE CL
GENERATOR 2 Bin Bout
CL
VSS CL

Figure 2. Power Dissipation Test Circuit and Waveforms

A — Feedback scheme for independent threshold adjustment: 80

R1 70
TYPICAL THRESHOLD POINT (%VDD)

POSITIVE

COMMON 60
R2
NEGATIVE 50

40

B — Feedback scheme for hysteresis adjustment: 30 VSS = 0

VDD = 5.0 V
POSITIVE
20 VDD = 10 V
R1
COMMON VDD = 15 V
10
6 8
NEGATIVE 10 20 40 100 1.0 k 10 k 100 k 1.0 M
R1, R2, RESISTANCE (OHMS)

Figure 3. Typical Threshold Points

MOTOROLA CMOS LOGIC DATA MC14583B

6–501
 VDD

PULSE
GENERATOR 1 Ain Aout
Aout
PULSE
GENERATOR 2 DIS 
Bout
PULSE
Bin Bout
GENERATOR 3
VSS CL CL CL CL CL
INPUT = tr = tf = 20 ns

VDD
Ain 50%
VSS

VDD
50%
Bin
VSS

VDD
3–STATE 50%
DISABLE VSS
tPLH tf tr
tPHL
VOH
90%
Aout 50%
10%
VOL
tPHL tr tf
tPLH VOH
90%
50%
Bout 10%
VOL
tPHL ton
tPLH tf toff
VOH
90%
50%
Aout 10%
tr VOL
tPLH ton
tPHL toff
VOH
Bout
tf tr VOL
tPHL tPHL
tPLH tPLH
VOH
90%
EXCLUSIVE 50%
OR 10%
VOL
tf tr

NOTE: Dashed lines indicate high output resistance

Figure 4. Switching Time Test Circuit and Waveforms

MC14583B MOTOROLA CMOS LOGIC DATA

6–502
 VDD VDD

Test Switch Position

PULSE 1 k*
Ain Aout ton HL 1
GENERATOR 1
Aout 1 ton LH 2
PULSE DIS  SW toff HL 2
GENERATOR 2 Bout 2
toff LH 1
Bin Bout
CL 1 k*

* Metal film, ± 1%, 1/4 W or greater

VSS
CL = 15 pF, which includes test circuit capacitance.

VDD
Ain
VSS

VDD
Bin
VSS

VDD
3–STATE 50%
DISABLE VSS
toff LH toff LH
ton LH
ton HL VOH
VOH′ 90%
Aout VOH 10% (VOH – VOL′)
90% VOL′
10% VOL
VOL toff LH
ton LH toff HL
VOH
VOH′ 90% VOH 10% (VOH – VOL′)
Bout 90%
10% VOH′ VOL′
VOL

SWITCH POSITION 2 SWITCH POSITION 1

VOL′ and VOH′ refer to the levels present as a result of the 1 k ohm load resistors.

Figure 5. 3–State Switching Time Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14583B

6–503
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14584B
Hex Schmitt Trigger
L SUFFIX
The MC14584B Hex Schmitt Trigger is constructed with MOS P–channel CERAMIC
and N–channel enhancement mode devices in a single monolithic structure. CASE 632
These devices find primary use where low power dissipation and/or high
noise immunity is desired. The MC14584B may be used in place of the
MC14069UB hex inverter for enhanced noise immunity to “square up” slowly P SUFFIX
changing waveforms. PLASTIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 646

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load over the Rated Temperature Range D SUFFIX
• Double Diode Protection on All Inputs SOIC
• Can Be Used to Replace MC14069UB CASE 751A
• For Greater Hysteresis, Use MC14106B which is Pin–for–Pin
Replacement for CD40106B and MM74Cl4 ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBD SOIC
Symbol Parameter Value Unit TA = – 55° to 125°C for all packages.
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA LOGIC DIAGRAM
per Pin
PD Power Dissipation, per Package† 500 mW 1 2

Tstg Storage Temperature – 65 to + 150 _C

3 4
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: 5 6
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
9 8

EQIVALENT CIRCUIT SCHEMATIC 11 10

(1/6 OF CIRCUIT SHOWN)
13 12

VDD = PIN 14
VSS = PIN 7

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MC14584B MOTOROLA CMOS LOGIC DATA

6–504
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
Vin = 0 “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
15 — 1.0 — 0.0015 1.0 — 30
Total Supply Current**† IT 5.0 IT = (1.8 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.6 µA/kHz) f + IDD
Per Package) 15 IT = (5.4 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Hysteresis Voltage VH‡ 5.0 0.27 1.0 0.25 0.6 1.0 0.21 1.0 Vdc
10 0.36 1.3 0.3 0.7 1.2 0.25 1.2
15 0.77 1.7 0.6 1.1 1.5 0.50 1.4
Threshold Voltage VT+ Vdc
Positive–Going 5.0 1.9 3.5 1.8 2.7 3.4 1.7 3.4
10 3.4 7.0 3.3 5.3 6.9 3.2 6.9
15 5.2 10.6 5.2 8.0 10.5 5.2 10.5
Negative–Going VT– 5.0 1.6 3.3 1.6 2.1 3.2 1.5 3.2 Vdc
10 3.0 6.7 3.0 4.6 6.7 3.0 6.7
15 4.5 9.7 4.6 6.9 9.8 4.7 9.9
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
‡VH = VT+ – VT– (But maximum variation of VH is specified as less than VT + max – VT – min).

MOTOROLA CMOS LOGIC DATA MC14584B

6–505
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

Characteristic Symbol
VDD
Vdc Min Typ # Max Unit
Output Rise Time tTLH 5.0 — 100 200 ns
10 — 50 100
15 — 40 80
Output Fall Time tTHL 5.0 — 100 200 ns
10 — 50 100
15 — 40 80
Propagation Delay Time tPLH, tPHL 5.0 — 125 250 ns
10 — 50 100
15 — 40 80
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD 20 ns 20 ns
14 VDD
INPUT 90%
PULSE OUTPUT 50%
GENERATOR 10% VSS
INPUT
CL tPHL tPLH
7 VSS 90% VOH
OUTPUT 50%
10% VOL
tf tr

Figure 1. Switching Time Test Circuit and Waveforms

Vin Vout

VH VDD VH VDD

VT+ VT+
Vin VT– Vin VT–

VSS VSS

VDD VDD

Vout Vout

VSS VSS
(a) Schmitt Triggers will square up inputs with slow (b) A Schmitt trigger offers maximum noise immunity
rise and fall times. in gate applications.
Figure 2. Typical Schmitt Trigger Applications

VDD
PIN ASSIGNMENT
Vout , OUTPUT VOLTAGE (Vdc)

IN 1 1 14 VDD
OUT 1 2 13 IN 6
IN 2 3 12 OUT 6
OUT 2 4 11 IN 5
IN 3 5 10 OUT 5
OUT 3 6 9 IN 4
VSS 7 8 OUT 4

0
0 VT– VT+ VDD
VH
Vin, INPUT VOLTAGE (Vdc)
Figure 3. Typical Transfer Characteristics

MC14584B MOTOROLA CMOS LOGIC DATA

6–506
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14585B
4-Bit Magnitude Comparator
The MC14585B 4–Bit Magnitude Comparator is constructed with comple-
L SUFFIX
mentary MOS (CMOS) enhancement mode devices. The circuit has eight
CERAMIC
comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0), three cascading inputs CASE 620
(A < B, A = B, and A > B), and three outputs (A < B, A = B, and A > B). This
device compares two 4–bit words (A and B) and determines whether they
are “less than”, “equal to”, or “greater than” by a high level on the appropriate P SUFFIX
output. For words greater than 4–bits, units can be cascaded by connecting PLASTIC
outputs (A > B), (A < B), and (A = B) to the corresponding inputs of the next CASE 648
significant comparator. Inputs (A < B), (A = B), and (A > B) on the least
significant (first) comparator are connected to a low, a high, and a low,
D SUFFIX
respectively.
SOIC
Applications include logic in CPU’s, correction and/or detection of
CASE 751B
instrumentation conditions, comparator in testers, converters, and controls.
• Diode Protection on All Inputs ORDERING INFORMATION
• Expandable MC14XXXBCP Plastic
• Applicable to Binary or 8421–BCD Code MC14XXXBCL Ceramic
• Supply Voltage Range = 3.0 Vdc to 18 Vdc MC14XXXBD SOIC
• Capable of Driving Two Low–power TTL Loads or One Low–power TA = – 55° to 125°C for all packages.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load over the Rated Temperature Range
• Can be Cascaded – See Fig. 3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
BLOCK DIAGRAM

4 (A > B)in
VDD DC Supply Voltage – 0.5 to + 18.0 V
6 (A = B)in
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V 5 (A < B)in (A > B)out 13
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA 10 A0
per Pin 11 B0
7 A1 (A = B)out 3
PD Power Dissipation, per Package† 500 mW 9 B1
Tstg Storage Temperature – 65 to + 150 _C 2 A2
1 B2 (A < B)out 12
TL Lead Temperature (8–Second Soldering) 260 _C
15 A3
* Maximum Ratings are those values beyond which damage to the device may occur. 14 B3
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C VDD = PIN 16
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C VSS = PIN 8
TRUTH TABLE (x = Don’t Care)
Inputs
Comparing Cascading Outputs
A3, B3 A2, B2 A1, B1 A0, B0 A<B A=B A>B A<B A=B A>B
A3 > B3 x x x x x x 0 0 1
A3 = B3 A2 > B2 x x x x x 0 0 1
A3 = B3 A2 = B2 A1 > B1 x x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 > B0 x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 x 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 x 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 1 x 1 1 0
A3 = B3 A2 = B2 A1 = B1 A0 < B0 x x x 1 0 0
A3 = B3 A2 = B2 A1 < B1 x x x x 1 0 0
A3 = B3 A2 < B2 x x x x x 1 0 0
A3 < B3 x x x x x x 1 0 0

MOTOROLA CMOS LOGIC DATA MC14585B

6–507
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.6 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.2 µA/kHz) f + IDD
Per Package) 15 IT = (1.8 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT
B2 1 16 VDD
A2 2 15 A3
(A = B)out 3 14 B3
(A u B)in 4 13 (A u B)out
(A t B)in 5 12 (A t B)out
(A = B)in 6 11 B0
A1 7 10 A0
VSS 8 9 B1

MC14585B MOTOROLA CMOS LOGIC DATA

6–508
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Turn–On, Turn–Off Delay Time tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 345 ns tPHL 5.0 — 430 860
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns 10 — 180 360
tPLH, tPHL = (0.5 ns/pF) CL + 105 ns 15 — 130 260
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns
20 ns
VDD
A3
1 VSS
2f VDD
B3
VSS
20 ns 20 ns
VOH
(A > B)out VDD
90%
VOL 50%
B0
VOH 10% VSS
(A = B)out tPLH tPHL
VOL VOH
90%
VOH 50%
(A < B)out
(A < B)out 10% VOL
VOL
tTLH tTHL
Inputs (A>B) and (A=B) high, and inputs B2, A2, B1,
A1, B0, A0 and (A<B) low. Inputs (A>B) and (A=B) high, and inputs B3, A3, B2,
f in respect to a system clock. A2, B1, A1, A0, and (A<B) low.

Figure 1. Dynamic Power Dissipation Figure 2. Dynamic Signal Waveforms

Signal Waveforms

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14585B

6–509
 WORD
B = B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
WORD
A= A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
VSS VDD VSS

(A<B)
(A=B)
(A>B)
B3 A3 B2 A2 B1 A1 B0 A0
OUTPUT MC14585B

(A<B)
(A=B)
(A>B)
INPUTS

MC14585B

MC14585B

WORD B = B11, B10, ..., B0.

WORD A = A11, A10, ..., A0.
(A<B)
(A=B)
(A>B)

OUTPUTS
Figure 3. Cascading Comparators

LOGIC DIAGRAM
15
A3

14
B3
2
A2

1
B2
7 12
A1 (A < B)out

9
B1
10
A0

11
B0

5
(A < B)in
3
6 (A = B)out
(A = B)in
13
4 (A > B)out
(A > B)in

MC14585B MOTOROLA CMOS LOGIC DATA

6–510
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14597B
MC14598B
8-Bit Bus-Compatible Latches
The MC14597B and MC14598B are 8–bit latches, one addressed with an
internal counter and the other addressed with an external binary address.
The 8 latch–outputs are high drive, three–state and bus line compatible. The L SUFFIX
drive capability allows direct applications with MPU systems such as the CERAMIC
Motorola 6800 family. CASE 620
With MC14597B, a 3–bit address counter (clocked on the falling edge of
Increment) selects the appropriate latch. The latches of the MC14598B are
accessed via the Address pins, A0, A1, and A2. A Full Flag is provided on P SUFFIX
the MC14597B to indicate the position of the Address counter. PLASTIC
All 8 outputs from the latches are available in parallel when Enable is in the CASE 648
low state. Data is entered into a selected latch from the Data pin when the
Strobe is high. Master reset is available on both parts.
• Serial Data Input D SUFFIX
• Three–State Bus Compatible Parallel Outputs SOIC
• Three–State Control Pin (Enable) TTL Compatible Input CASE 751B
• Open Drain Full Flag (Multiple Latch Wire–O Ring)
• Master Reset ORDERING INFORMATION
• Level Shifting Inputs on All Except Enable MC14597BCP Plastic
MC14597BCL Ceramic
• Diode Protection — All Inputs
MC14597BDW SOIC
• Supply Voltage Range — 3.0 Vdc to 18 Vdc
TA = – 55° to 125°C for all packages.
• Capable of Driving TTL Over Rated Temperature Range
With Fanout as Follows:
1 TTL Load
4 LSTTL Loads L SUFFIX
CERAMIC
BLOCK DIAGRAMS CASE 726
MC14597B

RESET 2 4 ENABLE
RESET P SUFFIX
LOGIC D0 1 16 VDD PLASTIC
CASE 707
RESET 2 15 D1
DATA 3 1 D0
STROBE 6 15 D1 DATA 3 14 D2 ORDERING INFORMATION
14 D2
THREE ENABLE 4 13 D3 MC14598BCP Plastic
3–BIT 13 D3
ADDRESS 8 STATE MC14598BCL Ceramic
ADDRESS 12 D4
DECODER LATCHES OUTPUT FULL 5 12 D4
COUNTER 11 D5
BUFFERS TA = – 55° to 125°C for all packages.
10 D6
7 9 D7
STROBE 6 11 D5
INCREMENT INCREMENT 7 10 D6
FULL
VDD = 16 LOGIC VSS 8 9 D7
VSS = 8
5 D0 1 18 VDD
FULL
RESET 2 17 D1
MC14598B
ENABLE OUTPUT DATA 3 16 D2
4 TRUTH TABLE ENABLE 4 15 D3
RESET 2
DATA 3 1 D0 Enable Outputs NC 5 14 D4
STROBE 6 17 D1
THREE
16 D2
1 High Impedance STROBE 6 13 D5
A0 7 8 STATE
15 D3 0 Dn
A1 8 ADDRESS LATCHES OUTPUT
14 D4 A0 7 12 D6
A2 10 DECODER BUFFERS
13 D5
Dn = State of nth latch A1 8 11 D7
12 D6
VDD = 18 11 D7
VSS = 9 NC = NO CONNECTION VSS 9 10 A2

MOTOROLA CMOS LOGIC DATA MC14597B MC14598B

6–511
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit This device contains protection circuitry to
VDD DC Supply Voltage – 0.5 to + 18.0 V guard against damage due to high static
voltages or electric fields. However, pre-
Vin Input Voltage, Enable (DC or Transient) – 0.5 to VDD + 0.5 V
cautions must be taken to avoid applications of
Vin Input Voltage, All other Inputs – 0.5 to VDD + 12 V any voltage higher than maximum rated volt-
(DC or Transient) ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
Vout Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
to the range VSS v (Vin or Vout) v
VDD.
Iin, lout Input or Output Current (DC or Transient), ± 10 mA Unused inputs must always be tied to an
per Pin appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
“P and D/DW” Packages: – 7.0 mW/C From 65_C To 125_C Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
“L” Packages: – 12 mW/_C From 100_C To 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic Symbol
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ # Max Min
125_C
Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage** — Enable “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 0.8 — 1.1 0.8 — 0.8
(VO = 9.0 or 1.0 Vdc) 10 — 1.6 — 2.2 1.6 — 1.6
(VO = 13.5 or 1.5 Vdc) 15 — 2.4 — 3.4 2.4 — 2.4
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 2.0 — 2.0 1.9 — 2.0 —
(VO = 1.0 or 9.0 Vdc) 10 6.0 — 6.0 3.1 — 6.0 —
(VO = 1.5 or 13.5 Vdc) 15 10 — 10 4.3 — 10 —
Input Voltage “0” Level VIL Vdc
Other Inputs
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current Source IOH mAdc
(Full — Sink Only)
(VOH = 4.6 Vdc) 5.0 – 1.0 – – 1.0 – 2.0 — – 1.0 —
(VOH = 9.5 Vdc) 10 — — — – 6.0 — — —
(VOH = 13.5 Vdc) 15 — — — – 12 — — —
(VOL = 0.4 Vdc) Sink IOL 5.0 1.6 — 1.6 3.2 — 1.6 — mAdc
(VOL = 0.5 Vdc) 10 — — — 6.0 — — —
(VOL = 1.5 Vdc) 15 — — — 12 — — —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 3.0 µAdc
Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
**Total Supply Current at an IT 5.0 IT = (2.0 µA/kHz) f + IDD µAdc
**External Load Capacitance of 10 IT = (4.0 µA/kHz) f + IDD
**130 pF IT = (6.0 µA/kHz) f + IDD
†Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.

MC14597B MC14598B MOTOROLA CMOS LOGIC DATA

6–512
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (TA = 25_C, CL = 130 pF + 1 TTL Load)

VDD
All Types
Characteristic Symbol Vdc Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (0.5 ns/pF) CL + 35 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.2 ns/pF) CL + 25 ns 10 — 50 100
tTLH, tTHL = (0.16 ns/pF) CL + 20 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Enable to Output tPHL 5.0 — 160 320
10 — 125 250
15 — 100 200
Strobe to Output 5.0 — 200 400
10 — 100 200
15 — 80 160
Strobe to Full (MC14597B only) 5.0 — 200 400
10 — 100 200
15 — 80 160
Reset to Output 5.0 — 175 350
10 — 90 180
15 — 70 140
Pulse Width tWH, ns
Enable tWL 5.0 320 160 —
10 240 120 —
15 160 80 —
Strobe 5.0 200 100 —
10 100 50 —
15 80 40 —
Increment (MC14597B only) 5.0 200 100 —
10 100 50 —
15 80 40 —
Reset 5.0 300 150 —
10 160 80 —
15 100 50 —
Setup Time tsu ns
Data 5.0 100 50 —
10 50 25 —
15 35 20 —
Address (MC14598B only) 5.0 200 100 —
10 100 50 —
15 70 35 —
Increment (MC14597B only) 5.0 400 200 —
10 200 100 —
15 170 85 —
Hold Time th ns
Data 5.0 100 50 —
10 50 25 —
15 35 20 —
Address (MC14598B only) 5.0 100 50 —
10 50 25 —
15 35 20 —
Reset Removal Time trem 5.0 20 – 25 — ns
10 20 – 15 —
15 20 – 10 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14597B MC14598B

6–513
 MC14597B FUNCTION DIAGRAM
VDD

ENABLE 4
TO OTHER VDD 5 FULL
R
LATCHES D Q
RESET 2
CLK

STROBE 6 VDD

DATA 3
1 D0
TO OTHER
LATCHES

SEVEN
SELECT ONE LATCH VSS
ZERO
R SELECT
15 D1
14 D2
3 STAGE COUNTER 13 D3
AND DECODER 12 D4
ADDITIONAL 7 LATCHES
11 D5
CLK 10 D6
9 D7
INCREMENT 7

MC14597B TIMING DIAGRAMS

D6 (INTERNAL)

D7 (INTERNAL)
tWL tWH

INCREMENT
20 ns tsu
90%
DATA 10%
tsu th
90%
STROBE 10%
tW 20 ns tPHL
FULL
trem

RESET 50%

NOTE: Enable in High state. tW

tTLH tTHL

Dn 1 90% 90%
10% 10%
tPHL

FULL

ENABLE * *
tWL

* 1.4 V with VDD = 5.0 V

NOTES:
1. High–impedance output state (another device controls bus).
2. Reset in High state.

MC14597B MC14598B MOTOROLA CMOS LOGIC DATA

6–514
 MC14598B FUNCTION DIAGRAM

RESET 2 VDD

DATA 3

TO OTHER 1 D0
LATCHES
STROBE 6

ENABLE 4 VSS
EACH LATCH
TO OTHER
LATCHES ZERO
SELECT 17 D1
A0 7 16 D2
15 D3
ADDRESS ADDITIONAL 7 LATCHES 14 D4
A1 8 DECODER 13 D5
12 D6
11 D7
A2 10
(M.S.B)

MC14598B TIMING DIAGRAM

90%
50% 10%
tTHL tPLH
D7 1 50% 90%
10%
tPLH tPHL tTLH
RESET
20 ns
tW 90%
A0, A1, A2 50% 10%
tsu th

DATA
tsu th
90% 90%
STROBE 10% 50% 10%
20 ns 20 ns tW
ENABLE *

tW

* 1.4 V with VDD = 5.0 V

NOTES:
1. High–impedance output state (another device controls bus).
2. Output Load as for MC14597B.

MOTOROLA CMOS LOGIC DATA MC14597B MC14598B

6–515
 LATCH TRUTH TABLE TRUTH TABLE FOR MC14597B
Address Other Address
Strobe Reset Latch Latches Increment Enable Reset Counter Full
0 1 * * X 1 Count Up —
1 1 Data * X 1 No Change —
X 0 0 0 X 1 0 Reset to Zero Set to One

* = No change in state of latch X 0 1 No Change Set to One

X = Don’t care If at To Zero on

X 1 1 ADDRESS 7 Falling Edge
of STROBE
X = Don’t care

TEST LOAD
ALL OUTPUTS
+5.0 V

RL = 2.5 k

Dn

130 pF 11.7 k

Circuit diagrams external to or containing Motorola prod-
ucts are included as a means of illustration only. Complete
information sufficient for construction purposes may not be
fully illustrated. Although the information herein has been
carefully checked and is believed to be reliable. Motorola
assumes no responsibility for inaccuracies. Information here-
in does not convey to the purchaser any license under the
patent rights of Motorola or others.
The information contained herein is for guidance only, with
no warranty of any type, expressed or implied. Motorola re-
serves the right to make any changes to the information and
the product(s) to which the information applies and to discon-
tinue manufacture of the product(s) at any time.

MC14597B MC14598B MOTOROLA CMOS LOGIC DATA

6–516
CMOS Reliability 7
RELIABILITY
Paramount in the mind of every semiconductor user is the
question of device performance versus time. After the
applicability of a particular device has been established, its
effectiveness depends on the length of troublefree service it
can offer. The reliability of a device is exactly that — an
expression of how well it will serve the customer. The
following discussion will attempt to present an overview of
Motorola’s reliability efforts.
BASIC CONCEPTS
It is essential to begin with an explanation of the various
parameters of Reliability. These are probably summarized
best in the Bathtub Curve (Figure 1). The reliability perfor-
mance of a device is characterized by three phases: infant
mortality, useful life, and wearout. When a device is
produced, there is often a small distribution of failure
mechanisms which will exhibit themselves under relatively
moderate stress levels and therefore appear early. This
period of early failures, termed infant mortality is reduced
significantly through proper manufacturing controls and
screening techniques. The most effective period is that in
which only occasional random failure mechanisms appear.
The useful life typically spans a long period of time with a
very low failure rate. The final period is that in which the
devices literally wear out due to continuous phenomena
which existed at the time of manufacture. Using strictly
controlled design techniques and selectivity in applications,
this period is shifted well beyond the lifetime required by the
user.
INFANT MORTALITY
FAILURE RATE
(SUCH AS EARLY
BURN–IN FAILURES)
WEAROUT
USEFUL LIFE FAILURES
10 100 1000 10,000 100,000 1,000,000
TIME (HOURS)
Figure 1.
Both the infant mortality and random failure rate regions
can be described through the same types of calculations.
During this time the probability of having no failures to a
specific point in time can be expressed by the equation:
Po = e–λt
where λ is the failure rate and t is time. Since λ is changing
rapidly during infant mortality, the expression does not
become useful until the random period, where λ is relatively
constant. In this equation λ is failures per unit of time. It is
usually expressed in percent failures per thousand hours.
MOTOROLA CMOS LOGIC DATA
Other forms include FIT (Failures in Time = (%/103 hrs) x
10–4 = 10–9 failures per hour) and MTTF (Mean Time To
Failure) or MTBF (Mean Time Between Failures), both being
equal to 1/λ and having units of hours.
Since reliability evaluations usually involve only samples
of an entire population of devices, the concepts of the Cen-
tral Limit Theorem apply and λ is calculated using x2 distribu-
tion through the equation:
λ vx2 (x, 2r + 2)
2nt
100 – CL
where x =
100
CL = Confidence Limit in percent
r = Number of rejects
n = Number of devices
t = Duration of test
The confidence limit is the degree of conservatism desired
in the calculation. The Central Limit Theorem states that the
values of any sample of units out of a large population will
produce a normal distribution. A 50% confidence limit is
termed the best estimate and is the mean of this distribution.
A 90% confidence limit is a very conservative value and
results in a higher λ which represents the point at which 90%
of the area of the distribution is to the left of that value
(Figure 2). The term (2r + 2) is called the degrees of freedom
and is an expression of the number of rejects in a form
suitable to x2 tables.
50% CL
FREQUENCY
90% CL
λ, FAILURE RATE
Figure 2.
The number of rejects is a critical factor since the definition
of rejects often differs between manufacturers. While
Motorola uses data sheet limits to determine failures, some-
times rejects are counted only if they are catastrophic. Due to
the increasing chance of a test not being representative of
the entire population, as sample size and test time are de-
creased, the x2 calculation produces surprisingly high values
of λ for short test durations even though the true long term
failure rate may be quite low. For this reason relatively large
amounts of data must be gathered to demonstrate the real
long term failure rate.
Since this would require years of testing on thousands of
devices, methods of accelerated testing have been devel-
oped.
Years of semiconductor device testing has shown that
temperature will accelerate failures and that this behavior fits
the form of the Arrhenius equation:
R (t) = R0(t)e – θ/kT
CHAPTER 7
7–2
 NOTE: This data sheet has a new look — the technical content has not changed.

where R(t) = Reaction rate as a function of time and corrosion in plastic devices and metal fatigue for Power
temperature devices.
R0 = A constant
t = Time 1.2 1.6 2.0 2.4 2.8 3.2 3.6
θ = Activation energy in electron volts 1000 k
k = Boltzman’s constant
T = Temperature in degrees Kelvin 100 k
To provide time–temperature equivalents this equation is
applied to failure rate calculations in the form:
10 k
t = t0e θ/kT t2
P2
where t = time

TIME (HOURS)
1.0 k
t0 = A constant
The Arrhenius equation essentially states that reaction
100
rate increases exponentially with temperature. This pro-
duces a straight line when plotted in log–linear paper with a
slope expressed by Θ. Θ may be physically interpreted as 10
t1
the energy threshold of a particular reaction or failure mecha- P1
nism. The activation energy exhibited by semiconductors 1.0 eV
varies from about 0.3 eV. Although the relationships do not 1.0
SLOPE
prohibit devices from having poor failure rates and high
activation energies, good performance usually does not
0.1
imply a high Θ. Studies by Bell Telephone Laboratories have T1 T2
500 200 100 50 0
indicated that an overall Θ for semiconductors is 1.0 eV. This
TEMPERATURE (°C)
value has been accepted by the Rome Air Development
Command for time–temperature acceleration in powered Figure 3. Normalized Time–Temperature
burn–in. Data taken by Motorola on Integrated Circuits have Regressions for Various Activation Energy Values
verified this number and it is therefore applied as our stan-
dard time–temperature regression for extrapolation of high
temperature failure rates to temperatures at which the
devices will be used (Figure 3). For Discrete products, 0.7 eV 100 k
is generally applied. 1.2 1.6 2.0 2.4 2.8 3.2 3.6
To accomplish this, the time in device hours (t1) and tem- 100
perature (T1) of the test are plotted as point P1. A vertical
line is drawn at the temperature of interest (T2) and a line
with a 1.0 eV slope is drawn through point P1. 10
Its intersection with the vertical line defines point P2, and
λ , FAILURE RATE (%/1000 HOURS)

determines the number of equivalent device hours (t2). This

1.0
number may then be used with the x2 formula to determine
the failure rate at the temperature of interest. Assuming T1 of
125_C at t1 of 10,000 hours, a t2 of 7.8 million hours results
λ2
at a T2 of 50_C. If one reject results in the 10,000 device
hours of testing at 125_C, the failure rate at that temperature
will be 0.1%/1,000 hours using a 60% confidence level. One 0.01
reject at the equivalent 7.8 million device hours at 50_C will
result in a 0.0008%/1,000 hour failure rate, as illustrated in
Figure 4. λ1
Three parameters determine the failure rate quoted by the
manufacturer: the failure rate at the test temperature, the
activation energy employed, and the difference between the 0.0001
test temperature and the temperature of the quoted λ. A term
often used in this manipulation is the “acceleration factor” 0.00001
which is simply the equivalent device hours at the lower tem- 500 200 100 50 0
perature divided by the actual test device hours. TEMPERATURE (°C)
Every device will eventually fail, but with the present tech-
niques in Semiconductor design and applications, the wear- Figure 4. Failure Rate
out phase is extended far beyond the lifetime required.
During wearout, as in infant mortality, the failure rate is
changing rapidly and therefore loses its value. The parame- For increased flexibility in working with a broad range of
ter used to describe performance in this area is “Median Life” device hours, the time–temperature regression lines have
and is the point at which 50% of the devices have failed. been normalized to 500_C and the time scale omitted, per-
There are currently only few significant wearout mecha- mitting the user to define the scale based on his own require-
nisms: electromigration of circuit metallization, electrolytic ments.

CHAPTER 7 MOTOROLA CMOS LOGIC DATA

7–3
 NOTE: This data sheet has a new look — the technical content has not changed.

THERMAL MANAGEMENT where

Circuit performance and long–term circuit reliability are
affected by die temperature. Normally, both are improved by
keeping the IC junction temperatures low.
Electrical power dissipated in any integrated circuit is a
source of heat. This heat source increases the temperature
of the die relative to some reference point, normally the
ambient temperature of 25 _C in still air. The temperature
increase, then, depends on the amount of power dissipated
in the circuit and on the net thermal resistance between the
heat source and the reference point.
The temperature at the junction is a function of the pack-
aging and mounting system’s ability to remove heat gen-
erated in the circuit — from the junction region to the ambient
environment. The basic formula for converting power
dissipation to estimated junction temperature is:
TJ = TA + PD(θJC + θCA)
or
TJ = TA + PD(θJA)
TJ = maximum junction temperature
TA = maximum ambient temperature
PD = calculated maximum power dissipation
including effects of external loads (see
Power Dissipation in section III).
θJC = average thermal resistance, junction to case
θCA = average thermal resistance, case to ambient
θJA = average thermal resistance, junction to ambient
This Motorola recommended formula has been approved
by RADC or DESC for calculating a “practical” maximum
operating junction temperature for MIL–M–38510 (JAN)
devices.
Only two terms on the right side of equation (1) can be var-
ied by the user — the ambient temperature, and the device
case–to–ambient thermal resistance, θCA. (To some extent
the device power dissipation can also be controlled, but
under recommended use the VCC supply and loading dictate
(1) a fixed power dissipation.) Both system air flow and the pack-
age mounting technique affect the θCA thermal resistance
term. θJC is essentially independent of air flow and external
mounting method, but is sensitive to package material, die
(2) bonding method, and die area.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Thermal Resistance in Still Air

ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Package Description

ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
θJC (_C/Watt)
No. Body Body Body Die Die Area Flag Area

ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
Leads Style Material WxL Bonds (Sq. Mils) (Sq. Mils) Avg. Max.

ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
14 DIL Epoxy 1/4″ x 3/4″ Epoxy 4096 6,400 38 61
16 DIL Epoxy 1/4″ x 3/4″ Epoxy 4096 12,100 34 54
NOTES:
1. All plastic packages use copper lead frames.
2. Body style DIL is “Dual–In–Line.”
3. Standard Mounting Method: Dual–In–Line Socket or P/C board with no contact between bottom of package and socket or P/C board.

Figure 5. Thermal Resistance Values for Standard I/C Packages

For applications where the case is held at essentially a
fixed temperature by mounting on a large or temperature–
controlled heat sink, the estimated junction temperature is
calculated by:
These figures show the proportionate increase in the junction
temperature of each dual in–line package as the air passes
over each device. For higher rates of air flow the change in
junction temperature from package to package down the air-
stream will be lower due to greater cooling.

ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
TJ = TC + PD(θJC) (3)

ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
where TC = maximum case temperature and the other pa-
rameters are as previously defined. Power Dissipation Junction Temperature Gradient

ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
The maximum and average θJC resistance values for stan- (mW) (_C/Package)

ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
dard IC packages are given in Figure 5. 200 0.4

ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
AIR FLOW 250 0.5

ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
300 0.63
The majority of users employ some form of air–flow cool-

ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ing. As air passes over each device on a printed circuit 400 0.88
board, it absorbs heat from each package. This heat gradient Devices mounted on 0.062″ PC board with Z axis spacing of 0.5″.
from the first package to the last package is a function of the Air flow is 500 Ifpm along the Z axis.
air flow rate and individual package dissipations. Figure 6
provides gradient data at power levels of 200 mW, 250 mW, Figure 6. Thermal Gradient of Junction Temperature
300 mW, and 400 mW with an air flow rate of 500 Ifpm. (16–Pin Dual–in–Line Package)

MOTOROLA CMOS LOGIC DATA CHAPTER 7

7–4
 NOTE: This data sheet has a new look — the technical content has not changed.

OPTIMIZING THE LONG TERM RELIABILITY OF Table 1 is graphically illustrated in Figure 7 which shows
PLASTIC PACKAGES that the reliability for plastic and ceramic devices are the
same until elevated junction temperatures induces inter-
Todays plastic integrated circuit packages are as reliable metallic failures in plastic devices. Early and mid–life failure
as ceramic packages under most environmental conditions. rates of plastic devices are not effected by this intermetallic
However when the ultimate in system reliability is required, mechanism.
thermal management must be considered as a prime system
design goal.
Modern plastic package assembly technology utilizes gold
wire bonded to aluminum bonding pads throughout the elec-
tronics industry. When exposed to high temperatures for pro-
tracted periods of time an intermetallic compound can form in FAILURE RATE OF PLASTIC = CERAMIC
the bond area resulting in high impedance contacts and deg- UNTIL INTERMETALLIC FAILURES OCCUR
radation of device performance. Since the formation of inter-

NORMALIZED FAILURE RATE

metallic compounds is directly related to device junction
temperature, it is incumbent on the designer to determine
that the device junction temperatures are consistent with

TJ = 130°C

TJ = 120°C

TJ = 110°C

TJ = 100°C

TJ = 90 °C

TJ = 80 °C
system reliability goals.

Predicting Bond Failure Time:

Based on the results of almost ten (10) years of +125_C
operating life testing, a special arrhenius equation has been
developed to show the relationship between junction temper-
ature and reliability.
11554.267
Eq. (1) T = (6.376 x 109)e
273.15 + TJ
Where: T = Time in hours to 0.1% bond failure (1 failure
Where: T = per 1,000 bonds).
TJ = Device junction temperature, _C.
And:
Eq. (2) TJ = TA + PDθJA = TA + ∆TJ
Where: TJ = Device junction temperature, _C.
TA = Ambient temperature, _C.
PD = Device power dissipation in watts.
θJA = Device thermal resistance, junction to air,
_C/Watt.
∆TJ = Increase in junction temperature due to
on–chip power dissipation.
Table 1 shows the relationship between junction tempera-
ture, and continuous operating time to 0.1%. bond failure,
(1 failure per 1,000 bonds).
Table 1. Device Junction Temperature versus Time
1
1 10 100 1000
TIME, YEARS
Figure 7. Failure Rate versus Time
Junction Temperature
Procedure
After the desired system failure rate has been established
for failure mechanisms other than intermetallics, each device
in the system should be evaluated for maximum junction
temperature. Knowing the maximum junction temperature,
refer to Table 1 or Equation 1 to determine the continuous
operating time required to 0.1% bond failures due to inter-
metallic formation. At this time, system reliability departs
from the desired value as indicated in Figure 7.
Air flow is one method of thermal management which

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
to 0.1% Bond Failures should be considered for system longevity. Other commonly

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
used methods include heat sinks for higher powered de-
Junction
Temperature _C
vices, refrigerated air flow and lower density board stuffing.

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Time, Hours Time, Years
Since θCA is entirely dependent on the application, it is the
80 1,032,200 117.8

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
responsibility of the designer to determine its value. This can
90 419,300 47.9 be achieved by various techniques including simulation,

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎ
100

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
110
178,700
79,600
20.4
9.4
modeling, actual measurement, etc.
The material presented here emphasizes the need to con-

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
sider thermal management as an integral part of system de-
120 37,000 4.2
sign and also the tools to determine if the management

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
130 17,800 2.0
methods being considered are adequate to produce the
140 8,900 1.0 desired system reliability.

CHAPTER 7 MOTOROLA CMOS LOGIC DATA

7–5
 NOTE: This data sheet has a new look — the technical content has not changed.

P , MAXIMUM POWER DISSIPATION PER PACKAGE (mW)

P , MAXIMUM POWER DISSIPATION PER PACKAGE (mW)

150°C 150°C
137°C 500 500
135°C
TJ , JUNCTION TEMPERATURE ( °C)

TJ , JUNCTION TEMPERATURE ( °C)

139°C 134°C
125°C TJ SOIC 400 125°C
129°C 130°C 400
121°C
PD TJ SOIC PD
TJ PDIP 300 300
100°C 99°C PDIP & SOIC 100°C PDIP & SOIC
– 7 mW/°C 98°C – 7 mW/°C
200 89°C 200
81°C
75°C 75°C TJ PDIP
100 100

58°C
50°C 50°C
25°C 65°C 125°C 25°C 65°C 125°C
TA, AMBIENT TEMPERATURE TA, AMBIENT TEMPERATURE

Figure 8. Junction Temperature for Worst Case Figure 9. Junction Temperature for Typical
CMOS Logic Device CMOS Logic Device
This graph illustrates junction temperature for the worst case CMOS This graph illustrates junction temperature for a CMOS Logic device
Logic device (MC14007UB) — smallest die area operating at (MC14053B) — average die area operating at maximum power
maximum power dissipation limit in still air. The solid line indicates the dissipation limit in still air. The solid line indicates the junction
junction temperature, TJ, in a Dual–In–Line (PDIP) package and in a temperature, TJ, in a Dual–In–Line (PDIP) package and in a Small
Small Outline IC (SOIC) package versus ambient temperature, TA. Outline IC (SOIC) package versus ambient temperature, TA. The
The dotted line indicates maximum allowable power dissipation dotted line indicates maximum allowable power dissipation derated
derated over the ambient temperature range, 25_C to 125_C. over the ambient temperature range, 25_C to 125_C.

MOTOROLA CMOS LOGIC DATA CHAPTER 7

7–6
Equivalent Gate Count 8
 
    
The following is a list of equivalent gate counts for some of Motorola’s CMOS devices. In general for CMOS, the number of
equivalent gates is equal to the total number of transistors on chip divided by four. This list includes only those devices with
equivalent gate counts known at the time of this printing.
EQUIVALENT EQUIVALENT
DEVICE GATE COUNT DEVICE GATE COUNT
MC14000UB 3.5 MC14094B 79
MC14001B 8 MC14099B 70
MC14001UB 4 MC14161B 72.5
MC14002B 7 MC14163B 72.5
MC14002UB 4 MC14174B 43.5
MC14006B 61.5 MC14175B 39.5
MC14007UB 1.5 MC14194B 40.5
MC14008B 40 MC14490 136.5
MC14011B 8 MC14500B 192
MC14011UB 4 MC1 4503B 17
MC14012B 7 MC14504B 37.5
MC14012UB 4 MC14508B 42
MC14013B 16 MC14510B 74
MC14014B 74 MC14511B 54
MC14015B 53 MC14512B 17.25
MC14016B 8 MC14514B 59
MC14017B 62.5 MC14515B 67
MC14018B 38.25 MC14516B 61
MC14020B 84 MC14517B 119
MC14021B 74 MC14518B 43.5
MC14023B 9 MC14519B 11.5
MC14023UB 4.5 MC14520B 43.5
MC14024B 59 MC14522B 86
MC14025B 9 MC14526B 86
MC14025UB 4.5 MC14527B 46
MC14028B 26 MC14528B 24
MC14029B 65.5 MC14530B 22
MC14034B 145 MC14531B 44
MC14035B 38.5 MC14532B 38.5
MC14040B 73 MC14534B 206
MC14042B 17.5 MC14536B 103
MC14046B 35 MC14538B 38
MC14049UB 3 MC14539B 20
MC14049B 9 MC14541B 93
MC14050B 6 MC14543B 52
MC14051B 48.5 MC14549B 122
MC14052B 38.5 MC14551B 35
MC14053B 38 MC14553B 147.5
MC14060B 73.5 MC14555B 21
MC14066B 13 MC14556B 25
MC14067B 65 MC14557B 232.5
MC14068B 8 MC14559B 122
MC14069UB 3 MC14562B 206
MC14071B 10 MC14568B 137.25
MC14072B 8 MC14569B 156
MC14073B 10.5 MC14572UB 4
MC14075B 10.5 MC14573 7
MC14076B 32.5 MC14574 9
MC14078B 7.5 MC14575 11
MC14081B 10 MC14583B 14
MC14082B 8 MC14584B 18
MC14093B 18

MOTOROLA CMOS LOGIC DATA

8–2
 Packaging Information 9
Including Surface Mounts
 PACKAGE DIMENSIONS
The standard package availability for each device is indicated on the front page of the individual data sheets. Dimensions for
the packages are given in this chapter. Surface mount packages may be special ordered by specifying the following suffixes: “D”
(narrow SOIC), “DW” (wide SOIC), or “FN” (PLCC). For example, to order a quad NOR gate, use MC14001BD.

–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
14 9 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
–B– 3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
1 7 4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
–T– C 0.155 0.200 3.94 5.08
SEATING
K D 0.015 0.020 0.39 0.50
PLANE F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
F G N M J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
D 14 PL J 14 PL L 0.300 BSC 7.62 BSC
M 0_ 15_ 0_ 15_
0.25 (0.010) M T A S
0.25 (0.010) M T B S N 0.020 0.040 0.51 1.01

CASE 632–08
ISSUE Y

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
N F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
–T– J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING
PLANE L 0.290 0.310 7.37 7.87
K J M ––– 10_ ––– 10_
H G D 14 PL M N 0.015 0.039 0.38 1.01

0.13 (0.005) M

CASE 646–06
ISSUE M

CHAPTER 9 MOTOROLA CMOS LOGIC DATA

9–2
PACKAGE OUTLINE DIMENSIONS (continued)

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
–A– Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
CASE 751A–03
ISSUE F

B
A A
M
16 9

B L
1 8

16X J
0.25 (0.010) M T B
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
F ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
C 4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

K INCHES MILLIMETERS
SEATING DIM MIN MAX MIN MAX
T PLANE A 0.750 0.785 19.05 19.93
N B 0.240 0.295 6.10 7.49
G C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
16X D E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
0.25 (0.010) M T A H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0_ 15 _ 0_ 15 _
N 0.020 0.040 0.51 1.01
CASE 620A–01
ISSUE O
(REPLACES 620–10)

MOTOROLA CMOS LOGIC DATA CHAPTER 9

9–3
PACKAGE OUTLINE DIMENSIONS (continued)

NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

CASE 648–08
ISSUE R

–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019

CASE 751B–05
ISSUE J

CHAPTER 9 MOTOROLA CMOS LOGIC DATA

9–4
PACKAGE OUTLINE DIMENSIONS (continued)

D A
q
16 9
M
B
H

h X 45 _
M

E
NOTES:
8X

0.25

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
1 8 PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
16X B B PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
0.25 M T A S B S CONDITION.

MILLIMETERS
DIM MIN MAX
A 2.35 2.65
A

A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32

L
SEATING
D 10.15 10.45
14X e PLANE
E 7.40 7.60
A1

T C e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
CASE 751G–03 q 0_ 7_
ISSUE B

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
18 10 MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
B 2. DIMENSION L TO CENTER OF LEADS WHEN
1 9 FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

A MILLIMETERS INCHES
DIM MIN MAX MIN MAX
L A 22.22 23.24 0.875 0.915
C B 6.10 6.60 0.240 0.260
C 3.56 4.57 0.140 0.180
D 0.36 0.56 0.014 0.022
F 1.27 1.78 0.050 0.070
N K G 2.54 BSC 0.100 BSC
J H 1.02 1.52 0.040 0.060
F D SEATING M J 0.20 0.30 0.008 0.012
PLANE K 2.92 3.43 0.115 0.135
H G L 7.62 BSC 0.300 BSC
M 0_ 15_ 0_ 15 _
N 0.51 1.02 0.020 0.040

CASE 7O7–02
ISSUE C

MOTOROLA CMOS LOGIC DATA CHAPTER 9

9–5
PACKAGE OUTLINE DIMENSIONS (continued)

B A A

18 10

1 9
OPTIONAL LEAD
CONFIGURATION (1, 9, 10, 18) NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
L 2. CONTROLLING DIMENSION: INCH.
18X F 3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F FOR FULL LEADS. HALF
LEADS OPTIONAL AT LEAD POSITIONS 1, 9,
C 10, AND 18.

INCHES MILLIMETERS
K DIM MIN MAX MIN MAX
A 0.880 0.910 22.35 23.11
T SEATING
PLANE B 0.240 0.295 6.10 7.49
M C ––– 0.200 ––– 5.08
N
D 0.015 0.021 0.38 0.53
G J 18 PL F 0.055 0.070 1.40 1.78
18X D G 0.100 BSC 2.54 BSC
0.25 (0.010) M T A 0.25 (0.010) M T B J 0.008 0.012 0.20 0.30
K 0.125 0.170 3.18 4.32
L 0.300 BSC 7.62 BSC
M 0_ 15 _ 0_ 15_
CASE 726B–01 N 0.020 0.040 0.51 1.02

ISSUE O
(REPLACES 726–04)

NOTES:
24 13 1. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
B POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
1 12
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 31.24 32.77 1.230 1.290
A B 12.70 15.49 0.500 0.610
C 4.06 5.59 0.160 0.220
SEATING D 0.41 0.51 0.016 0.020
F PLANE F 1.27 1.52 0.050 0.060
C G 2.54 BSC 0.100 BSC
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 15.24 BSC 0.600 BSC
L M 0_ 15 _ 0_ 15_
N 0.51 1.27 0.020 0.050
D N J
G M
K

CASE 623–05
ISSUE M

CHAPTER 9 MOTOROLA CMOS LOGIC DATA

9–6
PACKAGE OUTLINE DIMENSIONS (continued)

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
24 13 MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 12 FLASH.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 31.37 32.13 1.235 1.265
A C L B 13.72 14.22 0.540 0.560
C 3.94 5.08 0.155 0.200
N D 0.36 0.56 0.014 0.022
F 1.02 1.52 0.040 0.060
K G 2.54 BSC 0.100 BSC
H 1.65 2.03 0.065 0.080
H F M J J 0.20 0.38 0.008 0.015
SEATING K 2.92 3.43 0.115 0.135
G D PLANE
L 15.24 BSC 0.600 BSC
M 0_ 15_ 0_ 15_
N 0.51 1.02 0.020 0.040

CASE 709–02
ISSUE C

–A–

24 13 NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– 12X P MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
0.010 (0.25) M B M
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 12 PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
24X D J
MILLIMETERS INCHES
0.010 (0.25) M T A S B S
DIM MIN MAX MIN MAX
A 15.25 15.54 0.601 0.612
F B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
R X 45 _ D 0.35 0.49 0.014 0.019
F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
C J 0.23 0.32 0.009 0.013
K 0.13 0.29 0.005 0.011
–T– M 0_ 8_ 0_ 8_
SEATING M P 10.05 10.55 0.395 0.415
PLANE 22X G K R 0.25 0.75 0.010 0.029

CASE 751E–04
ISSUE E

MOTOROLA CMOS LOGIC DATA CHAPTER 9

9–7
1 Master Index

2 Product Selection Guide

3 The “Better” Program

4 B and UB Series Family Data

5 CMOS Handling and Design Guidelines

6 Data Sheets

7 CMOS Reliability

8 Equivalent Gate Count

9 Packaging Information
Including Surface Mounts