APPLIED PHYSICS LETTERS 98, 193504 共2011兲

Reliability of bottom-gate graphene field-effect transistors prepared

by using inductively coupled plasma-chemical vapor deposition
Jung-Kyu Lee,1 Hyun-Jong Chung,2 Jinseong Heo,2 Sunae Seo,2 Il Hwan Cho,3
Hyuck-In Kwon,4 and Jong-Ho Lee1,a兲
1
School of EECS and ISRC, Seoul National University, Seoul 151-742, Republic of Korea
2
Semiconductor Devices Laboratory, Samsung Advanced Institute of Technology (SAIT), Yongin,
Kyungi 446-712, Republic of Korea
3
Department of Electronics Engineering, Myongji University, Yongin, Kyungki 449-728, Republic of Korea
4
School of Electrical and Electronics Engineering, Chun-Ang University, Seoul 156-756, Republic of Korea
共Received 28 December 2010; accepted 18 April 2011; published online 12 May 2011兲
Stability degradation in bottom-gate graphene field-effect transistors prepared by using inductively
coupled plasma-chemical vapor deposition method are investigated under bias, temperature and
illumination stress. The stretched-exponential time dependence model, which can be derived based
on the trapping/detrapping of charges to/from existing traps and continuous redistribution of charges
in bulk dielectrics, is well applied in fitting the time dependence of the transfer curve shifts in all
stress conditions. The stress wavelength is considered as important factors as well as the bias and
temperature stress in the transfer characteristic instabilities of graphene FEFs. © 2011 American
Institute of Physics. 关doi:10.1063/1.3589120兴

Graphene, ultrathin graphite film, has been considered as
most attractive material for future nanoelectronic device ap-
plications due to its excellent merits such as very high carrier
mobility,1 ballistic transport,2 and high thermal conductivity.3
In the past few years, there have been several approaches to
implement graphene channels 共exfoliation method using
scotch tape,4 growth of graphene on SiC substrate at high
temperature of 1450 ° C 共Ref. 5兲 and formation of graphene
in ultrahigh vacuum environments6兲 and some reliability
reports.7,8 However, reliability issues of graphene field-effect
transistors 共FETs兲 prepared by using chemical vapor deposi-
tion 共CVD兲 have not been reported. Especially, the electrical
stability of the graphene FETs is critical to apply for sensor
application such as gas,9 pH,10 and optoelectronic sensor11
because it can lead to limit of sensing ability. So, it is pre-
requisite to investigate the electrical, optical and thermal sta-
bility of graphene FETs before sensor applications. In this
letter, we study extensively reliability of the bottom-gate
graphene FETs fabricated by CVD under prolonged gate
bias, temperature, and laser light illumination in the air.
Graphene grown by inductively coupled plasma 共ICP兲-
CVD on Cu film at 650 ° C is transferred into this prepat-
terned substrate, which has the source and drain electrodes of
Au formed on SiO2 共100 nm兲/Si, and then channel region is
defined by using oxygen plasma etching. High doped n-type
silicon is used as the back-gate. Mobility ranging from 3000
to 6000 cm2 / V s at 300 K was extracted through 4-point
gate dependent resistivity measurement in high vacuum.12
All measurements were carried out using an Agilent 4156 C
precision semiconductor parameter analyzer. The gate bias
was interrupted at fixed times to record the transfer charac-
teristics of the graphene FETs at a drain bias of ⫺10 mV by
sweeping the gate bias from ⫺10 to 10 V, while the source
electrode was grounded.
Figure 1共a兲 shows that the transfer curves shift by the
positive back-gate bias 共VBG兲 of 10 V in the positive direc-
tion, but the shape of the transfer curve is nearly constant.
The slope of the curves shows a small variation during the
applied bias stresses, which indicates that the shift can be
mainly described by the threshold voltage shift 共⌬VT兲 with-
out mobility degradation. Here, ⌬VT is a VBG difference be-
tween the VBG after the stress and initial VBG at a fixed drain
current. Two well-known degradation mechanisms are
charge trapping in the gate insulator and the defect creation
of new states in the channel or gate insulator.13 In general,
the defect state creation is accompanied by change in sub-
threshold slope and mobility while the charge trapping is not.
Therefore, the instability of our graphene FETs under gate
bias stress might be originated from the trapping of carriers

-0.21 V = - 10 mV, @ RT VST = -10 V constant voltage stress

D
-0.24 stress voltage VST = 10 V 4 VST = 10 V @ RT
Drain current (mA)

stretched-exponential fitting
-0.27 stress time : 3
0, 10, 100, 1000, 7000 s
DVT (V)

-0.30 FIG. 1. 共Color online兲 共a兲 ID − VBG curves shift under

2 the constant voltage stress of 10 V. 共b兲 The time depen-
-0.33
dence of ⌬VT under the constant gate biases of 10 and
-0.36 1
⫺10 V for 7 ⫻ 103 s at room temperature.
-0.39 0 (b)
(a)
-0.42 0 1 2 3
-9 -6 -3 0 3 6 9 10 10 10 10
VBG (V) Stress Time (s)

a兲
Author to whom correspondence should be addressed. Electronic mail: jhl@snu.ac.kr.

0003-6951/2011/98共19兲/193504/3/$30.00 98, 193504-1 © 2011 American Institute of Physics

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 193504-2 Lee et al.
3 gate bias stress is applied to the gate electrode, the transfer
t2 : 2100
2 Figure 2 shows that the time evolution of the ⌬VT under
t3 : 900
DVT (V)
t1 : 1150
1 the both stress and recovery times, the time dependences of
stress ( VBG = -10 V )
0
recovery ( VBG = 0 V )
stretched-exponential fitting
0 1000 2000 3000
Time (s)
FIG. 2. 共Color online兲 The time dependence of ⌬VT under dynamic stresses
with a duty cycle of 0.5 and a period of 2000 s at room temperature.
in the traps located in the interface or bulk dielectric layers.
Figure 1共b兲 shows the time dependence of ⌬VT under the
application of constant gate biases of 10 and ⫺10 V for 7
⫻ 103 s at room temperature. According to the previous
studies, Logarithmic14 and stretched-exponential time depen-
dence models15 were derived to quantitatively model the
⌬VT based on the charge trapping mechanism. The differ-
ence between them is that the logarithmic time dependence
model speculated no further redistribution of the charges
trapped at the interface deeper into the bulk dielectric,
whereas the stretched-exponential time dependence model
hypothesized the emission of trapped charges toward deep
states in the bulk dielectric for longer stress time 共t ⬎ ␶兲 and
larger stress field. Such a trap redistribution in the bulk di-
electric is plausible that the amorphous structure of the gate
dielectric will lend itself to an appreciable number of band-
tail states which can act as transport states for the emitted
lower energy trapped state charge.15 Our results show that
the time dependence of the ⌬VT is in agreement with the
stretched-exponential time dependence equation. The equa-
tion for the ⌬VT is defined as
⌬VT = ⌬VT-max兵1 − exp关− 共t/␶兲␤兴其,
where ⌬VT-max is the maximum threshold voltage variation,
␶ = ␶0 exp共E␶ / kT兲 represents the characteristic trapping time
of carriers where the thermal activation energy is given by
Ea = E␶␤ 共in which ␤ is the stretched-exponential exponent
and E␶ is the average effective energy barrier that carriers
need to overcome before they can enter the insulator兲, and ␶0
is the thermal prefactor for emission over the barrier. During
negative gate bias stress, the holes injected from graphene
channel partially screen the applied electric field so that the
effective applied gate voltage is smaller when injected holes
exist at the interface or bulk dielectric layers. When positive
10 104
60 oC VST = -10 V
8 40 oC
20 oC
stretched-exponential fitting 103
DVT (V)
6
t (s)
4
102
2
1
0 10
102 103
Stress Time (s)
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Appl. Phys. Lett. 98, 193504 共2011兲
curve moves to the initial one, which is due to the emission
t4 : 2800 of holes to the graphene channel.
dynamic stresses with a duty cycle of 0.5, a period of 2
⫻ 103 and gate bias of ⫺10 V at room temperature. During
the ⌬VT are well described by stretched-exponential time
dependence equation. The equation in recovery time are de-
fined as15
⌬VT = ⌬VT0 exp关− 共t/␶兲␤兴, 共2兲
4000
where ⌬VT0 is the ⌬VT at infinite time. This repetitive and
reversible VT behavior indicates that the relaxation behavior
is associated with the detrapping of the previously trapped
charges. The ⌬VT increases during the stress phase and de-
creases during the recovery phase but not fully recovered for
a given recovery time of 103 s. Considering that time con-
stants extracted from the stretched-exponential fitting during
the stress phase 共␶1 = 1150 s and ␶3 = 900 s兲 are smaller than
those during the recovery 共␶2 = 2100 s and ␶4 = 2800 s兲, the
results suggest that a part of trapped holes are located in deep
traps of dielectric, and remain relatively stable.
To further investigate the VT shift phenomenon in the
graphene FETs, stress measurements were performed with
various stress temperatures. Figure 3共a兲 shows the time de-
pendence of ⌬VT under different stress temperatures, which
indicates that the stretched-exponential time dependence
equation is well applied in all stress temperature conditions.
The reciprocal temperature dependency of ␶, obtained from
the fitting of experimental data with a stretched-exponential
equation, shows that it follows an Arrhenius relationship as
shown in Fig. 3共b兲. E␶ and Ea at room temperature 共297 K兲
are determined to be 0.28 eV and 0.13 eV, respectively. The
inset of Fig. 4共b兲 shows the values of ␤ as a function of
temperature. The temperature dependence of ␤ agrees with
the conventional model of bias stress instability, that is, lin-
early increases with temperature by the equation of ␤
共1兲 = TST / T0 − ␤0, where TST is the stress temperature and T0 is
related to the energy parameters of the charge trapping pro-
cess, although the physical meaning of ␤0 is not clarified.15
The values of each extracted parameter can be varied with
fabrication conditions but the aforementioned observation
about the bias stress and stress temperature dependency of
each fitting parameter leads us to the conclusion that the
stretched-exponential time dependence model can be effec-
tively applied to the bias-induced stability analysis of
graphene FET with a SiO2 gate dielectric.
Additionally, we investigated the degradation effect by a
illumination using the red 共660 nm兲, green 共532 nm兲, and
blue 共405 nm兲 laser sources. The inset of Fig. 4 shows the
Et = 0.28 eV
0.8 FIG. 3. 共Color online兲 共a兲 The time dependence of ⌬VT
Exponent (b)
0.7 under different stress temperatures. 共b兲 Characteristic
0.6 trapping time ␶ as a function of reciprocal temperature.
0.5 The inset shows the values of ␤ as a function of
0.4 temperature.
290 300 310 320 330 340
Stress Temperature (K)
34 35 36 37 38 39 40 41
1/kT (eV-1)
 193504-3 Lee et al. Appl. Phys. Lett. 98, 193504 共2011兲

25 In conclusion, the stability degradation characteristics of

10 Optical Stress Optical and p-type graphene FEF prepared by using ICP-CVD were stud-
TST : 300 s, PST : 10 mW ied under bias, temperature and/or optical stress. From the
DVT (V)
20 Bias Stress
1 VST : VS = VD = VBG = 0 V transfer curves measured before and after stresses, the charge
trapping model is considered as the main cause of stability
15
degradation in our graphene FET. In all stress conditions, the
DVT (V)

0.1
400 500 600 700
10 wavelength (nm)
PST = 12.6 mW
5 lST = 405 nm
VST = -10 V
0 stretched-exponential fitting
measurement
101 102 103
Stress Time (s)
FIG. 4. 共Color online兲 The time dependence of the ⌬VT under the blue light
and a constant voltage stress of ⫺10 V. The inset of Fig. 4 shows the ⌬VT
of our graphene FET under red, green and blue laser illumination for
3 ⫻ 102 s at room temperature.
⌬VT of our graphene FET under red, green and blue laser
illumination for 3 ⫻ 102 s at room temperature. The largest
⌬VT was observed under the blue light illumination. This is
because the holes generated in the graphene channel by the
optical illumination can be trapped more easily into deep
traps in dielectric under the blue light having the largest en-
ergy. Note that the heating effect from the laser illumination
can be ignorable because the temperature of a device being
illuminated is a few degrees 共⬍5 ° C兲 at an optical power of
10 mW. Figure 4 shows the time dependence of the ⌬VT
under the blue 共405 nm兲 light and a constant voltage stress of
⫺10 V, which indicates that the stability degradation under
the illumination is still primarily due to the charge trapping
in the gate insulator. The time dependence of ⌬VT can be
well fitted with the stretched-exponential equation with a
characteristic trapping time ␶ of 270 s and a stretched-
exponential exponent ␤ of 0.64. This trapping time is the
shorter compared to that under electrical or optical stress
only, because charge trapping process is activated more ef-
fectively under both electrical and optical stresses.
stretched-exponential equation is well applied in fitting the
time dependence of ⌬VT. The stress wavelength is also con-
sidered as an important factor as well as the bias stress in the
transfer characteristic instabilities of graphene FETs.
This work was supported by Basic Science Research
Program through the National Research Foundation of Korea
共NRF兲 grant funded by the Korea government 共MEST兲
共Grant No. 2010-0001870兲.
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