Goodone Dds

DIRECT DIGITAL FREQUENCY SYNTHESIZER
by
SHASHIKANT SHRIMALI, B.E.
A THESIS
IN
ELECTRICAL ENGINEERING
Submitted to the Graduate Faculty

of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of
MASTER OF SCIENCE
IN
ELECTRICAL ENGINEERING
Approved
Jon Bredeson
Chairperson of the Committee
Micheal Parten
Accepted
John Borrelli
Dean of the Graduate School
May 2007
Copyright 2007, Shashikant Shrimali
Texas Tech University, Shashikant Shrimali, May 2007
ACKNOWLEDGEMENTS
I wish to express my sincere gratitude to Prof. Dr. Jon Gustav Bredeson for
providing the opportunity to carry out this study, and for guidance and support. I am
deeply indebted to Prof. Dr. Micheal Eugene Parten for his valuable suggestions and
active cooperation and having been a part of every single stage of my thesis, from
inception to completion. I am very grateful to fellow graduate students for their constant
support, timely suggestions and inspiration. I gratefully acknowledge the cooperation I
received from other faculty members of this department. I will be failing in my duty if I
do not mention the administrative staff of this department for their timely help.
My friends outside the field of engineering have kept me interested in matters
other than just electrical. I have spent very relaxing moments with my friends taking part
in different activities and hopefully will continue to do so. I would like to thank all whose
direct and indirect support helped me completing my thesis in time. I would also like to
recognize the encouragement and unconditional love of my friends in India.
Finally, there are those whose spiritual support is even more important. I thank
my parents, who taught me the value of hard work by their own example. I would also
thank my sister, who has constantly encouraged me to study as much as possible.
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TABLE OF CONTENTS
ACKNOWLEDGEMENTS……………………………………………………………….ii
ABSTRACT……………………………………………………………………………….v
LIST OF FIGURES………………………………………………………………………vi
CHAPTER
I. INTRODUCTION TO DDFS…………………………………………………..1
1.1 DDFS- A Brief History………………………………………………..1
1.2 DDFS- An Overview………………………………………….………2
1.3 Aim of Thesis………………………………………………………….3
1.4 Thesis Organization…………………………………………………...4
II. OPERATION OF DDFS……………………………………………………….5
2.1 Architecture of Sine Output DDFS……………………………………5
2.2 Frequency Tuning Equation…………………………………………...7
2.3 Building Blocks of DDFS……………………………………………..9
2.3.1 Phase Accumulator………………………………………...10
2.3.2 Phase-to-Amplitude Converter (ROM/LUT)………………12
2.3.3 Digital-to-Analog Converter and Filter……………………13
III. OUTPUT SPECTRUM OF DDFS…………………………………………..14
3.1 Sampled Output of DDFS……………………………………………14
3.2 Spectral Purity Considerations……………………………………….16
3.3 Spurious Free Dynamic Range………………………………………16
3.4 DDFS with Phase Truncation and Spurious Performance…………...17
3.5 DDFS with Dither and its effect on SFDR…………………………..19
IV. SIMULATION AND RESULTS OF DDFS………………………………...21
4.1 High-level simulation of DDFS using MATLAB-Simulink………...21
4.2 RTL level simulation of DDFS using ModelSim……………………24
4.2.1 Simple DDFS simulation using ModelSim………………..24
4.2.2 DDFS with Phase Truncation and Dither……………….…30
iii
4.3 Cadence simulation of DDFS with Clock Jitter………...……………36

4.4 Quantization Error………………………………………..………….44
V. CONCLUSIONS AND FUTURE WORK ………………………….……….47
REFERENCES …………………………………………………………………….……49
APPENDIX A……………………………………………………………………..…….52
APPENDIX B……………………………………………………………………..…….64
iv
ABSTRACT
A frequency synthesizer is an electronic system for generating any of a range of

frequencies from a single fixed time base or oscillator. They are found in many modern
devices, including radio receivers, mobile telephones, radiotelephones, walkie-talkies,
CB radios, satellite receivers, GPS systems, etc. Direct Digital Synthesis (DDS) is a kind
of frequency synthesizer that use electronic methods for digitally creating arbitrary
waveforms and frequencies from a single, fixed source frequency. Direct Digital
Frequency Synthesis (DDFS) is a mixed signal part i.e. it has both digital and analog
parts. DDFS’s digital part is also known as Numerically Controlled Oscillator (NCO),
which consists of a Phase Register, a Phase Accumulator (PA) and a ROM. The analog
part has Digital-to-Analog Converter and a filter. NCO is a digital computing block
which renders digital word sequences in time at a given reference clock frequency f clk ,
which thereafter are converted into analog signals to serve as a synthesizer. The phase
accumulator (PA) clocked with f clk , generates the phase value sequence. Application of
the DDFS ranges from instrumentation to modern communication systems, which

employs spread-spectrum and phase shift-keying modulation techniques.
The focus of this thesis is on design, analysis and simulation of DDFS, using
tools like Xilinx and Cadence. Traditional designs of high bandwidth frequency
synthesizers employ the use of a phase locked- loop (PLL). DDFS provides many
significant advantages over the PLL approaches, such as fast settling time, sub-Hertz
frequency resolution, continuous-phase switching response and low phase noise.
v
LIST OF FIGURES
2.1 DDFS function blocks and signal flow diagrams [2]……………………...5

2.2 Sine magnitude and phase representation [19]……………………………7
2.3 Digital phase wheel [4]…………………………………………………..10
3.1 Spectral analysis of sampled output [4]………………………………….14
3.2 Phase truncation error and the phase wheel [6]………………………….18
4.1 MATLAB-Simulink model of DDS……………………………………..22
4.2 PA output for M = 51……………………………………………………23
4.3 LUT output for

f out = 10 MHz……………………………………………23
4.4 PA output for M = 102…………………………………………………..23
4.5 LUT output for

f out = 20 MHz……………………………………………24
4.6 RTL schematic of DDFS………………………………………………...24

4.7 Verilog code for 8-bit Register…………………………………………..25
4.8 Simulation result of Register…………………………………………….26
4.9 Simulation result of the PA………………………………………………26
4.10 Verilog code for the LUT………………………………………………..27
4.11 Simulation result of the LUT…………………………………………….27
4.12 Top-level with the interconnection of modules………………………….28
4.13 ModelSim simulation

f out = 3.1 MHz…………………………………….29
4.14 PSD plot

f out = 3.1 MHz………………………………………………….29
4.15 ModelSim simulation

f out = 5 MHz………………………………………30
4.16 PSD plot

f out = 5 MHz……………………………………………………30
4.17 DDFS with phase truncation……………………………………………..31

4.18 Verilog Code for Phase Truncation Module……………………………..32
4.19 Simulation result of the PT………………………………………………32
4.20 ModelSim simulation with PT…………………………………………...33
vi
4.21 PSD plot with PT………………………………………………………...33

4.22 DDFS with Phase Truncation and Dither Generator…………………….34
4.23 Verilog code for the random number generator…………………………34
4.24 Simulation result of the PA, PT and Dither……………………………...35
4.25 PSD Plot with PT and Dither…………………………………………….35
4.26 Random number and Clock Jitter Generator…………………………….36
4.27 VerilogA modules of Random Number and Clock Generator…………...37
4.28 Output of Random number generator……………………………………37
4.29 Ideal Clock

f clk =100 MHz……………………………………………….38
4.30 Ideal Clock, Jittered Clock and Random Number……………………….39

4.31 Jitter………………………………………………………………………39
4.32 DDFS with ideal clock…………………………………………………...40
4.33 DDFS with jittered clock………………………………………………...40
4.34 Phase Accumulator with Ideal Clock…………………………………….40
4.35 Phase Accumulator with jittered Clock………………………………….41
4.36 Output spectrum of DDFS with ideal clock

f out = 7.5MHz……………..41
4.37 Output spectrum with clock jitter

f out = 7.5MHz………………………...42
4.38 Comparison of output spectrums

f out = 7.5 MHz………………………...42
4.39 Comparison of output spectrums

f out =12.11 MHz……………………...43
4.40
f out =12.11M Hz with jitter = 2ns………………………………………..43
4.41
f out =12.11M Hz with jitter = 1ns………………………………………..44
4.42 DDFS Output Spectrum with LUT having 8-bit samples………………..44

4.43 DDFS Output Spectrum with LUT having 12-bit samples………………45
4.44 Comparison of output spectrums………………………………………...45
vii
CHAPTER I
INTRODUCTION TO DDFS
1.1 DDFS – A Brief History

The idea of DDFS was first proposed by J.Tierney in 1971[1]. Direct Digital
Synthesis (DDS) is an electronic method for digitally creating arbitrary waveforms and
frequencies from a single, fixed source frequency. With the development of VLSI
technology and the requirement of modern communication systems, direct digital
frequency synthesizers have been widely used in wireless transceivers since the 1980’s.
Direct Digital Frequency Synthesis (DDFS or simply DDS), also known as Numerically
Controlled Oscillator (NCO), is a technique which uses digital-data and mixed/analog-
signal processing blocks as a means to generate signal waveforms that are repetitive in
nature. A DDFS can achieve fast frequency switching in small frequency steps, over a
wide band. In addition, it provides linear phase and frequency shifting with good spectral
purity. A DDFS is used especially for a precise, high frequency and a phase tunable
output. A standard DDFS architecture consists of an accumulator, a ROM /lookup table, a
DAC and some reconstruction filters.
DDFS solutions are implemented in LSI (large-scale integration) and they play an
ever-increasing role in digital waveform and clock generation, and modulation. A major
advantage of a direct digital synthesizer (DDS) is that its output frequency, phase and
amplitude can be precisely and rapidly manipulated under digital processor control [2].
Other inherent DDFS attributes include the ability to tune with extremely fine frequency
and phase resolution, and to rapidly "hop" between frequencies.
It is easy to include different modulation capabilities in the DDFS by using digital
signal processing methods, because the signal is in digital form. By programming the
DDFS, adaptive channel bandwidths, modulation formats, frequency hopping and data
rates are easily achieved. The implementation of digital functional blocks makes it
possible to achieve a high degree of system integration. The DDFS addresses a variety of
applications, including cable modems, measurement equipments, arbitrary waveform
1
generators, cellular base stations and wireless local loop base stations.
1.2 DDFS – An Overview

Direct digital frequency synthesis (DDFS) is a method of producing an analog
waveform—usually a sine wave— by generating a time-varying signal in digital form
and then performing a digital-to-analog conversion. The operations within a DDFS
device are primarily digital, therefore, it can offer fast switching between output
frequencies, fine frequency resolution, and operation over a broad spectrum of
frequencies.
The digital frequency synthesis approach employs a stable source frequency i.e.
reference clock to define times at which digital sinusoidal sample values are produced.
These samples are converted from digital to analog format and smoothed by
reconstruction filter to produce analog frequency signals. A DDFS typically consists of a
phase accumulator (PA) and a sine lookup table (LUT). The input to the phase
accumulator is a frequency control word, which determines the periodicity of the phase
accumulator. The PA is updated to the frequency control word or tuning word, at each
clock, the output of the PA is fed to the LUT. The output of the LUT is then converted to
an analog signal using a digital to analog converter.
The size of the LUT depends on the length of the n-bit PA. If n is large then the
LUT becomes too large, which is not desirable. This slows down the speed of the DDS
and results in higher power consumption. To reduce the size of the LUT, a technique of
phase truncation (PT) is employed. Since in this technique part of the phase generated by
the PA is truncated that gives rise to spurs in output spectrum. To minimize these spurs,
dither is added to the system that reduces the spurs in output spectrum. Since, the DDFS
is a digital system clock jitter also introduces noise in the output spectrum. Jitter is an
abrupt and unwanted variation of one or more signal characteristics, such as the interval
between successive pulses, the amplitude of successive cycles, or the frequency or phase
of successive cycles.
2
With advances in design and process technology, today’s DDFS devices are very
compact and draw little power. The ability to accurately produce and control waveforms
of various frequencies and profiles has become a key requirement common to a number
of industries. Whether providing agile sources of low-phase-noise variable-frequencies
with good spurious performance for communications, or simply generating a frequency
stimulus in industrial or biomedical test equipment applications, convenience,
compactness, and low cost are important design considerations. Many possibilities for
frequency generation are open to a designer, ranging from phase-locked-loop (PLL)-
based techniques for very high-frequency synthesis, to dynamic programming of digital-
to-analog converter (DAC) outputs to generate arbitrary waveforms at lower frequencies.
The DDFS technique is rapidly gaining acceptance for solving frequency- (or waveform)
generation requirements in both communications and industrial applications because
single-chip IC devices can generate programmable analog output waveforms simply and
with high resolution and accuracy.
1.3 Aim of Thesis

A DDFS generates analog waves digitally; hence, the output spectrum has certain
amounts of distortion. Therefore, the output wave is not spectrally pure. The output
spectrum of a DDFS consists of fundamental frequency along with its image frequencies
and noise. Various factors affect the purity of the output spectrum of the DDFS some of
them are the DAC nonlinearity, spurs due to phase truncation, amplitude quantization and
clock jitter. The size of the LUT depends on the length of the n-bit PA. If n is large then
the LUT becomes too large, which is not desirable. This slows down the speed of the
DDS and results in higher power consumption.
This thesis examines the performance of direct digital frequency synthesizer and
shows the effect of non-ideal characteristics of building blocks of the DDFS on the output
spectrum. Different models of the DDFS are created, implemented and examined. This
provides the designer better understanding of the DDFS. These models would help to
examine different aspects of the DDFS and to determine what would work best for an
3
application.
In the digital part, phase truncation introduces errors and when some dither is
added, spurious free dynamic range (SFDR), is improved. The analog part of the DDFS
includes a D/A converter and a low pass filter. Random jitter is added to the input
reference clock for system-level verification and simulation.
Spurious performances of DDFS are partly caused by quantization operations in
its digital part. These errors are deterministic and periodic in the time domain; therefore,
they appear as undesired components: spurs in the frequency domain. Hence, it is quite
natural to analyze the effects by DFT (Discrete Fourier Transform). The amplitude
quantization (AQ) is present permanently and causes harmonically related spurs, while
phase truncation (PT) produces spurs around the output frequency by phase modulation.
1.4 Thesis Organization

The structure of this thesis is to provide some background on DDFS design,
followed by the design and simulation results. The focus of this thesis has been outlined
in CHAPTER I itself. Operation of a DDFS and the role of each building block is
explained in detail in CHAPTER II. The output spectrum of a DDFS is explained in
CHAPTER III, with the help of an example. Implementation of a DDFS, with simulation
results is explained in CHAPTER IV. At last, CHAPTER V gives conclusions and
recommendations for future work on DDFS.
4
CHAPTER II
OPERATION OF DDFS
2.1 Architecture of Sine Output DDFS

The basic block diagram of a direct digital frequency synthesizer is shown in
Figure 2.1 [2].
Figure 2.1: DDFS function blocks and signal flow diagrams [2]
As shown in Figure 2.1, the main components of a DDFS are a phase

accumulator, phase-to-amplitude converter (a sine look-up table), a Digital-to-Analog
Converter and filter. A DDFS produces a sine wave at a given frequency. The frequency
depends on three variables; the reference-clock frequency f clk and the binary number
programmed into the phase register (frequency control word, M ), length of n-bit
accumulator. The binary number in the phase register provides the main input to the
phase accumulator.
5
If a sine look-up table is used, the phase accumulator computes a phase (angle)
address for the look-up table, which outputs the digital value of amplitude—
corresponding to the sine of that phase angle—to the DAC. The DAC, in turn, converts
that number to a corresponding value of analog voltage or current. To generate a fixed-
frequency sine wave, a constant value (the phase increment—that is determined by the
binary number M ) is added to the phase accumulator with each clock cycle. If the phase
increment is large, the phase accumulator will step quickly through the sine look-up table
and thus generate a high frequency sine wave. If the phase increment is small, the phase
accumulator will take many more steps, accordingly generating a slower waveform [4].
The heart of the system is the phase accumulator whose contents are updated once
each clock cycle. Each time the PA is updated, the digital number or M , stored in the
phase register is added to the number in the phase accumulator register. If the number in
the phase register is 00...01 and the initial content of the phase accumulator are 00...00.
The phase accumulator is updated by 00...01 on each clock cycle. If the accumulator is
32-bits wide, 232 clock cycles (over 4 billion) are required before the phase accumulator
returns to 00...00, and the cycle repeats. The output of the phase accumulator serves as
the address to a sine (or cosine) lookup table/ROM/phase-to-amplitude converter. Each
address in the LUT corresponds to a phase point on the sine wave from 0° to 360°. The
LUT contains the corresponding digital amplitude information for one complete cycle of
a sine wave. The LUT, therefore, maps the phase information from the phase accumulator
into a digital amplitude word, which in turn drives the DAC. For n=32, and M =1. The
phase accumulator steps through each of 232 possible outputs before it overflows. The
corresponding output sine-wave frequency is equal to the clock frequency divided by 232.
If M=2, then the phase accumulator register "rolls over" twice as fast, and the output
frequency is doubled. For an n-bit phase accumulator (n generally ranges from 24 to 32 in
most DDFS systems), there are 2n possible phase points. The digital word in the phase
register, M represents the amount the phase accumulator is incremented each clock cycle.
6
If f clk is the clock frequency, then the frequency of the output sine wave is equal
to:
M * f clk
f out = (1)
2n
Above equation is known as the DDFS "tuning equation." The frequency resolution of
f clk
the system equals . In a practical DDFS system, all the bits out of the phase
2n
accumulator are not passed on to the LUT, but are truncated, leaving only the first 13 to
15 MSBs. This reduces the size of the LUT and does not affect the frequency resolution.
The phase truncation only adds a small but acceptable amount of phase noise to the final
output. The resolution of the DAC is typically 2 to 4 bits less than the width of the lookup
table. Even a perfect N-bit DAC adds quantization noise to the output [17].
2.2 Frequency Tuning Equation

A sine wave is generally expressed as a(t ) = sin(ωt ) which is non-linear and not
easy to generate except through constructing it from pieces. However, the angular
information is linear because the phase angle rotates through a fixed angle for each unit
of time. Thus, the angular rate depends on the frequency of the signal described
as ω = 2πf , where, ω is the angular frequency. As shown in Figure 2.2, the phase
increases linearly from 0 to 2π over one complete cycle of the sine wave.
Figure 2.2: Sine magnitude and phase representation [19]
7
Knowing that the phase of a sine wave is linear and that it depends on a reference clock
period, with clock frequency f clk , the phase rotation ( Δp ) for that period can be
determined by
Δp = ω.Δt (2)
Where, Δp = change in phase of sine wave, ω = angular frequency of wave, Δt = small
change in time. Solving for ω in Equation 2, gives
ω = ⎛⎜ Δp Δt ⎞⎟ = 2πf (3)
⎝ ⎠
The overflowing accumulator (phase accumulator, PA) clocked with f clk , generates the
phase value sequence, where, Δt is the minimum amount of change,
f clk = 1 (4)
Δt
Solving for from Equation 3 and substituting the reference clock frequency for the
reference period in Equation 4, specifies the frequency of the output signal:
Δp * f clk
f out =
2π (5)
Finally, for an n-bit accumulator the output signal will have the frequency specified
Δp * f clk
f out = (6)
2n
Where, Δp (in degree) is the phase increment word or frequency control word or
frequency tuning word and f clk is the clock frequency, n is the length of accumulator.
This phase value Δp is generated using the modulo 2 n overflowing property of an n-bit
PA. The rate of the overflow is the output frequency given by Equation 6 or,
Δp * f clk
f out = (7)
2n
8
Δp , is an integer, therefore the frequency resolution is found by setting Δp = 1,

f clk
Δf =
2n (8)
A DDFS works on a point (memory location)-skipping technique (and a constant

interpolation of the stored signal) and runs at constant update (clock)-rate or reference
clock. As the DDFS output frequency is increased, the number of samples per waveform
cycle decreases.
In the point (memory location)-skipping technique, N data points cover one
complete cycle of the (sine) waveform. A block of N samples is stored in the memory
LUT (look-up table). The address pointer of the LUT is a "D step size, modulo N (mod
N, overflowing)" phase accumulator. D, a positive integer, is the FCW: frequency control
word [3].
• D = 1 gives an "exact copy" of the stored waveform (the pointer steps sequentially
through each address, i.e. the pointer accesses each consecutive entry in the table
in the same fashion as the PPC: point-per-clock synthesis or the sample playback
synthesis).
• When D > 1 , the pointer will "skip" some address, resulting in a higher frequency
value:
f out D
=
f clk N D prime to N, and D < N 2 (9)
As the output frequency

f out is increased, the number of samples per (sinusoid) cycle
decreases.
2.3 Building Blocks of DDFS

A DDFS is a mixed signal device i.e. it has both analog and digital blocks. These blocks
are the Phase Register, Phase Accumulator, Phase-to-Amplitude Converter (ROM/LUT),
Digital-to-Analog Converter, and Reconstruction Filter. The functionality of each of
these blocks is discussed in the following section.
9
2.3.1 Phase Accumulator

Continuous-time sinusoidal signals have a repetitive angular phase range of 0 to
360 degrees. The digital implementation is no different. The counter’s carry function
allows the phase accumulator to act as a phase wheel in the DDFS implementation, as
shown in Figure 2.3 [4]. To understand this basic function, consider the sine-wave
oscillation as a vector rotating around a phase circle. Each designated point on the phase
wheel corresponds to the equivalent point on a cycle of a sine wave. As the vector rotates
around the wheel, visualize that the sine of the angle generates a corresponding output
sine wave. One revolution of the vector around the phase wheel, at a constant speed,
results in one complete cycle of the output sine wave. The phase accumulator provides
the equally spaced angular values accompanying the vector’s linear rotation around the
phase wheel. The contents of the phase accumulator correspond to the points on the cycle
of the output sine wave [4].
Figure 2.3: Digital phase wheel [4]
The PA is a modulo- M counter that increments its stored number each times it
10
receives a clock pulse. The magnitude of the increment is determined by the binary-coded
input word ( M ). This word forms the phase step size between reference-clock updates; it
effectively sets how many points to skip around the phase wheel. The larger the jump
size, the faster the phase accumulator overflows and completes the equivalent of a sine-
wave cycle. The number of discrete phase points contained in the wheel is determined by
the resolution of the PA (n-bits), which determines the tuning resolution of the DDFS.
For example, for an n = 28-bit phase accumulator, M will have a value of 0000...0001,
which would cause the phase accumulator to overflow after 228 reference-clock cycles
(increments). If the value of M is changed to 0111...1111, phase accumulator will
overflow after only 2 reference-clock cycles (the minimum required by Nyquist). This
relationship can be seen in the basic tuning equation for DDFS architecture:
M * f clk
f out =
2n (10)
where:
f out = output frequency of the DDFS,
M = frequency control word,
f clk = internal reference clock frequency (system clock),
n = length of the phase accumulator, in bits.
Any change to the value of M results in immediate and phase-continuous changes
in the output frequency. In a DDFS, no loop settling time is incurred as in the case of a
PLL. As the output frequency is increased, the number of samples per cycle decreases.
Since, sampling theory, dictates that at least two samples per cycle are required to
reconstruct the output waveform, the maximum fundamental output frequency of a DDFS
f clk
is . However, for practical applications, the output frequency is limited to somewhat
2
less than that, improving the quality of the reconstructed waveform and permitting
filtering on the output. When generating a constant frequency, the output of the PA
increases linearly, so the analog waveform, it generates is inherently a ramp.
11
2.3.2 Phase-to-Amplitude Converter (ROM/ LUT)

In this thesis, the DDFS’s ROM is a sine Look up Table; it converts digital phase
input from the accumulator to output amplitude. The accumulator output represents the
phase of the wave as well as an address to a word, which is the corresponding amplitude
of the phase in the LUT. This phase amplitude from the ROM LUT drives the DAC to
provide an analog output. It is also called a digital Phase-to-Amplitude Converter (PAC),
or polar-to-rectangular transformation (projection of the real or imaginary component in
time), or (sine) waveform mapping device - a Memory. All techniques of calculating data
as simple lookup table operation are modeled here. The lookup memory contains one
cycle of the waveform to be generated. The size of the LUT is 2n words. LUT translates
truncated phase information, being in digital form, into quantized numerical waveform
samples.
Some DDFS systems can be implemented with ROM or without ROM. Using, a
ROM LUT as a phase to amplitude converter has some advantages over other ROMless
architectures. The simplicity of the ROM circuit makes the ROM LUT easy to
implement. The advantages of ROMless architectures can be seen when higher bit
accuracy is desired. For higher bit accuracy, the ROM becomes very large, consumes
more power and becomes slow as compared to ROMless architecture. The ROM LUT
stores the values of phase amplitudes while ROMless architectures compute phase
amplitudes. Inherently, a ROM LUT provides better SFDR than any ROMless
architecture for same bit width [2]. In an ideal case with no phase and amplitude
quantization, the output sequence of the look up table is given by,
(
sin 2π .P(i) 2n ) (11)
where, P(i) is the (n-bit) phase register value (at the ith clock period). The numerical
period, Pe of the PA output sequence (in clock cycles) is
2n
Pe = (12)
GCD(Δp,2 n )
where, GCD(Δp,2n ) represents the greatest common divisor of Δp and 2n
12
2.3.3 Digital-to-Analog Converter and Filter

The phase accumulator computes a phase (angle) address for the look-up table,
which outputs the digital value of amplitude—corresponding to the sine of that phase
angle—to the DAC. The DAC, in turn, converts that number to a corresponding value of
analog voltage or current. The DAC and rest of the system run at the same reference
clock for synchronization. The DAC adds quantization error at the output to the sine
wave. Ideally, SIN ( x ) is used to filter the output of the DAC [2]. It removes the extra
x
frequency components added to the sine wave and hence produces a smooth sine wave.
13
CHAPTER III
OUTPUT SPECTRUM OF DDFS
3.1 Sampled Output of DDFS [4]

An understanding of sampling theory is necessary when analyzing the sampled
output of a DDFS based signal synthesis solution. The spectrum of a sampled output is
illustrated in Figure 3.1. In this example, the sampling clock f clk is 300 MHz and the
fundamental output frequency f out is 80 MHz [4].
Figure 3.1: Spectral analysis of sampled output [4]
The Nyquist Theorem dictates that there is a minimum of two samples per cycle
required to reconstruct the desired output waveform. Images are created in the sampled
output spectrum at f clk ± f out . The 1st image response occurs in this example at f clk − f out
or 220 MHz. The 3rd, 4th, and 5th images appear at 380 MHz, 520 MHz, 680 MHz, and
820 MHz (respectively). Figure 3.1 shows that nulls appear at multiples of the sampling
frequency. In the case of the f out frequency exceeding the f clk frequency, the 1st image
response will appear within the Nyquist bandwidth DC − 1 f clk as an aliased image.
2
14
In typical DDFS applications, a lowpass filter is utilized to suppress the effects of

the image responses in the output spectrum. In order to keep the cutoff requirements on
the lowpass filter reasonable, it is an accepted rule to limit the f out bandwidth to
approximately 40% of the f clk frequency [4]. This facilitates using an economical lowpass
filter implementation on the output.
Figure 3.1 indicates that the amplitude of f out and the image response follows a
sin( x ) roll off response. This is due to the quantized nature of the sampled output. The
x
amplitude of the fundamental and any given image response can be calculated using the
sin( x ) formula. Per the rolloff response function, the amplitude of the fundamental
x
output will decrease inversely to increases in its tuned frequency. The amplitude rolloff
due to sin( x ) in a DDFS system is –3.92 dB over its DC to Nyquist bandwidth. A

x
DDFS architecture can include inverse SINC filtering. This can pre-compensate for the
sin( x ) rolloff and maintain flat output amplitude (± .1 dB) from the D/A converter over
x
a bandwidth of up to 45% of the clock rate or 80% of Nyquist rate. It is important to
generate a frequency plan in DDFS applications and analyze the spectral considerations
of the image response and the sin( x ) amplitude response at the desired f out and f clk
x
frequencies.
The other anomalies in the output spectrum, such as integral and differential
linearity errors of the D/A converter, glitch energy associated with the D/A converter,
and clock feed-through noise, do not follow the sin( x ) roll-off response. These
x
anomalies appear as harmonics and spurious energy in the output spectrum and generally
are much lower in amplitude than the image responses. The general noise floor of a
DDFS is determined by the cumulative combination of substrate noise, thermal noise
effects, ground coupling, and a variety of other sources of low-level signal corruption.
The noise floor, spur performance, and jitter performance of DDFS is greatly influenced
15
by circuit board layout, the quality of the power supply, and the quality of the input
reference clock.
3.2 Spectral Purity Considerations

The fidelity of a signal formed by recalling samples of a sinusoid from a LUT is
affected by both the phase and amplitude quantization of the process. The length and
width of the look-up table affect the signal's phase angle resolution and the signal's
amplitude resolution respectively. These resolution limits are equivalent to time base
jitter and to amplitude quantization of the signal and add spectral modulation lines and a
white broadband noise floor to the signal's spectrum. In conjunction with the system
clock frequency, PA width determines the frequency resolution of the DDFS. The PA
must have a sufficient field width to span the desired frequency resolution. For most
practical applications, a large number of bits are allocated to the phase accumulator in
order to satisfy the system frequency resolution requirements.
3.3 Spurious Free Dynamic Range

In many DDFS applications, the spectral purity of the DAC output is of primary
concern. Unfortunately, a number of interacting factors complicate the measurement,
prediction, and analysis of this performance. Even an ideal N-bit DAC produces
harmonics in a DDFS system. The amplitude of these harmonics is highly dependent
upon the ratio of the output frequency to the clock frequency. The assumption that the
quantization noise appears as white noise and is spread uniformly over the Nyquist
bandwidth is simply not true in a DDFS system. For instance, if the DAC output
frequency is set to an exact sub multiple of the clock frequency, then the quantization
noise is concentrated at multiples of the output frequency, i.e., it is highly signal
dependent. If the output frequency is slightly offset, however, the quantization noise
becomes more random, thereby giving an improvement in the effective SFDR. To obtain
best SFDR clock and output frequencies must be carefully chosen.
16
In ADC-based systems, adding a small amount of random noise to the input tends
to randomize the quantization errors and reduce this effect. The same thing can be done
in a DDFS system. A pseudo-random digital noise generator output can be added to the
DDFS sine amplitude word before being loaded into the DAC. The amplitude of the
digital noise is set to about 1 LSB . This accomplishes the randomization process at the
2
expense of a slight increase in the overall output noise floor. In most DDFS applications,
however, there is enough flexibility in selecting the various frequency ratios so that
dithering is not required [5].
3.4 DDFS with Phase Truncation and Spurious Performance

Phase truncation is an important aspect of DDS architectures. Consider a DDS
with a 12-bit phase accumulator. To directly convert 32 bits of phase to corresponding
amplitude would require 232 entries in a lookup table. If each entry were stored with 8-bit
accuracy, then 4-gigabytes of lookup table memory would be required. Clearly, it would
be impractical to implement such a design. The solution is to use a fraction of the most
significant bits of the accumulator output to provide phase information. For example, in a
32-bit DDS design, only the upper most 12 bits might be used for phase information. The
lower 20 bits would be ignored (truncated) in this case. To understand the implications of
truncating the phase accumulator output, consider the concept of “digital phase wheel”.
Consider a simple DDS architecture that uses an 8-bit accumulator of which only the
upper 5 bits are used for resolving phase. The phase wheel for this example is shown
Figure 3.2 below [6],
17
Figure 3.2: Phase truncation error and the phase wheel [6]
With an 8-bit accumulator, the phase resolution associated with the accumulator is
1/256th of a full circle, or 1.41° (360/28). In Figure 3.2, the accumulator phase resolution
is identified by the outer circle of tic marks. If only the most significant 5 bits of the
accumulator are used to convey phase information, then the resolution becomes 1/32nd of
a full circle, or 11.25° (360/25).
These are identified by the inner circle of tic marks. If a tuning word, value of 6 is
used, then the accumulator counts by increments of 6. The first four phase angles
corresponding to 6-count steps of the accumulator are depicted in Figure 3.2. The first
phase step (6 counts on the outer circle) falls short of the first inner tic mark. Thus, a
discrepancy arises between the phase of the accumulator (the outer circle) and the phase
as determined by 5-bit resolution (the inner circle). This discrepancy results in a phase
error of 8.46° (6 x 1.41°), as depicted by arc E1 in the Figure 3.2. On the second phase
step of the accumulator (6 more counts on the outer circle) the phase of the accumulator
resides between the 1st and 2nd tic marks on the inner circle. Again, there is a
discrepancy between the phase of the accumulator and the phase as determined by 5 bits
of resolution. The result is an error of 5.64° (4 x 1.41°) as depicted by arc E2 in the
Figure 3.2.
18
Similarly, at the 3rd phase steps of the accumulator an error of 2.82° (2 x 1.41°)
results. On the 4th phase step, however, the accumulator phase and the 5-bit resolution
phase coincide resulting in no phase error. This pattern continues as the accumulator
increments by 6 counts on the outer circle each time.
The phase error introduced by truncating the accumulator will result in errors in
amplitude during the phase-to-amplitude conversion process inherent in the DDS. It turns
out that these errors are periodic. They are periodic because, regardless of the tuning
word chosen, after a sufficient number of revolutions of the phase wheel, the accumulator
phase and truncated phase will coincide. Since these amplitude errors are periodic in the
time domain, they appear as spurs in the frequency domain and are known as phase
truncation spurs.
It turns out that the magnitude and distribution of phase truncation spurs is
dependent on three factors [6]:
1. Phase Accumulator size
2. Phase word size; i.e., the number of bits of phase after truncation
3. Frequency control word
3.5 DDFS with Dither and its effect on SFDR

In the phase dithering model, the phase values generated by the PA contain a
certain amount of noise. This is accomplished by adding a small random number to each
phase value generated at the output of the PA. A dither generator is used to produce a
random number with each update of the accumulator. Typically, the MSB of the random
number is positioned one bit less than the LSB of the word that is fed to the LUT. In the
phase truncation DDFS, the PT (Phase Truncation) introduces a phase error in the phase
slope by discarding the least significant part. The phase error due to the discarded
fractional part of the address count is periodic which results in undesired spurs. These
spurs associated with this correlated error sequence are impressed on the final output
waveform and results in spur in the synthesizer output spectrum.
19
These spurs can be suppressed by breaking up the regularity of the address error
with an additive randomizing signal. This random sequence, called dither, a noise
sequence, with variance approximately equal to the least significant integer bit of the PA.
The dithered DDFS supplies, a higher spurious free dynamic range (SFDR) in
comparison to a phase truncation design. The additional logic resources required to
implement the dither sequence generator are not significant. Typically, a 3 or 4-bit
random number is sufficient.
20
CHAPTER IV
SIMULATION AND RESULTS OF DDFS
This chapter discusses the implementation of different models of the DDFS and
their simulation results. High-level modeling and simulation of a DDFS was carried out
using MATLAB-Simulink to understand the overall functionality and the flow from input
to output. The DDS has also been modeled using Verilog and simulated with the
ModelSim simulator. This Verilog code is synthesizable on an FPGA. A DDFS has also
been designed using VerilogA and simulated with Cadence. In the Cadence simulation,
the reference clock used is a jittered clock, to understand the effect of clock jitter on the
output spectrum. Simulations help to increase the understanding of design under non-
ideal operations. Simulations serve as a prototype for a design before it is actually built in
hardware. These simulations are used to understand the effect of the non-ideal
characteristics of the building blocks of a DDFS on its output spectrum. Operation of the
DDFS has been explained in previous chapters.
4.1 High-level simulation of DDFS with MATLAB-Simulink

Matlab-Simulink implementation of a direct digital synthesizer consists of Phase
Register (PR), Phase Accumulator (PA) and Look up Table (LUT). This model has been
developed to study the functionality of the DDS. Figure 4.1 shows the system-level
model of the DDFS. The PR contains the frequency tuning word. The unit delay block in
the Figure 4.1 along with an adder and feedback loop represents the PA. These unit delay
blocks act as register. The LUT is implemented using inbuilt sine LUT block of
MATLAB-Simulink. The input of the LUT is scaled using the gain block.
21
Figure 4.1: MATLAB-Simulink model of DDS
With every clock pulse the contents of the PR is added to that of PA. The PA
generates the phase values of the output sine wave. The output of the PA serves as the
address of the LUT. Each time the PA overflows, the LUT outputs sampled values of the
sine wave. This output of the LUT represents one cycle of the sine waveform, since the
LUT contains sampled values of one cycle of the sine wave. The overflow rate of the PA
depends on the bit-size of the PA (number of bits) and the frequency tuning word. Larger
the size of the frequency tuning word faster the PA overflows. The output frequency of
the DDFS is directly proportional to the frequency tuning word. Therefore, larger the
frequency tuning word, higher is the output frequency and faster the PA overflows. This
is shown with the help of simulations. These simulations help to understand the signal
flow through the DDFS and the overflow of the PA and the relation of output frequency
with the PA. The frequency of the output wave depends on the overflow rate of the PA
and the frequency tuning word. This overflow rate depends on the frequency tuning word
stored in the phase register.
To generate an output frequency of 10 MHz with a reference clock frequency of
50M Hz, a frequency tuning word ( M ) of 51 is stored in the Phase Register. The value
of the frequency tuning word ( M ) is calculated using the frequency tuning equation. The
Phase Accumulator is 8-bits wide. This control word M is added to the previous value of
PA with each clock pulse.
22
In the Figure 4.2, it can be seen that for a frequency tuning word of 51, for the
first 3000 clocks, the PA overflows slightly more than two times. Therefore, the sine
wave of lower frequency is produced, which is shown in Figure 4.3.
Figure 4.2: PA output for M = 51
Figure 4.3: LUT output for f out = 10 MHz
If the output frequency to be generated is increased to 20 MHz with the same

reference clock frequency of 50 MHz, a new value of frequency tuning word ( M ) 102 is
stored in the Phase Register. Phase Accumulator is 8-bit wide. This control word M is
added to the previous value of PA with each clock.
Figure 4.4: PA output for M = 102
23
Figure 4.5: LUT output for f out = 20 MHz
In the above Figure 4.4, it can be seen that for a frequency tuning word of 102, for
the first 3000 clocks, the PA overflows slightly more than four times. Therefore, sinne
wave of higher frequency is produced, which is shown in Figure 4.5.
For smaller values of M , the PA overflows slower than with larger values as can
be seen in Figure 4.2 and Figure 4.3 respectively. Hence, the output wave in Figure 4.4
has a frequency lower then the output wave in Figure 4.5.
4.2 RTL level simulation of DDFS using ModelSim

The DDFS has been modeled on a behavioral level with the help of Verilog. First,
a simple DDS is simulated and then later more modules are added to look for their effects
on the output spectrum. These models help in understanding the effect of each block on
output.
4.2.1 Simple DDFS Simulation using ModelSim

The Figure 4.6 shows the RTL level schematic of the DDFS. This model has been
implemented using Verilog and simulated in ModelSim. In this model, different modules
in Verilog are created and then put together; therefore, it can be easily modified
according one’s design requirements. This design consist of four basic modules, they are
Top level, Register, Adder and the Look up Table. These modules are discussed in detail
in this chapter.
24
Figure 4.6: RTL schematic of DDFS
This model of the DDFS uses an 8-bit PA. The PA consists of a register and adder
with a feedback network. The Adder module is an 8-bit adder that has two 8-bit inputs
and one 9-bit output.
Figure 4.7 Verilog code for 8-bit Register
The Figure 4.7 shows the Verilog code for module Register. This module takes
clock, reset and 8-bit data “d” as input and an 8-bit output “q”. At each clock, this module
checks if the reset is high then the output q is zero else, it is equal to input d. This code is
synthesizable.
25
Figure 4.8 Simulation result of Register
The PA is modeled by interconnecting Register and Adder modules, as shown in

RTL schematic of DDFS, in Figure 4.6. It has been mentioned earlier that with each
clock pulse the contents of the phase register are added to that of the PA. This shown in
Figure 4.9. Here the content of the phase register is 40 i.e. “d1”. When the reset is high,
the output of phase register is 0 and when the reset goes low the output “q1” is 40.
Initially sum1 is equal to 0. After reset goes low with each clock pulse the content of the
PA are incremented by a value of 40. This goes on until the accumulator overflows and
then the cycle starts again.
Figure 4.9 Simulation result of the PA
Next module used in this model is the Look up Table. This module takes clock,
reset and an 8-bit address as input and has one 8-bit output. The 8-bit address input is the
output of the PA. The LUT contains the sampled values of the amplitude of the one cycle
of the sine wave. The LUT has 28 entries i.e. 256 values and each entry is 8-bit in length.
Therefore, the size of the LUT is 256*8 i.e. 65536.
26
The contents of the LUT i.e. sampled values of the amplitude of the sine wave are
generated using MATLAB.
Figure 4.10 Verilog code for the LUT
Figure 4.10 shows the Verilog code of the LUT. This code is synthesizable. When
the reset is high, the LUT is loaded with the sampled values of the amplitude of the sine
wave and the output is 0. When the reset goes low, then based on the address generated
by the PA and received by the LUT the, corresponding values are present at the output of
the LUT, this is shown in Figure 4.11 below.
Figure 4.11 Simulation result of the LUT
27
Figure 4.12 Top-level with the interconnection of modules
This simulation, performed with a reference clock of 50 MHz because the

XILINX SPARTAN FPGA can run at maximum clock frequency of 50 MHz. Figure 4.6
shows the RTL schematic of the DDFS. In this simulation a output frequency of 3.1 MHz
is generated with an 8-bit PA and reference clock of 50M Hz, the frequency tuning word
is calculated to be 15.87 (binary- 00001111). When this tuning word is programmed into
the Phase Register, the fractional part is lost. This results in the loss of phase and
introduces some error in the phase calculation and the output frequency generated is a
little less than the desired frequency. Figure 4.14 shows the PSD plot for this simulation.
The output frequency generated is 2.93 MHz and the SFDR is calculated to be 61.35 dB.
28
Figure 4.13: ModelSim simulation f out = 3.1 MHz
Figure 4.14: PSD plot f out = 3.1 MHz
If the same simulation is performed to generate an output frequency of 5 MHz

keeping the reference clock and PA the same, then the tuning word is calculated to be
25.6 (binary- 00011001).
29
Figure 4.15: ModelSim simulation f out = 5 MHz
Figure 4.16: PSD plot f out = 5 MHz
The output frequency obtained is 4.887 MHz, which is a little less than the desired
frequency due to loss of the fractional part of frequency tuning word. SFDR of 55.04 dB
is found from the PSD plot in Figure 4.16.
30
4.2.2 DDFS with Phase Truncation and Dither

In the previous simulation, the PA was 8-bit in length. Therefore, the LUT had 28
entries i.e. 256 values and each entry was 8-bit in length. Therefore, the size of the LUT
was 256*8 i.e. 2048. If the size of the PA is 12-bit then the LUT will have 212 entries. If
each entry is 8-bit long then the size of the LUT will be 212 * 8 (i.e. 32768). This shows
that, as the length of the PA increases, the size of the LUT increases exponentially. This
reduces the speed of the DDFS but more the number of bits in the PA, higher is the
frequency resolution. The frequency resolution is directly proportional to the length of
the PA. Therefore, there exists a trade off between size, frequency resolution and the
speed. The solution to this problem is phase truncation (PT). With PT, the length of the
PA can be increased without increasing the size of the LUT but at the expense of the
spectral purity of the output spectrum. In phase truncation, the most significant bits
(MSB) of the phase are used to address the LUT. Figure 4.17 shows the RLT schematic
of a DDFS with a Phase Truncation block.
Figure 4.17: DDFS with phase truncation
The phase truncation and its effect on output spectrum of DDFS have been
examined through this simulation. A 12-bit PA will generate a 12-bit phase value and a
LUT with entries 212 i.e. 4096 samples will be required. In this simulation, an additional
module for PT has been implemented. This module takes the 12-bit phase value
generated by the PA and outputs the 8 MSB’s leaving 4 LSB’s. These 8 most significant
31
bits of the phase are used to address the LUT. This can be seen in Figure 4.19, “q2”
represents the output of the PA and “pt” is the truncated phase value.
Figure 4.18: Verilog Code for Phase Truncation Module
Figure 4.19: Simulation result of the PT
To generate an output frequency of 3.1 MHz with an 12-bit PA and a reference

clock of 50 MHz, the frequency tuning word is calculated to be 253.95 (binary-
000011111101).
32
Figure 4.20: ModelSim simulation with PT
The PSD of the output
-10 X: 3.128e+006
Y: -5.982
-20
-30
-40
dB
-50
-60
-70
-80
-90
7
10
Hz
Figure 4.21: PSD plot with PT
The SFDR from the PSD plot in Figure 4.21 is found to be 19.42 dB.
As indicated in previous chapters, phase truncation introduces amplitude errors,
and these errors are reflected as spurs in the output spectrum. To suppress these spurs a
random bit sequence, called dither, is added to the PA output before truncation. This
gives a better SFDR than phase truncation alone.
33
Figure 4.22: DDFS with Phase Truncation and Dither Generator
The dither generator implemented in this simulation generates a 3-bit random

number. This random number is added to the output of PA. The fractional part of the
tuning word is discarded, the phase generated by the PA contains error and this error is
periodic. Addition of a random number to this phase value breaks the periodicity.
Figure 4.23: Verilog code for the random number generator
34
Figure 4.24: Simulation result of the PA, PT and Dither
The figure 4.24 above shows the simulation result of the PA, PT and the Dither
modules connected together. The output of the PA is shown by signal “q2”, phase
truncated phase is shown by “pt” and the dither by “x”.
The PSD of the output
-10 X: 3.107e+006
Y: -5.538
-20
-30
-40
dB
-50
-60
-70
-80
-90
7
10
Hz
Figure 4.25: PSD Plot with PT and Dither
Looking at the PSD plot in Figure 4.25, SFDR is found to be 29.10 dB. As earlier
mentioned that PT introduces spurs in the output spectrum and addition of dither helps in
suppressing these spurs unto some extent.
These Verilog models are very user friendly and synthesizable on FPGA. One can
easily make changes to these models according to their application requirement and look
into different aspects of the DDFS.
35
4.3 Cadence simulation of DDFS with Clock Jitter

In this model, the effect of clock jitter on the output spectrum is analyzed. In the
real world, inputs are not ideal and are always associated with some kind of noise. In the
time domain, noise on clocks or input data is known as jitter. The DDFS has been
modeled in VerilogA the same way as it was modeled in the section 4.2. The VerilogA
code can be seen the Appendix section. This section demonstrates the use of behavioral
modeling to generate these non-ideal signals.
Jitter can be defined as the deviation of the significant instances of a signal from
their ideal location in time. To put it more simply, jitter is how early or late a signal
transition is with reference to when it should transition. In a digital signal, the significant
instances are the transition (crossover) points.
Figure 4.26: Random number and Clock Jitter Generator
The DDFS requires a reference clock input. In order to perform system-level

verification or simulation a certain amount of jitter is introduced. This jitter typically has
a Gaussian distribution. In this design, jitter is produced by generating a random number
using random distribution function of VerilogA, then integrating this random number
with the ideal clock. This causes the clock to make transitions more randomly. The
VerilogA function used for this purpose is
$rdist_normal (seed, mean, standard_deviation);
This function uses three parameters: a seed value, mean and standard deviation. The
mean parameter is an integer input, which causes the average value returned by the
function to approach the value specified. The standard deviation parameter used with the
36
$dist_normal function is an integer input which helps determine the shape of the density
function. Larger numbers for standard deviation will spread the returned values over a
wider range. With a mean of 0 and standard deviation of 1, $dist_normal generates
Gaussian distribution.
Figure 4.27: VerilogA modules of Random Number and Clock Generator
Figure 4.28 shows the random number generated using random function of VerilogA.
Figure 4.28: Output of Random number generator
37
This random number is used to vary the delay time of the clock. When this
random number is integrated with the ideal clock, it randomly changes the delay time of
the clock pulse, which introduces jitter in the clock. The Figure 4.29 shows ideal clock.
Jitter induced clock can be seen in Figure 4.30 below. As shown, the delay time of the
jittered clock, represented by green, is different from the ideal clock, represented in
black.
Figure 4.29: Ideal Clock f clk =100 MHz
38
Figure 4.30: Ideal Clock, Jittered Clock and Random Number
Figure 4.31: Jitter
The amount of jitter induced in the ideal clock is shown in Figure 4.31. The
amount of jitter can be varied by making very small changes in the clock module.
39
Figure 4.32: DDFS with ideal clock
Figure 4.33: DDFS with jittered clock
Figure 4.32 and Figure 4.33 shows DDFS with ideal clock and non-ideal clock
respectively. Figure 4.34 shows the output of the PA when clocked with the ideal clock.
Figure 4.35 shows the output of the PA when clocked with jittered clock.
Figure 4.34: Phase Accumulator with Ideal Clock
40
Figure 4.35: Phase Accumulator with jittered Clock
As shown in Figure 4.34 and Figure 4.35, the PA overflows uniformly with the
ideal clock but non-uniformly with the jittered clock. This non-uniform overflow of PA
in Figure 4.35 is due to the effect of jitter present in the clock. For the clock with jitter,
the PA goes through non-uniform iterations. When this PA output is fed to the input of
the LUT, the LUT output’s samples at different times and this gives rise to spurs in the
output spectrum of the DDFS.
If an output frequency of 7.5 MHz is generated with a reference clock frequency
of 100 MHz, a frequency tuning word ( M ) of 19 is stored in the Phase Register. In this
design, the Phase Accumulator is 8-bit wide. This control word M is added to the
previous value of PA with each clock update.
Figure 4.36: Output spectrum of DDFS with ideal clock f out = 7.5 MHz
41
Figure 4.37: Output spectrum with clock jitter f out = 7.5 MHz
Figure 4.38: comparison of output spectrums f out = 7.5 MHz

On comparing the two spectrum plots shown in Figure 4.36 and Figure 4.37, it
can be seen that the noise floor of the clock with jitter, represented by blue in the Figure
4.38, is more than the noise floor of ideal clock spectrum, represented by green. In case
of ideal clock, the SFDR is 41 dB while in case of clock with jitter SFDR is 38.5 dB,
which clearly shows that there is a 2.5 dB decrease in the dynamic range.
For another example, the output frequency is increased to 12.11 MHz with a
frequency tuning word ( M ) of 31 while keeping the reference clock frequency the same.
Figure 4.39 shows a comparison of output spectrums for this simulation. The noise floor
42
in the case of the clock with jitter, represented in red, is higher that the ideal clock.
Figure 4.39: comparison of output spectrums f out =12.11 MHz
Figure 4.39 above compares the output spectrums. For the output frequency of
12.11 MHz, the SFDR for the ideal clock spectrum is 36 dB and for the jitter clock
spectrum, the SFDR is 32.5 dB. There is a 3.5 dB loss of dynamic range.
Figure 4.40: f out =12.11M Hz with jitter = 2ns
43
Figure 4.41: f out = 12.11 MHz with jitter = 1ns
Figure 4.40 and Figure 4.41 shows the effect of different values of jitter for the same
output frequency of 12.11 MHz. For a jitter of 1ns, SFDR is found to be 51.2 dB and for
a jitter of 2ns SFDR is 48.8 dB. The values of jitter presented are the average of 30 clock
cycles.
4.4 Quantization Error

LUT contains the samples of one cycle of a sine wave. These samples are in
quantized form or in binary form. These samples represent the amplitude of the sine wave
at different phases. In this design, the LUT with 8-bit and 12-bit samples are used. In this
simulation, an output frequency of 7.5 MHz is generated with a reference clock of 100
MHz.
Figure 4.42: DDFS Output Spectrum with LUT having 8-bit samples
44
Figure 4.43: DDFS Output Spectrum with LUT having 12-bit samples
The spectrum plot, shown in Figure 4.42, is produced by using the LUT
containing 8-bit quantized samples and in Figure 4.43, using a LUT containing 12-bit
samples. Figure 4.42 shows a SFDR of 41.2dB and Figure 4.43shows a SFDR of 42dB.
If the output frequency is increased to 10 MHz, keeping the reference clock the
same and performing simulations for LUT containing 8-bit and 12-bit quantized samples.
Figure 4.44: comparison of output spectrums
In Figure 4.44, blue represents the spectrum generated by a LUT with 8-bit
quantized samples and red represents the spectrum generated by a LUT with 12-bit
quantized samples. The SFDR of the curve Blue is calculated to be 22.2 dB and red curve
45
is 23 dB. The change in SFDR, for this case, seems small and may be in an acceptable
range.
46
CHAPTER V
CONCLUSIONS AND FUTURE WORK
The DDFS models have been successfully created, implemented and simulated
using MATLAB-Simulink, ModelSim and Cadence Specter simulators. These models
have effectively shown the effect of each building block of the DDFS on the output.
These models are discussed in detail in Chapter IV along with simulation. The effects of
jitter on the output spectrum of DDFS with different simulation results have been
successfully presented. These simulations have provided a better understanding of the
response of DDFS with variation of jitter. Dynamic Range of 51.2 dB has been achieved
for a jitter of 1ns and 48.8 dB for a jitter of 2ns.
As the length of the phase accumulator increases, the size of the ROM/LUT
increases exponentially. This reduces the speed of the DDFS and increases the size of
hardware but more the number of bits in the phase accumulator, higher the frequency
resolution. Therefore, there exists a trade off between size, frequency resolution and the
speed. This issue of increase in the size of ROM can be solved with the phase truncation
but that introduces noise in the output. These spurs can be suppressed with the addition of
dither. This has been efficiently shown with different models of the DDFS.
The Verilog modules, presented in this thesis are synthesizable on FPGA. The
response of the DDFS mainly depends upon length of accumulator, desired output
frequency and the clock frequency, therefore one can change these values in the top
module and use these models to understand different aspects of DDFS and the effects on
output as per the application.
A methodology for the purpose of modeling and simulating the jitter in DDFS is
presented. The simulation is done at the behavioral level, and so is efficient enough to be
applied in a wide variety of applications. This methodology is flexible enough to be used
in a broad range of applications where noise and jitter is important.
47
DDFS can be implemented using ROMless architecture using quarter wave

symmetry or some different algorithm, to reduce the hardware, power dissipation and
increase the efficiency. Both simple and amplitude/ phase inversion techniques need a
factor of more than two increase in Rom size per bit, so the algorithmic LUT technique
can be implemented. With the increased size of the ROM, the speed of access time
becomes a limit to operational speed of DDFS. A transistor level implementation will
give better insight of functionality of system, since it will include effects of parasitic
involved. Those parasitic will also contribute to noise in the output wave.
48
LIST OF REFERENCES
[1] A Digital Frequency Synthesizer- J.Tierney, C.M.Radre, and B.Gold

IEEE Transactions on Audio and Electroacoustics, March 1971
[2] Direct Digital Synthesizers: Theory, Design and Applications- Jouko Vankka
Boston ; London : Kluwer Academic Publishers, 2001
[3] DDS Technology- Online Available WWW:

http://www.hit.bme.hu/~papay/sci/DDS/start.htm.
Accessed on 11 September, 2006.
[4] A Technical Tutorial on Digital Signal Synthesis, Online Available WWW:

http://www.analog.com/UploadedFiles/Tutorials/450968421DDS_Tutorial_rev12-2-
99.pdf#search=%22a%20technical%20tutorial%20on%20digital%20signal%20synth
esis%22.
Accessed on 1 January, 2007.
[5] High Speed DACs and DDS Systems- Walt Kester, Online Available WWW:
http://www.analog.com/UploadedFiles/Associated_Docs/3670548256311702750332
4650252sect6.pdf.
Accessed on 1 January, 2007.
[6] Ask The Application Engineer—33, All About Direct Digital Synthesis
Volume 38 – August 2004: Eva Murphy , Colm Slattery, Online Available WWW:
http://www.analog.com/library/analogDialogue/archives/38-08/dds.html.
Accessed on 11 August, 2006.
49
[7] CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Spectrum

Communications- D.A.Sunderland, R. A. Strauch, S.S. Wharfield, H.T. Peterson and
C.R. Cole, IEEE Journal of Solid-State Circuits, August 1984.
[8] Design of low-power ROM-less direct digital frequency synthesizer using

nonlinear digital-to-analog converter- Mortezapour, S.; Lee, E.K.F.
Solid-State Circuits, IEEE Journal of, Volume: 34 Issue: 10 , Oct. 1999
Page(s): 1350 –1359.
[9] New direct digital frequency synthesizer architecture for mobile transceivers
Hegazi, E.M.; Ragaie, H.F.; Haddara, H.; Ghali, H. Circuits and Systems, 1998.
ISCAS' 98. Proceedings of the 1998 IEEE International Symposium on, Volume:
3, 1998 Page(s): 647 -650 vol.3.
[10] Direct Digital Frequency Synthesizers, A Selected Reprint Volume IEEE

Ultrasonics, Ferroelectrics and Frequency Control Society.
[11] Digital Techniques in Frequency Synthesis- B.Goldberg, New York: McGraw-Hill,

1996.
[12] CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications
-D.Sunderland, R.Strauch, S.Wharfield, H.Peterson, and C.Cole, IEEE J. Solid-state
Circuits, vol. SC-19, pp 497-505, Aug. 1984.
[13] The optimization of direct digital frequency synthesizer performance in the presence
of finite word length effects- H.Nicholas, H.Samueli, and B.Ki, 42nd Annul.
Frequency Control Symp., 1988, pp.357-363.
50
[14] A low-power direct digital frequency synthesizer architecture for wireless

communications- Bellaouar, A.; Obrecht, M.; Fahim, A.; Elmasry, M.I.
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999, 1999
Page(s): 593 -596.
[15] A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless
communication- Yamagishi, A.; Ishikawa, M.; Tsukahara, T.; Date, S.
Solid-State Circuits, IEEE Journal of, Volume: 33 Issue: 2, Feb. 1998
Page(s): 210 –217.
[16] Direct Digital Synthesizer (DDS)- Ognjen Nikolic, University of Maine

Online Available WWW:
http://www.ece.umaine.edu/vlsi/2006/Nikolic/OgyECE547Report.pdf
Accessed on 15 October, 2006.
[17] Nicholas, H.T., and Samueli H., “ An analysis of output spectrum of direct digital
frequency synthesizer in the presence of phase accumulator truncation”,
Proceedings of the 41st. IEEE Annual Frequency Control Symposium pp495-502.
[18] James A. Crawford, “Frequency Synthesizer Design Handbook” 1994
[19] Low-power direct digital frequency synthesis for wireless communications

Bellaouar, A.; O'brecht, M.S.; Fahim, A.M.; Elmasry, M.I.
Solid-State Circuits, IEEE Journal of, Volume: 35 Issue: 3 , March 2000
Page(s): 385 -390.
51
APPENDIX A
VerilogA Modules:
VerilogA Module for Adder-

// VerilogA ADDER, veriloga
ìnclude "constants.h"
ìnclude "discipline.h"
module ADDER(in1,in2,out);
input in1,in2;
output out;
electrical in1,in2;
electrical out;
real out_reg;
analog begin
out_reg = V(in1)+V(in2);
if (out_reg > 1)
out_reg = out_reg - 1;
V(out) <+ transition(out_reg,1e-9,1e-9);
end
endmodule
VerilogA Module for Look up Table-
// VerilogA Look_up_table, veriloga
ìnclude "disciplines.h"
module Look_up_table(clk,address,LUT_out);
52
voltage clk, LUT_out;

voltage address;
input clk;
input address;
output LUT_out;
real LUT[0:255];
parameter integer dir=1 from [-1:1] exclude 0;
integer temp;
real temp1;
real threshold;
analog begin
threshold = 0.5;
@(initial_step)
begin
// sine values
LUT[0]=0.0234;
LUT[1]=0.0469;
LUT[2]=0.0703;
LUT[3]=0.0938;
LUT[4]=0.1172;
LUT[5]=0.1406;
LUT[6]=0.1641;
LUT[7]=0.1875;
LUT[8]=0.2188;
LUT[9]=0.2422;
LUT[10]=0.2656;
LUT[11]=0.2891;
LUT[12]=0.3125;
LUT[13]=0.3359;
LUT[14]=0.3594;
LUT[15]=0.375;
53
LUT[16]=0.3984;
LUT[17]=0.4219;
LUT[18]=0.4453;
LUT[19]=0.4688;
LUT[20]=0.4922;
LUT[21]=0.5078;
LUT[22]=0.5312;
LUT[23]=0.5547;
LUT[24]=0.5703;
LUT[25]=0.5938;
LUT[26]=0.6094;
LUT[27]=0.6328;
LUT[28]=0.6484;
LUT[29]=0.6641;
LUT[30]=0.6875;
LUT[31]=0.7031;
LUT[32]=0.7188;
LUT[33]=0.7344;
LUT[34]=0.75;
LUT[35]=0.7656;
LUT[36]=0.7812;
LUT[37]=0.7969;
LUT[38]=0.8125;
LUT[39]=0.8281;
LUT[40]=0.8438;
LUT[41]=0.8516;
LUT[42]=0.8672;
LUT[43]=0.875;
LUT[44]=0.8906;
LUT[45]=0.8984;
LUT[46]=0.9141;
LUT[47]=0.9219;
LUT[48]=0.9297;
LUT[49]=0.9375;
LUT[50]=0.9453;
LUT[51]=0.9531;
54
LUT[52]=0.9609;
LUT[53]=0.9688;
LUT[54]=0.9688;
LUT[55]=0.9766;
LUT[56]=0.9844;
LUT[57]=0.9844;
LUT[58]=0.9922;
LUT[59]=0.9922;
LUT[60]=0.9922;
LUT[61]=0.9922;
LUT[62]=0.9922;
LUT[63]=0.9922;
LUT[64]=0.9922;
LUT[65]=0.9922;
LUT[66]=0.9922;
LUT[67]=0.9922;
LUT[68]=0.9922;
LUT[69]=0.9844;
LUT[70]=0.9844;
LUT[71]=0.9766;
LUT[72]=0.9688;
LUT[73]=0.9688;
LUT[74]=0.9609;
LUT[75]=0.9531;
LUT[76]=0.9453;
LUT[77]=0.9375;
LUT[78]=0.9297;
LUT[79]=0.9219;
LUT[80]=0.9141;
LUT[81]=0.8984;
LUT[82]=0.8906;
LUT[83]=0.875;
LUT[84]=0.8672;
LUT[85]=0.8516;
LUT[86]=0.8438;
LUT[87]=0.8281;
55
LUT[88]=0.8125;
LUT[89]=0.7969;
LUT[90]=0.7812;
LUT[91]=0.7656;
LUT[92]=0.75;
LUT[93]=0.7344;
LUT[94]=0.7188;
LUT[95]=0.7031;
LUT[96]=0.6875;
LUT[97]=0.6641;
LUT[98]=0.6484;
LUT[99]=0.6328;
LUT[100]=0.6094;
LUT[101]=0.5938;
LUT[102]=0.5703;
LUT[103]=0.5547;
LUT[104]=0.5312;
LUT[105]=0.5078;
LUT[106]=0.4922;
LUT[107]=0.4688;
LUT[108]=0.4453;
LUT[109]=0.4219;
LUT[110]=0.3984;
LUT[111]=0.375;
LUT[112]=0.3594;
LUT[113]=0.3359;
LUT[114]=0.3125;
LUT[115]=0.2891;
LUT[116]=0.2656;
LUT[117]=0.2422;
LUT[118]=0.2188;
LUT[119]=0.1875;
LUT[120]=0.1641;
LUT[121]=0.1406;
LUT[122]=0.1172;
LUT[123]=0.0938;
56
LUT[124]=0.0703;
LUT[125]=0.0469;
LUT[126]=0.0234;
LUT[127]=0;
LUT[128]=-0.0234;
LUT[129]=-0.0469;
LUT[130]=-0.0703;
LUT[131]=-0.0938;
LUT[132]=-0.1172;
LUT[133]=-0.1406;
LUT[134]=-0.1641;
LUT[135]=-0.1875;
LUT[136]=-0.2188;
LUT[137]=-0.2422;
LUT[138]=-0.2656;
LUT[139]=-0.2891;
LUT[140]=-0.3125;
LUT[141]=-0.3359;
LUT[142]=-0.3594;
LUT[143]=-0.375;
LUT[144]=-0.3984;
LUT[145]=-0.4219;
LUT[146]=-0.4453;
LUT[147]=-0.4688;
LUT[148]=-0.4922;
LUT[149]=-0.5078;
LUT[150]=-0.5312;
LUT[151]=-0.5547;
LUT[152]=-0.5703;
LUT[153]=-0.5938;
LUT[154]=-0.6094;
LUT[155]=-0.6328;
LUT[156]=-0.6484;
LUT[157]=-0.6641;
LUT[158]=-0.6875;
LUT[159]=-0.7031;
57
LUT[160]=-0.7188;
LUT[161]=-0.7344;
LUT[162]=-0.75;
LUT[163]=-0.7656;
LUT[164]=-0.7812;
LUT[165]=-0.7969;
LUT[166]=-0.8125;
LUT[167]=-0.8281;
LUT[168]=-0.8438;
LUT[169]=-0.8516;
LUT[170]=-0.8672;
LUT[171]=-0.875;
LUT[172]=-0.8906;
LUT[173]=-0.8984;
LUT[174]=-0.9141;
LUT[175]=-0.9219;
LUT[176]=-0.9297;
LUT[177]=-0.9375;
LUT[178]=-0.9453;
LUT[179]=-0.9531;
LUT[180]=-0.9609;
LUT[181]=-0.9688;
LUT[182]=-0.9688;
LUT[183]=-0.9766;
LUT[184]=-0.9844;
LUT[185]=-0.9844;
LUT[186]=-0.9922;
LUT[187]=-0.9922;
LUT[188]=-0.9922;
LUT[189]=-0.9922;
LUT[190]=-0.9922;
LUT[191]=-0.9922;
LUT[192]=-0.9922;
LUT[193]=-0.9922;
LUT[194]=-0.9922;
LUT[195]=-0.9922;
58
LUT[196]=-0.9922;
LUT[197]=-0.9844;
LUT[198]=-0.9844;
LUT[199]=-0.9766;
LUT[200]=-0.9688;
LUT[201]=-0.9688;
LUT[202]=-0.9609;
LUT[203]=-0.9531;
LUT[204]=-0.9453;
LUT[205]=-0.9375;
LUT[206]=-0.9297;
LUT[207]=-0.9219;
LUT[208]=-0.9141;
LUT[209]=-0.8984;
LUT[210]=-0.8906;
LUT[211]=-0.875;
LUT[212]=-0.8672;
LUT[213]=-0.8516;
LUT[214]=-0.8438;
LUT[215]=-0.8281;
LUT[216]=-0.8125;
LUT[217]=-0.7969;
LUT[218]=-0.7812;
LUT[219]=-0.7656;
LUT[220]=-0.75;
LUT[221]=-0.7344;
LUT[222]=-0.7188;
LUT[223]=-0.7031;
LUT[224]=-0.6875;
LUT[225]=-0.6641;
LUT[226]=-0.6484;
LUT[227]=-0.6328;
LUT[228]=-0.6094;
LUT[229]=-0.5938;
LUT[230]=-0.5703;
LUT[231]=-0.5547;
59
LUT[232]=-0.5312;
LUT[233]=-0.5078;
LUT[234]=-0.4922;
LUT[235]=-0.4688;
LUT[236]=-0.4453;
LUT[237]=-0.4219;
LUT[238]=-0.3984;
LUT[239]=-0.375;
LUT[240]=-0.3594;
LUT[241]=-0.3359;
LUT[242]=-0.3125;
LUT[243]=-0.2891;
LUT[244]=-0.2656;
LUT[245]=-0.2422;
LUT[246]=-0.2188;
LUT[247]=-0.1875;
LUT[248]=-0.1641;
LUT[249]=-0.1406;
LUT[250]=-0.1172;
LUT[251]=-0.0938;
LUT[252]=-0.0703;
LUT[253]=-0.0469;
LUT[254]=-0.0234;
LUT[255]=0;
end
@(cross(V(clk) - threshold, dir)) begin

temp = V(address)*256; // normalization
temp1 = LUT[temp];
end
V(LUT_out) <+ transition(temp1, 1e-9, 1e-9);

end
endmodule
60
VerilogA Module for Random Number Generator-
// VerilogA random, veriloga
module random1(out);
output out;
electrical out;
parameter period = 1;
integer seed;
real x;
analog begin
@(timer(0, period))
seed = 1;
x= ($rdist_normal(seed,1,1));
V(out) <+ transition(x/1, 0, period/100);
end
endmodule
VerilogA Module for Clock Generator-
// VerilogA clk_gen, veriloga
ìnclude "constants.vams"
ìnclude "disciplines.vams"
61
module clk_gen(in, clk,clkout);
input in,clk;
output clkout;
electrical in, clk, clkout;
parameter real tr = 1e-9;
parameter real tf= 1e-9;
real vin;
real vout;
analog begin
vin = V(in)*1e-15;
V(clkout) <+ transition(V(clk),tr + vin, tf + vin);

// V(clkout) <+ transition(V(clk), td+vin,tr, tf);
end
endmodule
VerilogA Module for Register-

// VerilogA register, veriloga
ìnclude "discipline.h"
module register (clk, d, q);
voltage clk, d, q;
input clk;
input d;
output q;
real temp;
analog begin
@(initial_step)
temp = 0;
62
@(cross(V(clk) - 0.5, +1))

temp = V(d);
V(q) <+ transition(temp, 1e-9, 1e-9);
end
endmodule
VerilogA Module for Low Pass Filter-

// VerilogA lpf_new, veriloga
module lpf(in, out);
input in;
output out;
parameter real pole = 500000;
voltage in, out;
analog begin
V(out) <+ laplace_nd(V(in), [1], [1, 2/pole, 1/pow(pole,2)]); // second

order filter
//V(out) <+ laplace_nd(V(in), [1], [1, 1/pole]); // first order filter
endmodule
63
APPENDIX B
Verilog Modules:
Verilog Module for LUT

module LOOK_UP_TABLE(clk, reset, address, LUT_out);
input clk, reset;

input [0:7]address;
output [0:7]LUT_out;
reg [0:7]LUT_out;
reg [0:7] LUT [0:255];
always@(posedge clk)
begin
if(reset == 1'b1)
begin
LUT[0]<=8'b00000011;
LUT[1]<=8'b00000110;
LUT[2]<=8'b00001001;
LUT[3]<=8'b00001100;
LUT[4]<=8'b00001111;
LUT[5]<=8'b00010010;
LUT[6]<=8'b00010101;
LUT[7]<=8'b00011000;
LUT[8]<=8'b00011100;
LUT[9]<=8'b00011111;
LUT[10]<=8'b00100010;
LUT[11]<=8'b00100101;
LUT[12]<=8'b00101000;
LUT[13]<=8'b00101011;
LUT[14]<=8'b00101110;
LUT[15]<=8'b00110000;
64
LUT[16]<=8'b00110011;
LUT[17]<=8'b00110110;
LUT[18]<=8'b00111001;
LUT[19]<=8'b00111100;
LUT[20]<=8'b00111111;
LUT[21]<=8'b01000001;
LUT[22]<=8'b01000100;
LUT[23]<=8'b01000111;
LUT[24]<=8'b01001001;
LUT[25]<=8'b01001100;
LUT[26]<=8'b01001110;
LUT[27]<=8'b01010001;
LUT[28]<=8'b01010011;
LUT[29]<=8'b01010101;
LUT[30]<=8'b01011000;
LUT[31]<=8'b01011010;
LUT[32]<=8'b01011100;
LUT[33]<=8'b01011110;
LUT[34]<=8'b01100000;
LUT[35]<=8'b01100010;
LUT[36]<=8'b01100100;
LUT[37]<=8'b01100110;
LUT[38]<=8'b01101000;
LUT[39]<=8'b01101010;
LUT[40]<=8'b01101100;
LUT[41]<=8'b01101101;
LUT[42]<=8'b01101111;
LUT[43]<=8'b01110000;
LUT[44]<=8'b01110010;
LUT[45]<=8'b01110011;
LUT[46]<=8'b01110101;
LUT[47]<=8'b01110110;
LUT[48]<=8'b01110111;
LUT[49]<=8'b01111000;
LUT[50]<=8'b01111001;
LUT[51]<=8'b01111010;
65
LUT[52]<=8'b01111011;
LUT[53]<=8'b01111100;
LUT[54]<=8'b01111100;
LUT[55]<=8'b01111101;
LUT[56]<=8'b01111110;
LUT[57]<=8'b01111110;
LUT[58]<=8'b01111111;
LUT[59]<=8'b01111111;
LUT[60]<=8'b01111111;
LUT[61]<=8'b01111111;
LUT[62]<=8'b01111111;
LUT[63]<=8'b01111111;
LUT[64]<=8'b01111111;
LUT[65]<=8'b01111111;
LUT[66]<=8'b01111111;
LUT[67]<=8'b01111111;
LUT[68]<=8'b01111111;
LUT[69]<=8'b01111110;
LUT[70]<=8'b01111110;
LUT[71]<=8'b01111101;
LUT[72]<=8'b01111100;
LUT[73]<=8'b01111100;
LUT[74]<=8'b01111011;
LUT[75]<=8'b01111010;
LUT[76]<=8'b01111001;
LUT[77]<=8'b01111000;
LUT[78]<=8'b01110111;
LUT[79]<=8'b01110110;
LUT[80]<=8'b01110101;
LUT[81]<=8'b01110011;
LUT[82]<=8'b01110010;
LUT[83]<=8'b01110000;
LUT[84]<=8'b01101111;
LUT[85]<=8'b01101101;
LUT[86]<=8'b01101100;
LUT[87]<=8'b01101010;
66
LUT[88]<=8'b01101000;
LUT[89]<=8'b01100110;
LUT[90]<=8'b01100100;
LUT[91]<=8'b01100010;
LUT[92]<=8'b01100000;
LUT[93]<=8'b01011110;
LUT[94]<=8'b01011100;
LUT[95]<=8'b01011010;
LUT[96]<=8'b01011000;
LUT[97]<=8'b01010101;
LUT[98]<=8'b01010011;
LUT[99]<=8'b01010001;
LUT[100]<=8'b01001110;
LUT[101]<=8'b01001100;
LUT[102]<=8'b01001001;
LUT[103]<=8'b01000111;
LUT[104]<=8'b01000100;
LUT[105]<=8'b01000001;
LUT[106]<=8'b00111111;
LUT[107]<=8'b00111100;
LUT[108]<=8'b00111001;
LUT[109]<=8'b00110110;
LUT[110]<=8'b00110011;
LUT[111]<=8'b00110000;
LUT[112]<=8'b00101110;
LUT[113]<=8'b00101011;
LUT[114]<=8'b00101000;
LUT[115]<=8'b00100101;
LUT[116]<=8'b00100010;
LUT[117]<=8'b00011111;
LUT[118]<=8'b00011100;
LUT[119]<=8'b00011000;
LUT[120]<=8'b00010101;
LUT[121]<=8'b00010010;
LUT[122]<=8'b00001111;
LUT[123]<=8'b00001100;
67
LUT[124]<=8'b00001001;
LUT[125]<=8'b00000110;
LUT[126]<=8'b00000011;
LUT[127]<=8'b00000000;
LUT[128]<=8'b11111100;
LUT[129]<=8'b11111001;
LUT[130]<=8'b11110110;
LUT[131]<=8'b11110011;
LUT[132]<=8'b11110000;
LUT[133]<=8'b11101101;
LUT[134]<=8'b11101010;
LUT[135]<=8'b11100111;
LUT[136]<=8'b11100011;
LUT[137]<=8'b11100000;
LUT[138]<=8'b11011101;
LUT[139]<=8'b11011010;
LUT[140]<=8'b11010111;
LUT[141]<=8'b11010100;
LUT[142]<=8'b11010001;
LUT[143]<=8'b11001111;
LUT[144]<=8'b11001100;
LUT[145]<=8'b11001001;
LUT[146]<=8'b11000110;
LUT[147]<=8'b11000011;
LUT[148]<=8'b11000000;
LUT[149]<=8'b10111110;
LUT[150]<=8'b10111011;
LUT[151]<=8'b10111000;
LUT[152]<=8'b10110110;
LUT[153]<=8'b10110011;
LUT[154]<=8'b10110001;
LUT[155]<=8'b10101110;
LUT[156]<=8'b10101100;
LUT[157]<=8'b10101010;
LUT[158]<=8'b10100111;
LUT[159]<=8'b10100101;
68
LUT[160]<=8'b10100011;
LUT[161]<=8'b10100001;
LUT[162]<=8'b10011111;
LUT[163]<=8'b10011101;
LUT[164]<=8'b10011011;
LUT[165]<=8'b10011001;
LUT[166]<=8'b10010111;
LUT[167]<=8'b10010101;
LUT[168]<=8'b10010011;
LUT[169]<=8'b10010010;
LUT[170]<=8'b10010000;
LUT[171]<=8'b10001111;
LUT[172]<=8'b10001101;
LUT[173]<=8'b10001100;
LUT[174]<=8'b10001010;
LUT[175]<=8'b10001001;
LUT[176]<=8'b10001000;
LUT[177]<=8'b10000111;
LUT[178]<=8'b10000110;
LUT[179]<=8'b10000101;
LUT[180]<=8'b10000100;
LUT[181]<=8'b10000011;
LUT[182]<=8'b10000011;
LUT[183]<=8'b10000010;
LUT[184]<=8'b10000001;
LUT[185]<=8'b10000001;
LUT[186]<=8'b10000000;
LUT[187]<=8'b10000000;
LUT[188]<=8'b10000000;
LUT[189]<=8'b10000000;
LUT[190]<=8'b10000000;
LUT[191]<=8'b10000000;
LUT[192]<=8'b10000000;
LUT[193]<=8'b10000000;
LUT[194]<=8'b10000000;
LUT[195]<=8'b10000000;
69
LUT[196]<=8'b10000000;
LUT[197]<=8'b10000001;
LUT[198]<=8'b10000001;
LUT[199]<=8'b10000010;
LUT[200]<=8'b10000011;
LUT[201]<=8'b10000011;
LUT[202]<=8'b10000100;
LUT[203]<=8'b10000101;
LUT[204]<=8'b10000110;
LUT[205]<=8'b10000111;
LUT[206]<=8'b10001000;
LUT[207]<=8'b10001001;
LUT[208]<=8'b10001010;
LUT[209]<=8'b10001100;
LUT[210]<=8'b10001101;
LUT[211]<=8'b10001111;
LUT[212]<=8'b10010000;
LUT[213]<=8'b10010010;
LUT[214]<=8'b10010011;
LUT[215]<=8'b10010101;
LUT[216]<=8'b10010111;
LUT[217]<=8'b10011001;
LUT[218]<=8'b10011011;
LUT[219]<=8'b10011101;
LUT[220]<=8'b10011111;
LUT[221]<=8'b10100001;
LUT[222]<=8'b10100011;
LUT[223]<=8'b10100101;
LUT[224]<=8'b10100111;
LUT[225]<=8'b10101010;
LUT[226]<=8'b10101100;
LUT[227]<=8'b10101110;
LUT[228]<=8'b10110001;
LUT[229]<=8'b10110011;
LUT[230]<=8'b10110110;
LUT[231]<=8'b10111000;
70
LUT[232]<=8'b10111011;
LUT[233]<=8'b10111110;
LUT[234]<=8'b11000000;
LUT[235]<=8'b11000011;
LUT[236]<=8'b11000110;
LUT[237]<=8'b11001001;
LUT[238]<=8'b11001100;
LUT[239]<=8'b11001111;
LUT[240]<=8'b11010001;
LUT[241]<=8'b11010100;
LUT[242]<=8'b11010111;
LUT[243]<=8'b11011010;
LUT[244]<=8'b11011101;
LUT[245]<=8'b11100000;
LUT[246]<=8'b11100011;
LUT[247]<=8'b11100111;
LUT[248]<=8'b11101010;
LUT[249]<=8'b11101101;
LUT[250]<=8'b11110000;
LUT[251]<=8'b11110011;
LUT[252]<=8'b11110110;
LUT[253]<=8'b11111001;
LUT[254]<=8'b11111100;
LUT[255]<=8'b11111111;
LUT_out <= 8'd0;
end
else
LUT_out <= LUT[address];
end
endmodule
71
Verilog Module for Phase Truncate

module Phase_truncate(clk, reset, q2, pt, tbit);
input clk, reset;

input [0:11] q2;
output [0:7] pt;

output [0:3] tbit;
reg [0:7] pt;
reg [0:3] tbit;
always @(posedge clk)

if (reset == 1'b1)
begin
pt <= 8'b0;
tbit<= 4'b0;
end
else
begin
pt <= q2[0:7];
tbit <= q2[8:11];
end
endmodule
Verilog Module for Dither Generator

module dither(clk, reset, x);
input clk, reset;

output [0:2] x;
reg [0:2] x;
always @(posedge clk)
72
begin
if (reset==1)
x <= 0;
else
x <= {x[1:2], !x[0]};
end
endmodule
Verilog Module for Register

module REG(clk, reset, d, q);
input clk, reset;

input [0:11] d;
output [0:11] q;
reg [0:11] q;
always @ (posedge clk)

begin
if (reset == 1'b1)
begin
q <= 12'd0;
end
else
begin
q <= d;
end
end
endmodule
Verilog Module for TOP LEVEL

module top_level(clk, reset, out1);
73
input clk, reset;

output [0:11] out1;
reg [0:11] out1;

reg [0:11] d1;
wire clk, reset;

wire [0:11] q1, q2, sum1;
wire [0:11] out;
wire [0:7] pt, sum5;
wire [0:2] x;
REG reg1(clk, reset, d1, q1);

ADDER add(q1, q2, sum1);
REG reg2(clk, reset, sum1, q2);
Phase_truncate ptr(clk,reset, q2, pt);
digit_en, seven_seg_output);
dither l(clk, reset, x);
add2 add3(pt, x, sum5);
lutnew1 lut1(clk, reset, sum5, out);
always @ (posedge clk or posedge reset)
begin
if(reset ==1)
d1 <= 12'b000011111101;
else
out1 <= out;
end
endmodule
74
PERMISSION TO COPY
In presenting this thesis in partial fulfillment of the requirements for a master’s

degree at Texas Tech University or Texas Tech University Health Sciences Center, I
agree that the Library and my major department shall make it freely available for research
purposes. Permission to copy this thesis for scholarly purposes may be granted by the
Director of the Library or my major professor. It is understood that any copying or
publication of this thesis for financial gain shall not be allowed without my further
written permission and that any user may be liable for copyright infringement.
Agree (Permission is granted.)
__________________________________ ___________________
Student Signature Date
Disagree (Permission is not granted.)
_______Shashikant Shrimali__________ ____03/29/07_____

Student Signature Date

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DIRECT DIGITAL FREQUENCY SYNTHESIZER

SHASHIKANT SHRIMALI, B.E.

Submitted to the Graduate Faculty

4.3 Cadence simulation of DDFS with Clock Jitter………...……………36

A frequency synthesizer is an electronic system for generating any of a range of

the DDFS ranges from instrumentation to modern communication systems, which

2.1 DDFS function blocks and signal flow diagrams [2]……………………...5

4.3 LUT output for

4.4 PA output for M = 102…………………………………………………..23

4.5 LUT output for

4.6 RTL schematic of DDFS………………………………………………...24

4.13 ModelSim simulation

4.14 PSD plot

4.15 ModelSim simulation

4.16 PSD plot

4.17 DDFS with phase truncation……………………………………………..31

4.21 PSD plot with PT………………………………………………………...33

4.29 Ideal Clock

4.30 Ideal Clock, Jittered Clock and Random Number……………………….39

4.36 Output spectrum of DDFS with ideal clock

4.37 Output spectrum with clock jitter

4.38 Comparison of output spectrums

4.39 Comparison of output spectrums

4.42 DDFS Output Spectrum with LUT having 8-bit samples………………..44

1.1 DDFS – A Brief History

1.2 DDFS – An Overview

1.3 Aim of Thesis

1.4 Thesis Organization

2.1 Architecture of Sine Output DDFS

As shown in Figure 2.1, the main components of a DDFS are a phase

2.2 Frequency Tuning Equation

Figure 2.2: Sine magnitude and phase representation [19]

phase value sequence, where, Δt is the minimum amount of change,

Δp , is an integer, therefore the frequency resolution is found by setting Δp = 1,

A DDFS works on a point (memory location)-skipping technique (and a constant

As the output frequency

2.3 Building Blocks of DDFS

2.3.1 Phase Accumulator

Figure 2.3: Digital phase wheel [4]

2.3.2 Phase-to-Amplitude Converter (ROM/ LUT)

where, GCD(Δp,2n ) represents the greatest common divisor of Δp and 2n

2.3.3 Digital-to-Analog Converter and Filter

3.1 Sampled Output of DDFS [4]

fundamental output frequency f out is 80 MHz [4].

Figure 3.1: Spectral analysis of sampled output [4]

In typical DDFS applications, a lowpass filter is utilized to suppress the effects of

due to sin( x ) in a DDFS system is –3.92 dB over its DC to Nyquist bandwidth. A

3.2 Spectral Purity Considerations

3.3 Spurious Free Dynamic Range

3.4 DDFS with Phase Truncation and Spurious Performance

3.5 DDFS with Dither and its effect on SFDR

4.1 High-level simulation of DDFS with MATLAB-Simulink

Figure 4.1: MATLAB-Simulink model of DDS

Figure 4.2: PA output for M = 51

Figure 4.3: LUT output for f out = 10 MHz

If the output frequency to be generated is increased to 20 MHz with the same

Figure 4.4: PA output for M = 102

Figure 4.5: LUT output for f out = 20 MHz

4.2 RTL level simulation of DDFS using ModelSim

4.2.1 Simple DDFS Simulation using ModelSim

Figure 4.6: RTL schematic of DDFS

Figure 4.7 Verilog code for 8-bit Register