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In this tutorial, you will learn to create a design module from VHDL code. With
Xilinx ISE, you can easily create modules from VHDL code using the ISE Text Editor
tool. The VHDL code may then be connected to your top-level VHDL design through
instantiation and compiled with the rest of the design.
In this tutorial, you will author a new VHDL module. This program converts a
hexadecimal number to a 7-segment LED display format. If necessary, review the steps
in Project 1 to create a new project, generate a test bench, and perform a functional
simulation.
1. Select Project → New Source. A dialog box opens in which you specify the type of
source you want to create.
4. Click Next.
The hex2led component has a 4-bit input port named HEX and a 7-bit output port
named LED.
2. Click in the Direction field, set the direction to in, and select the Bus field.
3. In the MSB field enter 3, and in the LSB field enter 0. Refer to Figure 1. Repeat the
previous steps for the LED[6:0] output bus. Be sure that the direction is set to out.
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Tutorial: Using Xilinx ISE 9.1i for VHDL Based Design
4. Click Next to complete the Wizard session. A description of the module displays.
5. Click Finish to open the empty VHDL file in the ISE Text Editor. See Figure 2.
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Tutorial: Using Xilinx ISE 9.1i for VHDL Based Design
In the ISE Text Editor, the ports are already declared in the VHDL file, and some
of the basic file structure is already in place. Keywords are displayed in blue, data types
in red, comments in green, and values in black. This color-coding enhances readability
and recognition of typographical errors.
Note: You can add your own templates to the Language Templates for components or
constructs you use often.
To invoke the Language Templates and select the template for this tutorial:
2. To expand the view of any of these sections, click the (+) next to the topic. Click any
of the listed templates to view the template contents in the right-hand pane.
3. Under the VHDL hierarchy, expand the Synthesis Constructs, Coding Examples, Misc
hierarchy and select the template called 7-Segment Display Hex Conversion. The
contents display in the right-hand pane. Refer to Figure 3.
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Tutorial: Using Xilinx ISE 9.1i for VHDL Based Design
You will now use the Use in file method for adding templates to your VHDL file.
A copy and paste function is also available from the Language Templates Edit Menu and
the right click menu.
To add the template to your VHDL file using the Use in file method:
1. In the Language Templates, right click the 7-Segment Display Hex Conversion name
and select Use in file. This will add the template into the hex2led.vhd file. Before you
add the template to the hex2led.vhd, move the cursor under the architecture begin
statement.
2. Close the Language Templates window. You now have complete and functional
VHDL code.
4. Select hex2led in the Sources window and double-click Check Syntax in the Processes
window. Or Implement Design, Synthesize-XST, Check Syntax in Process window.
5. To create a schematic symbol, click (+) under Design Utilities and double click on
Create Schematic Symbol. The schematic symbol of hex2led will appear under Symbols
in a Schematic Editor window in the same project.
6. To simulate, open new Test Bench Waveform file and select hex2led as a source code.
Reference: ISE In-Depth Tutorial, www.xilinx.com
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