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Published in: IEEE Micro, Vol. 16, No. 5, October 1996, pp. 50-52

Analog non-linear function synthesis

Olivier Landolt CSEM Centre Suisse d'Electronique et de Microtechnique SA Jaquet-Droz 7 2007 Neuchâtel Switzerland

INTRODUCTION

Networks of resistors have been identified as interesting devices for analog computation. Since the analytical model of a network of constant resistors is a set of linear equations, such a circuit can be used to solve a large number of linear equations concurrently. Whenever such a resistive embodiment of a computational problem can be found, the resulting circuit is usually very simple, fast and dense compared to CPU-based hardware. Particular problems solved by such networks include simulation of electromagnetic fields [1], linear image filtering [2], regularization for image processing [3], and D/A conversion [4]. Networks of resistors are especially attractive for CMOS integrated circuits, since it has been shown that a circuit obtained by replacing every resistor by a single MOS transistor has exactly the same branch currents as its resistive counterpart [5]. In the following, a resistive network combining constant and controlled resistors is described, as well as its implementation with MOS transistors. The purpose of this circuit is to synthesize non-linear functions of possibly several variables. The circuit can be considered as an implementation of fuzzy rules, since its constituents can be identified as membership functions, fuzzy logic gates and center-of-gravity "defuzzification" circuits. Alternatively, the circuit can also be considered as a look-up table with interpolation, since fuzzy rules and look-up table entries are actually about the same thing. With a single generic circuit structure, a number of different non- linear functions can be synthesized by customizing geometrical parameters or connection patterns.

_{C}_{I}_{R}_{C}_{U}_{I}_{T} ARCHITECTURE

A circuit implementation of a function of N variables is made of N groups of membership function

circuits (MFC) and an array of rule cells (Figure 1). One of the input signals is applied to each group of MFC. Every MFC evaluates the membership function of a fuzzy set, and applies the

resulting activation grade to a part of the rule cell array. Every rule cell is connected to a distinct combination of MFC (one in each group). A fuzzy logic AND gate combines the activations applied by these MFC into a weight. A constant parameter stored in every rule cell defines the output value for the specific combination of input states defined by the peaks of the membership functions. Every cell delivers an additive contribution to the output, the magnitude of which is the product between the stored constant and the weight. As a whole, the circuit has the function of a look-up table with interpolation resulting from the continuity of the membership functions. The MFC groups are similar in purpose to the address decoders in a digital memory, in that they relate combinations of input signals to physical locations in an array of storage cells. However, unlike a digital decoder, the graded nature of the membership functions enables the simultaneous activation of multiple rule cells. Thereby, the output signal is not determined by the content of just a single memory cell, but by a weighted sum of several contributions. The elementary functional unit in this circuit is the rule cell. This element and the way it interacts with other cells is described in the following. MFC implementation will not be discussed.

A description of one possible MFC with a bell-shaped characteristic can be found in [6].

2

RULE CELL

For conceptual simplicity, the rule circuit will be described as a combination of linear, electrically controlled resistors (Figure 2a). Instead of resistors, the real circuit (Figure 2b) is actually made of MOS transistors, but the description is valid because the two circuits are functionally equivalent, as long as the transistors operate in weak inversion. This can easily be seen with help of the concepts of pseudo-voltage and pseudo-conductance [5]. A rule cell with N inputs is made of N linear resistors connected in series. The conductance of each resistor is controlled by the activation signal of an MFC, and ranges from zero to some maximum value g _{m}_{a}_{x} (the higher the activation, the higher the conductance). The equivalent conductance G _{i} of the N resistors in series is given by

G

i

=

1

N

∑

j = 1

1

g ji

(1)

The relation in Equation (1) can be shown to be a suitable fuzzy logic AND operator. In particular, the total conductance G _{i} is zero if any of the individual conductances g _{j}_{i} is zero, G _{i} is maximum only if all the g _{j}_{i} are equal to g _{m}_{a}_{x} , and G _{i} depends monotonically on any of the g _{j}_{i} . The individual g _{j}_{i} can thus be considered as the inputs and G _{i} as the output of a fuzzy logic AND gate. Therefore, the weight of the rule cell is proportional to the equivalent conductance G _{i} . One end of the resistor string is connected to a global power node, whereas the other end is maintained at ground potential. Power for the whole array is delivered by a single current source I _{0} . The current I _{i} flowing through a particular rule cell is given by

I

i

=

G i ⋅ I _{0}

∑

G

k

k

(2)

where the sum is calculated over the whole array of rule cells. A fraction A _{i} of this current (0≤A _{i} ≤1) flows onto a global output line, whereas the complement flows to ground. The fraction A _{i} is the actual look-up table entry stored in the rule cell, and is therefore generally different in every rule cell. By Kirchhoff's current law, the total current I _{o}_{u}_{t} flowing out of the rule cell array is

I

out

=

∑

i

AI

i

i

⋅=

∑ G

i

i

⋅ A

i

∑

i

G

i

⋅ I _{0}

(3)

This equation shows that the output current of the array is proportional to the center of gravity of the parameters A _{i} weighted by the conductances G _{i} , as expected from a fuzzy rule circuit. An interesting property of this rule circuit is that no DC bias current flows through inactive cells, which contributes to save power. Since only a few cells can be active simultaneously due to the operation principle of a look-up table, this circuit is inherently well suited for low power consumption.

_{C}_{U}_{R}_{R}_{E}_{N}_{T} SPLITTER

The transfer function of the circuit is determined by the ratios A _{i} of the current splitters. The two- transistor current splitter circuit shown in Figure 2b relies on device geometry to determine the ratio. It is a very simple circuit, but the dynamic range of A _{i} is restricted, and accurate control of the ratio can be problematic. These limitations can be overcome by using the more elaborate current splitter shown in Figure 3, which supports a digital representation of the ratio A _{i} . This circuit is a classical R/2R ladder network as used in many D/A converters. Its MOS transistor equivalent (not shown) can be obtained by replacing every resistor by a single transistor [7]. The

3

weight current I _{i} is applied at the input of the network. This current, divided by successive powers of two, flows in the successive stages of the network. Depending on the bits of the digital representation of A _{i} , each vertical resistor is connected either to ground, or to the output line. The transfer function of the circuit can thus be determined by customizing the connection pattern between every rule cell and the output line. By adding digital RAM or EPROM cells, the circuit can have a programmable instead of a hardwired transfer function. The overhead introduced by the presence of an R/2R network in every rule cell can be avoided by sharing a single R/2R network for the whole rule cell array. This is possible because this network computes a weighted sum of the contributions of the different bits in a rule cell, whereas the resulting current is in turn summed with the outputs of the other rule cells. It is easy to show analytically that flipping the summation order does not change the final result. The sum over the rule cell array can be computed separately for every bit, and a weighted sum of the results can be computed by a single R/2R network. Implementation details for this solution are available in [6].

PROTOTYPE CHIP

An integrated circuit based on the presented elements has been designed and tested in order to validate this function synthesis technique. A set of 80 rules with two inputs and five outputs, organized as an 8 by 10 array, is incorporated on the chip. The current splitter ratios are stored as digital hardwired coefficients with a total of 11 bits in every rule cell. The function of the chip is to generate periodic waveforms producing a specific display on an oscilloscope screen for demonstration purposes [6]. The chip has been fabricated in a 2µm CMOS technology with two metal layers and a single poly layer. The rule cell dimensions are 100µm by 70µm, whereas the chip core area including MFC, rule cell array and bias circuits is 1.3mm ^{2} . The chips works with a power supply of 1.8V, with a total power consumption of 850nW. Its step response time is about 400µs (90% of final level). Measurement of 5 different chips with the same parameter set stored in the rule cells showed a standard deviation of 2.6% between their transfer functions. The fluctuations are believed to be due mainly to local device mismatch, and not to process parameter variations from chip to chip.

APPLICABILITY

The presented circuit distinguishes from previous fuzzy rule circuits by its simplicity and its low transistor count. The regularity of its structure enables dense layout. If the layout topology matches the logical topology of the circuit, operation relies on local matching only, which ensures immunity against process parameter gradients on the die. The mirrorless connection of all cells to a single current source ensures an accurate distribution of the reference regardless of device matching. The absence of high impedance nodes, gain stages or feedback loops enables fast, stable and low power operation. The circuit can be used for function synthesis in applications with strong space or power constraints. Considered applications include microsensor and microactuator low level interfacing and management, in particular for implantable medical devices. Besides, the circuit is very suitable for the design of non-linear blocks in custom integrated circuits. In this case, its advantage resides in the straightforward design methodology whatever the target function, which contributes to reduce design costs.

REFERENCES

[1] |
F. Gardiol, Electromagnétisme, Traité d'Electricité vol. III, Editions Georgi, 1979 |

[2] |
C. Mead, Analog VLSI and Neural Systems, Addison Wesley, 1989 |

4

[3]

J. Hutchinson, C. Koch, J. Luo, C. Mead, "Computing motion using analog and binary resistive networks", Computer, March 1988, pp. 52-63

[4] J. Millman, Microelectronics: digital and analog circuits and systems, McGraw-Hill, 1979

[5] |
E. Vittoz, X. Arreguit, "Linear networks based on transistors", Electronics Letters, vol. 29, No 3, February 1993, pp. 297-298 |

[6] |
O. Landolt, "Low power analog fuzzy rule implementation based on a linear MOS transistor network", Proc. MicroNeuro '96, Lausanne, February 1996, pp. 86-93 |

[7] |
K. Bult, G. Geelen, "An inherently linear and MOST-only current division technique", IEEE Journal of Solid-State Circuits, vol. 27, No 12, December 1992, pp. 1730-1735 |

MFC group 1

input 1

rule cell array

output

input 3

MFC group 3

MFC group 2

input 2

Figure 1 Architecture of a circuit implementation of a function of three variables (input 1, 2 and 3). The interconnections between the MFC and the rule array are such that every cell is connected to a distinct combination of MFC. The connections of one particular rule cell are shown in bold as an example.

5

a)

b)

I 0

I 0

power

power

g

MFC 1

g

MFC 1

1i *

1i

g

MFC 2

g

MFC 2

2i *

2i

g

MFC 3

g

MFC 3

I i

3i *

3i

I i

current

bias

splitter

(1-A i )·I i

(1-A i )·I i

A i I i

output

A i I i

output

I out

I out

Figure 2 Schematic of a single rule cell (inside the dashed box) at a functional level (a) and transistor level (b). The current source I _{0} and the output line are common to all cells in an array. The cell in this example has three inputs, and is therefore suitable for implementing a function of three variables.

I

i

current splitter

R

R

R

2R

I

i /2

I i /4

I i /8

I i /16

output

10

1

1

2R

2R

2R

2R

Figure 3

Current splitter with a ratio encoded as a 4-bit digital word (binary code 1011 in this example). Adaptation of this circuit to other resolutions is straightforward.

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