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1. Which of the following is NOT a part of a typical embedded system?

A. Processor C. Power supply

B. Memory D. Hard disk

Ans: D

2. Indicate the INCORRECT statement of the following:

A. Standard outputs drive C. Tristating is a low

signals high or low impedance state
B. Tristated outputs drive the D. Open collector outputs drive
signals high, low or float. the signals low or float
Ans: C

3. A memory chip is labeled as ‰ !"#$%then indicate the INCORRECT

statement of the following

A. It has 512 KB storage C. Each memory location has a

locations of 8 bits each response time of 60
B. It has 512 KB storage nanoseconds
locations of 8 bytes each D. It has 524288 bytes of
storage locations
Ans: B

4. Indicate the INCORRECT statement of the following:

A. Masked ROMs are the C. EEPROMS are the fastest

cheapest type of permanent type of memory suitable for
memory storing programsand data
B. Flash is useful to store permanently
programs as well as data D. RAMs are very fast type of
permanently memory that best suitable
for reading/writing
temporarily

Ans: C

5. Indicate the INCORRECT statement regarding DMA

A. DMA is a software code C. DMA is a hardware circuitry

used for data transfer used for data transfer
between memory and I/O between memory and I/O
B. DMA stands for Direct D. DMA can either be level
Memory Access triggered or edge triggered

Ans: A
 6. With IRQ signal from an external interrupt device microprocessor
A. Temporarily stops current C. Resumes the interrupted
sequence of execution after execution after the
completing the current completion of ISR
instruction D. Do (A), (B) and (C) of the
B. Executes corresponding above in sequence
Interrupt Service Routine

Ans: D

.
7. The responsibilities of a typical Embedded systems software Engineer must include

A. Should understand the C. Should be able to read the

hardware in order to write hardware schematic and
correct software suggest corrections
B. Must be able to install the D. All of the abov
software on the hardware

Ans: D

8. Indicate the INCORRECT statement of the following

A. Microprocessor is a single C. Microcontroller is a single

chip microcomputer system chip microcomputer system
(MCS) (MCS)
B. Microprocessor is a single D. Embedded system is any
chip CPU computer system hidden
inside a product other than
a computer
Ans: A

9. A typical microcontroller consists of (select the most appropriate answer)

A. CPU C. CPU, Memory and I/O

B. CPU and MemoryC. subsystems
D. CPU, Memory, I/O
subsystems and
counters/timers
Ans: D

10.Which of the following is NOT an 8-bit microcontroller?

A. Intel 8051 C. Intel 8086

B. Atmel D. Microchip
89C51 PIC16XX
Ans: C
 11.Which of the following is NOT a feature of Intel 8051 microcontroller?

A. 128 bytes of on-chip RAM C. 2 timer/counters and 5

and 4 KB of on-chip ROM interrupt sources
B. RISC architecture D. 1 serial port and 32 I/O pins
Ans: B

12.Indicate the correct statement on I/O operations

A. I/O device sets a hardware C. When CPU reads/writes

handshake line when it is data port the I/O handshake
ready to transfer data line is reset
B. CPU checks I/O device D. (A), (B) and (C) of the
status by reading I/O above are correct
handshake line
Ans: D

13.The I/O transfer technique which involves highest hardware complexity and lowest
CPU overhead is

A. Programmed I/O C. DMA

B. Interrupt driven I/O D. None of the above
Ans: C

14.An interrupt is generated when

A. An I/O device finishes its C. An executing program
operation and wants to performs an incorrect
inform the CPU of the operation and raises an
completion exception
B. An executing program D. Any of (A), (B) and (C)
needs some service from above
the OS
Ans: D

15.In an instruction execution cycle CPU checks for the interrupt when

A. After execution of the C. Before executing the

current instruction instruction
B. After fetching the D. Never checks for the
instruction interrupt

Ans: A

16.Interrupt handling mechanism involves

A. Asserting INTR and INTA C. Executing ISR

signals D. All of the above
B. Saving and retrieving the
context
Ans: D
 17.The last instruction of every ISR must be

A. RETURN C. POP
B. PUSH D. RST
Ans: A

18.Divide error is

A. Hardware interrupt C. Exception software interrupt
B. Normal software interrupt D. None of the above
Ans: C

19.Power-failure interrupt is:

A. Maskable interrupt C. Periodic interrupt
B. Non-maskable interrupt D. Synchronous interrupt
Ans: B

20.The time taken by the system to respond to external interrupt is:
A. Interrupt latency C. Interrupt sequence
B. Interrupt priority D. Interrupt context
Ans: A

21.Identify the simplest software architecture of the following

A. Function-queue-scheduling C. Round-robin with interrupts
B. Real Time Operating D. Round-robin
Systems
Ans: D

22.Identify the most complex software architecture of the following

A. Function-queue-scheduling C. Round-robin
B. RTOS D. None of the above
Ans: B

23.Interrupts, shared data, priorities and deadlines are applicable to:
A. RTOS C. Round-robin
B. Function-queue-scheduling D. Round-robin with interrupts
E.
Ans: A

24.An Operating System is

A. An organized collection of C. An environment for
software extensions of execution of programs
hardware that control
routines for operating a
computer D. (A), (B) and (C) of the
B. One that manages above
computer system resources

Ans: D
 25.Which of the following features is NOT applicable to an embedded RTOS?
A. Program Interface C. File system manipulation
B. I/O operations D. All of the above
Ans: C

26.In a multi-user operating system the term protection refers to

A. The system is safe from C. Access to the system
weathering resource is controlled
B. Users need a password to D. Access is denied to external
login I/O devices

Ans: C

27.CPU executes OS kernel functions in

A. User mode C. Supervisor mode
B. Normal mode D. Abnormal mode
Ans: C

28.The switch-over from kernel space to user space is done by means of
A. A hardware interrupt C. A software trap
B. A Mutex D. A semaphore

Ans: C

29.The function of OS upper kernel is

A. File System Scheduler C. Memory protection
B. User process interface D. Multiplexing of Physical HW
Ans: A

30.The most appropriate tool when considering Embedded System Software
development is
A. Native Compiler C. Native Assembler
B. Cross-Compiler D. None of the above
Ans: B

31.Task scheduler in a multi-tasking OS

A. Supports communication C. Block running tasks
between different tasks D. Determines which task will
B. Performs necessary run next
bookkeeping to start a task
Ans: D

32.A real time system is characterized by

A. A fair access to all the C. Processing speed as a major
resources concern
B. Bug fixing is easy D. Ability to meet timing
constraints
Ans: D

33.In a drive by wire RT system the highest priority task is

A. Control system commands C. Control inputs
B. Sensor data acquisition D. Actuators
Ans: A
 34.The response time in an RT system is not equal to the execution time. This is due
to
A. Release time jitter C. Multi-tasking
B. Low processor speed D. Complexity of job
Ans: C

35.An RT system is ³feasible´, if

A. All the tasks are able to C. Tasks are scheduled with
meet deadlines equal priority
B. The system runs without D. Some tasks miss their
halt deadlines

Ans: A

36.Nuclear power plant control is a

A. Fast & hard RT system C. Slow & hard RT system
B. Fast & soft RT system D. Slow & soft RT system
Ans: C

37.Voice over packet switched networks is a

A. Fast & hard RT system C. Slow & hard RT system
B. Slow & soft RT system D. Fast & soft RT system

Ans: D

38.Blocking of a high priority task due to a shared resource while a low priority task is
running is
A. Priority sharing C. Priority inheritance
B. Priority conversion D. Priority inversion

Ans: D

39.Find the ODD one out

A. Windows XP C. Vx Works
B. Windows CE D. âC/OS-II

Ans: A

40.The correct sequence of Embedded Tool-Chain is

A. ROMCHIPŒ.HEXŒ.EXEŒ C. .HEXŒ.ASMŒ.OBJŒ.EXEŒ
.OBJŒ.ASM ROM CHIP
B. .EXEŒ.OBJŒ.ASMŒ.HEXŒ
ROM CHIP D. .ASMŒ.OBJŒ .EXEŒ.HEXŒ
ROM CHIP
Ans: D
 41.If you are servicing an 8051 based product which uses an 11.059 MHz crystal, you
might expect to find port 3 being used as

A. The high-order memory C. A general-purpose 8-bit

address bus connections parallel I/O port
B. A serial port using standard D. Any one of the above, since
baud rates the crystal frequency has no
effect on how the I/O port is
used
Ans: B

42.A microcontroller¶s serial port is full-duplex port. This means that

A. The microcontroller uses a C. The serial port can transmit
buffer to control the serial data at the same time it is
port. receiving data.
B. The serial port can be D. The serial port can either
receiving a second transmit or receive data but
transmission before the first not both simultaneously
one is read.
Ans: C

43.Clock stability is the highest for

A. RC oscillator C. IC clock oscillator
B. Ceramic resonator D. Crystal oscillator
Ans: D

44.Power saving in an embedded system can NOT be achieved with

A. Clever reduction of the clock structural units in the
rate processor by wait and stop
B. Optimizing the codes instructions
C. Clever enabling and D. Increasing clock rate
disabling of certain
Ans: D

45.Intel 8051 is a _______ type of processor

A. CISC C. RISC
B. DISC D. ASIC
Ans: A

46.Flash/EEPROM chips need _____ power supply

A. + 5 V C. + 9 V
B. + 3.3 V D. +12 V
Ans: D

47.A processor goes to STOP state when

A. Receives STOP instruction C. Operates in auto-shutdown
B. Clock input is disabled mode
D. Any of the above
Ans: D
 48.The functions of OS kernel include:
A. Task scheduler C. Inter-task communication
B. Task dispatcher D. All of the above
Ans: D

49.Task management in RTOS involve

A. Task creation C. Task deletion
B. Task scheduling D. All of the above
Ans: D

50.The main components of a typical embedded system include

A. Hardware C. Real Time Operating
System
B. Application software D. All of the above
Ans: D

51.Identify the feature which is not applicable to Digital Signal Processor
A. Low computational power C. Very Large Instruction Word
and high communication capability
capability D. Single Instruction Multiple
B. Multiply Add Accumulate Data
Units
Ans: A