Digital Integrated

Circuits
A Design Perspective

The Inverter
Introduction
q The inverter is the simplest of all digital logic gates

q However, building an understanding of its properties and operation is crucial for

the design and analysis of larger/ more complex logic gates.

q We will discuss: General properties of an inverter (and logic gates), and inverter
implementation issues in CMOS technology.
General Properties
q Small area is a desirable property for a digital logic gate
q Larger packing density
q Small parasitic capacitances
q Shorter interconnects
q Smaller chip area, hence higher number of devices per wafer (lower
cost)

q Fewer transistors for a logic gate usually results into smaller area.
Hence, minimum possible number of transistors for a given gate is
important.
The CMOS Inverter: A First Glance
V DD

V in V out

CL
CMOS Inverter - First-Order DC Analysis
Properties
1) High and low outputs = V DD and Ground.
Voltage swing= V DD. High Noise Margins.
2) Logic Levels are independent of device sizes
V DD V DD (ratioless logic)
3) In steady state, a path exists from O/P to VDD
or GND. Thus, low output impedance. Less
sensitive to noise.
Rp 4) Input resistance is extremly high, since MOS
gate draws no dc input current. Steady-state
input current ~ zero. An inverter can
theoretically drive infinite number of gates and
V out be functionally operational. This degrades the
V out transient response.
5) In steady-state, no direct path exists between
supply and ground rails. No static power
(ignoring leakage)
Rn

VOL = 0
VOH = VDD
V in = V DD V in = 0 VM = f(Rn, Rp)
Voltage Transfer
Characteristic
PMOS Load Lines

I DSp = − I DSn
VGSn = Vin ;VGSp = Vin − VDD
VDSn = Vout ;VDSp = Vout − VDD

IDp IDn IDn

Vin=0 Vin=0

V in=1.5 Vin=1.5

V DSp V DSp Vout

VGSp=-1

VGSp=-2.5
Vin = V DD +VGSp Vout = V DD +VDSp
IDn = - IDp
CMOS Inverter Load Characteristics
ID n
Vi n = 0 Vin = 2.5

PMOS Vin = 0.5 Vin = 2 NMOS

Vin = 1 Vin = 1.5

Vin = 1.5 Vi n = 1
Vi n = 1.5 Vin = 1
Vin = 2 Vi n = 0.5

Vi n = 2.5 Vi n = 0

Vout

For a dc operating point to be valid, the currents through NMOS and PMOS devices must be equal
(intersections) {Vin = 0, 0.5, 1, 1.5, 2, 2.5}

Operating points are located either at the high or low output levels. The Voltage Transfer Characteristics (VTC)
exhibit a very narrow transition zone (high gain during switching transient – a small change in the input voltage
results in a large output variation)
CMOS Inverter VTC (VDD=2.5V)

Vout
NMOS off
PMOS res Vout=Vin
2.5 NMOS sat
PMOS res
2

NMOS sat
1.5

PMOS sat
VM = switching
1

NMOS res threshold

PMOS sat NMOS res
0.5

PMOS off

0.5 1 1.5 2 2.5 Vin

Switching Threshold as a function of Transistor Ratio
Vin=Vout
PMOS and NMOS are saturated since V DS=VGS. Equate current through NMOS and PMOS.
1.8

1.7

1.6

1.5

1.4
V (V)

1.3
M

1.2

1.1

0.9

0.8 0 1
10 10
Wp/Wn
rVDD
VM ≈ VM=VDD/2 for comparable high and low noise margins. Thus, r=1.
1+ r
(W / L ) p = (W / L) n (VDSATn k n ) /(VDSATp k p )
' '

Increasing strength of NMOS (sizing it up), moves V M closer to GND. Vice versa for PMOS case.
Note: When designing CMOS circuits, it is advisable to balance the strengths of the transistors by
making PMOS wider than NMOS, to obtain large noise margins + symmetrical characteristics.
 Switching Threshold as a function of Transistor Ratio

Points

q VM is relatively insensitive to variations in the device ratio. Small variations of the

ratio do not disturb the VTC that much. Setting ratio of W p/W n to {3, 2.5, 2} yields
switching thresholds of {1.22V, 1.18V, 1.13V}

q VM shifts towards VDD or GND depending on strength of NMOS and PMOS.

Asymmetrical VTC is sometimes desirable in some designs.
Example in Page 187.
 Noise Margin - Determining VIH and VIL
In real life applications, output voltage of a gate may not have the nominal value, owing to load, high
switching speed..etc.
Hence, it is desirable to define an acceptable voltage range for logic “1” and logic “0”
Vout

VOH

VM

A simplified approach V
in
VOL
VIL VIH

These expressions make it clear that a high gain in the transition region is very desirable. For infinite gain:
NMH=VDD-VM, NML=VM
Logic gates have the property to restore the proper output logic values despite of non-ideal input
levels.
 Inverter Gain
0

-2

-4

-6

-8
gain

-10
NMOS and PMOS are in saturation. Equate
currents. Differentiate and solve for dVout/dVin
-12
The gain is almost purely determined by
technology parameters, especially the
-14
channel-length modulation.
-16

-18
0 0.5 1 1.5 2 2.5
V (V)
in
Gain as a function of VDD
2.5 0.2

2
0.15

1.5

(V)
V out (V)

0.1

out
V
1

0.05
0.5

Gain=-1
0
0 0 0.05 0.1 0.15 0.2
0 0.5 1 1.5 2 2.5
V (V)
V (V) in
in

The gain of the inverter actually increases with a reduction of VDD . At a VDD =0.5V, which is just 100mV
above V T of the transistors. So why can’t we operate all digital circuits at low V DD values?

• Yes, you get lower power consumption. But the delay of the gate drastically increases.
• DC characteristics become very sensitive to variations in device parameters such at V T once V DD and
intrinsic voltages become comparable.
• The signal swing is reduced. Although this is good for internal noise (crosstalk), this is bad for external
noise sources that do not scale.
 Impact of Process Variations
2.5

A CMOS inverter remains functional under a

wide range of operating conditions. We
showed that variations in device sizes have 2
minor impact on switching threshold. Good PMOS
Bad NMOS
This robust behavior, which ensures 1.5
functionality of the gate over a wide range of
Nominal

Vout(V)
conditions, has contributed in a big way to the
popularity of the static CMOS gate.
1
Good NMOS
Bad PMOS

0.5

0
0 0.5 1 1.5 2 2.5
Vin (V)
Propagation Delay
CMOS Inverter: Transient Response
V DD V DD

Rp tpHL = f(R on.C L)

= 0.69 R onCL

V out
V out
CL
CL
Rn

V in = 0 V in = V DD
(a) Low-to-high (b) High-to-low