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15
IN1A 29 M3 R61 C21
IN1A 5K C31 820µF 2200µF
17 L11 22µH
VL 23
+3.3V OUTPL
CONFIG 24 16 R41 C71
20 100nF
OUTPL C91 4Ω
PWRDN PWRDN 25 M2 1µF
14 PGND1P R51 C81 R62
PROTECTIONS C41 100nF
6 5K
R57 R59 FAULT 27 & 330pF
10K 10K LOGIC
26 12 VCC1N
TRI-STATE
C58 M5 C51 C61
100nF 11 1µF 100nF
R63
TH_WAR 28 OUTNL 5K C32 820µF
TH_WAR 10 L12 22µH
IN1B 30 OUTNL
IN1B R42 C72
M4 20 100nF
VDD 21 13 PGND1N C92 4Ω
1µF
VDD 22 R52 C82 R64
C42 100nF
6 5K
VSS 33 REGULATORS 330pF
7 VCC2P
VSS 34
M17 R65
C58 C53 C33 820µF
L13 22µH 5K
100nF 100nF VCCSIGN 8
35
OUTPR
C60 9 R43 C73
100nF VCCSIGN 20 100nF
36 OUTPR C93 4Ω
M15 1µF
IN2A 6 PGND2P R53 C83 R66
IN2A 31 C43 100nF
6 5K
330pF
GND-Reg
20 4 VCC2N
GND-Clean
19 M16 C52 C62
3 1µF 100nF
R67
OUTNR 5K C34 820µF
IN2B 2 L14 22µH
IN2B 32
OUTNR
R44 C74
GNDSUB M14 20 100nF
1 5 PGND2N C94 4Ω
1µF
R54 C84 R68
C44 100nF
6 5K
330pF
D03AU1474
REV. 2
November 2004 1/14
This is preliminary information on a new product now in development. Details are subject to change without notice.
STA518
18 NC Not connected
2/14
STA518
Note: 1. The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
2. To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) to implemented single BTL (MONO MODE) operation
for high current.
VCCSign 36 1 GND-SUB
VCCSign 35 2 OUT2B
VSS 34 3 OUT2B
VSS 33 4 VCC2B
IN2B 32 5 GND2B
IN2A 31 6 GND2A
IN1B 30 7 VCC2A
IN1A 29 8 OUT2A
TH_WAR 28 9 OUT2A
FAULT 27 10 OUT1B
TRI-STATE 26 11 OUT1B
PWRDN 25 12 VCC1B
CONFIG 24 13 GND1B
VL 23 14 GND1A
VDD 22 15 VCC1A
VDD 21 16 OUT1A
GND-Reg 20 17 OUT1A
GND-Clean 19 18 N.C.
D01AU1273
3/14
STA518
Table 7. Electrical Characteristcs refer to circuit in Fig.4 (VL = 3.3V; VCC = 30V; RL = 8Ω;
fsw = 384KHz; Tamb = 25°C unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
RdsON Power Pchannel/Nchannel Id=1A;T=25°C 200 270 mΩ
MOSFET RdsON
Idss Power Pchannel/Nchannel Vcc=35v;T=25°C 50 µA
leakage Idss
gN Power Pchannel RdsON Id=1A; T=25°C 95 %
Matching
gP Power Nchannel RdsON Id=1A; T=25°C 95 %
Matching
Dt_s Low current Dead Time (static) see test circuit no.4;T=25°C 10 20 ns
Dt_d High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω 50 ns
Id=3.0A; T=25°C; see fig. 6
td ON Turn-on delay time Resistive load; Vcc=30V;T=25°C 100 ns
td OFF Turn-off delay time Resistive load; Vcc=30V;T=25C 100 ns
tr Rise time Resistive load; as fig.4;T=25°C 25 ns
tf Fall time Resistive load; as fig. 4;T=25°C 25 ns
VCC Supply voltage operating voltage 10 36 V
VIN-H High level input voltage VL/2 V
+300mV
4/14
STA518
TABLE 7. (continued)
Table 8.
Notes: 1. The following table explains the VLOW, VHIGH variation with Ibias
VL VLow min VHigh max Unit
2.7 0.7 1.5 V
3.3 0.8 1.7 V
5 0.85 1.85 V
5/14
STA518
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
Duty cycle = 50% DTr DTf
M58
OUTxY R 8Ω
INxY
M57 +
-
V67 =
vdc = Vcc/2
gnd
D03AU1458
Figure 5.
+VCC
Q1 Q2
OUTxA OUTxB
INxA INxB
Q3 Q4
GND
D00AU1134
Figure 6.
+VCC
M58 Q1 Q2 M64
DTin(A) DTout(B) DTin(B)
OUTA Rload=8Ω OUTB
INA INB
L67 22µ L68 22µ
Iout=4.5A Iout=4.5A
M57 Q3 C69 C70 Q4 M63
470nF C71 470nF 470nF
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure D03AU1517
6/14
STA518
3 TECHNICAL INFO:
The STA518 is a dual channel H-Bridge that is able to deliver 50W per channel (@ THD=10% RL = 8Ω,
VCC = 29V) of audio output power in high efficiency.
The STA518 converts both DDX and binary-controlled PWM signals into audio power at the load. It includes a
logic interface , integrated bridge drivers, high efficiency MOSFET outputs and thermal and short circuit protec-
tion circuitry.
In DDX mode, two logic level signals per channel are used to control high-speed MOSFET switches to connect
the speaker load to the input supply or to ground in a Bridge configuration, according to the damped ternary
Modulation operation.
In Binary Mode operation , both Full Bridge and Half Bridge Modes are supported. The STA518 includes over-
current and thermal protection as well as an under-voltage
Lockout with automatic recovery. A thermal warning status is also provided.
INL[1:2] OUTPL
INR[1:2] Left
Logic I/F
VL
and Decode H-Bridge
PWRDN OUTNL
TRI-STATE
RightB
Regulators OUTNR
‰-Bridge
7/14
STA518
– 1) SHUTDOWN mode: with FAULT (pull-up resistor) and TRI-STATE pins independent, an activated
fault will disable the device, signaling low at the FAULT output.
The device may subsequently be reset to normal operation by toggling the TRI-STATE pin from
High to Low to High using an external logic signal.
– 2) AUTOMATIC recovery mode: This is shown in the Audio Application Circuit of Quad single End-
ed). The FAULT and TRI-STATE pins are shorted together and connected to a time constant circuit
comprising R59 and C58.
An activated FAULT will force a reset on the TRI-STATE pin causing normal operation to resume fol-
lowing a delay determined by the time constant of the circuit.
If the fault condition is still present , the circuit operation will continue repeating until the fault condition
is removed .
An increase in the time constant of the circuit will produce a longer recovery interval. Care must be
taken in the overall system design as not to exceed the protection thesholds under normal operation.
8/14
STA518
Figure 9. Typical Stereo Full Bridge Configuration to Obtain 50+50W @ THD = 10%, RL = 8Ω, VCC =29V
VCC1A +VCC
15
IN1A 29 M3 C30 C55
IN1A 1µF 1000µF
17 L18 22µH
VL 23
+3.3V OUT1A
CONFIG 24 16 C20
100nF
OUT1A
PWRDN PWRDN 25 M2 C52
14 GND1A 330pF R98 C99
PROTECTIONS 6 100nF
R57 R59 FAULT 27 & C23 8Ω
10K 10K LOGIC
26 12 VCC1B 470nF
R63 R100 C101
TRI-STATE
C58 M5 C31 20 6 100nF
100nF 11 1µF
C21
TH_WAR 28 OUT1B 100nF
TH_WAR 10
IN1B 30 OUT1B L19 22µH
IN1B
M4
VDD 21 13 GND1B
VDD 22
VSS 33 REGULATORS
7 VCC2A
VSS 34
M17 C32
C58 C53 1µF
100nF 100nF VCCSIGN 8 L113 22µH
35
OUT2A
C60 9 C110
100nF VCCSIGN 100nF
36 OUT2A
M15 C109
IN2A 6 GND2A 330pF R103 C107
IN2A 31 6 100nF
GND-Reg C108 8Ω
20 4 VCC2B 470nF
R104 R102
GND-Clean C106
C33 20 6
19 M16 100nF
3 1µF
C111
OUT2B 100nF
IN2B 2
IN2B 32
OUT2B L112 22µH
GNDSUB M14
1 5 GND2B
D00AU1148B
Figure 10. Typical Single BTL Configuration to Obtain 70W @ THD 10%, RL = 8Ω, VCC = 34V (note 1))
VL
+3.3V 23 18 N.C.
100nF 22µH
GND-Clean 17
19 OUT1A
16 100nF
GND-Reg OUT1A FILM
20
10K 100nF 11
OUT1B 22Ω 6.2 100nF
X7R VDD 10 X7R
1/2W 1/2W
21 OUT1B
VDD 470nF 8Ω
22 OUT2A FILM
CONFIG 9 6.2
24 OUT2A 330pF 100nF
1/2W
8 X7R
TH_WAR
TH_WAR 28 OUT2B 100nF
3 FILM
PWRDN OUT2B
nPWRDN 25 2
22µH
10K FAULT
27 VCC1A
15 32V
26
TRI-STATE 1µF 2200µF
100nF X7R 63V
IN1A VCC1B
29 12
IN1B
IN1A 30
IN2A VCC2A
31 7 32V
IN2B
IN1B 32 1µF
X7R
VSS VCC2B
33 4
VSS
34 GND1A
100nF 14
X7R VCCSIGN GND1B
35 13
Note: 1. "A PWM modulator as driver is needed . In particular, this result is performed using the STA308+STA518+STA50X demo board".
Peak Power for t ≤1sec
9/14
STA518
4 THERMAL INFORMATION:
The power dissipated within the device depends primarly on the supply voltage, load impedance and output
modulation level. The PSSO36 Package of the STA518 includes an exposed thermal slug on the top of the
device to provide a direct thermal path from the IC to the heatsink. For the Quad single ended application the
Dissipated Power vs Ouptut Power is shown in fig.11
Considering that for the STA518 the Thermal resistance Junction to slug is 1.5°C/W and the extimated
Thermal resistance due to the grease placed between slug and heat sink is 2.3°C/W ( the use of thermal
pads for this package is not recommended), the suitable Heat Sink Rth to be used can be drawn from the
following graph fig 12, where is shown the Derating Power vs.Tambient for different heatsinkers.
5 CHARACTERIZATION CURVES
5.1 The following characterization are obtained using the quad single ended configuration (fig.2)
with STA308A controller
Figure 11. Power Dissipation vs Output Power Figure 13. THD+N vs Output Power
Pd (W) 16 THD(%) 10
14 Vcc = 26V
5
Vcc=30V
12 Rl = 4 ohm
Rl=4ohm
F =1Kz F = 1KHz
10 2
Single Ended
8 1
6
0.5
4
2
0.2
0
0 4 8 12 16 20 24 0.1
100m 200m 500m 1 2 5 10 20 30
Pout(W)
4 x Pout (W)
Figure 12. Power Derating Curve Figure 14. Output Power vs Supply Voltage
Pout(W)
Pd(W) 30
25
27.5
1 1)Infinite Rl=4 ohm
25
20 2) 1.5 C/W
22.5
F=1KHz
3 2 3) 3 C/W Single Ended
20
4 4) 4.5 C/W
15 17.5
5) 6 C/W
15
THD=10%
10 5 12.5
10
THD=1%
5 7.5
2.5
0 20 40 60 80 100 120 140 160 +10 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30
Tambient(C) Vdc
10/14
STA518
Figure 15. THD vs Frequency Figure 18. Power Dissipation vs Output Power
Pd (W)
12
THD(%)
1
Vcc=29V
10
Rl=8ohm
0.5
8 F=1KHz
6
0.2
Rl=4 ohm 4
0.1
Pout=1W
2
Single Ended
0.05
0
0 10 20 30 40 50
0.02 2 X Pout (W)
0.01
20 50 100 200 500 1k 2k 5k 10k 20k
Freq(Hz) 5.3 The following characterizations are
obtained using the single BTL
configuration (fig. 10) with STA308A
5.2 The following characterizations are
controller
obtained using the stereo full bridge
configuration (fig. 9) with STA308A Figure 19. THD+N vs Output Power
controller
THD(%)
10
Figure 16. Output Power vs Supply Voltage 5
Vcc=34V
2
Po(W) 90 Rl=8ohm
1
80 F=1KHz
0.5
Rl=8ohm Single BTL
70
F=1KHz 0.2
60
0.1
THD=10%
50 0.05
Stereo Full
BTL
40
0.02
30 0.01
Single
Parallel BTL
THD=1% 100m 200m 500m 1 2 5 10 20 50 80
20
Pout(W)
10
0
+10 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 +32 +34 +36
Vsupply(V)
2 Vcc=29V
Rl=8ohm
1
F=1KHz
0.5 Double BTL
0.2
0.1
0.05
0.02
0.01
100m 200m 500m 1 2 5 10 20 60
Pout(W)
11/14
STA518
Figure 20. PSSO36 (Slug Up) Mechanical Data & Package Dimensions
mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
OUTLINE AND
A 2.15 2.47 0.084 0.097
A2 2.15 2.40 0.084 0.094 MECHANICAL DATA
a1 0 0.075 0 0.003
b 0.18 0.36 0.007 0.014
c 0.23 0.32 0.009 0.012
D (1) 10.10 10.50 0.398 0.413
E (1) 7.4 7.6 0.291 0.299
e 0.50 0.020
e3 8.50 0.035
F 2.3 0.090
G 0.10 0.004
G1 0.06 0.002
H 10.10 10.50 0.398 0.413
h 0.40 0.016
L 0.55 0.85 0.022 0.033
M 4.3 0.169
N 10˚ (max)
O 1.2 0.047
Q 0.8 0.031
S 2.9 0.114
T 3.65 0.144
U 1.0 0.039
X 4.10 4.70 0.161 0.185
Y 6.50 7.10 0.256 0.279
(1) “D and E” do not include mold flash or protusions. PowerSSO-36
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads. (slug-up)
(3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm
per side
7618147 A
12/14
STA518
13/14
STA518
nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
14/14
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