Chapter 11

CONCLUSIONS

In this book, design and integration issues of broad band VCO and PLL
frequency synthesizer in CMOS technology are investigated. A fully integrated
radio solution requires concurrent design ofthe transceiver and synthesizer with
particular attention paid to frequency planning in order to ease implementation.
The full integration of a broadband VCO requires attention at the transceiver
architecture and frequency planning, synthesizer architecture, and technology
aspects. Summary. of conclusions and contributions exploring the above issues
are listed as follows:

• An analytical model is developed to investigate the noise properties of

closed-loop PLL. The closed-loop PLL noise is an important factor of the to-
tal system performance in modem digital communications which use phase
modulation, such as QPSK and QAM. The PLL noise model includes noise
contributions from the blocks forming a PLL as well as the VCO. A SPICE
implementation of the model is also compared with measured results. The
models allow optimization of closed-loop PLL noise.

• Broadband VCO design issues are explored. As an individual block, VCO

specifications include phase noise, tuning range and power consumption.
However, full integration of a VCO in a transceiver also demands manu-
facturability (robust design against process variation, temperature and sup-
plylbias variations) and tolerance to integrated environment disturbances
(substrate coupled noise, cross talk between signal lines, and supply line
bounces). Active circuit design for negative resistance generation is ex-
plored for broadband operation. The resonator design is also presented.

• An application of broad band PLL frequency synthesizers is designed and im-

plemented for a muW-band/standard (IEEE 802.11a1b/g) WLAN frequency
166 CMOS PLLs AND VCOs FOR 4G WIRELESS

synthesizer in O.18j1m CMOS. Phase noise trade-offs for PLL noise specifi-
cations are explored in this application. A loop filter architecture suited
for integrated environments is also developed. VCO interface between
prescaler and mixers require particular attention for isolation considera-
tions. A quadrature signal generation architecture is also developed. The
quadrature signal is generated by driving PPF with the VCO directly. Dual-
modulus prescaler design and integration issues are investigated.
• Design and development of 4GHz VCO in CMOS technology for use in
WLAN frequency synthesizer is presented. PMOS and complementary
CMOS active circuit topologies are evaluated for integration considerations.
PMOS active circuit topology exhibits better performance with accumula-
tion mode varactor.

• An auto calibration circuit for VCO tuning band selection is developed and
implemented. The auto calibration circuit eases the tuning range issue for
broadband operation.
• A fully integrated dual-mode frequency synthesizer for GSM and WCDMA
standards is developed as another application. A dual-band VCO is designed
to support the required frequency channels. This example explores hardware
sharing in PLL components by using integer-N/frac-tional-N architectures
for dual-band/standard operation.
• RF CMOS characterization issues are investigated. Microwave wafer mea-
surement and pad de-embedding techniques are developed. CM OS tech-
nologies are evaluated for RP design.
Other issues which require further study in the design and implementation
of fully integrated RP PLL frequency synthesizer in sub-micron CMOS tech-
nologies include:
• Amplitude control architecture and circuit techniques for broadband VCOs
are needed. VCO output amplitude varies over the tuning range due to
change of the resonator Q. Also, inductor metal sheet resistance varies due
to temperature and process variations. This results in variation of the Q for
the resonator since the loaded resonator Q is determined primarily by the
inductor Q.
• Flicker noise of the MOS devices under large signal condition require further
research and understanding for better VCO noise prediction.
• Fractional-N architectures for multi-standard operations should be investi-
gated.
• Further investigation of RP CMOS modeling issues at 10GHz and beyond
is needed.