ECE 565 – Shantanu Dutt

Register Organizations in HLS

Register Organizations for FUs in HLS
Disjoint register organization Shared register orgamization
(mainly non−commutative opers) (only commutative opers)
Mux Mux Mux Mux
FU FU
 Register Allocation in HLS
Use the commutative register organization
Lifetime of variable = [production time, finish time of target oper]
Use graph coloring to obtain mimimum # of registers
o1
+
o2(d1) pa=12 d1
C8 pseudo−alap
D m1 m2 (pa) = 13 ROM d2
G
i2(d1) i1 r3 r2 r1
Mux
C2 C4 C6 C7 mux3
C
+ x x + Mux Mux
pa=11 pa=9 pa=9 F pa=11 mux1 mux2
o3(d2)
m3 m4 X
B +
i1 E
C1 pa=7 C3 i3(d2) C5
+ x x en2 demux1
pa=10 pa=9 en1
A
X c3 c4 c5 c6 c3
Schedule for pipelined
execution:
+ c1 c2 c7 c8 c1
r3 r1
A B E r2
CC’s
r3 r1
variable lifetimes
C D
A B E
G
r3 F r2
C D
Variable Lifetime Conflict/Overlap Graph
A
F G
A second schedule:
o1
+
o2(d1) pa=12 d1
C8 pseudo−alap
D m1 m2 (pa) = 13 ROM d2
G
i2(d1) i1 r3 r2 r1
Mux
C2 C4 C6 C7 mux3
C
+ x x + Mux Mux
pa=11 pa=9 pa=9 F pa=11 mux1 mux2
o3(d2)
m3 m4 X
B +
E
i1 pa=7
C1 C3 i3(d2) C5
+ x x en2 demux1
pa=10 pa=9 en1
A
c3 c5 c6 c4 c3
Schedule 2 for pipelined X
execution:
+ c1 c7 c2 c8 c1
r3 r1
A B E r2
CC’s
r3 r1
C D A B A
L= 10 cc’s
E C D
G
r3 F r2 F
variable lifetimes G
Variable Lifetime Conflict/Overlap Graph
 Static Timing Analysis (STA)

Input: DAG with node and/or arc delays; Output: Critical path de-




lay, max-path delay of every node.
Forward Trace Process:


 

1. Let be the # of levels of from 0 to , w/ 0 corresponding to inputs

and to outputs.










2. For every input (level-0) node , ; /* is delay of ;









Inputs of level-0 nodes are all assumed to be available at time 0 */



3. For to do:









[1] For every level- node , its max-input-arrival time







;

#
$%

&



" !















[2] ; /* is the time when the output from

 


('






would be available (assuming no hardware constraints); */
End for;

)
)

*+
,-
*




*+
,-
*


.
.
4. for every output node ; /* is the

 








max-path delay through ; */

)
*+
,-
*

.
5. Critical path delay = max among all output nodes;


 Static Timing Analysis (STA) (Contd)
Backward Trace Process:

1. For each output node do






*+
,-
*



.
(a) ;

 








(b) Max del ptr(u) = , where is the level node s.t.

 




;


End for;






2. For down to do:


3. For every level- node u do

)

)



*+
,-
*



*+
,-
*



.
.
4.

 


' 
#
$


$

&



" !









*+
,-
*






*+
,-
*


.
.
5. ;

 
#
$%

' 
$

&



" !








*

,








*










*+
,-
*


.
.

6. ;

 











7. if ( ) then












Max del ptr(u) = , where is the level node s.t. ;

 




8. End for
9. End for

)
*+
,-





10. Tracing back through the ’s from the output node with


the largest output delay gives the actual critical path.