You are on page 1of 9

Ted Borys - CSI 404 4/19/2004 Page 10-1

Section 10 Digital Hardware Algorithms


z Arithmetic operations
„ Addition, subtraction, multiplication, division
z Data types
Computer Arithmetic „ Fixed-point binary
‹ Signed-magnitude representation
‹ Signed-2’s complement representation
„ Floating-point binary
„ Binary-coded decimal (BCD)
Slides with white background courtesy of Mano text for this class
1 2

Add / Subtract Signed-Magnitude Hardware

Forces zero to be positive


3 4

Description Flowchart
z AS Sign of A
z BS Sign of B
z AS & A Accumulator
z AVF Overflow bit for A + B
z E Output carry for parallel adder

5 6

© 2004 by Ted Borys. All rights reserved.


Ted Borys - CSI 404 4/19/2004 Page 10-2

Add / Sub Signed-2’s Complement Algorithm

7 8

Multiply Signed-Magnitude Hardware


z Series of successive shift and add operations
z 23 10111 Multiplicand
19 x 10011 Multiplier
10111
10111
00000
00000
10111 +
437 110110101 Product
9 10

Description Flowchart
z Q multiplier
z B multiplicand
z A 0
z SC number of bits in multiplier
z E overflow bit for A
z Do SC times
„ If low-order bit of Q is 1
‹A ←A+B
„ Shift right EAQ
z Product is in AQ 11 12

© 2004 by Ted Borys. All rights reserved.


Ted Borys - CSI 404 4/19/2004 Page 10-3

Example: 23 x 19 = 437 Multiply Signed-2’s Complement


z Booth algorithm
z QR multiplier
z Qn least significant bit of QR
z Qn+1 previous least significant bit of QR
z BR multiplicand
z AC 0
z SC number of bits in multiplier

13 14

Algorithm Hardware
z Do SC + 1 times
„ QnQn+1 = 10
‹ AC ← AC + BR + 1
„ QnQn+1 = 01
‹ AC ← AC + BR
„ Arithmetic shift right AC & QR
„ SC ← SC – 1

15 16

Flowchart Example: -9 x -13 = 117

17 18

© 2004 by Ted Borys. All rights reserved.


Ted Borys - CSI 404 4/19/2004 Page 10-4

Array Multiplier 2-bit by 2-bit Array Multiplier


z Combination circuit
z Product generated in one microoperation
z Requires large number of gates
z Became feasible after integrated circuits
developed
z Needed for j multiplier and k multiplicand bits
„ j x k AND gates
„ j – 1 k-bit adders to produce product of j + k bits

19 20

4-bit by 3-bit Array Multiplier Divide Fixed-Point Signed-Mag


z Series of successive compare, shift, and
subtract operations

21 22

Example: 448 ⁄ 17 = 26 r 6 Algorithm


Initially,
AQ dividend
B divisor

At end of operation,
Q quotient
A remainder
DVF divide overflow

23 24

© 2004 by Ted Borys. All rights reserved.


Ted Borys - CSI 404 4/19/2004 Page 10-5

Floating-Point Registers Biased Exponent


z Example
„ Real exponent range is -50 to +49
„ Add bias of 50 for new range of 0 to 99
„ Biased exponent is always a positive number
‹ Easier to deal with

Sign Mantissa Exponent


Signed-magnitude mantissa & biased exponent 25 26

Floating-Point Add / Subtract F-P Add / Subtract Flowchart


z Check for zeros
z Align the mantissas
AC ← AC + BR
z Add or subtract the mantissas or
z Normalize the result AC ← AC – BR

27 28

Floating-Point Multiply F-P Multiply Flowchart


z Check for zeros
z Add the exponents
z Multiply the mantissas
z Normalize the product

29 30

© 2004 by Ted Borys. All rights reserved.


Ted Borys - CSI 404 4/19/2004 Page 10-6

Floating-Point Division F-P Division Flowchart


z Check for zeros
z Initialize registers and evaluate the sign
z Align the dividend
z Subtract the exponents
z Divide the mantissas

31 32

33 34

Booth Multiplication Algorithm


z Zeros in multiplier require no addition
„ But shifting still required
z String of 1s in the multiplier from weight 2k
to 2m can be rewritten as 2k+1 – 2m
„ Example: 001110 [+14]
‹ String of 1s from 23 to 21: 24 – 21 = 16 – 2 = 14
‹ Multiplicand M: M x 14 = M x 24 – M x 21
‹ Product obtained by M 4 times to the left and
subtracting M shifted left once

35 36

© 2004 by Ted Borys. All rights reserved.


Ted Borys - CSI 404 4/19/2004 Page 10-7

BCD Adder Block Diagram BCD Adder


z Output can’t exceed 9 + 9 + 1 = 19
z If binary sum in BCD digit > 1001, add 0110
z Given
„ Output of binary adder is Z8Z4Z2Z1
„ Output carry K
„ BCD output carry C = K + Z8Z4 + Z8Z2

37 38

Examples BCD Subtraction


z 9 1001 9 1001 6 0110 z Subtract by adding 9s complement of
7 0111 9 1001 4 0100 subtrahend to minuend
16 1 0000 18 1 0010 10 1010 z First 9s complement algorithm
0110 0110 0110 „ Complement bits
0110 1000 1 0000 „ Add 1010 (decimal 10) and discard carry
z Second 9s complement algorithm
„ Add 0110 (decimal 6)
„ Complement bits

39 40

Examples Stage of Decimal Arithmetic Unit


z 0111 decimal 7 0111
1000 complement + 0110 add decimal 6
+1010 decimal 10 1101
1 0010 decimal 2 0010 complement

41 42

© 2004 by Ted Borys. All rights reserved.


Ted Borys - CSI 404 4/19/2004 Page 10-8

Decimal Arithmetic Microops Parallel Decimal Addition

43
Fast 44

Digit-Serial, Bit-Parallel Dec Add All Serial Decimal Addition

Slow 45
Very slow 46

Dec Arith Registers for Mult & Div Decimal Multiplication Flowchart
0456 0456
x 0123 0456
56088 + 0456
1368
0136 8 shift
0456
+ 0456
1048
0104 88 shift
+ 0456
0560
0056 088 shift
0005 6088 shift
47 48

© 2004 by Ted Borys. All rights reserved.


Ted Borys - CSI 404 4/19/2004 Page 10-9

Decimal Division Flowchart

49

© 2004 by Ted Borys. All rights reserved.