Design of Distributed Amplifiers in 130 nm

CMOS SOI Technology

Mehdi SI MOUSSA
simoussa@ieee.org
http://www.linkedin.com/in/simoussa
http://www.emic.ucl.ac.be/People/Presentation/SiMoussa.htm

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 Outline

Motivations & Challenges

Distributed amplification

Designed circuits

Performances vs. Temperature

Conclusions

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 Why SOI CMOS

Historical motivation: radiation hardness Gate

- small cross section for ionizing particles Source Drain
Present motivation: enhanced performance
- higher speed
- lower power
New design options: Buried oxide

- high resistivity substrates Silicon substrate)

Silicon substrate
- bondingAttosame
“exotic” substrates
power consumption:
(e.g. quartz) Speed > 15 % MOSFET
MOSFETtransistor
transistor on
on Bulk
SOI CMOS

- multiple-gate(double,
At sametriple,
speed:etc.) devices
Power consumption < 30 %

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Where SOI is being used?

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Where SOI is being used?

How about RF in SOI ???

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 Motivations

(International Technology Roadmap for Semiconductors, ITRS 2003)

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 Motivations

• Use of CMOS for full integration ( low cost ).

• UWB Networks require broadband circuits.

• High speed needed beyond 10 GHz.
• Increase of the cut-off frequencies in CMOS/SOI transistors.

350
[Crolles II Alliance:04]
CMOS Bulk
300 CMOS SOI
CMOS SOI DTMOS
F max (GHz)

250 [Intel:04] ST-M. - Floating-Body

[IBM:04] ST-M. - Body-Contact
200
[IMEC:04]
150 [ST-M.:04]
100
50 [ST-M.:04]

0
0 50 100 150 200 250 300
Lpoly (nm)
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 Challenges

• Quality of Passive structures, key to success: High-performance

passives on lossy silicon substrate.
• Performances vs. temperature.

Goal of this work:

investigate the capabilities of SOI CMOS process
for wideband applications

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 CMOS vs. SOI

CMOS Bulk & SOI Technology SOI Technology

- Low-cost and mature technology. - Reduced parasitic capacitances lead to
- Low-Voltage-Low-Power consumption. higher frequency devices.
- Mixed analog-digital circuits (one-chip). - Lower leakage current.
- High degree of integration. - High-resistivity SOI wafers Low losses.

MOSFET Bulk MOSFET SOI

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 Distributed Amplification (1)

• Wideband amplification is important for many systems: Ultra

Wide Band (UWB) transceivers, optical communication …

• Distributed Amplification would allow us to operate close to ft,

enhancing CMOS microwave potential.

Ld/2 Ld Ld Ld Ld/2

Termination Drain line

Z0

Vout

Lg/2 Lg Lg Lg/2
Vin
Gate line Z0
Termination

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 Distributed Amplification (2)

Question : How to reduce the parasitic elements effects ?

Solution : the input and output capacitances of the transistors are
combined with lumped inductors to form artificial transmission lines.

Birth of the Distributed Amplifier

Historical

invented by Percival in 1936

landmark paper by Ginzton et al. in 1948

Reappearance since about 1980 (GaAs technology)

Now: CMOS implementation

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 Distributed Amplification (3)

• Limited Gain- Bandwidth product in conventional circuit design.

• Placing devices in parallel manner gm but BW

•Cascading the active devices multiplicative gain + need of

interstage circuit matching networks.

• Distributed Amplification adds FET’s gain without combining their

input capacitance.

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 Distributed Amplification (4)

Characteristics : Flat frequency response from DC to several GHz.

Topology
Two artificial transmission lines (gate and drain lines) are coupled
through common-source transistor devices.

Relaxed gain-bandwidth trade-off:

Gain added up by active devices.

Bandwidth limited by loaded transmission lines.

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 Distributed Amplification (5)
Vdrain Drain Line
Zd
(4)
Output
(3)
Vgate
Zg
Input

(1) Gate Line (2)

Operating
•The forward wave (from (1) to (2)) on the gate line is amplified by each
transistor.
•Each transistor adds power in phase to signal at each tap point on the
drain line.
•The forward traveling wave on the gate line and the backward (to (3)) on
the drain line are absorbed by terminations matched to load
characteristic impedance of the gate and drain lines.

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 Design Issues

• FET’s Cgs increases with transistor size.

• Distributed Amplification adds FET’s gain without combining their
input capacitance.
• Absorbs input/output capacitance as part of the lumped elements of an
“Artificial Transmission Line”
• Uses line delay equalization to add signals constructively at the FET’s
drain.
•Passives require high Q to minimize losses.

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 Design methodology

STEP 1: Specifications

STEP 2 : Choose a topology

STEP 3 : Choose an active

device

STEP 4 : Power and noise No

figure matching conditions
Satisfied Yes
STEP 7 :
specifications Final layout
STEP 5 : Choose a bias circuit

End
STEP 6 : Basic circuit simulation
and optimization

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 Specifications
Reference Ft/Fmax (GHz) Topology Gain (dB) BW (GHz)

[Lui et al.:2003] 3 cascode stages,

70/58 7.3 0.1-22 GHz
CMOS bulk 180 nm Inductances

State-of-the art - CMOS technology - (2003)

• Gain : 7 dB.

• Bandwidth : 0.5 – 20 GHz .

• Number of transistors : 4.
(Most of the designed DAs use 4 transistors)

• Active elements: 130 nm SOI Floating Body transistors.

(ST Microelectronics)

• Passive elements : TFMS (Thin Film Micro Strip) line.

• Bias : use the voltage values which provide the maximum gm.

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 Transmission line
TFMS on 130 nm SOI CMOS Technology

W
ADVANTAGES
Alucap
1.78 µm

Electrical characteristics are Copper (M6) 0.9 µm
independent of substrate resistivity: 2.9 µm
 possible use of low or high Mulilayered-dielectric (oxide/nitride)
resistivity substrate
Copper (M1 + VIA1 + M2)
STI (oxide)
Buried Oxide
DRAWBACKS

Si Substrate

High impedance (narrow
conductor):
 high metallic losses

Reduction of metallic losses with
ALUCAP stacked on Cu-6

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 Common source distributed amplifier (1)

130 nm SOI CSDA

Transistors Floating Body

WT = 60 x 2
Fmax = 83 GHz
Gate line L = 400 µm
W= 4.5 µm Drain line
Drain line L = 600 µm
Output
W= 9 µm RF pad
Cg
Area (mm²) 0.5x1.5
Cd

Input
RF pad
Gate line Transistors

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 Common source distributed amplifier (2)
130 nm SOI CSDA
10
S21 (dB) 4.5±1.2 5

S21, S11 (dB)

S11/S22 (dB) <-7.9/ <-6.7 0 S21

BW (GHz) 0.4-30 -5 S11

-10
Area (mm²) 0.5x1.5
-15
NF (dB) 4.6 - 7.0 0 10 20 30 40
Vdd (V) 1.4 Frequency (GHz)

Pdc (mW) 66
10
5

NF, S22 (dB)

0 NF
Problems S22
-5
-10

Gain < 7 dB -15
0 10 20 30 40
Frequency (GHz)

No flat gain
 Miller effect

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 Cascode pair

• MOSFET : important Miller effect

Consequence : ripple on the gain
Lcg G2

Solution : cascode pair D2

G2 S
• Microstrip lines: high losses D22

Consequence : fast decrease of the gain Lsd
S2
.
Solution : cascode pair + additional lines
G1 D1
 Output impedance at drain D2 :
S1
Rds2  gm2 
ℜe(ZD2)= 1− Rds2Cds2 +ℜe(Zgs2)
1+ω2C2ds2R2ds2 Cgs2 
=
Negative resistance
Trade-off between loss compensation and stability

Aim: have a flatter gain !

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 Cascode distributed amplifier (1)

4 stages, cascode

Drain line loss compensation RF pad
Drain Line DC bias
technique

Transmission lines: TFMS Cd
with Cu-6 Output
RF pad
Input
RF pad
130 nm SOI CSDA
Transistors Floating Body Gate Line Cg
WT = 30 x 2
Fmax = 125 GHz
T2 Drain line
Gate line L = 480 µm
Biasing of T2’s Gate
W= 2 µm Cdec
Lsd
Drain line L = 380 µm Lcg
W= 2 µm
Area (mm²) 0.5x1.5 T1 Gate line

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 Cascode distributed amplifier (2)

10

S21, S11 (dB)

0 S21
-10
130 nm SOI This work This work S11
FB CSDA FB CDA -20 FB DA
B CDA
S21 (dB) 4.5±1.2 6.8±1.0 -30
S11/S22 (dB) <-7.9/ <-6.7 <-6.2/ <-6.7 0 10 20 30 40
Frequency (GHz)
BW (GHz) 0.4-30 0.4-27
10
Area (mm²) 0.5x1.5 0.5x1.5
NF

S22, NF (dB)
NF (dB) 4.6 - 7.0 6.4-7.8 0
Vdd (V) 1.4 1.4 -10
Pdc (mW) 66 55 S22
-20
FBDA
BCDA
-30
0 10 20 30 40
Frequency (GHz)

BCDA designed by Dr. C. Pavageau (IEMN)

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 State-of-the art
Gain, Matching, Bandwidth, Area, Noise Figure, Linearity, DC Power for
state-of-the art DA

Technology S21 S11/S22 Bandwidth Area N.F OP1dB Vdd PDC

(dB) (dB) (GHz) (mm²) (dB) (dBm) (V) (mW)
0.18µm Bulk 7.3±
±0.8 <-8/<-9 0.6 –22 0.90 X 1.50 4.3 – 6.1 - 1.3 52
CMOS
InAlAs HBT 5.1±
±1.2 <-5/<-5 2.0 –50 1.80 X 1.20 - - 4 89

InP HEMT 14±

±0.8 <-9/<-10 1.0 – 90 2.50 X 1.10 8.0 – 9.0 - - -

GaAs HEMT 6.0±

±1.0 <-13/<-4 2.0 –50 1.97 X 1.25 - 22 15 1900

0.12µm SOI- 7.3±

±1.3 <-7/<-7 4.0 –86 1.46 X 0.72 5.0 – 3.6 10 2.6 130
7stg
0.12µm SOI- 4.0±
±1.2 <-7/<-7 4.0 –91 1.11 X 0.72 6.2 – 4.2 9 2.6 90
5stg
This work 7.1±
±1.1 <-6.2/<-6.7 1 –26 0.50 X 1.50 6.4 – 7.8 6.2 1.4 55
FBCDA-4stg

This work 5.4±

±1.4 <-7.9/<-6.7 1 –20 0.50 X 1.50 6.5 – 7.5 6.2 1.4 58
BCDA-4stg

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 Cascode DA: FB and BC

Summary of the best performances of our designs

10 12 Body- Floating
Transistor
5 11 contact -Body
0 10 Fmax (GHz) 76 125
S21 (dB)

NF (dB)
-5 9
-10 8 Gain (dB) 5.4±1.4 7.1±1.1
-15 7
BW (GHz) 1-20 1-26
-20 6
Body Contact
-25
Floating Body
5 S11/S22 (dB) < -8 < -6
-30 4
0 10 20 30 40
6.5-7.5
NF (dB)
Frequency (GHz) 6-20 GHz

Problem

Line losses deeply reduce gain and bandwidth !!!

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 Passive performances

- Main contributor to the losses in the DA

Losses in the TFMS lines.

- How to decrease the losses:

CPW on HR silicon substrate. W S

0.9 µm Cu

Oxide (SiO2)
(2.2 µm)
Dielectric
(770 nm)
BOX
STD-Si substrate (400 nm)
(20 Ω.cm)
OR
HR-Si substrate
(>1000 Ω.cm)

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 CPW on High resistivity substrates

- Performances

TFMS with M6 : 1 dB/mm @20GHz.

TFMS with M6+ALUCAP : 0.75 dB/mm @20GHz.

CPW on HR : ~ 0.3 dB/mm on HR-1kΩ @ 20 GHz.

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 Distributed amplifier with CPW lines (1)
Vbias
RF pad Output
Drain line RF pad

Cd

Cg
Gate line Cdec
Input
RF pad
Drain line
Bias transmission line

Connexion gnd-gnd
-
(Metal -1)
T2

Cdec
T1

Gate line

Layout area: 675 x 2180 µm²

CPW_CDA designed by Dr. C. Pavageau (IEMN)

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 Distributed amplifier with CPW lines (2)

1st run 2nd run

TFMS wo CPW on HR
Lines
ALUCAP substrate
Transistor Floating-Body
Fmax (GHz) 125
GBW (GHz) 61 98
Gain (dB) 7.1±1.1 7.1±
±1.6
BW (GHz) 1-26 1-40
Area (mm²) 0.75 1.5
Pdc (mW) 55 75

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 Distributed amplifier with CPW lines (3)

• Using high resistivity substrate enables low loss CPW

transmission lines.

• Using the same architecture as for TFMS lines

~ 50% increase of the bandwidth !

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 SOI @ high temperature
Application Temperatures
 Advantages of SOI over bulk Well logging 75-600◦C
CMOS: Oil Wells 75-175◦C
Gas Wells 150-225◦C
• absence of thermally-activated Steam injection 200-300◦C
latch up. Geothermal energy 200-600◦C
• reduced leakage current. Automotive 150-600◦C
Underhood 50-600◦C
Engine sensors up to 600◦C
Combustion and exhaust up to 600◦C
sensors
ABS up to 600◦C
Increase temperature
Aircraft 150-600◦C
operation !
Internal equipment 150-250◦C
Engine monitoring 300-600◦C
Surface controls 300-600◦C
J.-P. Colinge, “Silicon-on-Insulator Technology: Satellites (Venus probe) 150-600◦C
Materials to VLSI”, Kluwer Academic Publishers.
2nd Ed. 1997. Commercial nuclear 30-550◦C

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Performances vs. high temperature

10
9
8
7 T=25°C
6 T=50°C
|S21| (dB)

5
4 T=100°C

3 T=150°C
2
T=200°C
1 T=250°C
0
0 10 20 30
Frequency (GHz)

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 Gain & Bandwidth vs. temperature

Temperature S21@ midband Cut-off frequency

(dB) @ 0 dB (GHz)
Room temperature 6.8 27

50°C 6.2 27
100°C 4.3 26
150°C 3.6 25
200°C 3.2 22
250°C 2.7 12

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 Temperature effect analysis

- The gain of the DA depends mainly on:

• The transconductance of the MOSFET gm

• Gate and drain line losses αg and αd

- Temperature effect measurements:

• S parameters of the MOSFET vs. T

• S parameters of the microstrip line vs. T

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Measured transconductance vs. temperature

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Measured lineic losses vs. temperature

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 Temperature effect results

- On the MOSFET:

Decrease of 30% of the gate transconductance gm

- On the Microstrip line:

Increase of 80% of the lineic losses

Due to the increase of the metallic losses

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Contribution of passive and active devices
9
T=25°C
8

6
FET effect
|S21| (dB) 5

4 TFMS effect

3 TFMS & FET effect

2

0
0 5 10 15 20 25 30 35
Frequency (GHz)

Distributed Amplifiers at high-temperature:

TFMS are the main contributor to the decrease
of the gain and the bandwidth !!!
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 Conclusion (1)

• SOI is a proven solution for digital applications.

SOI brings higher speed and lower power for

the digital world
Yes
• Is SOI suitable for RF applications ?

SOI brings the RF Soc capabilities

• low voltage for RF design => low power
• less substrate crosstalk => digital and RF closer
• high resistivity substrate => high Q factor for passives
• mature technology for the realization of high-temperature IC’s

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 Conclusion (2)

Yes
• Can we do wideband circuits on SOI ?

Take advantages of the SOI technology

and the distributed architecture
• low parasitic capacitances => higher Ft and Fmax
• Enhancement of the bandwidth due to the use of Distributed
Amplification.
• Distributed Amplification places CMOS – SOI in competition
with GaAs and SiGe for High Speed Microwave circuit applications
and UWB.

BUT
Be careful with the passives!!!
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 Perspectives

The future of interconnection technology*

*T. N. Theis, IBM J. RES. DEVELOP. VOL. 44 NO. 3 MAY 2000

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 Perspectives
One-chip RF Transceiver

One of the main goal for microwave designers is to build one-chip RF

transceivers

One-chip RF transceiver means:

• Integration of multi-standard applications in the same device (GSM,

UMTS, Bluetooth, …)

• Portable applications

- High integration degree

- Light devices
- Low-power consumption
- Low-voltage supply

• Mass production: low cost

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 Perspectives

ZigBee: Target Market

— TV
— VCR
— Monitors — DVD
— Sensors Industrial & Consumer
— CD
— Automation Commercial Electronics — Remote
— Control

PC
Peripherals
— Mouse
Personal Low Data Rate — Keyboard
Healthcare Radio Devices — Joystick
— Gamepad

— Monitors
— Diagnostics
— Sensors — Security
— PETs Home — HVAC
Toys & — Gameboys Automation — Lighting
Games — Educational — Closures

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 Perspectives

Motivation

Design of RF circuits for ZigBee Standard

• Very low cost,

• Low power consumption,
• High Temperature Environment

Take advantages of the SOI CMOS technology

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Questions ??

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