Lecture 190 – Differential Amplifier (3/27/10) Page 190-1

LECTURE 190 – DIFFERENTIAL AMPLIFIER

LECTURE ORGANIZATION
Outline
• Characterization of a differential amplifier
• Differential amplifier with a current mirror load
• Differential amplifier with MOS diode loads
• An intuitive method of small signal analysis
• Large signal performance of differential amplifiers
• Differential amplifiers with current source loads
• Design of differential amplifiers
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 180-199

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-2

CHARACTERIZATION OF A DIFFERENTIAL AMPLIFIER

What is a Differential Amplifier?
A differential amplifier is an amplifier that amplifies the difference between two
voltages and rejects the average or common mode value of the two voltages.
Differential and common mode voltages:
v1 and v 2 are called single-ended voltages. They are voltages referenced to ac
ground.
The differential-mode input voltage, vID, is the voltage difference between v1 and v2.
The common-mode input voltage, vIC, is the average value of v1 and v2 .
v1+v2
 vID = v1 - v2 and vIC = 2
v1 = vIC + 0.5vID and v2 = vIC - 0.5vID
 
vID  v1
+
v2
2
vOUT = AVDvID ± AVCvIC = AVD(v1 - v2) ± AVC  2 

+
- + where
vID
vIC 2 vOUT AVD = differential-mode voltage gain
- AVC = common-mode voltage gain
Fig. 5.2-1B

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-3

Differential Amplifier Definitions

• Common mode rejection rato (CMRR)

A


VD

CMRR =
AVC

CMRR is a measure of how well the differential amplifier rejects the common-mode
input voltage in favor of the differential-input voltage.
• Input common-mode range (ICMR)
The input common-mode range is the range of common-mode voltages over which
the differential amplifier continues to sense and amplify the difference signal with the
same gain.
Typically, the ICMR is defined by the common-mode voltage range over which all
MOSFETs remain in the saturation region.
• Output offset voltage (VOS(out))
The output offset voltage is the voltage which appears at the output of the differential
amplifier when the input terminals are connected together.
• Input offset voltage (VOS(in) = VOS)
The input offset voltage is equal to the output offset voltage divided by the differential
voltage gain.
V OS(out)
V OS = AVD

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-4

Transconductance Characteristic of the Differential Amplifier

Consider the following n-channel differential VDD
amplifier (called a source-coupled pair). Where

;y ;y
should bulk be connected? Consider a p-well, vG1 M1
iD1 iD2 M2 v
G2
CMOS technology:
+ +
D1 G1 S1 S2 G2 D2 VDD v vGS1 vGS2
IBias ID - -
M4 M3 ISS
n+ n+ p+ n+ n+ n+
VBulk
p-well
n-substrate Fig. 5.2-2
Fig. 5.2-3

1.) Bulks connected to the sources: No modulation of VT but large common mode
parasitic capacitance.
2.) Bulks connected to ground: Smaller common mode parasitic capacitors, but
modulation of VT.
What are the implications of a large common mode capacitance?
+
R − R
vIN
vIN 0V
Little −
+ Large charging
charging of of capacitance
capacitance 070416-02

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-5

Transconductance Characteristic of the Differential Amplifier - Continued

Defining equations:
   
 2iD1 1/2  2iD2 1/2
vID = vGS1
vGS2 =   
 
  
 and ISS = iD1 + iD2
Solution:
2 4 2 4
ISS ISS vID 2vID1/2 ISS ISS vID 2vID1/2
iD1 = 2 + 2  ISS


2  and iD2 = 2
2  ISS


2 
 4I  SS  4I  SS
which are valid for vID < 2(ISS/)1/2.
Illustration of the result:
iD/ISS
1.0
0.8
iD1
0.6
0.4 iD2
Differentiating iD1 (or iD2) 0.2
vID
with respect to vID and -2.0 -1.414 0.0 1.414 2.0 (ISS/ß)0.5 Fig. 5.2-4
setting VID =0V gives
diD1 bISS K'1ISSW 1
gm = dvID(VID = 0) = 4 = 4L1 (half the gm of an inverting amplifier)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-6

DIFFERENTIAL AMPLIFIER WITH A CURRENT MIRROR LOAD

Voltage Transfer Characteristic of the Differential Amplifier
In order to obtain the voltage transfer characteristic, a load for the differential amplifier
must be defined. We will select a current mirror load as illustrated below.
VDD
2μm 2μm
1μm 1μm
M3 M4
iD3 iD4 iOUT
2μm 2μm +
1μm iD1 iD2
1μm
VDD
M1 M2 2
+ vGS2 +
GS1 v vOUT
Note that output signal to ground is - -
vG1 2μm ISS vG2
equivalent to the differential output 1μm
signal due to the current mirror. -
M5
- -
The short-circuit, transconductance is VBias
given as Fig. 5.2-5

diOUT K'1ISSW 1
gm = dvID (VID = 0) =
ISS = L1

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-7

Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load
VDD = 5V
5
2μm 2μm
1μm 1μm M4 active
4
iD3 M3 M4 iD4 iOUT M4 saturated

vOUT (Volts)
2μm 2μm +
1μm iD1 iD2 3
1μm
VIC = 2V
M1 M2
+ + 2
vGS1 - - vGS2 vOUT
2μm ISS M2 saturated
vG1 1μm vG2 1 M2 active
M5
- - -
VBias 0
-1 -0.5 0 0.5 1
vID (Volts) 060705-01
Regions of operation of the transistors:
M2 is saturated when,
vDS2  vGS2-V TN  vOUT-V S1  VIC-0.5vID-V S1-V TN  vOUT  VIC-V TN
where we have assumed that the region of transition for M2 is close to vID = 0V.
M4 is saturated when,
vSD4  vSG4 - |VTP|  VDD-vOUT  VSG4-|VTP|  vOUT
VDD-V SG4+|VTP|
The regions of operations shown on the voltage transfer function assume ISS = 100μA.
2·50
Note: VSG4 = 50·2 +|VTP| = 1 + |VTP|  vOUT
5 - 1 - 0.7 + 0.7 = 4V

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-8

Differential Amplifier Using p-channel Input MOSFETs

VDD

M5
VBias IDD
- -
vSG1 vSG2
+ M1 +
M2
+ +
iD1 iD2 iOUT
iD3 iD4 +
vG1 vG2
M3 vOUT
M4
- - -

Fig. 5.2-7

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-9

Input Common Mode Range (ICMR) VDD

ICMR is found by setting vID = 0 and varying vIC 2μm
1μm
2μm
1μm
until one of the transistors leaves the saturation. M3 M4
iD3 iD4 iOUT
Highest Common Mode Voltage
2μm 2μm +
Path from G1 through M1 and M3 to VDD: 1μm iD1 iD2
1μm
VDD
M1 M2
V IC(max) =VG1(max) =VG2(max) +
vGS1 vGS2 +
vOUT
2
- -
=VDD -VSG3 -VDS1(sat) +VGS1 vG1 2μm
1μm ISS vG2
or M5
- - -
V IC(max) = VDD - VSG3 + VTN1 VBias
Fig. 330-02
Path from G2 through M2 and M4 to VDD:
V IC(max)’ =VDD -VSD4(sat) -VDS2(sat) +VGS2
=VDD -VSD4(sat) + VTN2


VIC(max)
=
VDD
-
VSG3
+
VTN1

Lowest Common Mode Voltage (Assume a VSS for generality)

VIC(min)
=
VSS
+VDS5(sat)
+
VGS1
=
VSS
+VDS5(sat)
+
VGS2

where we have assumed that VGS1 = VGS2 during changes in the input common mode
voltage.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-10

Example 190-1 - Small-Signal Analysis of the Differential-Mode of the Diff. Amp

A requirement for differential-mode operation is that the differential amplifier is balanced†
VDD

C3
M3 M4 D1=G3=D3=G4
iD3 iD4 iout G1 G2 rds1 S1=S2 rds2 D2=D4
+ vid -
+ + i3 +
iD1 iD2 +
vg1 vg2 1 rds5 i3 vout
M1 M2 C1
gm3 rds3 gm1vgs1 gm2vgs2 rds4 C2
- - -
vid vout S3 S4

M5 iout'
ISS G1 G2 D1=G3=D3=G4 D2=D4
- + vid -
VBias + + i3 +
vgs1 vgs2 C3
1 vout
gm1vgs1 C1 gm2vgs2 i3 rds2 rds4 C2
- - rds1 rds3 gm3 -
S1=S2=S3=S4 Fig. 330-03
Differential Transconductance:
Assume that the output of the differential amplifier is an ac short.
gm1gm3rp1
iout’ = 1
+
g r vgs1  gm2vgs2
gm1vgs1  gm2vgs2 = gmdvid
m3 p1
where gm1 = gm2 = gmd, rp1 = rds1rds3 and i'out designates the output current into a short
circuit.

†
It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue to use
the assumption regardless.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 190 – Differential Amplifier (3/27/10) Page 190-11

Small-Signal Analysis of the Differential-Mode of the Diff. Amplifier - Continued

Output Resistance: Differential Voltage Gain:
1 vout gmd
rout = gds2
+
gds4 = rds2||rds4 Av = vid = gds2
+
gds4
If we assume that all transistors are in saturation and replace the small signa
parameters of gm and rds in terms of their large-signal model equivalents, we achieve
vout (K'1ISSW 1/L1)1/2 2 K'1W 1 1/2 1
Av = vid = (2
+
4)(ISS/2) = 2
+
4  ISSL1  
ISS
Note that the small-signal gain is inversely vout
proportional to the square root of the bias vin Strong Inversion
current! Weak
Invers-
Example: ion
If W1/L1 = 2μm/1μm and ISS = 50μA log(IBias
≈ 1μA
(10μA), then 060614-01

Av(n-channel) = 46.6V/V (104.23V/V)

Av(p-channel) = 31.4V/V (70.27V/V)
1 1
rout = gds2
+
gds4 = 25μA·0.09V-1 = 0.444M
(2.22M
)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-12

Common Mode Analysis for the Current Mirror Load Differential Amplifier
The current mirror load differential amplifier is not a good example for common mode
analysis because the current mirror rejects the common mode signal.
VDD
-M3-M4
M1
M3 M4

+
M2
v ≈ 0V
M1 M2 out
vic
+ -
VBias M5
- Fig. 5.2-8A

Total
common
Common
mode 
Common
mode
     
 mode
Output  =  output
due
to  -  output
due
to 
 due
to
vic  M1-M3-M4
path M2
path
Therefore:
• The common mode output voltage should ideally be zero.
• Any voltage that exists at the output is due to mismatches in the gain between the two
different paths.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-13

DIFFERENTIAL AMPLIFIER WITH MOS DIODE LOADS

Small-Signal Analysis of the Common-Mode of the Differential Amplifier
The common-mode gain of the differential amplifier with a current mirror load is ideally
zero.
To illustrate the common-mode gain, we need a different type of load so we will consider
the following: VDD VDD VDD

M3 M4 M3 M4 M3 M4
vo1 vo2 vo1 vo2 vo1 vo2

v1 v2
M1 M2 M1 M2 M1 M2
ISS M5x 12 ISS
vid vid ISS 2 2
2 2 vic vic
M5
VBias VBias

Differential-mode circuit General circuit Common-mode circuit

Fig. 330-05

Differential-Mode Analysis:
vo1 gm1 vo2 gm2
 -
vid 2gm3 and vid  + 2gm4
Note that these voltage gains are half of the active load inverter voltage gain.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-14

Small-Signal Analysis of the Common-Mode of the Differential Amplifier – Cont’d

Common-Mode Analysis:
+ vgs1 - gm1vgs1
+ +
Assume that rds1 is large and can be ignored
1
(greatly simplifies the analysis). vic 2rds5 rds1 rds3 gm3 vo1
- -
 vgs1 = vg1-vs1 = vic - 2gm1rds5vgs1 Fig. 330-06
Solving for vgs1 gives
vic
vgs1 = 1
+
2gm1rds5
The single-ended output voltage, vo1, as a function of vic can be written as
vo1 gm1[rds3||(1/gm3)] (gm1/gm3) gds5
vic = - 1
+
2gm1rds5
- 1
+
2gm1rds5
- 2gm3
Common-Mode Rejection Ratio (CMRR):
|vo1/vid| gm1/2gm3
CMRR = |vo1/vic| = gds5/2gm3 = gm1rds5
How could you easily increase the CMRR of this differential amplifier?

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-15

Frequency Response of the Differential Amplifier

Back to the current mirror load differential amplifier:
VDD
Cgs3+Cgs4
G1 G2 D1=G3=D3=G4 D2=D4
Cbd3 M3 M4 + vid -
Cbd4 + + i3 +
vgs1 vgs2 C3
1 vout
Cgd1 Cgd4 gm1vgs1 C 1 i3 rds2 rds4 C2
Cgd2 + - - gm3 gm2vgs2 -
Cbd1
vout S1=S2=S3=S4
Cbd2 CL
vid -
M1 M2
+ vid -
M5 + + i3 +
vgs1 vgs2 vout
gm1vgs1 1
VBias
gm3 gm2vgs2 i3 rds2 rds4 C2
- - -
070416-03
Ignore the zeros that occur due to Cgd1, Cgd2 and Cgd4.
C1 = Cgd1+Cbd1+Cbd3+Cgs3+Cgs4, C2 = Cbd2 +Cbd4+Cgd2+CL and C3 = Cgd4
If gm3/C1 >> (gds2+gds4)/C2, then we can write
gm1 
 2
 gds2+gds4
V out(s)
gds2+gds4 s+ [Vgs1(s) - Vgs2(s)] where 2 

C2
2
then the approximate frequency response of the differential amplifier reduces to
V out(s)  gm1   2 
V id(s)  gds2+gds4  s+2 (A more detailed analysis will be made in Lecture 220)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-16

AN INTUITIVE METHOD OF SMALL SIGNAL ANALYSIS

Simplification of Small Signal Analysis
Small signal analysis is used so often in analog circuit design that it becomes desirable to
find faster ways of performing this important analysis.
Intuitive Analysis (or Schematic Analysis)
Technique:
1.) Identify the transistor(s) that convert the input voltage to current (these transistors
are called transconductance transistors).
2.) Trace the currents to where they flow into an equivalent resistance to ground.
3.) Multiply this resistance by the current to get the voltage at this node to ground.
4.) Repeat this process until the output is reached.
Simple Example: VDD VDD

R1 M2
vo1 gm2vo1 vout
gm1vin

vin M1 R2

Fig. 5.2-10C

vo1 = -(gm1vin) R1
vout = -(gm2vo1)R2
vout = (gm1R1gm2R2)vin

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-17

Intuitive Analysis of the Current-Mirror Load Differential Amplifier

VDD

M3 M4
gm1vid gm1vid rout
2 2
+
M1 gm1vid gm2vid M2
+ 2 2 -
vid vid
vout
2 - + 2
+ -
M5 vid
-
VBias
Fig. 5.2-11

1.) i1 = 0.5gm1vid and i2 = -0.5gm2vid

2.) i3 = i1 = 0.5gm1vid
3.) i4 = i3 = 0.5gm1vid
1
4.) The resistance at the output node, rout, is rds2||rds4 or gds2
+
gds4
gm1vin gm2vin vout gm1
5.)  vout = (0.5gm1vid+0.5gm2vid )rout =gds2+gds4 = gds2+gds4
v = g +g
in ds2 ds4

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-18

Some Concepts to Help Extend the Intuitive Method of Small-Signal Analysis

1.) Approximate the output resistance of any cascode circuit as
Rout
(gm2rds2)rds1
where M1 is a transistor cascoded by M2.
2.) If there is a resistance, R, in series with the source of the transconductance transistor,
let the effective transconductance be
gm
gm(eff) = 1+gmR
Proof:
gm2(eff)vin gm2(eff)vin
gm2vgs2 iout
M2 M2 + vgs2 -
vin rds1
vin M1 vin
rds1
VBias Small-signal model
Fig. 5.2-11A

vin
 vgs2 = vg2 - vs2 = vin - (gm2rds1)vgs2  vgs2 = 1+gm2rds1
gm2vin
Thus, iout = 1+gm2rds1 = gm2(eff) vin

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-19

Noise Analysis of the Differential Amplifier

VDD VDD
M5
M5 M5
VBias VBias
en12 en22 eeq2

* M1 M2 * * M1 M2
ito2 vOUT
en32 en42
M3 * * M4 Vout M3 M4

Fig. 5.2-11C
Solve for the total output-noise current to get,
ito 2 = gm12en12 + gm22en22 + gm32en32 + gm42en42
This output-noise current can be expressed in terms of an equivalent input noise voltage
eeq2, given as ito2 = gm12eeq2
Equating the above two expressions for the total output-noise current gives,
 
gm3 2
eeq = en1 + en2 + gm1
en32
+
en42

2 2 2

1/f Noise (en12=en22 and en32=en42): Thermal Noise (en12=en22 and en32=en42):
    
 
2BP K’N
BN L1 2

16kT 
W 3L1K'3 1/2
eeq(1/f)= f W1L1 1
+
 K’PBP 
L3
  eeq(th)= 3[2K' (W/L) I ]1/2
1+
L3W 1K'1


1 1 1

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-20

LARGE SIGNAL PERFORMANCE OF THE DIFFERENTIAL AMPLIFIER

Linearization of the Transconductance
iout iout
Goal:
ISS ISS

Linearization
vin vin

-ISS -ISS
060608-03

Method (degeneration):
VDD VDD
M3 M4 M3 M4
iout iout

M1 M2 M1 M2
+ RS RS VDD or + VDD
vin 2 2 2 vin RS 2
− −
M5
VNBias1 M5 VNBias1 M6
060118-10

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-21

Linearization with Active Devices

VDD VDD
M3 M4 M3 M4
iout iout

M1 VBias M2 M1 M2
+ VDD + VDD
or
vin M6 2 M6 2
vin
− M7
M5x1/2 −
VNBias1 M5x1/2 M5
VNBias1 M6

M6 is in deep triode region 060608-05 M6 and M7 are in the triode region

Note that these transconductors on this slide and the last can all have a varying
transconductance by changing the value of ISS.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-22

Slew Rate of the Differential Amplifier

Slew Rate (SR) = Maximum output-voltage rate (either positive or negative)
dvOUT
It is caused by, iOUT = CL dt . When iOUT is a constant, the rate is a constant.
Consider the following current-mirror load, differential amplifiers:
VDD VDD
M5
M3 M4
iD4 iOUT VBias IDD
iD3
- -
vSG1 vSG2
iD1 iD2 + + +
M1 M2
M1 CL + +
+ M2 iD1 iD2 iOUT
vGS1 vGS2 +
- - iD3 iD4 +
vG1 ISS vG2 vOUT vG1 vG2
M3 M4 CL vOUT
M5
- - - - - -
VBias
Fig. 5.2-11B
Note that slew rate can only occur when the differential input signal is large enough to
cause ISS (IDD) to flow through only one of the differential input transistors.
ISS IDD
SR = CL = CL
If CL = 5pF and ISS = 10μA, the slew rate is SR = 2V/μs.
(For the BJT differential amplifier slewing occurs at ±100mV whereas for the MOSFET
differential amplifier it can be ±2V or more.)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-23

DIFFERENTIAL AMPLIFIERS WITH CURRENT SOURCE LOADS

Current-Source Load Differential Amplifier
Gives a truly balanced differential amplifier. VDD
M3 M4
X1
X1 X1
Also, the upper input common-mode range is M7 I3 I4
v3 v4
extended. v1 I1 I2 v2
IBias
M1 X1 X1 M2
M6 M5 I5
However, a problem occurs if I1
I3 or if I2
I4. X1 X2

Current Current Fig. 5.2-12

I1 I3
I3 I1

0 vDS1 0 vDS1
0 VDS1<VDS(sat) VDD 0 VSD3<VSD(sat) VDD
(a.) I1>I3. (b.) I3>I1. Fig. 5.2-13

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-24

A Differential-Output, Differential-Input Amplifier

Probably the best way to solve the current mismatch problem is through the use of
common-mode feedback.
Consider the following solution to the previous problem.
VDD
M3 M4
IBias MC3
MC4 v3 I3 I4 v4
Common- IC3 IC4
mode feed- Self-
back circuit resistances
MC1 MC2A of M1-M4
v1 v2
VCM M1 M2
MC2B
MC5 M5
MB

VSS Fig. 5.2-14

Operation:
• Common mode output voltages are sensed at the gates of MC2A and MC2B and
compared to VCM.
• The current in MC3 provides the negative feedback to drive the common mode output
voltage to the desired level.
• With large values of output voltage, this common mode feedback scheme has flaws.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-25

Common-Mode Stabilization of the Diff.-Output, Diff.-Input Amplifier - Continued

The following circuit avoids the large differential output signal swing problems.
VDD
M3 M4
IBias MC3
MC4 v3 I3 I4 v4
Common- IC3 IC4 RCM1
mode feed- Self-
back circuit resistances
RCM2
MC1 MC2 of M1-M4
v1 v2
VCM M1 M2

MC5 M5
MB

VSS Fig. 5.2-145

Note that RCM1 and RCM2 must not load the output of the differential amplifier.
(We will examine more CM feedback schemes in Lecture 280.)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-26

DESIGN OF DIFFERENTIAL AMPLIFIERS

Design of a CMOS Differential Amplifier with a Current Mirror Load
Design Considerations: VDD
Constraints Specifications
Power supply Small-signal gain
Technology Frequency response (CL) M3 M4
vout
Temperature ICMR CL
Slew rate (CL) +
vin M1 M2
Power dissipation -
Relationships I5
Av = gm1Rout
VBias M5

-3dB = 1/RoutCL
VSS ALA20
V IC(max) = VDD - VSG3 + VTN1
V IC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
SR = ISS/CL
Pdiss = (VDD+|VSS|)x(All dc currents flowing from VDD or to VSS)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-27

Design of a CMOS Differential Amplifier with a Current Mirror Load - Continued

Max. ICMR Schematic-wise, the design procedure is illustrated as

VDD shown:
+
VSG4
- Procedure:
1.) Pick ISS to satisfy the slew rate knowing CL or
M3 M4
vout the power dissipation
gm1Rout CL 2.) Check to see if Rout will satisfy the frequency
+ response, if not change ISS or modify circuit
vin M1 M2 3.) Design W3/L3 (W 4/L4) to satisfy the upper ICMR
-
Min. ICMR I5 = SR·CL, 4.) Design W1/L1 (W 2/L2) to satisfy the gain
I5
ω-3dB, Pdiss 5.) Design W5/L5 to satisfy the lower ICMR
+
VBias M5 6.) Iterate where necessary
-
VSS ALA20

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-28

Example 190-2 - Design of a MOS Differential Amp. with a Current Mirror Load
Design the currents and W/L values of the current mirror load MOS differential amplifier
to satisfy the following specifications: VDD = -VSS = 2.5V, SR  10V/μs (CL=5pF), f-3dB
 100kHz (CL=5pF), a small signal gain of 100V/V, -1.5V
ICMR
2V and Pdiss
1mW
Use the parameters of K N’=110μA/V2, K P’=50μA/V2, V TN=0.7V, V TP=-0.7V
N=0.04V-1 and P=0.05V-1.
Solution
1.) To meet the slew rate, ISS  50μA. For maximum Pdiss, ISS
200μA.
2
2.) f-3dB of 100kHz implies that Rout
318k. Therefore Rout = (N+P)ISS
318k
 ISS  70μA Thus, pick ISS = 100μA
3.) VIC(max) = VDD - VSG3 + VTN1  2V = 2.5 - VSG3 + 0.7
2·50μA
V SG3 = 1.2V = 50μA/V2(W 3/L3) + 0.7
W3 W4 2
 L3 = L4 = (0.5)2 = 8

gm1 2·110μA/V2(W 1/L1) W1 W1 W2

4.) 100=gm1Rout=gds2+gds4 = = 23.31 L1 
L1 =
L2 =18.4
(0.04+0.05) 50μA

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-29

Example 190-2 - Continued

2·50μA
5.) VIC(min) = VSS +VDS5(sat)+VGS1
-1.5 = -2.5+VDS5(sat)+ 110μA/V2(18.4) + 0.7
W5 2ISS
V DS5(sat) = 0.3 - 0.222 = 0.0777 
L = K ’V (sat)2 = 150.6
5 N DS5
We probably should increase W1/L1 to reduce VGS1. If we choose W1/L1 = 40, then
V DS5(sat) = 0.149V and W5/L5 = 41. (Larger than specified gain should be okay.)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 190 – Differential Amplifier (3/27/10) Page 190-30

SUMMARY
• Differential amplifiers are compatible with the matching properties of IC technology
• The differential amplifier has two modes of signal operation:
- Differential mode
- Common mode
• Differential amplifiers are excellent input stages for voltage amplifiers
• Differential amplifiers can have different loads including:
- Current mirrors
- MOS diodes
- Current sources/sinks
- Resistors
• The small signal performance of the differential amplifier is similar to the inverting
amplifier in gain, output resistance and bandwidth
• The large signal performance includes slew rate and the linearization of the
transconductance
• The design of CMOS analog circuits uses the relationships of the circuit to design the dc
currents and the W/L ratios of each transistor

CMOS Analog Circuit Design © P.E. Allen - 2010