design

Edited by Bill Travis

ideas The best of
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8 Check it out at:
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Circuit provides 4- to 20-mA loop

for microcontrollers
Robert Most, Dow Corning Corp, Auburn, MI
15V 15V
he 4- to 20-mA current loop is ubiq-

T uitous in the world of controls in

manufacturing plants. Discrete log-
ic, microprocessors, and micro-
Figure 1
15V

6 _
100
1%

controllers easily cover the digital 100 1/2 7 680 Q3

portions of control schemes, such as lim- 1M 1%
5
TL032 2N3906
8.2k 8 +
it switches, pushbuttons, and signal FROM
3
+ 4
27k

lights. Interfacing a 4- to 20-mA output PROCESSOR 1/2 1 IOUT

100k TL032
TIMER Q2
to a rudimentary microcontroller can be 4.7 F 2 _ Q1
2N3906
2N3904 56k
problematic. A built-in A/D converter RL
would be nice, but such a device is some- TO
PROCESSOR
140 27k
times unavailable in the “economy” line 1% INPUT PORT
of these processors. Serial 4- to 20-mA
chips exist but are relatively expensive
and require serial programming and in- This configuration provides both a 4- to 20-mA loop and an open-circuit indication.
volve microcontroller overhead. Most
lower end chips lack dedicated serial ditional voltage swing below ground po- back through its emitter-base junction
ports and require pin-programming. tential to keep it in its active region and and through the 680
resistor to the op
This circuit is a low-cost alternative does not cut off. The emitter resistor of amp. The voltage developed across the
that provides not only a 4- to 20-mA out- npn transistor Q1 sets the current span of 680
resistor turns on Q2, resulting in
put, but also a digital feedback signal that the circuit. With a 5V drive from the mi- a logic-one feedback to the microcon-
indicates an open wire in the current loop crocontroller, the output current is 20 troller. Note that the open loop requires
(Figure 1). One output-port pin sets the mA. A grounded input results in less than at least 1 mA of current for the open in-
current, and one input-port pin monitors 1 mA. A duty cycle of 12.5% drives the dication to function, which is below the
an open circuit in the loop wire. The cir- loop at 4 mA and exhibits linear control normal 4 mA—a “zero” output condi-
cuit does not require the open-loop feed- to full scale. Although it may not be
back portion of the circuit for the current mandatory, most current loops prefer a
loop to operate; you can omit it for fur- grounded return path. The purpose of Circuit provides 4- to 20-mA loop
ther cost savings. the second operational amplifier is to for microcontrollers........................................89
The circuit derives its drive from a sim- provide a current source, rather than the Minimize the short-circuit current pulse
ple timer output in the microcontroller. current sink of the first stage, and the in a hot-swap controller ..............................90
The duty cycle of the timer determines grounded return path. Hence, pnp tran- Reduce EMI by sweeping
the output current of the circuit. The in- sistor Q3 provides this high-side drive. a power supply’s frequency ........................92
put RC network in front of the first op- Bipolar-junction transistors Q1 and Q3
erational-amplifier signal conditions the meet cost considerations, but you could Get just enough boost voltage ..................94
pulse train from the processor, so that the also use MOSFETs for slightly better per- Processor’s PWM output controls
op amp interprets it as a dc voltage. In ad- formance. LCD/LED driver ..............................................96
dition, the network ensures that the min- The open-loop feedback portion of
Method provides automatic
imum input voltage is close to 100 mV, this circuit lets the microcontroller
machine shutdown........................................98
even if the input is at ground potential. know that a fault condition exists on the
This minimum voltage ensures that the line. The processor can then execute Circuit makes simple high-voltage
feedback loop of the first op amp does alarm, shutdown, or other control func- inverter ..........................................................100
not fold back to the positive rail when tions to mitigate possible safety con- Publish your Design Idea in EDN. See the
you cut off npn transistor Q1. If you use cerns. When an open-loop condition oc- What’s Up section at www.edn.com.
a dual supply, the transistor has the ad- curs, Q3 shunts the entire loop current
www.edn.com May 27, 2004 | edn 89
design
ideas
tion for this type of control system.
Response time for a step change is ap-
proximately 500 msec, which is accept-
able for most current-loop control de-
vices, such as control valves. If the
microcontroller you select has a built-
in A/D converter, response time can de-
crease by a couple of orders of magni-
tude with the elimination of the in-
put-filtering network. Op-amp selec-
tion is important if you use a single-
supply topology. An operational ampli-
fier that can maintain stability close to
its negative, or ground, rail is an im-
portant asset.왏

Minimize the short-circuit current pulse

in a hot-swap controller
Jim Sherwin and Thong Huynh, Maxim Integrated Products, Sunnyvale, CA
ecause of internal circuit- tor chip. The circuit of Figure 5

B
M1
RS
breaker delay and limited FDS7788 can limit short-circuit current to
0.006
MOS-gate pulldown current, 12VIN 12VOUT approximately 100A for less than
many hot-swap controllers do not 200 nsec. The pnp transistor, Q1A,
limit current during the first 10 to which triggers when the voltage
50 sec following a shorted out- across RS reaches approximately
put. The result can be a brief flow IN SENSE GATE 600 mV, drives the npn transistor,
of several hundred amperes. A ON MAX4272ESA STAT POR Q1B,to quickly discharge M1’s gate
simple external circuit can count- capacitance. The steep voltage
CSPD GND CTIM
er this problem by minimizing the waveform aids quick triggering of
initial current spike and terminat- C1 the pnp transistor.
ing the short circuit 22 nF The oscilloscope’s ground lead
Figure 1 NC
within 200 to 500 nsec. A introduces an artifact, which ap-
typical 12V, 6A, hot-swap-con- A typical hot-swap controller circuit exhibits a 30- sec short- pears as the leading-edge oscilla-
troller circuit contains, as do many circuit current pulse of 400A peak. tion in Figure 6. Again, as in Fig-
others, slow and fast comparators ure 4, the apparent reverse-
with trip thresholds of 50 and 200 mV resistances. The waveform recorded dur- overshoot current and the steep rise in the
(Figure 1). The 6-m
sense resistor, RS, ing a short circuit indicates a peak cur- waveform of Figure 6 arise from parasitic
allows a nominal slow-comparator trip at rent of 400 from the 2.4V peak across RS, series inductance in the sense-resistor
8.3A for overload conditions and a fast- decreasing to 100A in 28 sec (Figure 2). chip. C2 connects between the gate and
comparator trip at 33.3A for short cir- You can limit the short-circuit current source of M1 to reduce the positive-tran-
cuits. Only circuit resistances limit the duration to less than 0.5 sec by adding sient step voltage applied to the gate dur-
initial short-circuit current spike during a Darlington pnp transistor, Q1, to speed ing a short circuit. Zener diode D1 reduces
a period that includes the fast-compara- the gate discharge (Figure 3). D1 allows ID(ON) by limiting VGS to less than the 7V
tor delay and the 30 sec it takes to com- the gate to charge normally at turn-on, available from the MAX4272.Although D1
plete interruption of the short circuit by but, at turn-off, the con- M1
discharging M1’s gate capacitance. Vari- troller’s 3-mA gate-dis- RS FDS7788
ous elements, such as RS and the on-re- charge current is direct- 12VIN
0.006
12VOUT
sistance of M1, contribute to the circuit ed to the base of Q1. Q1
then acts quickly to dis- MMBTA64FSTR-ND
FLAG-COMPARATOR charge the gate, in less Q1
TRIGGER POINT
than 100 nsec. Thus, the D1
high-current portion of MMBD4148
the short circuit is limit-
ed to slightly more than
IN SENSE GATE
the fast comparator’s de-
VOLTAGE MEASURED ACROSS RS=6 m
. lay time of 350 nsec. The ON MAX4272ESA STAT POR
apparent reverse over- CSPD GND CTIM
shoot current and the
C1
1V M5 SEC CH1 –200 mV steep rise in the wave- NC 22 nF
form of Figure
Figure 2 The short-circuit current 4 arise from Figure 3
in Figure 1 is 400A, decreasing to 100A in parasitic series induc- The addition of Q1 increases the gate-pulldown current, lim-
28 sec. tance in the sense-resis- iting the short-circuit-current duration to less than 0.5 sec.
90 edn | May 27, 2004 www.edn.com
design
ideas
M1
RS FDS7788
STEEP RISE AND
REVERSE OVERSHOOT 0.006
IN SENSE-RESISTOR 12VIN 12VOUT
VOLTAGE MEASUREMENT C2
IS AN ARTIFACT OF
SENSE-RESISTOR PARA- R1 D1 100 nF R3
SITIC INDUCTANCE.
100 5.1V 1k
Q1B
R2
100 FFB2227A
Q1A

M 250 nSEC CH1 –360 mV

IN SENSE GATE
Figure 5
ON MAX4272ESA STAT POR
Figure 4 The steep rise and reverse This hot-swap
overshoot in Figure 3’s circuit are artifacts of controller has CSPD GND CTIM
sense-resistor parasitic inductance. fast limiting of C1
short-circuit- NC 22 nF

is rated at 5.1V when biased at 5 mA, it current peaks.

limits VGS to approximately 3.4V in this
circuit because only 100 A of gate-charg-
ing current (zener-bias current) is avail-
able from the IC. The limited VGS lowers
ID(ON)—at some expense to on-resist-
ance—and allows a quicker turn-off of
M1. You could also use D1 and C2 to some
advantage in figures 1 and 3, to reduce
ID(ON) during short circuits.
Either of the two circuits can protect a
backplane power source by minimizing
slightly more complex circuit (Figure 5)
reduces the peak short-circuit current to
100A, as well as truncating the pulse width
to less than 200 nsec. You can apply either
technique to most hot-swap-controller
circuits. Individual results vary according
to the impedance of the power source, the
impedance of the short circuit, and the
quality and attack time of the short circuit
itself. Note that it is inordinately difficult M 100 nSEC CH1 –520 mV

the energy dissipated when a hot-swap- to achieve a repeatable low-resistance short

controller circuit incurs a short circuit. The
simpler circuit (Figure 3) dramatically
shortens the short-circuit-current interval
to somewhat less than 500 nsec, and the
circuit by manual manipulation of a
Figure 6 This waveform depicts the
shorting bar. You require careful lay-
out and low-ESR capacitors to create a short-circuit-current peaks for the circuit in
power source with very low ESR.왏 Figure 4.

Reduce EMI by sweeping a power supply’s frequency

John Betten, Texas Instruments, Dallas, TX
witching power supplies can be but at diminished amplitudes. The sim- parator output trips to a low state. The

S notorious noise generators. You

should prevent this noise, which is
conducted, radiated, or both, from re-
turning to the input source, where it can
potentially wreak havoc on other devices
operating from the same input power.
The goal of an EMI (electromagnetic-in-
terference) filter is to block this noise and
provide a low-impedance path back to
the noise source. The larger the noise, the
greater the size, expense, and difficulty of
the filter design. Power supplies that op-
erate at a fixed frequency have their
largest EMI emission at this fundamen-
tal, fixed frequency. Emissions also occur
at multiples of the switching frequency
92 edn | May 27, 2004
ple circuit in Figure 1 makes the switch-
ing converter operate over multiple fre-
quencies rather than one, thereby
reducing the time average at any one fre-
quency. This scheme effectively lowers
the peak emissions.
The circuit in Figure 1 is a self-starting
oscillator with an oscillation frequency of
approximately 500 Hz. When you apply
power, C3 begins to charge up from 0V,
and the output of the TL331 comparator
is in a high-impedance state because its
noninverting input sees a higher voltage
than that of the inverting input. As C3
charges, its voltage crosses the voltage ref-
erence of the R1-R6 divider, and the com-
voltage on R6 instantly drops to a lower
reference level because R5 is now in par-
allel with R6. C3 begins to discharge to-
ward this new reference level because R3
is simultaneously in parallel with C3. The
cycle repeats after C3 discharges to the
voltage on R6 when the comparator out-
put reopens. You must carefully select the
components to ensure that the two volt-
age-reference states of R6 are lower than
the upper and lower possible charge
states of C3. The circuit uses C3 to adjust
the oscillator frequency; you should se-
lect C3 to have a lower value than C2. The
oscillator’s frequency is approximately
equal to
www.edn.com
design
ideas 5V BIAS

C1 R1 R2
R3 0.1 F 10k 49.9k
10k
IC1
5 1 UCC3813
RT 1 8
4 COMP REF
IC1 C2 13.7k
TL331DBV 3 R4 2 7
1 F FB VCC
Capacitor C2 ac-couples the ramp R5 2 24.9k 3
CS OUT
6
voltage of C3 into the UCC3813’s oscil- 6.04k 4
RC GND
5

lator pin. The injected signal adds to the R6 C3 CT

charging current of CT during its posi- 4.99k 0.1 F 330 pF

tive portion (ac signal), thus increasing

the controller’s operating frequency.
During the injected signal’s
negative portion, some of CT’s Figure 1 A low-frequency oscillator ramp, injected into the RC pin, modulates the supply’s switch-
charging current disappears, slowing ing frequency.
the controller’s operating frequency.
Figure 2 shows the effects of the inject- the frequency-sweep rate. the circuit below the power converter’s
ed signal on the charging of CT. R4 con- The differential EMI-current measure- low-frequency limits, or saturation of
trols the magnitude of the current that ment of Figure 3 (1 dBV1 dBA) magnetics may occur. This circuit demon-
is injected. Reducing R4’s value increas- shows the before-and-after effects of strates a low-cost, small-area approach to
es the range, or spread, of the operat- adding the frequency-shifting oscillator. reducing conducted-EMI emissions.왏
ing frequency around its nominal fixed This design easily achieves a 10-
frequency. The injected signal’s oscilla- dBA reduction with a 12-kHz
tion frequency, which C3 sets, controls sweep window. A wider win-
1 dow further reduces EMI, but
1 SEC the modulator frequency may
0.50V
be noticeable in the converter’s
10115 SWPS
output ripple voltage. It is also
desirable to make the injected
ramp voltage as linear in shape
as possible to prevent the
switching converter from
1 SEC BWL
1 50 mV DC
spending excess time at its
2 50 mV DC
200 mSAMPLES/SEC switching-frequency limits. The
3 0.1V DC
4 0.5V DC 1 DC 1.39V □ STOPPED nonlinearity can result in an
EMI response with two
Figure 2 The external oscillator varies distinct frequencies. You Figure 3 The EMI of the flyback converter
the charging of the timing capacitor. must take care not to operate differs with and without external modulation.

Get just enough boost voltage

Kieran O’Malley, On Semiconductor, East Greenwich, RI
VIN14V
dding a current-mirror circuit to

A a typical boost circuit allows you to

select the amount of boost voltage
and to ensure a constant difference be- SHUTDOWN
+
C1
22 F
5
L1
22 H
D1
VOUT24V

tween the input and the output voltages 4

SS
VOC
VSW
8
(Figure 1). This circuit is useful for high- 3 IC1
BC856BDWLT1 +
MBRS120T3 C3
side-drive applications, in which a sim- NC
CS5171 22 F
ple voltage doubler is unacceptable be- 1 2 Q1A Q1B
VC VFB
cause of the voltage range of the
C2 AGND PGND R2 R4
components involved or where the input 0.01 F 6 7 10k 8.2k
voltage can vary widely. You can also use R1
the circuit at the front end of a 4.7k R3
power supply to ensure that the Figure 1 1.27k

PWM controller has enough voltage to

start correctly in low-input-voltage con- Adding a current-mirror circuit to a boost circuit allows you to get just enough boost voltage.
94 edn | May 27, 2004 www.edn.com
design
ideas
ditions. The circuit maintains a 10V dif- of 65V. In this case, VIN14V (nominal), you use a 10-k
resistor.
ference between VIN and VOUT, but you so you need VOUT to be 24V (nominal). Q1B mirrors the current and sets up the
can easily change it to provide other volt- First, calculate a value for R2, thus estab- feedback voltage to the PWM circuit. The
ages. The PWM circuit in Figure 1 is the lishing the reference current. If you select CS5171 has an internal voltage of 1.28V
CS5171 from On Semiconductor (www. a reference current of 1 mA, you obtain (typical), so R3 yields the correct feedback
onsemi.com), but you can use the idea voltage when the current flowing
with any boost circuit. The current-mir- through it is 1 mA. In this case, by select-
ror circuit, comprising the dual-pnp ing 1.27 k
for R3, you obtain an output
transistor, Q1, and the associated resis- voltage of 24V. As VIN varies, VOUT tracks
tors, establishes a current that depends on it and maintains a 10V difference be-
the voltage difference between VIN and tween the input and the output. R4 helps
VOUT. The dual-pnp transistor has a VCEO Because the output voltage is not critical, reduce the power dissipation in Q1B.왏

Processor’s PWM output controls LCD/LED driver

Joe Neubauer, Maxim Integrated Products, Sunnyvale, CA
he PWM (pulse-width-modulation) LED driver (Figure 3). The circuit com- voltage, VCONT:

T output available from many micro-

processors is based on an internal 8-
or 16-bit counter and features a pro-
prises simply the PWM source, capacitor
C, and resistors RD and RW. For CMOS
circuits, you calculate the open-circuit
grammable duty cycle. It is suitable for output voltage as VCONTDVDD, where
adjusting the output of an LCD driver VCONT is the control circuit’s output volt- where VREF is the reference voltage at the
(Figure 1), a negative-voltage LCD driv- age, D is the PWM duty cycle, and VDD is feedback input.
er (Figure 2), or a current-controlled the logic-supply voltage. The control cir- Bear in mind that the initial charge on
cuit’s output im- filter capacitor C produces a turn-on
VIN
IN MAIN 3.3V pedance is the sum transient. The capacitor forms a time
+
C1 SWIN C3
300 mA of the resistor values constant with RCONT, which causes the
RD and RW: RCONT output to initialize at a voltage higher
SDIG 3.3V RDRW. For the cir- than that intended. You can minimize
200 mA
REF C5 cuit of Figure 1, the this overshoot by scaling the value of RD
C8 MAX1552 output voltage, as high as possible with respect to R1 and
1.5V VOUT, is a function R2. As an alternative, the microprocessor
COR1
200 mA
C4 of the PWM average can disable the LCD until the PWM volt-
ON
SDIG ENSD 1.8V
OFF COR2 VIN
20 mA 5V
C6
ON
COR2 ENC2
OFF +
SW
RSENSE
ON C9
LCD ENLCD LCD
OFF L1 0.1 F 1
D1 20V V CS 8
1 mA
MAIN 2 7
LX ADJ
C2 DHI
R3 R4 C7 DIGITAL
R1 VOUT
ADJUST MAX749
RESET RS LFB 3 6
OUTPUT CTRL DLOW
R2 ON/OFF
LOW-BATTERY LBO GND 4 +
5
OUTPUT FB GND

Figure 2
CONNECTION FOR RFB
PWM-CONTROLLED
LCD BIAS
CCOMP
CONNECTION FOR
VDD RD PWM-CONTROLLED
RW
FROM LCD BIAS
PROCESSOR
VDD RD
PWM OUTPUT RW
0 C FROM
PROCESSOR
PWM OUTPUT C
0
Figure 1

This simple circuit provides positive-output voltage LCD drive. This configuration provides negative-output-voltage LCD drive.
96 edn | May 27, 2004 www.edn.com
design
ideas VIN
1 F

C1F C1N
1 F

C2P C2N

2.7 TO 5.5V 1/1.5 OUT

REGULATING CHARGE PUMP

age stabilizes. For Figure 2, the output + 4.7 F
1 F
voltage, VOUT, is a function of the PWM
MAXIM
average voltage, VCONT: MAX1570

LED1
EN1
ON/OFF
AND REFERENCE LED2
DIMMING EN2 AND LOW-DROPOUT
LED3
where VREF is the reference voltage at Figure 3
CONTROL CURRENT
REGULATORS
SET LED4
the feedback input. For Figure 3, the
LED5
output current is a function of the PWM RSET

average voltage, VCONT:

GND PGND
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
VDD RD
RW
FROM
PROCESSOR
PWM OUTPUT C
where VREF is the reference voltage at the 0

Set output and K is the current-scaling
factor.
RD isolates the capacitor from the feed-
back loop in the PWM-control methods.
Assuming a stable voltage at the feedback
PWM combines with current control in this LED-driver circuit.
point, the following equation defines the mize ripple voltage at the output, you
lowpass filter’s cutoff frequency: fC should set the cutoff frequency at least two
1/(2 RC), where RRD||RW. To mini- decades below the PWM frequency.왏

Method provides automatic machine shutdown

Jean-Bernard Guiot, Mulhouse, France
ome machines need to run for long 15 of relay K2T incurs a delay before open- tacts of K2T open, K1 turns off, and the ma-

S periods and therefore may finish ing, because K2T is a time-delay relay, the chine completely turns off. The varistors,
their work in the middle of the night machine stays on during the delay time. VR1, suppresses voltage spikes.You must se-
or during the weekend. For the time re- This delay allows a second contact of KSTOP lect VR1, K1, K2T, and H1 in accordance with
maining, until the operator returns, the to control an automatic telephone dialer the power-mains voltage and the power
machines stay idle, uselessly consuming (not shown) to inform the remotely locat- rating of the machine. You select KSTOP ac-
power. This Design Idea allows a machine ed operator and allows the process to fin- cording to the controller’s output (the re-
to completely shut itself down after fin- ish supplementary tasks, such as cooling lay coil) and the power-mains voltage (the
ishing its work. In addition, the method down, removing chips, allowing coolant to relay contacts). The circuit has worked sat-
allows for informing the machine opera- flow back into the tanks, for example. isfactorily in hundreds of machines over
tor by phone. You insert the circuit into Once the delay time expires, the con- a five-year period.왏
the area that Figure 1 indicates as a
ADD CIRCUIT IN DASHED LINES TO EXISTING MACHINE
dashed line into the main supply line of
the machine. The relay, KSTOP, connects to FROM 1 2 TO
a free output of the programmable con- POWER
3 4 MACHINE
MAINS
troller of the machine.You must program 5 6
the controller in such a way that relay K1
FUSE 1A
KSTOP is energized as long as the process
is running. In normal operation, switch VCC
S1 stays in manual position; thus, the MANUAL AUTO 1 18 14
A1
power contactor, K1, is on, and the ma- K2T KSTOP KSTOP

chine receives power. When an operator 2 15 11

S1 A2
starts the process, relay KSTOP energizes,
and the indicator, H1, lights, signaling the
operator that switch S1 is ready for
operation. The timer relay, K2T, is Figure 1 FROM
A1 A1 B1
1 CONTROLLER
also on, closing its contact 18-15. Switch- K1 VR1 K2T H1
ing S1 to automatic now has no effect. A2 A2
2

At the end of the process, relay KSTOP and

indicator H1 turn off. Because contact 18- This circuit allows a machine to completely shut itself off after doing its assigned task.
98 edn | May 27, 2004 www.edn.com
design
ideas
Circuit makes simple high-voltage inverter
Francesc Casanellas, Aiguafreda, Spain
L1
simple high-voltage MOSFET in-

A
30 H
verter solves the problem of driving R1 D1
TO THE OTHER INVERTER
a high-side MOSFET, using a low- 340V
4.7 BYV26C
voltage transistor, Q1, and a special C1
+
C2
D2

arrangement involving D6 (Figure 1). 680 F 220 nF 12V

BYV26C R2 +
This inverter is much faster than those 22k
C3
D3 22 F D4
that optocouplers drive, so dead-time 1N4148 BYV28-50
problems are minimal. The inverter has Q1
D5
the usual blocking diodes D4 and D6, and C4
2N2907A
UF5406
the parallel diodes D5 and D8. Q3 provides 100 pF R3 R4
1M 22
the turn-off signal to Q2. When Q3 turns Q2
IRFP450
on, Q2’s gate short-circuits to ground
through R4. R4 limits current and damp- D6 OUTPUT
ens oscillations. Q2’s gate dis- BYV28-50
charges quickly; only the value Figure 1
D7
of R4 limits discharge time. Q1 stays off, 1N4148
D8
thanks to R2, and C3 charges to 12V This circuit is probably the Q3 UF5406
PWM
through D2. The gate pulse creates a cur- simplest high-voltage R5 IRFP450
rent through C4, and D3 protects the inverter you can build. 22

100 edn | May 27, 2004 www.edn.com

design
ideas
base-emitter junction of Q1. 12V inverter with 150% overload ca-
In the turn-on of Q2, the fol- pacity. If you change the MOS-
lowing scenario occurs: When FET, the value of C4 has to change
the control input, PWM, 1k
2N2222A according to the total gate charge
goes low, Q3 quickly turns Figure 2 plus the output capacitance of Q3,
off, thanks to D7. A displacement which is much lower and, in fact,
current, C4dV/dt, flows 2.2 nF 300
OUTPUT negligible. Q1 amplifies the ca-
through C4 to the base of Q1. Q1 1N4148 pacitor current, so C4 is propor-
charges the output capacitance tional to QG2hFE1. Make C4’s val-
INPUT
of Q3 and the gate capacitance of 2.2k ue no higher than necessary,
2N2222A
Q2, and Q2 turns on. C3 supplies 560 because the base current in Q1
the collector current. If the pe- would be too high. To obtain all
riod is long, Q1 keeps conduct- the speed advantages of the cir-
ing and compensating the leak- cuit, the PWM signal should be
age of Q3. If D6 were a Schottky This buffer enhances speed at the PWM input of Figure able to quickly drive Q3. If neces-
diode, which is leaky, you would 1’s circuit. sary, you can use a buffer circuit
have to reduce the value of R1. A (Figure 2). You can drive the cir-
short cross-conduction period exists be- current spikes. The inductor needs a cuit with a single CMOS gate. The circuit
tween the two MOSFETs, a phenomenon snubber comprising D1, R1, and C2. Note in Figure 1 is probably the simplest high-
that is more apparent when Q3 turns off that the inductor value is conservative voltage inverter you can design. It has
and Q2 turns on. A small inductor, L1, in and can be smaller. served in thousands of three-phase mo-
series with the main supply limits the The values are for a 370W, three-phase tor drives from 0.37 to 0.75 kW.왏

102 edn | May 27, 2004 www.edn.com