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Lab 7 & Lab 8 Designing a full Adder

Objective: This lab will teach you how to make a bigger circuit. For full adder we need 2 X-or gate, 3 NAND gate and one 3-input NOR gate. We can also implement the adder by using 2 X-or gate, 3 NAND, 1 NOR gate and 1 Inverter. So we will make the schematic of each of the gate and connect those. We will also draw the layout and run the simulation. This will be an open Lab. No groups, so student will work individually. The flexibility is you can come any time and finish the work. TA will present in the lab at the scheduled time. It can take more than 10 hours to finish the whole lab, so start as soon as possible. Grad Student: Will do 8-bit Adder. Undergrad Student: 1-bit full adder. Run the cadence. Create a library. Then create a New Cell View. Copy the previous cell views Nand, Nor or X-or gate to the new library. So you can use your previous drawing here. Follow the UTK Cadence tutorial to draw a schematic of all the basic gates using the ami06 library. Use the Tutorial link http://analog.ece.utk.edu/Cadence/utk_schematic.htm Note that for the AMI-0.6 process in which lambda = 0.3 micron. So L = 2*lambda = 0.6 micron = 600nm. Assume width, for n-type transistor: W = 3.0 micron. So W/L = 3.0/0.6 = 5. for p-type transistor: W = 3.0/0.6 = 10/2. You can also vary the the W/L ratio by changing the width.

Figure 1: Schematic of full Adder in cadence Creating the Symbol, http://analog.ece.utk.edu/Cadence/create_symbol.htm Simulationg by Spectra http://analog.ece.utk.edu/Cadence/spectre.htm

Figure 2 Pre Spectra Simulation of full Adder To get the overall layout we need to draw individual layout and then we need to connect all the layout. As all the transistor has same Height, so we can add all the gates side by side. The Transistor sizing is as follows: nfets pfets with with W/L W/L = = 10/2 10/2 (lambda) (lambda) = = 3.0/0.6 3.0/0.6

The layout topology that can be used for compact design: | XOR | | | p-n | Vdd | NAND/NOR | | | n-p | GND | | | | | Vdd XOR p-n | INV/NAND/NAND | | | | | | n-p | | | GND Vdd

Doing this topology is not strict. For other topology, think before doing the layout. For the I/O, let Ai and Bi enter from the left on poly and SUMi exit on the right on metal-2. The carry signals should align perfectly in the vertical dimension as well as the

Vdd and GND buses. You should have room to also let the Carry-in enter each bit-slice on the left in poly and the Carry-out exit on the right in metal-2. Only the LSB Carry-in and the MSB Carry-out need to be connected externally when you simulate the 8-bit adder.

Figure 3 Layout of 1-bit full Adder Follow the following link to get a good example of the whole design: http://vlsi1.engr.utk.edu/~nislam/hw3.html Before moving to Post Spectre Simulation we need to extract the adder layout. Go to verify > extract and click in the "Set Switch". Then choose "Extract_Parasitic_Caps" and press OK. After that press of in extract window. So you will find the extraction is done in the lab4 directory. The extraction of the layout is shown below:

Figure 4 Extraction of 1-bit full Adder

Then we need to generate the LVS http://analog.ece.utk.edu/Cadence/LVS.htm

whose

tutorial

is

as

follows:

Post layout simulatin by Spectra can be found here http://analog.ece.utk.edu/Cadence/postlayout_simulation.htm, see also the Pre-Spectra simulation at http://analog.ece.utk.edu/Cadence/spectre.htm

Figure 5 LVS of 1-bit full Adder

8-bit adder (For Grad Student only): 8-bit adder is the composition of eight 1-bit adder. So when you copied all the 1-bit adder side by side you will get the 8-bit adder.

Figure 6: Schematic of 8-bit full Adder in cadence To get the layout of 8-bit adder you need to add the layout of 1-bit adder side by side. So that all the VDD and GND is connected together.

Figure 7 Layout of 8-bit full Adder You also need to simulate the 8-bit full Adder. Show your LVS result & simulation waveform to the TA.