I/O organization

Peripheral Devices Computer device, such as a CD-ROM drive or printer, that is not part of the essential computer, i.e., the memory and microprocessor.

Peripheral devices can be external -- such as a mouse, keyboard, printer, monitor, external Zip drive or scanner -- or internal, such as a CDROM drive, CD-R drive or internal modem.
1

I/O organization
Peripheral Devices I/O Interface Asynchronous Data transfer Modes of Transfer Priority Interrupt Direct Memory Access(DMA) Input-Output processor Data communication processor
2

I/O organization
Input/Output Interfaces
Provides a method for transferring information between internal storage (Such as memory and CPU registers) and external I/O devices Resolves the differences between the computer and peripheral devices Peripherals-electromechanical devices CPU or Memory electronics device Data transfer rate Peripherals-usually slower CPU or Memory-Usually faster than peripherals , some kinds of synchronization mechanism may be needed
3

I/O organization
Input/Output Interfaces
Unit of Information Peripherals-byte CPU or Memory-Word Operating Modes Peripherals-Autonomous, Asynchronous CPU or Memory-synchronous
4

I/O BUS AND INTERFACE MODULES

I/O BUS and Interface Modules

The I/O bus consists of data lines, address lines, and control lines Each peripheral device has associated with it an interface unit. Each interface decodes the address and control received from the I/O bus, interprets them for the peripheral and provides signals for the peripheral controller.
6

I/O BUS and Interface Modules

The I/O bus from the processor is attached to all peripheral interfaces. The selected responds to the function code and proceeds to execute it. There are four types of commands that an interface may receive. They are classified as control, status, data output and data input.
7

I/O BUS and Interface Modules

A control command is issued to activate the peripheral and to inform it what to do. A status command is used to test various status conditions in the interface and the peripheral. A data output command causes the interface to respond by transferring data from the bus into one of its registers. A data input command is the opposite of the data output.
8

I/O BUS and Memory Bus

Functions of Buses MEMORY BUS is for information transfers between CPU and the Main Memory I/O BUS is for information transfers between CPU and I/O devices through their I/O interface Physical Organizations

I/O BUS and Memory Bus

Physical Organizations Many computers use a common single bus system for both memory and I/O interface units 2-way bus - Use one common bus but separate control lines for each function - Use one common bus with common control lines for both functions Some computer systems use two separate buses, one to communicate with memory and the other with I/O interfaces

10

I/O BUS and Memory Bus

I/O Bus -Communication between CPU and all interface units is via a common I/O Bus An interface connected to a peripheral device may have a number of data registers , a control register , and a status register A command is passed to the peripheral by sending to the appropriate interface register Function code and sense lines are not needed (Transfer of data, control, and status information is always via the common I/O Bus)
11

I/O versus Memory Bus

In addition to communicating with I/O, the processor must communicate with the memory unit. Like the I/O bus, the memory bus contains data, address, and read/write control lines. There are three ways that computer buses can be used to communicate with memory and I/O 1. Use two separate buses, one for memory and other for I/O

12

I/O versus Memory Bus

2. Use one common bus for both memory and I/O but have separate control lines for each 3. Use one common bus for memory and I/O with common control lines In the first method, the computer has independent sets of data, address and control buses, one for accessing memory and other for I/O. We need separate I/O processor for that to do these task

13

I/O versus Memory Bus

The memory communicates with both the CPU and the IOP through a memory bus. The IOP communicates also with the input and output devices through a separate I/O bus with its own address, data and control lines. The purpose of IOP is to provide an independent pathway for the transfer of information between external devices and internal memory.

14

Example of I/O interface

15

ISOLATED vs MEMORY MAPPED I/O

Isolated I/O Separate I/O read/write control lines in addition to memory read/write control lines Separate (isolated) memory and I/O address spaces Distinct input and output instructions

16

ISOLATED vs MEMORY MAPPED I/O

Memory-mapped I/O A single set of read/write control lines (no distinction between memory and I/O transfer) Memory and I/O addresses share the common address space reduces memory address range available No specific input or output instruction The same memory reference instructions can be used for I/O transfers Considerable flexibility in handling I/O operations

17

Isolated versus Memory-Mapped I/O

In the isolated I/O configuration, the CPU has distinct input and output instructions, and each of these instructions is associated with address of an interface register. When the CPU has distinct input and output instructions, and each of these instructions is associated with the address of an interface register. When the CPU fetches and decodes the operation code of an input or output instruction, it places the address associated with the instruction onto the common address lines. At the same time, it enables the I/O read (for input) or I/O write ( for output) control line.

18

Isolated versus Memory-Mapped I/O

This informs the external components that are attached to the common bus that the address in the address lines is for an interface register and not for a memory word. On the other hard, when the CPU is fetching an instruction or an operand from memory, it places the memory address on the address lines and enables the memory read or memory write control line. This informs the external components that the address is for memory word and not for an I/O interface.

19

Isolated versus Memory-Mapped I/O

When the CPU fetches and decodes the operation code of an input or output instruction, it places the address associated with the instruction onto the common address lines. At the same time, it enables the I/O read (for input) or I/O write ( for output) control line. This informs the external components that are attached to the common bus that the address in the address lines is for an interface register and not for a memory word. On the other hard, when the CPU is fetching an instruction or an operand from memory, it places the memory address on the address lines and enables the memory read or memory write control line. This informs the external components that the address is for memory word and not for an I/O interface.

20

Input Output Techniques

Programmed Interrupt driven Direct Memory Access (DMA)

21

Programmed I/O
CPU has direct control over I/O
Sensing status Read/write commands Transferring data

CPU waits for I/O module to complete operation Wastes CPU time

22

Programmed I/O - detail

CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically I/O module does not inform CPU directly I/O module does not interrupt CPU CPU may wait or come back later
23

I/O Commands
CPU issues address
Identifies module (& device if >1 per module)

CPU issues command

Control - telling module what to do
e.g. spin up disk

Test - check status

e.g. power? Error?

Read/Write
Module transfers data via buffer from/to device
24

Addressing I/O Devices

Under programmed I/O data transfer is very like memory access (CPU viewpoint) Each device given unique identifier CPU commands contain identifier (address)

25

I/O Mapping
Memory mapped I/O
Devices and memory share an address space I/O looks just like memory read/write No special commands for I/O
Large selection of memory access commands available

Isolated I/O
Separate address spaces Need I/O or memory select lines Special commands for I/O Limited set
26

Interrupt Driven I/O

Overcomes CPU waiting No repeated CPU checking of device I/O module interrupts when ready

27

Interrupt Driven I/O Basic Operation

CPU issues read command I/O module gets data from peripheral, CPU does other work I/O module interrupts CPU CPU requests data I/O module transfers data

28

CPU Viewpoint
Issue read command Do other work Check for interrupt at end of each instruction cycle If interrupted:Save context (registers) Process interrupt
Fetch data & store
29

Direct Memory Access

The transfer of data between a fast storage device such as magnetic disk and memory is often limited by the speed of the CPU. Removing the CPU from the path and letting the peripheral device manage the memory buses directly would improve the speed of transfer. This transfer technique is called direct memory access (DMA) A DMA controller takes over the buses to manage the transfer directly between the I/O device and memory.
30

Direct Memory Access(DMA)

31

Direct Memory Access

The CPU may be placed in an idle state in a difference of ways first common method extensively used in microprocessors is to disable the buses through special control signals. The bus request (BR) input is used by the DMA controller to request the CPU to release control of the buses.

32

DMA Controller
The DMA controller needs the usual circuits of an interface to communicate with the CPU and I/O device. In additional, it needs an address register, a word count register and a set of address lines. The address register and address lines are used for direct communication with the memory The word count register specifies the number of words that must be transferred.
33

DMA Controller
The data transfer may be done directly between the device and memory under control of DMA. The DMA controller has three resisters An address register A word count register A control register

a) b) c)

34

DMA Controller
The address register contains an address to specify the desired location in memory. The address bits go through bus buffers into the address bus. The address register is incremented after each word that is transferred to memory. The word count register holds the number of words to be transferred.
35

DMA Controller
This register is decremented by one after each word transfer. The control register specifies the mode of transfer. All registers in the DMA appear to the CPU as I/O interface register. Thus the CPU can read from or write into the DMA registers under program control via the data bus.
36

DMA Controller
The DMA first initialized by the CPU then after the DMA starts and continues to transfer data between memory and peripheral unit until an entire block is transferred. The initialization process is essentially a program consisting of I/O instructions that include the address for selecting particular DMA registers. The CPU initializes the DMA by sending the following information through the data bus:
37

DMA Controller
1.

2.

3.

4.

The starting address of the memory block where data are available for read) or where data are to be stored (for write) The word count, which is the number of words in the memory block Control to specify the mode of transfer such as read or write A control to start the DMA transfer
38

DMA Controller
The starting address is stored in the address register. The word count is stored in the word count register and the control information in the control register. Once the DMA is initialized, the CPU stops communicating with DMA unless it receives an interrupt signal or if it wants to check how many words have been transferred.
39

DMA TRANSFER

40

Direct Memory Access

Interrupt driven and programmed I/O require active CPU intervention
Transfer rate is limited CPU is tied up

DMA is the answer

41

DMA Function
Additional Module (hardware) on bus DMA controller takes over from CPU for I/O

42

DMA Operation
CPU tells DMA controller:Read/Write Device address Starting address of memory block for data Amount of data to be transferred

CPU carries on with other work DMA controller deals with transfer DMA controller sends interrupt when finished
43

DMA Transfer Cycle Stealing

DMA controller takes over bus for a cycle Transfer of one word of data CPU suspended just before it accesses bus
i.e. before an operand or data fetch or a data write

Slows down CPU but not as much as CPU doing transfer

44

DMA Configurations (1)

CPU

DMA Controller

I/O Device

I/O Device

Main Memory

Single Bus, Detached DMA controller Each transfer uses bus twice
I/O to DMA then DMA to memory

CPU is suspended twice

45

DMA Configurations (2)

CPU DMA Controller I/O Device I/O Device DMA Controller I/O Device Main Memory

Single Bus, Integrated DMA controller

Controller may support >1 device Each transfer uses bus once DMA to memory CPU is suspended once
46

DMA Configurations (3)

CPU DMA Controller I/O Device I/O Device I/O Device Main Memory I/O Device

Separate I/O Bus

Bus supports all DMA enabled devices Each transfer uses bus once DMA to memory CPU is suspended once
47

I/O Processors
The DMA controller introduced in the previous lecture can improve system performance by speeding up data transfers between memory and I/O devices. However, multiple transfers require separate DMA transfers, along with the necessary setup for each transfer. In some cases, data must be manipulated once it is read from the I/O device; the DMA controller can only transfer data.

48

I/O Processors
Each of these shortcomings is addressed by I/O processors. I/O processors, sometimes called I/O controllers, channel controllers or peripheral processing units (PPUs), perform the functions of DMA controllers and much more. The I/O processor is situated between the I/O devices and the rest of the system, very much like the DMA controller.
49

Input/output Processor (IOP)

50

I/O Processors
Unlike the DMA controller however, the I/O processor connects to more than one I/O device. The I/O devices are grouped together on an I/O bus, as opposed to the regular system bus. Thus, one I/O processor can coordinate transfers from several different I/O devices. Generally speaking , I/O processors handle all of the interactions between the I/O devices and the CPU.
51

I/O Processors
The CPUs only direct I/O interaction is with the I/O processor itself If the CPU must read in data from an I/O device or initiate a block transfer between an I/O device and memory, the CPU instructs the I/O processor to perform this task. The I/O processor coordinates the actual data transfer. The only exception is that the CPU coordinates the transfer of data between itself and the I/O processor.

52

Channel /CPU Communication

53

Data Communication Processor

A data communication processor is an I/O processor that distributes and collects data from many remote terminals connected through telephone and other communication lines. It is specialized I/O processor designed to communicate directly with data communication networks. An I/O processor communicates with peripherals through a common I/O bus that comprised of many data and control lines.
54

Data Communication Processor

A data communication processor communicates with each terminal through a single pair of wires. The way that remote terminals are connected to a data communication processor is via telephone lines or other public or private communication facilities. The converter are called modem. Data can be transmitted between two points in three different modes:
55

Data Communication Processor

1. 2.

3.

Simplex: 0ne direction only Half-duplex: transmitting in both directions but data can be transmitted in only one direction at a time. Need pair of wires. Full-duplex: transmission can send and receive data in both directions simultaneously

56