Data Converters

EECS 247 Lecture 16: Data Converters 2005 H.K.
Page 1
EE247
Lecture 16
D/A converters continued:
Current based DACs-unit element versus binary weighted
Static performance
Component matching-systematic & random errors
Practical aspects of current-switched DACs
Segmented current-switched DACs
DAC self calibration techniques
Current copiers
Dynamic element matching
ADC Converters
Sampling
Sampling switch induced distortion
Sampling switch charge injection
EECS 247 Lecture 16: Data Converters 2005 H.K. Page 2
Current Source DAC
Unit Element
Unit elements
2
B
-1 current sources & switches
Monotonicity does not depend on element matching
Suited for both MOS and BJT technologies
Output resistance of current source causes gain error
I
ref
I
ref
I
out
I
ref
I
ref

Current Source DAC
Unit Element
Output resistance of current source gain error problem
Use transresistance amplifier
- Current source output held @ virtual ground
- Error due to current source output resistance eliminated
- New issues: offset & speed of the amplifier
I
ref
I
ref
I
ref
I
ref
Vout
R
-
+
Current Source DAC
Binary Weighted
Binary weighted
B current sources & switches (2
B
-1 unit current
sources but less # of switches)
Monotonicity depends on element matching
4 I
ref
I
ref
I
out
2I
ref
2
B-1
I
ref

Static DAC INL / DNL Errors
Component matching
Systematic errors
Finite current source output resistance
Contact resistance
Edge effects in capacitor arrays
Process gradient
Random errors
Lithography
Often Gaussian distribution (central limit
theorem)
*Ref: C. Conroy et al, Statistical Design Techniques for D/A Converters, JSSC Aug. 1989, pp.
1118-28.
Gaussian Distribution
-3 -2 -1 0 1 2 3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
x /
P
r
o
b
a
b
i
l
i
t
y

d
e
n
s
i
t
y

p
(
x
)
( )
2
2
x
2
2 2
1
p( x ) e
2
where st andard devi at i on : E( x )

Yield
( )
2
x
X
2
X
P X x X
1
e dx
2
X
erf
2
| `

. ,
0
0.1
0.2
0.3
0.4
P
r
o
b
a
b
i
l
i
t
y

d
e
n
s
i
t
y

p
(
x
)
0 0.5 1 1.5 2 2.5 3
0
0.2
0.4
0.6
0.8
1
X
38.3
68.3
95.4
P
(
-
X

+
X
)
Yield
X/ P(-X x X) [%]
0.2000 15.8519
0.4000 31.0843
0.6000 45.1494
0.8000 57.6289
1.0000 68.2689
1.2000 76.9861
1.4000 83.8487
1.6000 89.0401
1.8000 92.8139
2.0000 95.4500
X/ P(-X x X) [%]
2.2000 97.2193
2.4000 98.3605
2.6000 99.0678
2.8000 99.4890
3.0000 99.7300
3.2000 99.8626
3.4000 99.9326
3.6000 99.9682
3.8000 99.9855
4.0000 99.9937
Example
Measurements show that the offset voltage of
a batch of operational amplifiers follows a
Gaussian distribution with = 2mV and = 0.
Fraction of opamps with |V
os
| < 6mV:
X/ = 3 99.73 % yield
Fraction of opamps with |V
os
| < 400V:
X/ = 0.2 15.85 % yield
Component Mismatch
R
R
1000
0
100
200
300
400
N
o
.

o
f

r
e
s
i
s
t
o
r
s
1004
1008
1012 996 992 988
R[ ]
Example: Side-by-side resistors
E.g. Let us assume in this example large # of Rs with
average of 1000OHM measured:
68.5% within +-4OHM or +-0.4% of average
1 for resistors0.4%
Large # of devices
measured & curved
typically if sample size is
large shape is Gaussian
. .
Component Mismatch
1 2
1 2
2
dR
R
R R
R
2
dR R R
1
Area
R
R
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
P
r
o
b
a
b
i
l
i
t
y

d
e
n
s
i
t
y

p
(
x
)
2
3 2 3
dR
R
Two side-by-side
Resistors
For typical technologies & geometries
1 for resistors0.02 5%
In the case of resistors is a function of area
DNL Unit Element DAC
i i ref
R I
DNL of unit element DAC is
independent of resolution!
E.g. Resistor string DAC:
I
ref
i
i
medi an ref
i i ref
medi an i
i
medi an
i
medi an
i
medi an medi an
DNL dR
R
R I
R I
DNL
R R
dR dR
R R R

V
ref
Example:
If
dR/R
= 0.4%, what
DNL spec goes into
the datasheet so that
99.9% of all converters
meet the spec?
DNL of unit element DAC is independent of resolution!
Note similar results for all unit-element based DACs
i
i
DNL dR
R

Yield
X/ P(-X x X) [%]
0.2000 15.8519
0.4000 31.0843
0.6000 45.1494
0.8000 57.6289
1.0000 68.2689
1.2000 76.9861
1.4000 83.8487
1.6000 89.0401
1.8000 92.8139
2.0000 95.4500
X/ P(-X x X) [%]
2.2000 97.2193
2.4000 98.3605
2.6000 99.0678
2.8000 99.4890
3.0000 99.7300
3.2000 99.8626
3.4000 99.9326
3.6000 99.9682
3.8000 99.9855
4.0000 99.9937
Example:
If
dR/R
= 0.4%, what DNL spec
goes into the datasheet so that
99.9% of all converters meet
the spec?
Answer:
From table: for 99.9%
X/ = 3.3
DNL
=
dR/R
= 0.4%
3.3
DNL
= 1.3%
DNL= +/- 0.013 LSB
i
i
DNL dR
R

DAC INL Analysis
B
A
N=2
B
-1
n
n
N
O
u
t
p
u
t

[
L
S
B
]
Input [LSB]
E
Ideal Variance
A=n+E n n.
2
B=N-n-E N-n (N-n).
2
E = A-n r =n/N N=A+B
= A-r(A+B)
= A (1-r) -B.r
Variance of E:
E
2
=(1-r)
2
.
2
+ r
2
.
B
2
=N.r .(1-r).
2
DAC INL
Error is maximum at mid-scale (N/2):
INL depends on DAC resolution and element matching

While
DNL
=
Ref: Kuboki et al, TCAS, 6/1982

2 2
E
2
E
B
INL
B
n
1 n
N
d
To f i nd max. vari ance: 0
dn
n N / 2
1
2 1
2
wi t h N 2 1

| `

. ,

Untrimmed DAC INL
Example:
Assume the following requirement:
INL
= 0.1 LSB
Then:
= 1% B = 8.6
= 0.5% B = 10.6
= 0.2% B = 13.3
= 0.1% B = 15.3
]
]
]

INL
B
INL
B
2
log 2 2
1 2
2
1
Simulation Example
= 1%
B = 12
Random #
generator used
in MatLab
Computed INL:
DNL
= 0.01 LSB
INL
= 0.3 LSB
(midscale)
500 1000 1500 2000 2500 3000 3500 4000
-1
0
1
2
bin
D
N
L

[
L
S
B
]
12 Bit converter DNL and INL
-0.04 / +0.03 LSB
500 1000 1500 2000 2500 3000 3500 4000
-1
0
1
2
bin
I
N
L

L
S
B
]
-0.2 / +0.8 LSB
Binary Weighted DAC INL/DNL
INL same as for unit element
DAC
DNL depends on transition
Example:
0 to 1
DNL
2
=
(d/)
2
1 to 2
DNL
2
= 3
(d/)
2
Consider MSB transition:
0111 1000
4 I
ref
I
ref
I
out
2I
ref
2
B-1
I
ref

MOS Device Matching Effects
d1 d2
d
d d1 d2
d d
W
d th L
W
GS d th L
I I
I
2
dI I I
I I
dI d dV
I V V
+
I
d1 I
d2
Current matching depends on:
- Device W/L ratio matching
Larger device area less mismatch effect
- Threshold voltage matching
Larger gate-overdrive less threshold voltage mismatch effect
Current-Switched DACs in CMOS
W
d t h L
W
d GS t h L
dI d dV
I V V
+
I
out
I
ref
Switch Array
Advantages:
Can be very fast
Small area for < 9-10bits
Disadvantages:
Accuracy depends on device W/L &V
th
matching
256 128 64 ....1
Example: 8bit Binary Weighted
Binary Weighted DAC DNL
( ) ( )
DNL
max
B
I NL DNL max
max
2 B 1 2 B 1 2
DNL
B 2
B/ 2
1 1
2 1
2 2
2 1 2
0111. . . 1000. . .
2
2
1442443 14243
Worst-case transition occurs at
mid-scale:
Example:
B = 12,
= 1%
DNL
= 0.64 LSB
INL
= 0.32 LSB
2 4 6 8 10 12 14
0
5
10
15
DAC input code
D
N
L
2
/

2
Another Random Run
Now (by chance) worst
DNL is mid-scale.
Close to statistical result!
500 1000 1500 2000 2500 3000 3500 4000
-2
-1
0
1
2
bin
D
N
L

[
L
S
B
]
DNL and INL of 12 Bit converter
-1 / +0.1 LSB,
500 1000 1500 2000 2500 3000 3500 4000
-1
0
1
2
bin
I
N
L

[
L
S
B
]
-0.8 / +0.8 LSB
Unit Element versus Binary Weighted DAC
Unit Element DAC Binary Weighted DAC
Number of switched elements:
Key point: Significant difference in performance and complexity!
B
2
B
2
DNL INL
1
INL
2 2
2
S B
B
2
DNL
1
INL
B
2
S 2

Unit Element versus Binary Weighted DAC
Example: B=10
B
2
DNL
1
INL
B
2 16
S 2 1024

Significant difference in performance and complexity!
B
2
B
2
DNL
1
INL
2 32
2 16
S B 10

Unit Element DAC Binary Weighted DAC
Number of switched elements:
DAC INL/DNL Summary
DAC architecture has significant impact on DNL
INL is independent of DAC architecture and requires
element matching commensurate with overall DAC
precision
Results are for uncorrelated random element
variations
Systematic errors and correlations are usually also
important
Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D
converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9.
Segmented DAC
Objective:
Compromise between unit element and binary weighted DAC
Approach:
B
1
MSB bits unit elements
B
2
LSB bits binary weighted
INL: unaffected
DNL: worst case occurs when LSB DAC turns off and one more MSB
DAC element turns on- same as binary weighted DAC with B
2
+1 bits
Number of switched elements: (2
B1
-1) + B
2
Unit Element Binary Weighted
V
Analog
MSB (B1 bits) (B2 bits) LSB

B
Total
= B
1
+B
2
Comparison
Example:
B = 12, B
1
= 5, B
2
= 7
B
1
= 6, B
2
= 6
= 1%
( ) B 1 2
2
B
2
DNL INL
1
INL
B1
2
2 2
2
S 2 1 B
+
4095
12
31+7=38
63+6=69
0.01
0.64
0.16
0.113
0.32
0.32
0.32
0.32
Unit element (12+0)
Binary weighted(0+12)
Segmented (5+7)
Segmented (6+6)
# of switched
elements
DNL[LSB]
INL[LSB]
DAC Architecture
MSB LSB
Practical Aspects
Current-Switched DACs
Unit element DACs ensure monotonicity by turning
on equal-weighted current sources in succession
Typically current switching performed by differential
pairs
Based on the code only one of the diff. pair devices
are ondevice mismatch not an issue
Issue: While binary weighted DAC can use the
incoming binary digital code directly, unit element
requires a decoder
N to (2
N
-1) decoder
Binary Thermometer
000 0000000
001 0000001
010 0000011
011 0000111
100 0001111
101 0011111
110 0111111
111 1111111
Segmented
Current-Switched DAC
4-bit MSB Unit
element DAC +
4-bit binary
weighted DAC
Note: 4-bit MSB
DAC requires
extra 4-to-16 bit
decoder
Digital code for
both DACs
stored in a
register
Segmented Current-Switched DAC
Contd
4-bit MSB
Unit element
DAC + 4-bit
binary
weighted
DAC
Note: 4-bit
MSB DAC
requires extra
4-to-16 bit
decoder
Digital code
for both
DACs stored
in a register
Contd
MSB Decoder
Domino logic
Example: D4,5,6,7=1
OUT=1
Register
Latched NAND gate:
CTRL=1 OUT=INB
Register
Domino Logic
IN
Reference Current Considerations
I
ref
is
referenced to
V
DD
Problem:
Reference
current
varies with
supply
voltage
+
-
Reference Current Considerations
I
ref
is
referenced to
V
ss
GND
+
-
Considerations
Example: 2-bit MSB
Unit element DAC +
3-bit binary
weighted DAC
To ensure
monotonicity at the
MSBLSB
transition: First OFF
MSB current source
is routed to LSB
current generator
Dynamic DAC Error: Glitch
Consider binary weighted
DAC transition 011 100
DAC output depends on
timing
Plot shows situation where
LSB/MSBs on time
LSB early, MSB late
LSB late, MSB early
1 1.5 2 2.5 3
0
5
10
I
d
e
a
l
1 1.5 2 2.5 3
0
5
10
E
a
r
l
y
1 1.5 2 2.5 3
0
5
10
Time
L
a
t
e
Glitch Energy
Glitch energy (worst case) proportional to: dt x 2
B-1
dt error in timing & 2
B-1
associated with half of the switches
changing state
LSB energy proportional to: T=1/f
s
Need dt x 2
B-1
<< T or dt << 2
-B+1
T
Examples:
<< 488
<< 1.5
<< 2
12
16
10
1
20
1000
dt [ps] B f
s
[MHz]
DAC Reconstruction Filter
Need for and
requirements depend
on application
Tasks:
Correct for sinc distortion
Remove aliases
(stair-case
approximation)
B f
s
/2
0 0.5 1 1.5 2 2.5 3
x 10
6
0
0.5
1
D
A
C

I
n
p
u
t
0 0.5 1 1.5 2 2.5 3
x 10
6
0
0.5
1
s
i
n
c
0 0.5 1 1.5 2 2.5 3
x 10
6
0
0.5
1
D
A
C

O
u
t
p
u
t
Frequency
Reconstruction Filter Options
Digital and SC filter possible only in combination with
oversampling (signal bandwidth B << f
s
/2)
Digital filter
Bandlimits the input signal prevent aliasin
Could also provide high-frequency pre-emphasis to
compensate in-band sinc amplitude droop associated with
the inherent DAC ZOH function
Di gi tal
Filter
DAC
SC
Fi l ter
ZOH
CT
Filter
DAC Implementation Examples
Untrimmed segmented
T. Miki et al, An 80-MHz 8-bit CMOS D/A Converter, JSSC
December 1986, pp. 983
A. Van den Bosch et al, A 1-GSample/s Nyquist Current-Steering
CMOS D/A Converter, JSSC March 2001, pp. 315
Current copiers:
D. W. J. Groeneveld et al, A Self-Calibration Techique for
Monolithic High-Resolution D/A Converters, JSSC December
1989, pp. 1517
Dynamic element matching:
R. J. van de Plassche, Dynamic Element Matching for High-
Accuracy Monolithic D/A Converters, JSSC December 1976, pp.
795
2 tech., 5Vsupply
6+2 segmented
8x8 array
Two sources of systematic error:
- Finite current source output resistance
- Voltage drop due to finite ground bus resistance
Current-Switched DACs in CMOS
( )
( )
( )
( )
M1
M2 M1
M3 M1
M4 M1
M2
M1
M1
M1
M1
M1
M1
M1
M1
2
GS th 1
GS GS
GS GS
GS GS
2
2
GS th 2 1
GS th
1
m
GS th
2
m
2 1 1 m
2
m
3 1 1 m
m
4 1
V V I k
V V 3RI
V V 5RI
V V 6RI
3RI
1
V V I k I
V V
2I
g
V V
3Rg
I I I 1 3Rg 1
2
5Rg
I I I 1 5Rg 1
2
6Rg
I I 1
2

| `
. ,
| `

. ,
| `

. ,
| `

. ,
( )
M1
2
1 m
I 1 6Rg
I
out
Assumption: RI is small compared to transistor gate overdrive
Desirable to have gm small
Example: 4 unit element current sources
V
DD
I
1
I
2
I
3
I
4
3RI 2RI RI
M
1
M
2
M
3
M
4
More recent published DAC using symmetrical switching built in 0.35micron/3V
(5+5)
I
I/2 I/2
Current
Divider
16bit DAC (6+10)- MSB DAC uses calibrated current sources
I
I/2 I/2
Ideal Current
Divider
Current Divider Accuracy
I
I/2+dI
d
/2
Real Current
Divider
M1& M2 mismatched
d1 d2
d
d d1 d2
d d
W
L d
t h
W
L d GS t h
I I
I
2
dI I I
I I
d
dI 2
dV
I V V
+
] | `
+
]
. , ]
I/2-dI
d
/2
M1 M2 M1 M2
Problem: Device mismatch could severely limit DAC accuracy
Dynamic Element Matching
( ) ( )
(1) ( 2 )
2 2
2
1 1 o
o
1
I I
I
2
1 1 I
2 2
I
f or smal l
2
+
+ +

( )
( )
(1)
1
o 1
1 2
(1)
1
o 1
2 2
I I 1
I I 1
+

/ 2 error
1
I
1
During
1
During
2
I
2
f
clk
I
o
I
o
/2 I
o
/2
( )
( )
( 2)
1
o 1
1 2
( 2)
1
o 1
2 2
I I 1
I I 1

+
Dynamic Element Matching
( )
( )
( )
( )( )
2 1 4
1
2
) 1 (
1 2
1 ) 1 (
3
1 2
1 ) 1 (
2
1 2
1 ) 1 (
1
1 1
1
1
1
+ +
+

+
o
o
o
I
I I
I I
I I ( )
( )
( )
( )( )
2 1 4
1
2
) 2 (
1 2
1 ) 2 (
3
1 2
1 ) 2 (
2
1 2
1 ) 2 (
1
1 1
1
1
1

+

o
o
o
I
I I
I I
I I
During
1
During
2
( )( ) ( )( )
( )
2 1
2 1 2 1
) 2 (
3
) 1 (
3
3
1
4
2
1 1 1 1
4
2
+
+ + +
o
o
I
I
I I
I
E.g.
1
=
2
= 1% matching error is (1%)
2
= 0.01%
/ 2 error
1
I
1
I
2
f
clk
I
o
I
o
/2
/ 2 error
2
I
3
I
4
f
clk
I
o
/4 I
o
/4
Summary
D/A Converter
D/A architecture
Unit element complexity proportional to 2
B
- excellent DNL
Binary weighted- complexity proportional to B- poor DNL
Segmented- unit element MSB(B
1
)+ binary weighted LSB(B
2
)complexity
proportional (2
B1
-1) + B
2
DNL compromise between the two
Static performance
Component matching
Dynamic performance
Glitches
DAC improvement techniques
Symmetrical switching rather than sequential switching
Current source self calibration
Dynamic element matching
MOS Sampling Circuits
Re-Cap
How can we
build circuits
that "sample"
Analog
Post processing
D/A
Conversion
DSP
A/D
Conversion
Analog
Preprocessing
Analog Input
Analog Output
000
...001...
110
Anti-Aliasing
Filter
Sampling
+Quantization
"Bits to
Staircase"
Reconstruction
Filter
Ideal Sampling
In an ideal world,
zero resistance
sampling switches
would close for the
briefest instant to
sample a continuous
voltage v
IN
onto the
capacitor C
Not realizable!
v
IN
v
OUT
C
S1
1
T=1/f
S
Ideal T/H Sampling
v
IN
v
OUT
C
S1
1
V
out
tracks input when switch is closed
Grab exact value of V
in
when switch opens
"Track and Hold" (T/H) (often called Sample & Hold!)
1
T=1/f
S
Ideal T/H Sampling
Continuous
Time
T/H signal
(SD Signal)
Clock
DT Signal
time
Practical Sampling
v
IN
v
OUT
C
M1
1
Switch induced noise power kT/C
Finite R
sw
limited bandwidth
R
sw
= f(V
in
) distortion
Switch charge injection
Clock jitter
kT/C Noise
In high resolution ADCs kT/C noise usually dominates
overall error (power dissipation considerations).
2
2
1 2
12
12
,
`
.
|
FS
B
B
B
V
T k C
C
T k
0.003 pF
0.8 pF
13 pF
206 pF
52,800 pF
8
12
14
16
20
C
min
(V
FS
= 1V) B
Acquisition Bandwidth
The resistance R of
switch S1 turns the
sampling network into a
lowpass filter with
risetime = RC =
Assuming V
in
is
constant during the
sampling period and C
is initially discharged
v
IN
v
OUT
C
S1
1
R
( )
/
1 ) (
t
in out
e v t v

Switch On-Resistance
Example:
B = 14, C = 13pF, f
s
= 100MHz
T/ >> 19.4, R << 40
v
IN
v
OUT
C
S1
1
T=1/f
S
R
( )
( )
1
2
1
2
Worst Case:
1
2
ln 2 1
1 1
2
ln 2 1
s
in out
s
f
in
in FS
B
B
s
V V t
f
V e
V V
T
R
f C
| `
<<

. ,
<<
<<
<<

Switch On-Resistance
( ) ( )
( )
( )
( )
0
1
,
2
1 1
1
for
1
DS
D triode
DS
D triode ox GS TH DS
ON DS
V
ON
ox GS th ox DD th in
o
ox DD th
o
ON
in
DD th
dI
W V
I C V V V
L R dV
R
W W
C V V C V V V
L L
R
W
C V V
L
R
R
V
V V
| `

. ,


Sampling Distortion
in
DD t h
out
T V
1
2 V V
i n
v
v 1 e

| `

. ,
| `

. ,
10bit ADC & T/ = 10
V
DD
V
th
= 2V V
FS
= 1V
Sampling Distortion
10bit ADC T/ = 20
V
DD
V
th
= 2V V
FS
= 1V
SFDR is very sensitive to
sampling distortion
Solutions:
OverdesignLarger
switches
increased switch
charge injection
Complementary switch
Maximize V
DD
/V
FS
decreased dynamic
range
Constant V
GS
? f(V
in
)

Data Converters

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EECS 247 Lecture 16: Data Converters 2005 H.K.

EECS 247 Lecture 16: Data Converters 2005 H.K. Page 3

EECS 247 Lecture 16: Data Converters 2005 H.K. Page 5

Ref: Kuboki et al, TCAS, 6/1982

EECS 247 Lecture 16: Data Converters 2005 H.K. Page 21

EECS 247 Lecture 16: Data Converters 2005 H.K. Page 26

EECS 247 Lecture 16: Data Converters 2005 H.K. Page 64

EECS 247 Lecture 16: Data Converters 2005 H.K. Page 65

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