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Agenda
Introduction Market Dynamics Technology & Equipment Xilinx Solutions Summary
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Targets users in a location with poor or nonexistent terrestrial infrastructure Early one-way systems capable of up to 400 kbps download, but used 56 kbps analog modem for upload New two-way systems expected to perform at 1 Mbps download and 500 kbps upload typically
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Challenges
Decreasing cost for equipment two-way terminals Latency needs to be improved Increasing capacity to mitigate shared bandwidth architecture Line of sight issues
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* Pioneer Consulting
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One-way Architecture
Satellite Access Service Provider Hub Station
Do wn loa d
Internet
PSTN
Upload
Home User
Home users dial-up connection to upload data to the service providers Hub station which forwards the request to the internet Requested data is broadcast back to home users via satellite Have fast download, but slow upload
Sufficient for normal web surfing, downloading, video/audio streaming
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Two-way Architecture
Do wn loa Up d loa d
Internet
Home User
Satellite transmission in both Download and Upload channels Download is a broadcast protocol and Upload is TDMA-based Much faster upload speeds compared to one-way architecture
Good for applications like video conferencing (high-bandwidth, two-way communication)
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Standards
Proprietary standards
DSS: Hughes Network Systems (HNS) proprietary
Open standard
DVB consortium standard: DVB (ETS 300-421) Recently proposed DVB Return Channel over Satellite (DVBRCS) as the standard for the return channel on newer two-way systems
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Xilinx Solutions
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Cost-optimized silicon and packaging System features reduce discrete parts on boards Stock one part for many applications
I O B I O B I O B I O B
B R A M
2ns
s 2n
2ns
CLB CLB
CLB CLB
CLB CLB
CLB CLB
CLB CLB
CLB CLB
B R A M
CLB
CLB
CLB
CLB
CLB
CLB
B R A M
Port B
I O B I O B
B R A M
CLB
CLB
CLB
CLB
CLB
CLB
CLB IOB
CLB IOB
CLB IOB
CLB IOB
CLB IOB
CLB IOB
B R A M
CL DLL
DLL CL
System I/OTM 19 signaling standards Chip to Backplane Chip to Memory Chip to Chip
Delay Lock Loops 200+ MHz performance 4 DLLs in every device Deskew 4 system Clks Zero-delay clock conv.
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ADC
ADC
Clock Generator
De-Interleaver RAM
USB Controller
QPSK/BPSK Demodulator
ODU
Viterbi Decoder
ReedSolomon Decoder
Descrambler
Data
FIFO
Clock
Tuner Interface
I/O
CPU
System Interconnectivity
RAM Flash
Decryption
RF In
RAM
Video Encoder
MPEG A/V
VIDEO
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AUDIO
Processor interface
Control registers, watchdog timer
10/100 MAC
Used to interface Satellite gateway to the 10/100 local network
Encryption
AES, DES, 3-DES
Block Diagram
Machine Status Reg
r3 1
I-LMB
Instruction Buffer
D-LMB
ply
PROCESSOR
CoreConnec t OPB I/F I-OPB
TM
UART
TM
Timer / Counters
PERIPHERALS
MicroBlaze Features
Processor
Powerful 32-bit RISC architecture Efficient Harvard-style busses Efficient 3-operand instruction word 100 D-MIPS (Dhrystone 2.1) 32-bit data path (non-multiplexed) 32-bit general purpose registers (32 registers) Fast operation 125MHz on Virtex-II (-5) FPGAs Minimal logic requirements uses less than 900 Logic Cells IBM CoreConnect bus for interconnect
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Peripheral set:
UART, GPIO Timer/Counter Interrupt Controller Watchdog Timer External Flash and SRAM interface Arbiter 10/100 Ethernet MAC SPI IIC
PSTN Internet
Router
Streaming Server
Cache
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1 Gbps SelectIO with ChipSync 500 MHz XtremeDSP Slice 10/100/1000 Ethernet MAC
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LX Platform
SX Platform
Unrivaled DSP performance Logic Memory DCMs DSP
Only FPGA with hard P & serial transceivers Logic Memory DCMs DSP RocketIO PowerPC
FX Platform
Choice of 17 Devices
Device XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 Logic Cells 13,824 24,192 41,472 59,904 80,640 110,592 152,064 200,448 23,040 34,560 55,296 12,312 19,224 41,904 56,880 94,896 142,128 Block RAM [Kb] 864 1,296 1,728 2,880 3,600 4,320 5,184 6,048 2,304 3,456 5,760 648 1,224 2,592 4,176 6,768 9,936 DCM 4 8 8 8 12 12 12 12 4 8 8 4 4 8 12 12 20 SelectIO 320 448 640 640 768 960 960 960 320 448 640 320 320 448 576 768 896 XtremeDSP Slice 32 48 64 64 80 96 96 96 128 192 512 32 32 48 128 160 192 PowerPC 1 1 2 2 2 2 10/100/ 1000 EMAC 2 2 4 4 4 4 RocketIO transceiver 8 12 16 20 24
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NOT TO SCALE
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Reg Reg
ICK1
OCK2
3-State
ICK2
OCK1
PAD
Output
Reg
OCK2
P N
25 I/O Standards XCITE Technology 840 Mbps LVDS Dedicated DDR Registers
DDR FF
IOB
Helps preserve investment in legacy designs Eases transition from parallel to serial technology Parallel interface designs will not go away
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BlockRAM BlockRAM XtremeDSP -- multipliers XtremeDSP multipliers DCM DCM XCITE technology -- DCI XCITE technology DCI SelectIO-Ultra SelectIO-Ultra Triple DES security Triple DES security IP-Immersion technology IP-Immersion technology
Virtex-II Features
50
50
4000XL
Virtex
Delay (ps)
Virtex-II
600 800 1000
LUTs Reached
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Networking / Telecom
1/10Gb Ethernet MACs - XAUI, XGMII 10/100 Mbps Ethernet MACs T1/E1 Framer/De-framer UTOPIA Level-2/3 PHY-ATM Network Classification Processor (2.5Gbps) HDLC Controller 8b/10b Encoder Decoder Cell Assembler/Delineation CRC10/32 Generator/Verifier ADPCM 16 - 1024 channels
SystemIO Interfaces
RapidIO PCI-X 64-bit / 100 MHz PCI 32/33, PCI 64/66 SPI-3, SPI-4 P1/P2, FlexBus 3/4, POS PHY L3/L4, SFI-4 CSIX, HyperTransport, 3GIO, Fibre Channel, Infiniband
Encryption
AES, DES, Triple DES
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Summary
Satellite Internet Access is a growing segment of the larger Broadband Access market
Is considered a niche market compared to DSL and Cable Access, but still significant
Xilinx provides Silicon and IP solutions for Satellite Broadband equipment at the SP and Customer Premises
Spartan IIE series of FPGAs is a solution for designs requiring low cost and high volume, e.g. modem Virtex-II & Virtex-II Pro are solutions for high-end designs requiring highest density and performance, e.g. gateway Suite of IP for Networking, System & Memory I/F, Processing
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