Beruflich Dokumente
Kultur Dokumente
DUAL, VOLTAGE MODE, DDR SELECTABLE, SYNCHRONOUS, STEP DOWN CONTROLLER FOR NOTEBOOK SYSTEM POWER
FEATURES D Wide Input Voltage Range: 4.5-V to 28-V D Selectable Dual and DDR Modes D Selectable Fixed Frequency Voltage Mode D Integrated Selectable Output Discharge D Advanced Power Good Logic Monitors both D D D D D D D D D
Channels Selectable Autoskip Mode Integrated Boot Strap Diodes 180 Phase Shift Between Channels Integrated 5-V, 60-mA Regulator Input Feedforward Control 1% Internal 0.85-V Reference RDS(on) Overcurrent Detection (4200 ppm/C) Integrated OVP, UVP and Power Good Timers 30-pin TSSOP Package
DESCRIPTION
The TPS51020 is a multi-function dualsynchronous step-down controller for notebook system power. The part is specifically designed for high performance, high efficiency applications where the loss associated with a current sense resistor is unacceptable. The TPS51020 utilizes feed forward voltage mode control to attain high efficiency without sacrificing line response. Efficiency at light load conditions can be maintained high as well by incorporating autoskip operation. A selectable, Suspend to RAM (STR) supported, DDR option provides a one chip solution for all switching applications from 5-V/3.3-V supply to a complete DDR termination solution.
ORDERING INFORMATION
TA 40C to 85C PLASTIC TSSOP (DBT) TPS51020DBT TPS51020DBTR (T&R)
APPLICATIONS D Notebook Computers System Bus and I/O D DDR I or DDR II Termination SIMPLIFIED APPLICATION DIAGRAM
VO1 1 INV1 2 COMP1 3 SSTRT1 4 SKIP VIN VO1 5 VO1_VDDQ 6 DDR 7 GND 8 REF_X 9 ENBL1 10 ENBL2 VO2 VREG5 11 VO2 12 PGOOD 13 SSTRT2 14 COMP2 VO2 15 INV2 TPS51020 OUT1_U LL1 OUT1_D OUTGND1 TRIP1 VIN TRIP2 VREG5 REG5_IN OUTGND2 OUT2_D LL2 OUT2_U VBST2 VBST1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VIN
VO1
VIN
VREG5 EXT_5V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
Operating free-air temperature, TA 40 85 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
TSSOP (0.5 mm) DBT PACKAGE (TOP VIEW) INV1 COMP1 SSTRT1 SKIP VO1_VDDQ DDR GND REF_X ENBL1 ENBL2 VO2 PGOOD SSTRT2 COMP2 INV2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VBST1 OUT1_U LL1 OUT1_D OUTGND1 TRIP1 VIN TRIP2 VREG5 REG5_IN OUTGND2 OUT2_D LL2 OUT2_U VBST2
ELECTRICAL CHARACTERISTICS
TA = 40C to 85C, 4.5 V < VIN < 20 V, CVIN = 0.1 F, CVREG5 = 2.2 F, CREF_X = 0.01 F, PGOOD = 0.2 V, ENBLx = DDR = VIN, INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND = OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated) PARAMETER INPUT CURRENTS IVIN IVIN(STBY) IVIN(SHDN) IVIN(REG5) IREG5 IVBSTx VIN supply current VIN standby current VIN shutdown current VIN supply current, REG5_IN as 5-V input current REG5_IN input supply current VBST supply current REG5V_IN = OPEN, OSC = OFF ENBLx = 0 V, REG5V_IN = OPEN, ENBLx = DDR = 0 V, REG5V_IN = OPEN REG5V_IN = 5 V, REG5V_IN = 5 V, ENBLx = DDR = VIN ENBLx = DDR = 0 V IOUT = 0 A 0 mA IOUT 50 mA, IOUT = 20 mA, High to low REG_IN voltage 4.8 VIN = 12 V 7 VVIN 28 V 3.45 100 4.2 50 OSC = OFF OSC = OFF TRIPx = VIN, DDR = VIN, OSC = OFF 1.4 350 0.05 200 1.0 0.05 0.05 5.0 2.2 550 1.00 500 1.7 1.00 1.00 5.2 mA A A A mA TEST CONDITIONS MIN TYP MAX UNIT
IVBSTx VBST shutdown current VREG5 INTERNAL REGULATOR VVREG5 VLD5 VLN5 VTHL VHYS(UV) VTH(SW) VHYS(SW) VREG5 voltage Load regulation Line regulation UVLO threshold voltage UVLO hysteresis Switchover voltage Switchover hysteresis
0.6% 2.5% 0.4% 2.0% 3.65 200 4.5 3.85 300 4.8 250 V mV V mV
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
IOUT = 100 A, 14 VVIN 28 V DDR = 0 V wrt VO1_VDDQ input divided by 2 VVO1 = 2.5 V 0 mA IO 3 mA Undervoltage PGOOD
VREFVTT VTT reference load regulation POWERGOOD COMPARATORS VTHDUAL(PG) PGOOD threshold (dual mode)
Overvoltage PGOOD, VO1_VDDQ = 2.5 V INVx > undervoltage PGOOD, Delay time from SSTRTx > 1.5 V to PGOOD going high DDR, ENBL1, ENBL2, SKIP DDR, ENBL1, ENBL2, SKIP DDR, ENBL1, ENBL2, SKIP= 5 V VVOUTx = 0.5 V, fault engaged Fault condition removed, restart DDR= VIN, DDR= 0 Sensed at INVx VO1_VDDQ = 2.5 V Sensed at INVx VO1_VDDQ = 2.5 V VOx = 5 V
TPG(del)
2048
clks
DIGITAL CONTROL INPUTS VIH VIL High-level input voltage, logic Low-level input voltage, logic 2.2 0.3 |1.0| 6 0.25 0.32 1.5 945 1.31 510 750 970 1.36 20 553 813 4096 VTRIPx = VIN 100 mV, VTRIPx = 100 mV, TA = 25C TA = 25C TA = 25C 11 10 13 13 4200 0 0 REF5V_IN = 4.8 V 3.7 100 3.9 200 |3.0| |5.0| 4.1 300 mV V mV 15 16 595 875 mV clks 1010 1.41 10 0.40 |1.0| V A V A M mV V s
IINLEAK Logic input leakage current VO1_VDDQ and VO2 RVOUT VVOUTOK VVO2LEAK RVOUT VOVPDUAL VOVPDDR TOVP(del) VUVPDUAL VUVPDDR TUVP(del) ITRIPSNK ITRIPSRC TCITRIP VOCPHI VOCPLO VVINUVLO VVINHYS VOx sink impedance VOx low restart voltage VOx input leakage current VO1_VDDQ input impedance OVP trip output threshold (dual) OVP trip output threshold (DDR) OVP propagation delay time(1) UVP trip output threshold (dual) UVP trip output threshold (DDR) UVP propagation delay time TRIPx sink current TRIPx source current TRIP current temperature coeficient(1) High-level OCP comparator offset voltage(1) Low-level OCP comparator offset voltage(1) VIN UVLO trip threshold VIN UVLO trip hysteresis
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
TEST CONDITIONS
MIN
TYP
MAX UNIT
0.86
VCHMM Channel 2 to channel 1 voltage mismatch CONTROL LOOP: SKIP HYSTERSTIC COMPARATOR AND ZERO CURRENT COMPARATOR VLLHYS Skip hysteresis comparator hysteresis(1) VLLOFF VZOFF THLTOLL THLTOHL IEASRC IEASNK FUGB AOL CMRCOMP IINVLEAK Lload hysteresis comparator offset(1) Zero current comparator offset(1) PWM skip delay time Skip to PWM delay time COMPx source current COMPx sink current Unity gain bandwidth(1) Open loop gain(1) COMPx voltage range(1)(6) INVx input current
|5.0| 3 1 18
mV
mV
clks
CONTROL LOOP ERROR AMPLIFIER mA MHz dB V A |0.5| 86% 84% 80% 88% 85% 82% 180 100 RSSTRTx = OPEN RSSTRTx = 1M or VSSTRT = 3 V 306 450 270 360 414 kHz ns
CONTROL LOOP: DUTY CYCLE, VOLTAGE RAMP, CHANNEL PHASE AND PWM DELAY PATH fOSC = 270 kHz(3) DCMAX PHCH Maximum duty cycle Channel to channel phase difference(5) OUTX_U minimum pulse width(1) Fast oscillator frequency initial accuracy(2) Slow oscillator frequency initial accuracy fOSC = 360 kHz fOSC = 450 kHz(2) PWM phase reversal only
fOSC(tc) Oscillator frequency over line and temperature Trimmed for 360 kHz (1) Ensured by design. Not production tested. (2) Maximum 450-kHz frequency can be achieved when both channels are enabled. (3) 270 kHz is the default frequency during start-up for both channels. (4) See Table 1. (5) See PWM detailed description
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
OUTPUTS: INTERNAL BST DIODE VFBST Forward voltage 0.80 0.1 3 3 2.5 2.5 100 0.85 0.5 10 10 5.0 5.0 ns V A
IRBST Reverse current OUTPUTS: N-CHANNEL MOSFET GATE DRIVERS RUSRC RDSRC RUSNK RDSNK OUTx_U source impedance OUTx_D source impedance OUTx_U sink impedance OUTx_D sink impedance
TDEAD Gate non-overlap dead time (1) Ensured by design. Not production tested. (2) Maximum 450-kHz frequency can be achieved only when both channels are enabled. (3) 270 kHz is the default frequency during start-up for both channels. (4) See Table 1. (5) See PWM detailed description (6) Feedforward Gain can be approximated as follows: VRAMP= K1VIN+B1, VOFFSET=K2VIN+B2 where K1=0.017, K2=0.01, B1=0.35 V, B2=0.4 V. At the running duty cycle, the VCOMP should be approximately: V COMP + V OUT (7) See waveform point A in Figure 1 (8) See waveform point B in Figure 1 (9) See waveform point C in Figure 1 K1 ) B1 ) (K2 VIN VIN ) B2)
1 M || CSSTRT to GND 1 M || CSSTRT to GND 270 (10) Although selection is made by placing a 1M resistor in parallel with the SSTRTx timing capacitor, the softstart time to 0.85V is altered by about only 20%.
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
ENBL1 ENBL2
ENBL1
ENBL2
C B A
3.6
C B
1.5 1.2 0 t0 t1 t2 t3 t4 t5
1.5 1.2 0 t0 t1 t2 t3 t4 t5
Figure 1
Figure 2
TERMINAL FUNCTIONS
TERMINAL NAME COMP1 COMP2 NO. 2 14 I/O O O Error amplifier output. Connect feedback network to this pin and INVx for compensation of control loop. DDR selection pin. If this pin is grounded, the device runs in DDR Mode. The error amplifier reference for VO2 is (VO1_VDDQ)/2, the REF_X output voltage becomes (VO1_VDDQ)/2 and skip mode is disabled for VO2, Also, VREG5 is turned off when both ENBLx are at low in this mode. If this pin is at 2.2-V or higher, the device runs in ordinary dual SMPS mode (dual mode), then the error amplifier reference for VO2 is connected to internal 0.85-V reference, the REF_X output voltage becomes 10 V, VREG5 is kept on regardless of ENBLx status. CAUTION: Do not toggle DDR while ENBL1 or ENBL2 are high. (See Table 2) TTL Enable Input. If ENBLx is greater than 2.2 V, then the VREG5 is enabled (DDR mode) and the SMPS of that channel attempts to turn on. If both ENBL1 and ENBL2 are low then the 10-V (or (VO1_VDDQ)/2 output) voltage as well as the oscillator are turned off. (See Table 2) Signal ground pin. Error amplifier inverting input. Also input for skip comparator, and OVP/UVP comparators. Switch-node connection for high-side driver and overcurrent protection circuitry. Synchronous N-channel MOSFET driver output. High-side N-channel MOSFET driver output. Ground return for OUTx_D. DESCRIPTION
DDR
ENBL1 ENBL2 GND INV1 INV2 LL1 LL2 OUT1_D OUT2_D OUT1_U OUT2_U OUTGND1 OUTGND2
9 10 7 1 15 28 18 27 19 29 17 26 20
I I O I I I/O I/O O O O O O O
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
PGOOD
12
REF_X
21 3 13 4
I I I I
TRIP1
25
TRIP2
23
30 16 5
I I I
11 22 24
I O I
VREG5 VIN
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
10
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
CASCADE CONFIGURATION
If the TRIP2 pin is tied through a resistor to the input voltage, the TPS51020 assumes that the conversion voltage for channel two is the VIN voltage, usually VBATT. Conversely, if TRIP2 is tied through a resistor to ground, the controller assumes that the conversion voltage for channel two is the output voltage of channel one or some other stable bus voltage.
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
12
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
The soft-start capacitor is discharged upon UVLO, OVP or UVP is detected as well as ENBLx is set low.
D REXTERNAL is the series resistor between VOx and the output D RDS(on) = 6
When grounded, corresponding channel disables the low-side MOSFET during softstart until the high-side MOSFET attempts to turn on. This allows the user to start up with precharged output.
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13
TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
APPLICATION INFORMATION 10-V N-CHANNEL FET BIAS or (VOUT1)/2 VTT VOLTAGE REFERENCE (REF_X)
TPS51020s REF_X provides two functions depending on the operational mode. One is a linear regulator that supply 10-V for FET switch biasing in the dual mode, the other is VTT reference voltage in the DDR mode. If DDR is high ( > 2.2 V) then the REF_X output is a convenient 10-V, 2-mA (maximum) output, useful for biasing N-channel FET switches typically used to manage S0, S3 and S5 sleep states where the main supply is switched to many outputs. When VIN is < 12 V, REF_X approximately tracks VIN2 V. If DDR is low, then the REF_X output becomes the VDDQ/2 (VO1_VDDQ/2) reference. This output is capable of 5-mA source current and is left on even if channel two (VTT switcher) is turned off. REF_X is turned off if ENBL1 and ENBL2 are both low (see Table 2).
POWERGOOD
The TPS51020 has advanced powergood logic that allows single powergood circuit to monitor both SMPS output voltages (see Figure 3 ).
VOUT1
VOUT2
2048 c
PGOOD
ENBL2
t0
t1
t2
Figure 3. PowerGood Timing Diagram The PGOOD terminal is an open drain output. The PGOOD pin remains low until both power supplies have started and have been in regulation ( 7.5%) for 2048 clock pulses.
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
APPLICATION INFORMATION
If one channel is enabled in the period between T0 and T1, (the other channels ramp time plus delay time,) the PGOOD delay counter restarts counting softstart finish after the last channel has finished softstart. Enabling after T1 is ignored by PGOOD until the channel finishes its softstart. If either of the SMPS output goes out by 7.5% or UVLO is detected while ENBLx is high, PGOOD pulls low. If a channel is disabled while the other is still active PGOOD maintains its logic state and only monitor the active channel.
PROTECTION FUNCTIONS
The TPS51020 is equipped with input undervoltage lock out (UVLO), output undervoltage protection (UVP) and overvoltage (OVP) protection. Overcurrent is detected using RDS(on) of the external power MOSFETs and protected by triggering UVP, or latch off in some cases. The states of output drive signal depends on which protection was involved. Please refer to each protection description below for the detail. When the input voltage UVLO is tripped, the TPS51020 resets and waits for the voltage to rise up over the threshold voltage and restart the device. Alternatively, if output UVP or OVP is triggered, the device latches off after a delay time defined by the internal fault counter counting the PWM oscillator pulses. The VREF5 and REF_X is kept on in this latch off condition. The fault latch can be reset by toggling both of ENBLx pins in DDR mode. The fault latch can be reset by either toggling VIN or bringing DDR, ENBL1 and ENBL2 all low. Be sure to bring DDR high prior to ENBLx when TPS51020 is being used in dual mode. If a false trip of the UVLO appears due to input voltage sag during turn-on of the high-side MOSFET such as a large load transient, first consider adding several micro-farads of input capacitance close to the MOSFETs drain. Also consider adding a small VIN filter, ex. a 2.2- resistor and a 2.2-F, for decoupling. The trip resistors should be connected to the same node as VIN pin of the device when this filter is applied. The filter resistor should be as small as possible since a voltage drop across this resistor biases the OCP trip point.
OVERVOLTAGE PROTECTION
For overvoltage protection (OVP), the TPS51020 monitors INVx voltage. When the INVx voltage is higher than 0.95V (+12%), the OVP comparator output goes high (after a 20-s delay) and the circuit latches the top MOSFET driver OFF, and bottom driver ON for the SMPS detected overvoltage. In addition, the output discharge (softstop) function is enabled to discharge the output capacitor if VO1_DDR, VO2 is connected to corresponding output terminal. The fault latch can be reset by either toggling VIN or bringing DDR, ENBL1 and ENBL2 all low. Be sure to bring DDR high prior to ENBLx when TPS51020 is being used in dual mode.
UNDERVOLTAGE PROTECTION
For undervoltage protection (UVP), the TPS51020 monitors INVx voltage. When the INVx voltage is lower than 0.55 V (35 %), the UVP comparator output goes high, and the internal FLT timer starts to count PWM oscillator pulses. After 4096 clock pulses, the part latches off. Both top and bottom drivers are turned off at this condition. Output discharge (soft-stop) function is enabled to discharge the output capacitor if VO1_DDR, VO2 is connected to corresponding output terminal. The fault latch can be reset by either toggling VIN or bringing DDR, ENBL1 and ENBL2 all low. Be sure to bring DDR high prior to ENBLx when TPS51020 is being used in dual mode.
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15
TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
10 *6
Precaution should be taken with board layout in order to design OCP point as desired. The conversion voltage point must avoid high current path. Any voltage difference between the conversion point and VIN input for the TPS51020 is included in the threshold voltage. VIN plane layout should consider the other channels high-current path as well. A brief discussion is required for TRIP2 function. When TRIP2 is connected, via a resistor to GND, only low-side OCP is used. This is the case for cascade configuration been selected. In this mode, UVP does not play a roll in the shut off action and there is only a short delay between the over current trigger level been hit and the power MOSFETs turn off. However, as with UVP, the SSTRTx pins are discharged and both SMPS goes though a restart.
LAYOUT CONSIDERATIONS
Below are some points to consider before the layout of the TPS51020 design begins.
D Signal GND and power GND should be isolated as much as possible, with a single point connection
between them.
D All sensitive analog components such as INV, SSTRT, SKIP, DDR, GND, REF_X, ENBL and PGOOD
should be reference to signal GND and be as short as possible.
D The source of low-side MOSFET, the Schottky diode anode, the output capacitor and OUTGND should be
referenced to power GND and be as short and wide as possible, otherwise signal GND is subject to the noise of the outputs.
D PCB trace defined as the node of LL should be as short and wide as possible. D Connections from the drivers to the gate of the power MOSFET should be as short and wide as possible
to reduce stray inductance and the noise at the LL node.
D The drain of high-side MOSFET, the input capacitor and the trip resistor should be as short and wide as
possible. For noise reduction, a 22-pF capacitor CTRIP can be placed in parallel with the trip resistor.
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
APPLICATION INFORMATION
D The output voltage sensing trace and the feedback components should be as short as possible and be
isolated from the power components and traces.
D The low pass filter for VIN should be placed close to the TPS51020 and be referenced to signal GND. D The bootstrap capacitor CBST (connected from VBST to LL) should be placed close to the TPS51020. D VREG5 requires at least 4.7-F bypass capacitor which should be placed close to the TPS51020 and be
referenced to signal GND.
D The discharge (VO1_VDDQ, VO2) should better have a dedicated trace to the output capacitor. In case of
limiting the discharge current, series resistors should be added.
D Ideally, all of the area directly under the TPS51020 chip should also be signal GND.
TPS51020 1 INV1 2 COMP1 3 SSTRT1 4 SKIP 5 VO1_VDDQ 6 DDR 7 GND 8 REF_X 9 ENBL1 10 ENBL2 11 VO2 12 PGOOD 13 SSTRT2 14 COMP2 15 INV2 VBST1 30 OUT1_U 29 LL1 28 L_FET1 OUT1_D 27 OUTGND1 26 TRIP1 25 Rvin Signal GND VIN 24 Cin TRIP2 23 VREG5 22 Cvreg5 REG5_IN 21 CH2 Output Voltage (GND) OUTGND2 20 OUT2_D 19 L_FET2 LL2 18 OUT2_U 17 VBST2 16 CBST2 Cin2 Co2 CH2 Output Voltage (+) + L02 H_FET2 Rtrips Ctrip2 Cvinbp Power GND Input Voltage (GND) Input Voltage (+) + Co1 CH1 Output Voltage (GN CBST1 Cin1 H_FET1 L01 Rtrip1 Ctrip1 CH1 Output Voltage (+) +
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17
TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
APPLICATION INFORMATION
C01a GND C12 R101 R101 100k R03 100k 10k C15 0.01u 100k R02 330 6800p R01 C14 49.7k 3900p R04 1.8k C08 0.1u 1 2 3 4 5 6 7 (10V_REF ) 8 INV1 COMP1 SSTRT1 SKIP VO1_VDDQ DDR GND REF_X TPS51020 VBST1 30 OUT1_U 29 LL1 28 OUT1_D 27 OUTGND1 26 TRIP1 25 VIN 24 TRIP2 23 VREG5 22 REG5_IN 21 OUTGND2 20 OUT2_D 19 LL2 18 OUT2_U 17 VBST2 16 C03 R11 330 28.8k C22 2200p R07 100k Q03 3300p 2.7k C11 0.1u R15 15 R202 51k R203 51k Q15 C01a : Sanyo 35SVPD22M C01c, C02, C03, C27 : Taiyo Yuden GMK325BJ225MHB C04a, C05a : Panasonic EEFUE0J151R Q01, Q03 : Fairchild FDS6612A Q02, Q04 : Fairchild FDS6690S L01, L02 : Sumida CEP1254R0MCH 2.2ux2 4u Q14 R14 18k R13 18k C27 0 R16 0 C01c Q12 C13 4.7u GND GND 51k R201 51k 2.2u R12 15 Q02 C02 2.2ux2 L01 4u C04a C04c Q10 150u GND 0.01u R200 Q11 5V_X 5V_OUT Q01 22u VBAT 8 V to 20 V
R102
9 ENBL1 10 ENBL2 11 VO2 C19 0.01u R09 GND R10 10k C20 R08 12 PGOOD 13 SSTRT2 14 COMP2 15 INV2
GND
3.3V_OUT
Q13 3.3V_X
GND
9 ENBL1 10 ENBL2 11 VO2 C19 0.01u 12 PGOOD 13 SSTRT2 14 COMP2 15 INV2 GND R10 C20 R08
C05b
150u
18
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
APPLICATION INFORMATION
C01a GND C12 4700p R01 R101 100k R102 R03 100k 3.9k C15 0.01u 1 2 3 4 5 6 7 (VO1_VDDQ/2_REF ) 8 INV1 COMP1 SSTRT1 SKIP VO1_VDDQ DDR GND REF_X TPS51020 VBST1 30 OUT1_U 29 LL1 28 OUT1_D 27 OUTGND1 26 TRIP1 25 VIN 24 TRIP2 23 VREG5 22 REG5_IN 21 OUTGND2 20 OUT2_D 19 LL2 18 OUT2_U 17 16 VBST2 C04d R11 1.2k 19.7k C22 2200p R07 100k 2.5V_OUT R15 15 Q03 6800p 3.9k C11 0.1u 150u 5.6u L02 R02 1.2k C14 7.62k 4700p R04 4.7k C08 0.1u C04a 150u 150u GND 0.01u R12 15 L01 Q02 5.6u C04b C04c 2.5V_OUT C02 2.2ux2 Q01 22u VBAT 8 V to 20 V
R13 18k C27 0 (EXT_5V ) R14 18k GND GND R16 0 C01c 2.2u C13 4.7u
9 ENBL1 10 ENBL2 11 VO2 C19 0.01u 12 PGOOD 13 SSTRT2 14 COMP2 15 INV2 R08
Q04 C05a
C05b
GND R10
C20
150u
C01a C01c, C02, C27 C04a, C05a, C04b, C05b,C04d Q01, Q03 Q02, Q04 L01, L02
: Sanyo 35SVPD22M : Taiyo Yuden GMK325BJ225MHB : Panasonic EEFUE0J151R : Fairchild FDS6612A : Fairchild FDS6690S : Sumida CEP1255R6MCH
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs JUNCTION TEMPERATURE
2.5 VVIN = 12 V IVIN(SHTDWN) Shutdown Current nA 120
2.0
100
80
1.5
60
1.0
40
20
0.5 50
50
100
150
0 50
50
100
150
TJ Junction Temperature C
TJ Junction Temperature C
Figure 8
TRIP CURRENT vs JUNCTION TEMPERATURE
25 VTRIP VVIN = 0.1 V ITRIPSINK TRIP1 Sink Current A 20 ISSQ SSRTx Charge Current A
Figure 9
SOFTSTART CURRENT vs JUNCTION TEMPERATURE
2.50 2.45 VVIN = 12 V VSSTRTx = 1 V
2.40 2.35
15
2.30 2.25
10
2.20 2.15
2.10 50
150
Figure 10
Figure 11
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
SOFTSTART TIME vs SOFTSTART CAPACITANCE
100 k VVIN = 12 V TA = 25C 10 k tSS Softstart Time s fOSC Oscillator Frequency kHz 450 500 VVIN = 12 V fOSC(HI)
1k
100
10
200 50
50
100
150
TJ Junction Temperature C
Figure 12
UNDERVOLTAGE PROTECTION THRESHOLD vs JUNCTION TEMPERATURE
VUVP Undervoltage Protection Trip Voltage mV 900 VOVP Overvoltage Protection Trip Voltage mV VVIN = 12 V 850 800 750 700 650 600 550 DDR = HI 500 50 0 50 100 150 DDR = LO VVO1_VDDQ = 2.5 V 1400 VVIN = 12 V 1300
Figure 13
OVERVOLTAGE PROTECTION THRESHOLD vs JUNCTION TEMPERATURE
1200
1100
1000
900
DDR = HI
800 50
TJ Junction Temperature C
150
Figure 14
Figure 15
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
VREG5 OUTPUT VOLTAGE vs VREG5 OUTPUT CURRENT
5.2 5.1 VVREG5 VREG5 Output Voltage V 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 0 20 40 60 80 100 t Time 100 ms / div IVREG VREG5 Output Current mA fOSC= 290 kHz VIN = 20 V, VOUT1 = 2.5 V 1 A IOUT1 6 A, 1A/ms IOUT1 2 A/div VVIN = 12 V TA = 25C VOUT1 50 mV/div
Figure 16
VOUT1 1 V/div
PGOOD 2 V/ div
PGOOD 2 V/ div
t Time 5 ms / div
t Time 5 ms / div
22
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TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
VDDQ Disabled S5
VTT Disabled S3 VOUT1 2 V/div VOUT2 2 V/div VTT (1 V/div) fOSC = 290 kHz VVO1 = 5 V t Time 5 ms / div t Time 5 ms / div
VVIN = 12 V VVIN = 20 V Efficiency % Efficiency % 60 VVIN = 20 V 40 VVIN = 12 V 20 fOSC = 290 kHz VVO1 = 5 V 0 0.01 0.1 1 10 0 0.01 20 fOSC = 290 kHz VVO1 = 5 V 0.1 1 IOUT Output Current A 10 60
VVIN = 8 V 40
Figure 22
Figure 23
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23
TPS51020
SLUS564B JULY 2003 REVISED DECEMBER 2003
VVIN = 12 V
VVIN = 20 V
40
40
20 fOSC = 290 kHz VVO1 = 2.5 V 0 0.01 0.1 1 IOUT Output Current A 10
Figure 24
Figure 25
24
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16-Aug-2005
PACKAGING INFORMATION
Orderable Device TPS51020DBT TPS51020DBTG4 TPS51020DBTR TPS51020DBTRG4
(1)
Pins Package Eco Plan (2) Qty 30 30 30 30 60 60 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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