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Kultur Dokumente
S.SANGAMESHWAR RAO
ENGINEERING PHYSICS IIT DELHI
OVERVIEW
Metallization Importance of Multilevel metallization
RC Time Delay
Interconnection materials
Metals Junction spiking, Stress migration, Electromigration Properties of Al, Cu, W etc Dielectrics Diffusion Barriers and Adhesion Promoters
Metallization processing
PVD, CVD, Electroplating Damascene Process Chemical Mechanical Polishing
Conclusion References
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Metallization
Metallization is the process that makes accessible the IC to the outside world through conducting pads. Doped silicon conduct electricity but have large resistance and lack interconnecting facility Thin conductive metal films (Al, Cu, Au, Ag etc) are used as interconnects between Si and external leads
Global Interconnects First Level Dielectric Local Interconnects
RC
R
W Ls
Dielectric
Metal
Global Interconnect
R=L WH C = HL Ls RC = L2 WLs
Ref: Multilevel interconnections for ULSI era, S.P.Murarka, MSE, R(19), 4 87-151
Lower resistivity metal for interconnect wiring Lower dielectric constant material for the interlayer dielectric Smaller wire lengths-Multilevel Metallization
Vias Global Interconnects Second level dielectric First Level Dielectric Local Interconnects
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Ref: Modified Picture from SILICON VLSI TECHNOLOGY By Plummer et al
Design flexibility
Interconnection materials
Metals
Metal Issues
Junction spiking Electromigration Stress migration
Important metals
Aluminum Copper Tungsten Silver, Gold
Metals Requirements
Low resistivity Easy to deposit Easy to etch and planarize High melting point
High electromigration resistance
Metals Requirements.contd
Controlled microstructure
Preferably uniform large grains and smooth surfaces
Oxidation/corrosion resistance
Low chemical reactivity Ideally passivates itself
Compatible with surrounding materials and their processing Bondable to wirings in package Environmentally safe material during processing and actual use, and recyclable Reliable Low cost
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Metals
Property\Metal Resistivity Youngs modulus(x10-11 dyn cm-2) Thermal conductivity(Wcm-1) Coeff. of thermal expansion CTE x 106(0C-1) M.P (0C) Specific heat capacity(Jkg-1K-1) Corrosion in air Adhesion to SiO2 Delay Thermal stress per degree for films on Si(x107 dyn cm-2 0C-1) Cu 1.67 12.98 3.98 17 1085 38 Poor Poor 2.3 2.5 Ag 1.59 8.27 4.25 19.1 962 234 Poor Poor 2.2 1.9 Au 2.35 7.85 3.15 14.2 1064 132 Excellent Poor 3.2 1.2 Al 2.66 7.06 2.358 23.5 660 917 Good Good 3.7 2.1 W 5.65 41.1 1.74 4.5 3387 138 Good Poor 7.8 0.8
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Aluminum
Early ICs used pure Al as the interconnect material Low resistivity Strong adhesion with Si Corrosion resistant
Problems with pure Al Junction spiking Electromigration Stress migration Later ICs used Al alloyed with Cu
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Junction spiking
Consider Al-Si contact
Solubility of Si in Al is 0. 5 wt% at 4500C Si will dissolve into the Al during annealing (at 4500C)
Solution
Add Si to the Al
Al spikes
Introduce a barrier metal layer between the Al and the Si substrate. (TiN)
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Stress migration
Due to difference between coefficient of thermal expansion for Al and Si Al 23 x 10-6 0C-1 and Si 2.6 x 10-6 0C-1 High compressive stresses in Al at high temperatures Movement of Al occurs along grain boundaries Whole grains of Al pushed upward forming hillocks Under tensile stress voids are formed
Al hillock
Compressive stress (due to thermal expansion difference between film and substrate)
Grain Boundary
Al SiO2 Si substrate
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Stress migrationcontd
Consequences Electrical shorts between interconnect levels Rough surface topography making lithography and etch difficult
Solution
Addition of elements that have limited solubility Ex:- Cu atoms segregate and precipitate preferentially along the grain boundaries suppressing hillock formation
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Electromigration
Transport of mass in metals under the influence of high current Occurs by transfer of momentum from electrons to the positive metal ions High current densities in the smaller devices are responsible for electron migration Grain boundary diffusion is the primary vehicle of mass transport Metal in some regions pile up and voids form in other regions
Void Hillock formation Al film SiO2
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Electron Flow
Solutions - Electromigration
Oxide
Current Flow
Al Ti Void
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Tungsten
Good corrosion resistance Electromigration and stress migration stability Excellent deposition methods Sometimes used for filling of vias called plugs High resistivity Poor adhesion (Adhesion promoter required-Ti/TiN)
Gold
Low resistivity
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Copper
Benefits
Higher conductivity More electromigration resistance Higher ultimate tensile strength Higher melting point, low CTE Higher thermal conductivity, high specific heat, lesser Joule heating
Draw backs
Lack of feasible dry etching method Lack of self passivating oxide similar to Al2O3 on Al Poor adhesion to dielectric materials such as SiO2 and low-k polymers
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Silicides
Silicon forms stable metallic compound (MSix) with metal, called silicide Low resistivity and high thermal stability of metal silicides make them suitable for VLSI applications Silicides be used as local interconnects and adhesion promoters
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Dielectrics
Dielectric Requirements Small dielectric constant High breakdown voltage Good adhesion High temperature stability Low stress Some dielectrics Conventional SiO2-high dielectric constant-high RC delay New materials Fluorine doped SiO2 ~3 Polymers ~1.9-2.9 Aerogels ~1.01-2.0
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Sputtering
DC, RF sputtering Magnetron sputtering
CVD Electroplating
Vias Global Interconnects Second level dielectric First Level Dielectric Local Interconnects
Evaporation
E-Beam Evaporation
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Sputter Deposition
Simple DC sputtering is used for elemental metal deposition For deposition of insulating materials such as SiO2, Si3N4, an RF plasma is used Application of magnetic field increases ion bombardment rate Magnetic sputtering
Earlier generation ICs- Evaporation Present technique Sputtering- Better step coverage
Ref: Prof.S.Kal, IIT Kharagpur
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Step Coverage
Conformal step coverage refers to uniform thickness on both horizontal and vertical surfaces In evaporation, the deposition species travel essentially in straight lines because of very low pressure Step coverage is very poor
Solution:
1) Rotate the wafer
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Bias sputtering
If substrate and deposited films are conductive, it is possible to adjust the bias on the substrate with respect to the plasma Placing a negative bias on the substrate, the ion bombardment of the substrate is increased Since the sputter etched film may redeposit on the wafer if sputtered at low bias, a net improvement in the step coverage may be achieved
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Silicide Deposition
Direct deposition and selective etching
Sputtering from a composite target Co-sputtering from two targets Co-evaporation of metal and Si CVD
31 Ref: Multilevel interconnections for ULSI era, S.P.Murarka, MSE, R(19), 87-151
Aluminum
CVD not good for alloys
Unwanted reactions between the precursors for the various metals
Heat the wafers to 150-3500C-To improve step coverage Further high temperatures 450-5500C For filling deep contacts and vias
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Etching
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Copper
Step coverage poor with PVD methods Electroplating
Cu2+ + 2eCu Thin seed layer (Cu) is required for electrical contact for electroplating Seed layer by sputtering or CVD
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Damascene Technology
Via and trench formation Adhesion and Barrier Layer deposition Chemical Mechanical Planarization Second Level Dielectric Deposition Via and trench formation
Damascene Technology
Trench first approach Via first approach
Major Drawback of Trench first approach: After trench formation, photoresist completely pools down into the trench Forming fine vias in thick photoresists becomes problem Via first approach is most preferred
Ref: www.icknowledge.com/threshold_simonton/techtrends01.pdf
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Components Mechanism
Combination of chemical and mechanical effects Abrasive particles in slurry grind against material and loosens it Chemicals in slurry etch and dissolve the material Chemicals help in damage free sample Surface to be polished (Wafer) Slurry abrasive + chemical component Polishing pad
Fig: Schematic set-up for CMP
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Ref: http://www.agc.co.jp/english/products/semiconductor/cmp.html
After CMP
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Conclusion
Interconnect parameter now dominate nearly all aspects of IC performance such as delay, power dissipation, and electromigration Multi level metallization reduces the RC delay Different physical properties of the materials and deposition techniques have to be considered Sometimes multilayer structures may have to be used (adhesion & barrier layers etc) Al as the interconnect material has limitations, Cu is being used now But even Cu has some limitations. New technologies like damascene, CMP have been developed to overcome the limitations of etching etc
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References
1. Multilevel interconnections for ULSI era, S.P.Murarka, Materials Science and Engineering, R(19), 87-151 2. 3. 4. 5. SILICON VLSI TECHNOLOGY By Plummer et al VLSI Metallization, Prof.S.kal, IIT Kaharagpur Microchip Fabrication, Peter van Zant, Mc Graw hill Fundamentals of Semiconductor Processing Technologies, Badih-el Kareh, Kluwer Academic Publishers 6. 7. 8. Semiconductor Devices Physics and Technology, S.M.Sze, Wiley http://www.agc.co.jp/english/products/semiconductor/cmp.html www.icknowledge.com/threshold_simonton/techtrends01.pdf
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