ZIG-BEE BASED HOME AUTOMATION CONTROL

ABSTRACT
The main aim of this project is to provide automation based on zig-bee transceiver modules for home / office/ industries. In this project Zig-bee modules are used to transmit and receive data. One module is interfaced on micro controller. The second module is connected to the PC. The module connected to the PC is used as transmitter, through which commands are issued to the micro controller. The module connected to the PC receives the command from the PC received by the user/ operator and transmits the received commands to the zig-bee module connected to the micro controller unit. After receiving the commands the zig-bee module send the data to the micro controller through MAX-232. The micro controller then analyses by the zig-bee then performs the necessary action according to the command. With the we can operate the remote devices in the home/ office/ industry using zigbee.

UNDERSTANDING OF: Embedded controller, Zig-bee module, IR sensor, Keil Compiler, Embedded C.

Power supply

MAX 232

Device 1
Zig-bee modem Device 2
Micro Controller

Device 3

Zig-bee modem

PC

INTRODUCTION TO EMBEDDED SYSTEMS

EMBEDDED SYSTEM:An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions, sometimes with real-time computing constraints. It is usually embedded as part of a complete device including hardware and mechanical parts. In contrast, a general-purpose computer, such as a personal computer, can do many different tasks depending on programming. Embedded systems have become very important today as they control many of the common devices we use. Since the embedded system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance. Some embedded systems are mass-produced, benefiting from economies of scale. Physically, embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure. In general, "embedded system" is not an exactly defined term, as many systems have some element of programmability. For example, Handheld computers share some elements with embedded systems such as the operating systems and microprocessors which power them but are not truly embedded systems, because they allow different applications to be loaded and peripherals to be connected.

An embedded system is some combination of computer hardware and software, either fixed in capability or programmable, that is specifically designed for a particular kind of application device. Industrial machines, automobiles, medical equipment, cameras, household appliances, airplanes, vending machines, and toys (as well as the more obvious cellular phone and PDA) are among the myriad possible hosts of an embedded system. Embedded systems that are programmable are provided with a programming interface, and embedded systems programming is a specialized occupation. Certain operating systems or language platforms are tailored for the embedded market, such as Embedded Java and Windows XP Embedded. However, some low-end consumer products use very inexpensive microprocessors and limited storage, with the application and operating system both part of a single program. The program is written permanently into the system's memory in this case, rather than being loaded into RAM (random access memory), as programs on a personal computer are.

APPLICATIONS OF EMBEDDED SYSTEM

We are living in the Embedded World. You are surrounded with many embedded products and your daily life largely depends on the proper functioning of these gadgets. Television, Radio, CD player of your living room, Washing Machine or Microwave Oven in your kitchen, Card readers, Access Controllers, Palm devices of your work space enable you to do many of your tasks very effectively. Apart from all these, many controllers embedded in your car take care of car operations between the bumpers and most of the times you tend to ignore all these controllers.

In recent days, you are showered with variety of information about these embedded controllers in many places. All kinds of magazines and journals regularly dish out details about latest technologies, new devices; fast applications which make you believe that your basic survival is controlled by these embedded products. Now you can agree to the fact that these embedded products have successfully invaded into our world. You must be wondering about these embedded controllers or systems. What is this Embedded System? The computer you use to compose your mails, or create a document or analyze the database is known as the standard desktop computer. These desktop computers are manufactured to serve many purposes and applications. You need to install the relevant software to get the required processing facility. So, these desktop computers can do many things. In contrast, embedded controllers carryout a specific work for which they are designed. Most of the time, engineers design these embedded controllers with a specific goal in mind. So these controllers cannot be used in any other place.

Theoretically, an embedded controller is a combination of a piece of microprocessor based hardware and the suitable software to undertake a specific task. These days designers have many choices in

microprocessors/microcontrollers. Especially, in 8 bit and 32 bit, the available variety really may overwhelm even an experienced designer. Selecting a right microprocessor may turn out as a most difficult first step and it is getting complicated as new devices continue to pop-up very often. In the 8 bit segment, the most popular and used architecture is Intel's 8031. Market acceptance of this particular family has driven many semiconductor manufacturers to develop something new based on this particular architecture. Even after 25 years of existence, semiconductor manufacturers still come out with some kind of device using this 8031 core.

 Military and aerospace software applications:From in-orbit embedded systems to jumbo jets to vital battlefield networks, designers of mission-critical aerospace and defense systems requiring real-time performance, scalability, and high-availability facilities consistently turn to the LynxOS RTOS and the LynxOS-178 RTOS for software certification to DO178B. Rich in system resources and networking services, LynxOS provides an off-theshelf software platform with hard real-time response backed by powerful distributed computing (CORBA), high reliability, software certification, and longterm support options.

The LynxOS-178 RTOS for software certification, based on the RTCA DO178B standard, assists developers in gaining certification for their mission- and safety-critical systems. Real-time systems programmers get a boost with LynuxWorks' DO-178B RTOS training courses. LynxOS-178 is the first DO-178B and EUROCAE/ED-12B certifiable, POSIX-compatible RTOS solution.

 Communications applications:"Five-nines" availability, CompactPCI hot swap support, and hard real-time responseLynxOS delivers on these key requirements and more for today's carrier-class systems. Scalable kernel configurations, distributed computing capabilities, integrated communications stacks, and fault-management facilities make LynxOS the ideal choice for companies looking for a single operating system for all embedded telecommunications applicationsfrom complex central controllers to simple line/trunk cards. LynuxWorks Jumpstart for Communications package enables OEMs to rapidly develop mission-critical communications equipment, with pre-integrated, state-ofthe-art, data networking and porting software componentsincluding source code for easy customization. The Lynx Certifiable Stack (LCS) is a secure TCP/IP protocol stack designed especially for applications where standards certification is required.

 Electronics applications and consumer devices:As the number of powerful embedded processors in consumer devices continues to rise, the BlueCat Linux operating system provides a highly reliable and royalty-free option for systems designers. And as the wireless appliance revolution rolls on, web-enabled navigation systems, radios, personal communication devices, phones and PDAs all benefit from the cost-effective dependability, proven stability and full product life-cycle support opportunities associated with BlueCat embedded Linux. BlueCat has teamed up with industry leaders to make it easier to build Linux mobile phones with Java integration. For makers of low-cost consumer electronic devices who wish to integrate the LynxOS real-time operating system into their products, we offer special MSRPbased pricing to reduce royalty fees to a negligible portion of the device's MSRP.  Industrial automation and process control software:Designers of industrial and process control systems know from experience that LynuxWorks operating systems provide the security and reliability that their industrial applications require. From ISO 9001 certification to fault-tolerance, POSIX conformance, secure partitioning and high availability, we've got it all. Take advantage of our 20 years of experience.

MICROCONTROLLER VERSUS MICROPROCESSOR

What is the difference between a Microprocessor and Microcontroller? By microprocessor is meant the general purpose Microprocessors such as Intel's X86 family (8086, 80286, 80386, 80486, and the Pentium) or Motorola's 680X0 family (68000, 68010, 68020, 68030, 68040, etc). These microprocessors contain no RAM, no ROM, and no I/O ports on the chip itself. For this reason, they are commonly referred to as general-purpose Microprocessors. A system designer using a general-purpose microprocessor such as the Pentium or the 68040 must add RAM, ROM, I/O ports, and timers externally to make them functional. Although the addition of external RAM, ROM, and I/O ports makes these systems bulkier and much more expensive, they have the advantage of versatility such that the designer can decide on the amount of RAM, ROM and I/O ports needed to fit the task at hand. This is not the case with Microcontrollers.

A Microcontroller has a CPU (a microprocessor) in addition to a fixed amount of RAM, ROM, I/O ports, and a timer all on a single chip. In other words, the processor, the RAM, ROM, I/O ports and the timer are all embedded together on one chip; therefore, the designer cannot add any external memory, I/O ports, or timer to it. The fixed amount of on-chip ROM, RAM, and number of I/O ports in Microcontrollers makes them ideal for many applications in which cost and space are critical. In many applications, for example a TV remote control, there is no need for the computing power of a 486 or even an 8086 microprocessor.

MICROCONTROLLERS FOR EMBEDDED SYSTEMS

In the Literature discussing microprocessors, we often see the term Embedded System. Microprocessors and Microcontrollers are widely used in embedded system products. An embedded system product uses a microprocessor (or Microcontroller) to do one task only. A printer is an example of embedded system since the processor inside it performs one task only; namely getting the data and printing it. Contrast this with a Pentium based PC. A PC can be used for any number of applications such as word processor, print-server, bank teller terminal, Video game, network server, or Internet terminal. Software for a variety of applications can be loaded and run. Of course the reason a pc can perform myriad tasks is that it has RAM memory and an operating system that loads the application software into RAM memory and lets the CPU run it. In an Embedded system, there is only one application software that is typically burned into ROM. An x86 PC contains or is connected to various embedded products such as keyboard, printer, modem, disk controller, sound card, CD-ROM drives, mouse, and so on. Each one of these peripherals has a Microcontroller inside it that performs only one task. For example, inside every mouse there is a Microcontroller to perform the task of finding the mouse position and sending it to the PC. Table 1-1 lists some embedded product

AT89S51 MICRO CONTROLLER

Description:

The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. The AT89S51 provides the following standard features: 4K bytes of flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a Five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.
Pin Description:

VCC: Supply voltage GND: Ground PORT 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.

PORT 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low. will source current (IIL) because of the internal pull-ups Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The PORT 2: Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The PORT 3: Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table. Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (timer 0 external input)

P3.5 P3.6 P3.7

T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe)

RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. Address Latch Enable (ALE) is an output pulse for latching the ALE/PROG: low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. Program Store Enable (PSEN) is the read strobe to external program PSEN: memory. When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP: External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming. XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2: Output from the inverting oscillator amplifier

Memory Organization:
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

Program Memory:

If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory
.

Data Memory:

The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.

TIMER/COUNTERS:
The AT89S51 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. All two can be configured to operate either as Timers or event Counters.

TIMER 0 REGISTERS:

The 16-bit register of Timer 0 is accessed as low byte and high byte. The low byte register is called TL0 (Timer 0 Low byte) and the high register is referred to as TH0 (Timer 0 High byte).
---------------------------TH0--------------------------D15 D14 D13 D12 D11 D10 D9 Timer 0 Registers D8 ----------------------TL0--------------------------D7 D6 D5 D4 D3 D2 D1 D0

TIMER 1 REGISTERS:

The 16-bit register of Timer 1 is accessed as low byte and high byte. The low byte register is called TL1 (Timer 1 Low byte) and the high register is referred to as TH1 (Timer 1 High byte).
--------------------------TH1------------------------------------------------TL1--------------------------

D15 D14 D13 D12 D11 D10 D9 Timer 1 Registers

D8

D7

D6

D5

D4

D3

D2

D1

D0

TMOD REGISTER:

Both timers 0 and 1 use the same register, called TMOD, to set the various timer operation modes. TMOD is an 8-bit register in which the lower 4 bits are set aside for timer 0 and the upper 4 bits for timer 1. In each case, the lower 2 bits are used to set timer mode and the upper 2 bits to specify the operation.
MSB GATE C/T Timer 1 M1 M0 GATE C/T Timer 2 M1 LSB M0

GATE:

When TRx (in TCON) is set and GATE=1, TIMER/COUNTERx will run only while pin is high (hardware control). When GATE=0, TIMER/COUNTERx will run only while TRx=1 (software control).
C/ T:

Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin). M1: Mode selector bit. M0: Mode selector bit.

M1

M0

Mode Operating Mode 0 1 2 3 . 13-bit Timer mode. 16-bit Timer/Counter 8-bit auto-load Timer/Counter Splits Timer 0 into TL0 and TH0. TL0 is an 8-bit controller by the standard Timer 0 control bits. TH0 is an 8 bit Timer and is controlled by Timer 1 control bits.) Timer/Counter 1 stopped.

0 0 0 1 1 0 1 1 Timer/Counter

As a Timer, the register is incremented every machine cycle. Thus, the register counts machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. As a Counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 and T1. The external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. Interrupts: The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown below

EA

ES

ET1

EX1

ET0

EX0

Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. Symbol Position Function Disables all interrupts. If EA = 0, no interrupt is EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ES ET1 EX1 ET0 EX0 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 Reserved Reserved Serial Port interrupt enable bit Timer 1 interrupt enable bit External interrupt 1 enable bit Timer 0 interrupt enable bit External interrupt 0 enable bit

EA IE.7 acknowledged. If

Idle Mode: In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special function registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. Power-down Mode: In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated is restored to its normal operating level and must be held active long enough to allow before VCC the oscillator ssto restart and stabilize. . 8051 micro controller architecture:
The 8051 architecture consists of these specific features:

y y y y

Eight bit CPU with registers A (the accumulator) and B Sixteen-bit program counter (PC) and data pointer (DPTR) Eight- bit stack pointer (PSW) Eight-bit stack pointer (Sp)

y y

Internal ROM or EPROM (8751) of 0(8031) to 4K (8051) Internal RAM of 128 bytes: 1. Four register banks, each containing eight registers 2. Sixteen bytes, which maybe addressed at the bit level 3. Eighty bytes of general- purpose data memory

y y y y y y

Thirty two input/output pins arranged as four 8-bit ports:p0-p3 Two 16-bit timer/counters: T0 and T1 Full duplex serial data receiver/transmitter: SBUF Control registers: TCON, TMOD, SCON, PCON, IP, and IE Two external and three internal interrupts sources. Oscillator and clock circuits.

4.4.5. 8051 PIN DIAGRAM:

FUNCTIONAL BLOCK DIAGRAM OF MICROCONTROLLER

Fig4.3: Functional block diagram of micro controller

4.4.7. The 8051 Oscillator and Clock:

The heart of the 8051 circuitry that generates the clock pulses by which all the internal all internal operations are synchronized. Pins XTAL1 And XTAL2 is provided for connecting a resonant network to form an oscillator. Typically a quartz crystal and capacitors are employed. The crystal frequency is the basic internal clock frequency of the microcontroller. The manufacturers make 8051 designs that run at specific minimum and maximum frequencies typically 1 to 16 MHz.

Fig 4.4: Oscillator and timing circuit

4.4.8. Types of memory:

The 8051 have three general types of memory. They are on-chip memory, external Code memory and external Ram. On-Chip memory refers to physically existing memory on the micro controller itself. External code memory is the code memory that resides off chip. This is often in the form of an external EPROM. External RAM is the Ram that resides off chip. This often is in the form of standard static RAM or flash RAM.

4.4.8.1. Program memory:

Code memory is the memory that holds the actual 8051 programs that is to be run. This memory is limited to 64K. Code memory may be found on-chip or off-chip. It is possible to have

4K of code memory on-chip and 60K off chip memory simultaneously. If only off-chip memory is available then there can be 64K of off chip ROM. This is controlled by pin provided as EA.

4.4.8.2. Data memory RAM:

The 8051 have a bank of 128 bytes of internal RAM. The internal RAM is found on-chip. So it is the fastest Ram available. And also it is most flexible in terms of reading and writing. Internal Ram is volatile, so when 8051 is reset, this memory is cleared. 128 bytes of internal memory are subdivided. The first 32 bytes are divided into 4 register banks. Each bank contains 8 registers. Internal RAM also contains 128 bits, which are addressed from 20h to 2Fh. These bits are bit addressed i.e. each individual bit of a byte can be addressed by the user. They are numbered 00h to 7Fh. The user may make use of these variables with commands such as SETB and CLR.

4.4.8.3. Special Function registers:

Special function registers are the areas of memory that control specific functionality of the 8051 micro controller.

a) Accumulator (0E0h)
As its name suggests, it is used to accumulate the results of large no of instructions. It can hold 8 bit values.

b) B register (0F0h)
The B register is very similar to accumulator. It may hold 8-bit value. The b register is only used by MUL AB and DIV AB instructions. In MUL AB the higher byte of the product gets stored in B register. In div AB the quotient gets stored in B with the remainder in A.

c) Stack pointer (81h)

The stack pointer holds 8-bit value. This is used to indicate where the next value to be removed from the stack should be taken from.When a value is to be pushed onto the stack, the 8051 first store the value of SP and then store the value at the resulting memory location. When a value is to be popped from the stack, the 8051 returns the value from the memory location indicated by SP and then decrements the value of SP.

d) Data pointer

The SFRs DPL and DPH work together work together to represent a 16-bit value called the data pointer. The data pointer is used in operations regarding external RAM and some instructions code memory. It is a 16-bit SFR and also an addressable SFR.

e) Program counter
The program counter is a 16 bit register, which contains the 2 byte address, which tells the 8051 where the next instruction to execute to be found in memory. When the 8051 is initialized PC starts at 0000h. And is incremented each time an instruction is executes. It is not addressable SFR.

f) PCON (power control, 87h)

The power control SFR is used to control the 8051s power control modes. Certain operation modes of the 8051 allow the 8051 to go into a type of sleep mode which consume much lee power. Table 4.1:PCON Register

g) TCON (timer control, 88h)

The timer control SFR is used to configure and modify the way in which the 8051s two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related bits are located in TCON SFR. These bits are used to configure the way in which the external interrupt flags are activated, which are set when an external interrupt occurs. Table 4.2:PCON Register

h) TMOD (Timer Mode, 89h)

The timer mode SFR is used to configure the mode of operation of each of the two timers. Using this SFR your program may configure each timer to be a 16-bit timer, or 13 bit timer, 8-bit auto reload timer, or two separate timers. Additionally you may configure the timers

to only count when an external pin is activated or to count events that are indicated on an external pin.

Table 4.3:TMOD Register

i) TO (Timer 0 low/high, address 8A/8C h)

These two SFRs taken together represent timer 0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value.

j) T1 (Timer 1 Low/High, address 8B/ 8D h)

These two SFRs, taken together, represent timer 1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up..

k) P0 (Port 0, address 90h, bit addressable)

This is port 0 latch. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port 0 is pin P0.0, bit 7 is pin p0.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.

l) P1 (port 1, address 90h, bit addressable)

This is port latch1. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port 0 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level

m) P2 (port 2, address 0A0h, bit addressable) :

This is a port latch2. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port 0 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.

n) P3(port 3,address B0h, bit addressable)

This is a port latch3. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port 0 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level

o) IE (interrupt enable, 0A8h):

The Interrupt Enable SFR is used to enable and disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where the MSB bit is used to enable or disable all the interrupts. Thus, if the high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt is enabled by setting a lower bit. Table 4.4 :IE Register

p) IP (Interrupt Priority, 0B8h)

The interrupt priority SFR is used to specify the relative priority of each interrupt. On 8051, an interrupt maybe either low or high priority. An interrupt may interrupt interrupts. For e.g., if we configure all interrupts as low priority other than serial interrupt. The serial interrupt always interrupts the system, even if another interrupt is currently executing. However, if a serial interrupt is executing no other interrupt will be able to interrupt the serial interrupt routine since the serial interrupt routine has the highest priority. Table 4.5: IP Register

q) PSW (Program Status Word, 0D0h)

The program Status Word is used to store a number of important bits that are set and cleared by 8051 instructions. The PSW SFR contains the carry flag, the auxiliary carry flag, the parity flag and the overflow flag. Additionally, it also contains the register bank select flags, which are used to select, which of the R register banks currently in use. Table4.6: PSW Register

r) SBUF (Serial Buffer, 99h)

SBUF is used to hold data in serial communication. It is physically two registers. One is writing only and is used to hold data to be transmitted out of 8051 via TXD. The other is read only and holds received data from external sources via RXD. Both mutually exclusive registers use address 99h.

4.4.9. I/O ports:

One major feature of a microcontroller is the versatility built into the input/output (I/O) circuits that connect the 8051 to the outside world. The main constraint that limits numerous functions is the number of pins available in the 8051 circuit. The DIP had 40 pins and the success of the design depends on the flexibility incorporated into use of these pins. For this reason, 24 of the pins may each used for one of the two entirely different functions which depend, first, on what is physically connected to it and, then, on what software programs are used to program the pins.

4.4.9.1. PORT 0:
Port 0 pins may serve as inputs, outputs, or, when used together, as a bi directional low-order address and data bus for external memory. To configure a pin as input, 1 must be written into the corresponding port 0 latch by the program. When used for interfacing with the external memory, the lower byte of address is first sent via PORT0, latched using Address latch enable (ALE) pulse and then the bus is turned around to become the data bus for external memory.

4.4.9.2. PORT 1:
Port 1 is exclusively used for input/output operations. PORT 1 pins have no dual function. When a pin is to be configured as input, 1 is to be written into the corresponding Port 1 latch.

4.4.9.3. PORT 2:
Port 2 may be used as an input/output port. It may also be used to supply a high order address byte in conjunction with Port 0 low-order byte to address external memory. Port 2 pins are momentarily changed by the address control signals when supplying the high byte a 16bit address. Port 2 latches remain stable when external memory is addressed, as they do not have to be turned around (set to 1) for data input as in the case for Port 0.

4.4.9.4. PORT 3:
Port 3 may be used to input /output port. The input and output functions can be programmed under the control of the P3 latches or under the control of various special function registers. Unlike Port 0 and Port 2, which can have external addressing functions and change all eight-port b se, each pin of port 3 maybe individually programmed to be used as I/O or as one of the alternate functions. The Port 3 alternate uses are:

Table-4.7: Port 3 Alternate Uses

Pin (SFR)
P3.0-RXD (SBUF) P3.1-TXD (SBUF) P3.2-INTO 0 (TCON.1) P3.3 - INTO 1 (TCON.3) P3.4 - T0 (TMOD) P3.5 T1 (TMOD)

Alternate Use
Serial data input Serial data output External interrupt 0 External interrupt 1 External Timer 0 input External timer 1 input

P3.6 - WR

External memory write pulse

P3.7 - RD

External memory read pulse

4.4.10. INTERRUPTS:

Interrupts are hardware signals that are used to determine conditions that exist in external and internal circuits. Any interrupt can cause the 8051 to perform a hardware call to an interrupt handling subroutine that is located at a predetermined absolute address in the program memory. Five interrupts are provided in the 8051. Three of these are generated automatically by the internal operations: Timer flag 0, Timer Flag 1, and the serial port interrupt (RI or TI) Two interrupts are triggered by external signals provided by the circuitry that is connected to the pins INTO 0 and INTO1. The interrupts maybe enable or disabled, given priority or otherwise controlled by altering the bits in the Interrupt Enabled (IE) register, Interrupt Priority (IP) register, and the Timer Control (TCON) register. . These interrupts are

mask able i.e. they can be disabled. Reset is a non maskable interrupt which has the highest priority. It is generated when a high is applied to the reset pin. Upon reset, the registers are loaded with the default values. Each interrupt source causes the program to do store the address in PC onto the stack and causes a hardware call to one of the dedicated addresses in the program memory. The appropriate memory locations for each for each interrupt are as follows: Table-4.8: Interrupts

Interrupt
RESET

Address
0000

IE0 (External interrupt 0) 0003 TF0 (Timer 0 interrupt) 000B

IE1 (External interrupt 1) 0013 TF1 (Timer 1 interrupt) SERIAL 001B 0023

2. ZigBee
ZigBee is the name of a specification for a suite of high level communication protocols using small, low-power, low data rate digital radios based on the IEEE 802.15.4 standard for wireless personal area networks (WPANs), such as wireless headphones connecting with cell phones via short-range radio. The technology is intended to be simpler and cheaper than other WPANs, such as Bluetooth. ZigBee is targeted at radio-frequency (RF) applications which require a low data rate, long battery life, and secure networking. ZigBee is a low data rate, two-way standard for home automation and data networks. The standard specification for up to 254 nodes including one master, managed from a single remote control. Real usage examples of ZigBee includes home automation tasks such as turning lights on, setting the home security system, or starting the VCR. With ZigBee all these tasks can be done from anywhere in the home at the touch of a button. ZigBee also allows for dial-in access via the Internet for automation control. The ZigBee standard uses small very low-power devices to connect together to form a wireless control web. A ZigBee network is capable of supporting up to 254 client nodes plus one full functional device (master). ZigBee protocol is optimized for very long battery life measured in months to years from inexpensive, off-the-shelf non-rechargeable batteries, and can control lighting, air conditioning and heating, smoke and fire alarms, and other security devices. The standard supports 2.4 GHz (worldwide), 868 MHz (Europe) and 915 MHz (Americas) unlicensed radio bands with range up to 75 meters.

2.1. IEEE 802.15.4:

IEEE 802.15.4 is a standard which specifies the physical layer and medium access control for low-rate wireless personal area networks (LR-WPAN's).This standard was chartered to investigate a low data rate solution with multi-month to multi-year battery life and very low complexity. It is operating in an unlicensed, international frequency band. Potential applications are sensors, interactive toys, smart badges, remote controls, and home automation.

802.15.4 Is part of the 802.15 wireless personal-area network effort at the IEEE? It is a simple packet-based radio protocol aimed at very low-cost, battery-operated widgets and sensors (whose batteries last years, not hours) that can intercommunicate and send low-bandwidth data to a centralized device. As of 2007, the current version of the standard is the 2006 revision. It is maintained by the IEEE 802.15 working group. It is the basis for the ZigBee specification, which further attempts to offer a complete networking solution by developing the upper layers which are not covered by the standard

2.2. 802.15.4 Protocol Features:

y y y y y y y y y y y y y y

Data rates of 250 kbps with 10-100 meter range. Two addressing modes; 16-bit short and 64-bit IEEE addressing. Support for critical latency devices, such as joysticks. CSMA-CA channel access. Automatic network establishment by the coordinator. Fully handshaked protocol for transfer reliability. Power management to ensure low power consumption. 16 channels in the 2.4GHz ISM band Low duty cycle - Provides long battery life Low latency Support for multiple network topologies: Static, dynamic, star and mesh Direct Sequence Spread Spectrum (DSSS) Up to 65,000 nodes on a network 128-bit AES encryption Provides secure connections between devices

2.3. ZigBee Applications:

ZigBee enables broad-based deployment of wireless networks with low-cost, low-power solutions. It provides the ability to run for years on inexpensive batteries for a host of monitoring applications: Lighting controls, AMR (Automatic Meter Reading), smoke and CO detectors, wireless telemetry, HVAC control, heating control, home security, Environmental controls and shade controls, etc. Zigbee vs other wireless technologies

Standard Transmission Range (meters) Battery Life (days) Network Size (# of nodes) Application Stack Size (KB) Throughput kb/s)

ZigBee 802.15.4 1 100* 100 1,000 > 64,000 Monitoring & Control 4 32 20 250

Wi-Fi 802.11b 1 - 100 0.5 5.0 32 Web, Email, Video 1,000 11,000

Bluetooth 802.15.1 1 10 1-7 7 Cable Replacement 250 720

Use Case Scenario:

It is 4:00 a.m. on a farm in Iowa. Sensors distributed throughout the fields report the moisture content in the soil and humidity of the air. The staff on the farm uses this data to decide where and when to water for optimum effect. The information also serves as an early warning system for environmental issues such as frost. Precious resources are used more efficiently and productivity increases. The sensors distributed in the field are interconnected in a mesh network. If a sensor node goes down, the network is self-healing; the nodes are able to connect with one another dynamically, finding another route to stay connected within the network.

Zigbee stack architecture:

Fig 2.1: ZigBee Stack Architecture It may be helpful to think of IEEE 802.15.4 as the physical radio and ZigBee as the logical network and application software, as Figure 1 illustrates. Following the standard Open Systems Interconnection (OSI) reference model, ZigBee's protocol stack is structured in layers. The first two layers, physical (PHY) and media access (MAC), are defined by the IEEE 802.15.4 standard. The layers above them are defined by the ZigBee Alliance. The IEEE working group passed the first draft of PHY and MAC in 2003. A final version of the network (NWK) layer is expected sometime this year. ZigBee-compliant products operate in unlicensed bands worldwide, including 2.4GHz (global), 902 to 928MHz (Americas), and 868MHz (Europe). Raw data throughput rates of 250Kbps can be achieved at 2.4GHz (16 channels), 40Kbps at 915MHz (10 channels), and 20Kbps at 868MHz (1 channel). The transmission distance is expected to range from 10 to 75m, depending on power output and environmental characteristics. Like Wi-Fi, Zigbee uses directsequence spread spectrum in the 2.4GHz band, with offset-quadrature phase-shift keying

modulation. Channel width is 2MHz with 5MHz channel spacing. The 868 and 900MHz bands also use direct-sequence spread spectrum but with binary-phase-shift keying modulation.

Frame structure:
Figure 2 illustrates the four basic frame types defined in 802.15.4: data, ACK, MAC command, and beacon.

Fig 2.2: Frame Structure

The data frame provides a payload of up to 104 bytes. The frame is numbered to ensure that all packets are tracked. A frame-check sequence ensures that packets are received without error. This frame structure improves reliability in difficult conditions. Another important structure for 802.15.4 is the acknowledgment (ACK) frame. It provides feedback from the receiver to the sender confirming that the packet was received

without error. The device takes advantage of specified "quiet time" between frames to send a short packet immediately after the data-packet transmission. A MAC command frame provides the mechanism for remote control and configuration of client nodes. A centralized network manager uses MAC to configure individual clients' command frames no matter how large the network. Finally, the beacon frame wakes up client devices, which listen for their address and go back to sleep if they don't receive it. Beacons are important for mesh and cluster-tree networks to keep all the nodes synchronized without requiring those nodes to consume precious battery energy by listening for long periods of time.

Channel access, addressing:

Two channel-access mechanisms are implemented in 802.15.4. For a nonebeacon network, a standard CSMA-CA (carrier-sense medium-access with collision avoidance) communicates with positive acknowledgement for successfully received packets. In a beaconenabled network, a super frame structure is used to control channel access. The super frame is set up by the network coordinator to transmit beacons at predetermined intervals (multiples of 15.38ms, up to 252s) and provides 16 equal-width time slots between beacons for contentionfree channel access in each time slot. The structure guarantees dedicated bandwidth and low latency. Channel access in each time slot is contention-based. However, the network coordinator can dedicate up to seven guaranteed time slots per beacon interval for quality of service. Device addresses employ 64-bit IEEE and optional 16-bit short addressing. The address field within the MAC can contain both source and destination address information (needed for peer-to-peer operation). This dual address information is used in mesh networks to prevent a single point of failure within the network.

PROTOCOLS
The protocols build on recent algorithmic research (Ad-hoc On-demand Distance Vector, neuRFon) to automatically construct a low-speed ad-hoc network of nodes. In most large network instances, the network will be a cluster of clusters. It can also form a mesh or a single cluster. The current profiles derived from the ZigBee protocols support beacon and non-beacon enabled networks. In non-beacon-enabled networks (those whose beacon order is 15), an unslotted CSMA/CA channel access mechanism is used. In this type of network, ZigBee Routers typically have their receivers continuously active, requiring a more robust power supply. However, this allows for heterogeneous networks in which some devices receive continuously, while others only transmit when an external stimulus is detected. The typical example of a heterogeneous network is a wireless light switch: the ZigBee node at the lamp may receive constantly, since it is connected to the mains supply, while a battery-powered light switch would remain asleep until the switch is thrown. The switch then wakes up, sends a command to the lamp, receives an acknowledgment, and returns to sleep. In such a network the lamp node will be at least a ZigBee Router, if not the ZigBee Coordinator; the switch node is typically a ZigBee End Device. In beacon-enabled networks, the special network nodes called ZigBee Routers transmit periodic beacons to confirm their presence to other network nodes. Nodes may sleep between beacons, thus lowering their duty cycle and extending their battery life. Beacon intervals may range from 15.36 milliseconds to 15.36 ms * 214 = 251.65824 seconds at 250 kbit/s, from 24 milliseconds to 24 ms * 214 = 393.216 seconds at 40 kbit/s and from 48 milliseconds to 48 ms * 214 = 786.432 seconds at 20 kbit/s. However, low duty cycle operation with long beacon intervals requires precise timing, which can conflict with the need for low product cost.

In general, the ZigBee protocols minimize the time the radio is on so as to reduce power use. In beaconing networks, nodes only need to be active while a beacon is being transmitted. In non-beacon-enabled networks, power consumption is decidedly asymmetrical: some devices are always active, while others spend most of their time sleeping. ZigBee devices are required to conform to the IEEE 802.15.4-2003 Low-Rate Wireless Personal Area Network (WPAN) standard. The standard specifies the lower protocol layersthe physical layer (PHY), and the medium access control (MAC) portion of the data link layer (DLL). This standard specifies operation in the unlicensed 2.4 GHz, 915 MHz and 868 MHz ISM bands. In the 2.4 GHz band there are 16 ZigBee channels, with each channel requiring 5 MHz of bandwidth. The center frequency for each channel can be calculated as, FC = (2405 + 5 * (ch 11)) MHz, where ch = 11, 12, ..., 26. The radios use direct-sequence spread spectrum coding, which is managed by the digital stream into the modulator. BPSK is used in the 868 and 915 MHz bands, and orthogonal QPSK that transmits two bits per symbol is used in the 2.4 GHz band. The raw, over-the-air data rate is 250 kbit/s per channel in the 2.4 GHz band, 40 kbit/s per channel in the 915 MHz band, and 20 kbit/s in the 868 MHz band. Transmission range is between 10 and 75(up to 1500meteres for zigbee pro.)meters (33 and 246 feet), although it is heavily dependent on the particular environment. The maximum output power of the radios is generally 0 dBm (1 mW). The basic channel access mode is "carrier sense, multiple access/collision avoidance" (CSMA/CA). That is, the nodes talk in the same way that people converse; they briefly check to see that no one is talking before they start. There are three notable exceptions to the use of CSMA. Beacons are sent on a fixed timing schedule, and do not use CSMA. Message acknowledgments also do not use CSMA. Finally, devices in Beacon Oriented networks that have low latency

real-time requirements may also use Guaranteed Time Slots (GTS), which by definition do not use CSMA.

Software and hardware:The software is designed to be easy to develop on small, inexpensive microprocessors. The radio design used by ZigBee has been carefully optimized for low cost in large scale production. It has few analog stages and uses digital circuits wherever possible. Even though the radios themselves are inexpensive, the ZigBee Qualification Process involves a full validation of the requirements of the physical layer. This amount of concern about the Physical Layer has multiple benefits, since all radios derived from that semiconductor mask set would enjoy the same RF characteristics. On the other hand, an uncertified physical layer that malfunctions could cripple the battery lifespan of other devices on a ZigBee network. Where other protocols can mask poor sensitivity or other esoteric problems in a fade compensation response, ZigBee radios have very tight engineering constraints: they are both power and bandwidth constrained. Thus, radios are tested to the ISO 17025 standard with guidance given by Clause 6 of the 802.15.4-2006 Standard. Most vendors plan to integrate the radio and microcontroller onto a single chip.

Controversy:An academic research group has examined the Zigbee address formation algorithm in the 2006 specification, and argues[6] that the network will isolate many units that could be connected. The group proposed an alternative algorithm with similar complexity in time and space. A white paper published by a European manufacturing group (associated with the development of a competing standard, Z-Wave) claims that wireless technologies such as ZigBee, which operate in the 2.4 GHz RF band, are subject to significant

interference - enough to make them unusable.[7] It claims that this is due to the presence of other wireless technologies like Wireless LAN in the same RF band. The ZigBee Alliance released a white paper refuting these claims.[8] After a technical analysis, this paper concludes that ZigBee devices continue to communicate effectively and robustly even in the presence of large amounts of interference.

Advantages:y low cost allows the technology to be widely deployed in wireless control and monitoring applications. y low power-usage allows longer life with smaller batteries,. y mesh networking provides high reliability and larger range.

APPLICATIONS:-

- Home Automation - ZigBee Smart Energy - Telecommunication Applications - Personal Home - Hospital Care

RS232 (SERIAL PORT):RS-232 (Recommended Standard - 232) is a telecommunications standard for binary serial communications between devices. It supplies the roadmap for the way devices speak to each other using serial ports. The devices are commonly referred to as a DTE (data terminal equipment) and DCE (data communications equipment); for example, a computer and modem, respectively. RS232 is the most known serial port used in transmitting the data in communication and interface. Even though serial port is harder to program than the parallel port, this is the most effective method in which the data transmission requires less wires that yields to the less cost. The RS232 is the communication line which enables the data transmission by only using three wire links. The three links provides transmit, receive and common ground... The transmit and receive line on this connecter send and receive data between the computers. As the name indicates, the data is transmitted serially. The two pins are TXD & RXD. There are other lines on this port as RTS, CTS, DSR, DTR, and RTS, RI. The 1 and 0 are the data which defines a voltage level of 3V to 25V and -3V to -25V respectively. he electrical characteristics of the serial port as per the EIA (Electronics Industry Association) RS232C Standard specifies a maximum baud rate of 20,000bps, which is slow compared to todays standard speed. For this reason, we have chosen the new RS-232D Standard, which was recently released. The RS-232D has existed in two types. i.e., D-TYPE 25 pin connector and DTYPE 9 pin connector, which are male connectors on the back of the PC. You need

a female connector on your communication from Host to Guest computer. The pin outs of both D-9 & D-25 are show .

D-Type-9 D-Type- Pin outs Function pin no. 25 no. 3 2 2 3 RD TD Receive Data (Serial data input) Transmit output) 7 4 RTS Request to send (acknowledge to modem that UART is ready to exchange data 8 5 CTS Clear to send (i.e.; modem is ready to exchange data) 6 6 DSR Data ready state (UART Data (Serial data pin

establishes a link) 5 1 7 8 SG DCD Signal ground Data Carrier detect (This line is active when modem detects a carrier 4 9 20 22 DTR RI Data Terminal Ready. Ring Indicator (Becomes active when modem detects ringing signal from PSTN

Rs232:

When communicating with various micro processors one needs to convert the RS232 levels down to lower levels, typically 3.3 or 5.0 Volts. Here is a cheap and simple way to do that. Serial RS-232 (V.24) communication works with voltages 15V to +15V for high and low. On the other hand, TTL logic operates between 0V and +5V . Modern low power consumption logic operates in the range of 0V and +3.3V or even lower.

RS-232

TTL

Logic

-15V -3V +2V +5V

High

+3V +15V 0V +0.8V Low

Thus the RS-232 signal levels are far too high TTL electronics, and the negative RS-232 voltage for high cant be handled at all by computer logic. To receive serial data from an RS-232 interface the voltage has to be reduced. Also the low and high voltage level has to be inverted. This level converter uses a Max232 and five capacitors. The max232 is quite cheap (less than 5 dollars) or if youre lucky

you can get a free sample from Maxim. The MAX232 from Maxim was the first IC which in one package contains the necessary drivers and receivers to adapt the RS-232 signal voltage levels to TTL logic. It became popular, because it just needs one voltage (+5V or +3.3V) and generates the necessary RS-232 voltage levels.

MAX 232 PIN DIAGRAM

+---\/---+ 1 -|C1+ Vcc|- 16 2 -|V+ gnd|- 15 3 -|C1- T1O|- 14 4 -|C2+ R1I|- 13 5 -|C2- R1O|- 12 6 -|V- T1I|- 11 7 -|T2O T2I|- 10 8 -|R2I R2O|- 9 +--------+

RS232 INTERFACED TO MAX 232

J2 9 8 7 6 5 4 3 2 1 16 U3 T1OUT TXD P3.1 C4 5V C5 0.1uf C6 0.1uf 0.1uf C7 MAX3232 0.1uf 15 13 8 R1IN R2IN 10 11 T2IN T1IN 1 3 C1+ 4 C15 C2+ C22 6 V+ VGND C1 1uf P3.0 RXD T1OUT

12 R1OUT 9 R2OUT 14 T1OUT 7 T2OUT

Rs232 is 9 pin db connector, only three pins of this are used ie 2,3,5 the transmit pin of rs232 is connected to rx pin of microcontroller

MAX232 INTERFACED TO MICROCONTROLLER

MAX232 is connected to the microcontroller as shown in the figure above 11, 12 pin are connected to the 10 and 11 pin ie transmit and receive pin of microcontroller.

VCC

6.1. REGULATED POWER SUPPLY:

A variable regulated power supply, also called a variable bench power supply, is one where you can continuously adjust the output voltage to your requirements. Varying the output of the power supply is the recommended way to test a project after having double checked parts placement against circuit drawings and the parts placement guide. This type of regulation is ideal for having a simple variable bench power supply. Actually this is quite important because one of the first projects a hobbyist should undertake is the construction of a variable regulated power supply. While a dedicated supply is quite handy e.g. 5V or 12V, it's much handier to have a variable supply on hand, especially for testing. Most digital logic circuits and processors need a 5 volt power supply. To use these parts we need to build a regulated 5 volt source. Usually you start with an unregulated power supply ranging from 9 volts to 24 volts DC (A 12 volt power supply is included with the Beginner Kit and the Microcontroller Beginner Kit.). To make a 5 volt power supply, we use a LM7805 voltage regulator IC .

Fig 6.1: Voltage Regulator-LM7805 The LM7805 is simple to use. You simply connect the positive lead of your unregulated DC power supply (anything from 9VDC to 24VDC) to the Input pin, connect the negative lead to the Common pin and then when you turn on the power, you get a 5 volt supply from the Output pin.

6.1.1. CIRCUIT FEATURES:

Brief description of operation: Gives out well regulated +5V output, output current capability of 100 mA Circuit protection: Built-in overheating protection shuts down output when regulator IC gets too hot Circuit complexity: Very simple and easy to build Circuit performance: Very stable +5V output voltage, reliable operation Availability of components: Easy to get, uses only very common basic components Design testing: Based on datasheet example circuit, I have used this circuit successfully as part of many electronics projects Applications: Part of electronics devices, small laboratory power supply Power supply voltage: Unregulated DC 8-18V power supply Power supply current: Needed output current + 5 mA Component costs: Few dollars for the electronics components + the input transformer cost .

6.1.2.BLOCK DIAGRAM

Fig 6.2: Block Diagram of Power Supply

6.1.3CIRCUIT DIAGRAM

Fig 6.3: Circuit Diagram of Power Supply

Dot-Matrix LCD

he L

nit receives character codes ( bits per character) rom a microprocessor or ( byte or storing

microcomp ter, latches the codes to its display data characters), trans orms each character code into a pattern, and displays the characters on its L he L di erent generator screen

v7 dot matrix character which prod ces

nit incorporates a character generator he

v7 dot matrix character patterns (

nit also provides a character

bytes) thro gh which the ser may de ine p to eight additional

v7 dot matrix character patterns, as req ired by the application o display a character, positional data is sent via the data b s rom the microprocessor to the L nit, where it is written into the instr ction register

character code is then sent and written into the data register he L position L he nit displays the corresponding character pattern in the speci ied

nit can either increment or decrement the display position a tomatically a ter

each character entry, so that only s ccessive characters codes need to be entered to display a contin o s character string he display/c rsor shi t instr ction allows the entry o characters in either the le t

to right or right to le t direction Since the display data ( ) and the character generator ( may be

)many be accessed by the microprocessor, n sed portions o each sed as general p rpose data areas bit or single he L

nit may be operated with either d al bit and

bit data transers, to accommodate inter aces with both he low power eat re o the L S microprocessor nit will be

bitmicroprocessors

rther appreciated

when combined with a

Functional Blocks

Registers
he L register ( R) nit has two he bit registers an instr ction register ( R) and a data

instr ction register stores instr ction codes s ch as "clear display" or "shi t c rsor", and also stores address in ormation or the display data RAM and character generator RAM. he R can be accessed by the microprocessor only or writing. he data register is sed or temporarily storing data d ring data transactions with the microprocessor. When writing data to the L nit, the data is initially stored in the data register, and is

then a tomatically written into either the display data RAM or character generator RAM, as determined by the c rrent operation. he data register is also sed as a temporary storage area when reading data rom the display data RAM or character generator RAM. When address in ormation is written into the instr ction register, the corresponding data rom the display data RAM or character generator RAM is moved to the data register. ata trans er is completed when the microprocessor reads the contents o the data register by the next instr ction. After the transfer is completed, data from the next address position of the appropriate RAM is moved to the data register, in preparation for s bseq ent reading operations by the microprocessor. selected by the register select (RS) signal. ne of the two registers is

Register Selection

Busy Flag (BF)

When the busy flag is set at a logical " ", the L unit is executing an internal

operation, and no instruction will be accepted. he state of the busy flag is output on data line B7 in response to the register selection signals RS = , R/W = as shown in

able . he next instruction may be entered after the busy flag is reset to logical " ".

Address

ounter (AC)
he address counter generates the address for the display data RAM and

character generator RAM. When the address set instruction is written into the instruction register, the address information is sent to the address counter. he same instruction also determines which of the two RAMs is to be selected. After data has been written to or read from the display data RAM or character generator RAM, the address counter is automatically incremented or decremented by one. he contents of the address counter are output on data lines register selection signals RS = 0, R/W = . B0 B6 in response to the

isplay ata RAM (

his 0 x

RAM)
bit character codes as display data. he unused

bit RAM stores up to 0

area of the RAM may be used by the microprocessor as a general purpose RAM area. he display data RAM address, set in the address counter, is expressed in hexadecimal (HE ) numbers as follows:

The address of the display data RAM corresponds to the display position on the LCD panel as follows:
a. Address type a . . . . For dual line display

When a display shift takes place, the addresses shift is as follows:

The addresses for the second line are not continuous to the addresses for the first line. A 0-character RAM area is assigned to each of the two line as follows: line : 00H - 7H line : 0H - 67H For an LCD unit with a display capacity of less than 0 characters per line, characters equal in number to the display capacity, as counted from display position , are displayed.
b. Address type b . . . .For single-line display with logically dual-line addressing

When a display shift takes place, the addresses shift as follows:

Character

enerator ROM (CG ROM)

v7 dot-matrix character pattern for each of 60 different and . nquiries are invited for units with custom character x7

This ROM generates a patterns is shown in Tables

-bit character codes. The correspondence between character codes and character patterns. Character Generator RAM (CG RAM) This RAM stores eight arbitrary dot-matrix character patterns, as programmed by the user. For displaying a character pattern stored in the CG RAM, a character code corresponding to the leftmost column in Tables and is written into the display data

RAM. For the relationship among the CG RAM address, the display data, and the displayed pattern, see Table 6. As shown in Table 6., the unused portion of the CG RAM may be used as a general purpose RAM area.

Timing Generator The timing generator produces timing signals used for the
internal operation of the display data RAM, character generator ROM,and character generator RAM. Timing in controlled so that read-out of the RAM for display and access to the RAM by the external microprocessor do not interfere. Display flicker when data is written to the display data RAM is eliminated.

Cursor/Blink Controller This circuit can be used to generate a cursor or blink a

character in the display position indicated by the DD RAM address, which is set in the address counter (AC). The following example shows the cursor position when the address counter contains "08" (HE ).

arallel-to-Serial Converter
This circuit converts parallel data read from the CG ROM or CG RAM to serial data for use by the display driver. Bias oltage Generator This circuit provides the bias voltage level required for driving the liquid crystal display. Some models incorporate a temperature compensation circuit which generates a temperature dependent bias voltage in order to provide constant display contrast at all ambient temperature levels. LCD Driver This circuit receives display data, timing signals, and bias voltage, and produces the common and segment display signals. LCD

anel This is a dot-matix liquid crystal display panel arranged in either

characters, rows of 6 characters, rows of 0 characters, or

row of 6

rows of 0 characters.

Microprocessor Interface The LCD unit performs either dual -bit or single 8-bit data transers, allowing the user to interface with either a -bit or 8-bit microprocessor -Bit Microprocessor

nterface. Data lines DB4 - DB7 are used for data transfers. Data transactions with the
external microprocessor take place in two 4-bit data transfer operations. The high-order 4 bits (corresponding to DB4 - DB7 in an 8-bit transfer) are transferred first, followed by the low-order 4 bits (corresponding to DB0 - DB3 in an 8-bit transfer). The busy flag is to be checked on completion of the second 4-bit data transfer. Busy flag and address counter are output in two operations.

8-bit Microprocessor nterface

Each 8-bit piece of data is transferred in a single operation using the entire data bus DB0 - DB7.

Reset Function

nitialization by nternal Reset Circuit

The LCD unit has an internal reset circuit for implementing an automatic reset operation at power-on. During the initalization operation, the busy flag is set. The busy state lasts for 0 msec after unit.
DD reaches

4.5 . The following instructions are executed in initializing the LCD

. Clear Display . Function Set DL = . . . . 8-bit data length for interface

= 0 . . . . Single-line display F = 0 . . . . 5 v7 dot-matrix character font 3. Display ON/OFF Control

D = 0 . . . .Display OFF C = 0 . . . .Cursor OFF B = 0 . . . .Blink function OFF 4. Entry Mode Set /D = . . . .Increment Mode

S = 0 . . . .Display shift OFF

RELAY
A relay is an electrically operated switch. Current flowing through the coil of the relay creates a magnetic field which attracts a lever and changes the switch contacts. The coil current can be ON or OFF so relays have two switch position and they are double throw (changeover) switches. Relays allow one circuit to switch a second circuit which can be completely separate from the first. For example a low voltage battery circuit can use a relay to switch a 230V AC mains circuit. There is no electrical connection inside the relay between the two circuits; the link is magnetic and mechanical. The coil of a relay passes a relatively large current, typically 30mA for a 12V relay, but it can be as much as 100mA for relays designed to operate from lower voltages. Most ICs (chips) can not provide this current and a transistor is usually used to amplify the small IC current to the larger value required for the relay coil. The maximum output current for the popular 555 timer IC is 200mA so these devices can supply relay coils directly without amplification. Relays are usually SPDT or DPDT but they can have many more sets of switch contacts, for example relay with 4 sets of changeover contacts are readily available. Most relays are designed for PCB mounting but you can solder wires directly to the pins providing you take care to avoid melting the plastic case of the relay. The supplier's catalogue should show you the relay's connection. The coil will be obvious and it may be connected either way round. Relay coils produce brief high voltage 'spikes' when they are switched off and this can destroy transistors and ICs in the circuit. To prevent damage you must connect a protection diode across the relay coil.

The relays switch connections are usually contains COM, NC and NO. COM = Common, always connect to this; it is the moving part of the switch. NC = Normally Closed, COM is connected to this when the relay coil is off. NO = Normally Open, COM is connected to this when the relay coil is on. Connect to COM and NO if you want the switched circuit to be on when the relay coil is on. Connect to COM and NC if you want the switched circuit to be on when the relay coil is off. Most relays are SPDT or DPDT which are often described as "single pole changeover" (SPCO) Or "double pole changeover"(DPCO).

Fig 6.5: SPDT This is a Single Pole Double Throw relay. Current will flow between the movable contact and one fixed contact when the coil is energized and between the movable contact and the alternate fixed contact when the relay coil is energized. The most commonly used relay in car audio, the Bosch relay, is a SPDT relay..

Fig 6.5: DPDT This relay is a Double Pole Double Throw relay. It operates like the SPDT relay but has twice as many contacts. There are two completely isolated sets of contacts.

Relay Construction: Relays are amazingly simple devices. There are four parts in every relay: 1. Electromagnet 2. Armature that can be attracted by the electromagnet 3. Spring 4. Set of electrical contacts A relay consists of two separate and completely independent circuits. The first is at the bottom and drives the electromagnet. In this circuit, a switch is controlling power to the electromagnet. When the switch is on, the electromagnet is on, and it attracts the armature. The armature is acting as a switch in the second circuit. When the electromagnet is energized, the armature completes the second circuit and the light is on. When the electromagnet is not energized, the spring pulls the armature away and the circuit is not complete. In that case, the light is dark. When you purchase relays, you generally have control over several variables: 1. The voltage and current that is needed to activate the armature. 2. The maximum voltage and current that can run through the armature and the armature contacts.

3. The number of armatures (generally one or two). 4. The number of contacts for the armature (generally one or two -- the relay shown here has two, one of which is unused). 5. Whether the contact (if only one contact is provided) is normally open (NO) or normally closed (NC). 6.3.3. Relay Applications:
In general, the point of a relay is to use a small amount of power in the electromagnet coming, say, from a small dashboard switch or a low-power electronic circuit -- to move an armature that is able to switch a much larger amount of power. For example, you might want the electromagnet to energize using 5 volts and 50 milliamps ( 50 mill watts), while the armature can support 0V AC at amps ( 40 watts).

Relays are quite common in home appliances where

there is an electronic control turning on something like a motor or a light. They are also common in cars, where the 12V supply voltage means that just about everything needs a large amount of current. In later model cars, manufacturers have started combining relay panels into the fuse box to make maintenance easier. In places where a large amount of power needs to be switched, relays are often cascaded. In this case, a small relay switches the power needed to drive a much larger relay, and that second relay switches the power to drive the load. Relays can also be used to implement Boolean logic.

6.3.4. Advantages of Relay:

1. Relays can switch AC and DC, transistors can only switch DC. 2. Relays can switch high voltages, transistors cannot. 3. Relays are a better choice for switching large currents (> 5A). 4. Relays can switch many contacts at once.

Source Code
/*ORG 00H ; Reset

AJMP MAIN

MAIN:

MOV TMOD,#20H Generation MOV TH1,#0FDH MOV SCON,#50H SETB ES SETB EA SETB TR1 MOV A,#'B' MOV SBUF,A JNB TI , $ CLR TI END */

;Enable

Timer

from

Baud

rate

;Enable serial port for 9600Baud rate

;Enable serial port interrupt

VAR1 equ r7 TEMP equ 10H COUNT equ 11H

;Temporary Variable ;Temp variable ;Count ;Device address ;Command ;Flip bit

ADDR equ 12H CMD equ 13H FLIP bit 00H

TOG bit 01H IR equ P3.3

;Temp bit for flip ;IR Receiver connected to this pin ;Switch 1 connected here ;Switch 2 connected here ;Switch 3 connected here ;Switch 4 connected here ;Switch 5 connected here ;Switch 6 connected here ;Switch 7 connected here ;Switch 8 connected here ;Port at which switches are connected

SW1 equ P2.0 SW2 equ P2.1 SW3 equ P2.2 SW4 equ P2.3 SW5 equ P2.4 SW6 equ P2.5 SW7 equ P2.6 SW8 equ P2.7 SWport equ P2

org 00H AJMP MAIN1

;Start of prog

MAIN1: MOV TMOD,#20H Generation MOV TH1,#0FDH MOV SCON,#50H SETB ES SETB EA SETB TR1 MOV A,#'B' MOV SBUF,A JNB TI , $ CLR TI mov SWport,#00H ;switch all relays off! mov sp,#50H clr TOG ;Stack pointer initialization ;Clear temp bit ;Enable serial port interrupt ;Enable serial port for 9600Baud rate ;Enable Timer 1 from Baud rate

main: jb IR,$ mov VAR1,#255 djnz VAR1,$ mov VAR1,#255 djnz VAR1,$ mov VAR1,#100 djnz VAR1,$ mov c,IR mov FLIP,c clr A mov COUNT,#5 fadd: mov VAR1,#255 djnz VAR1,$ mov VAR1,#255 djnz VAR1,$ mov VAR1,#255 djnz VAR1,$ mov VAR1,#4 djnz VAR1,$ mov c,IR rlc a djnz COUNT,fadd mov ADDR,A clr a mov COUNT,#6 fcmd: mov VAR1,#255 djnz VAR1,$ ;1.728mS Delay for each bit ;Count for Command ;Save the address ;1.728mS delay for each bit ;Count for address ;Read Flip bit ;Wait for first bit ;3.024mS delay

mov VAR1,#255 djnz VAR1,$ mov VAR1,#255 djnz VAR1,$ mov VAR1,#4 djnz VAR1,$ mov c,IR rlc a djnz COUNT,fcmd mov TEMP,CMD mov CMD,a mov a,ADDR cjne a,#00,nvalid mov a,TEMP cjne a,CMD,valid nvalid: ljmp main valid: clr a mov c,FLIP rlc a mov TEMP,a clr a mov c,TOG cjne a,TEMP,valid1 sjmp nvalid valid1: mov c,FLIP mov TOG,c mov a,CMD clr c ;Key press check ;Check for valid command ;Save the old command ;Save the new command ;Cheack for valid address

cjne a,#1,skip1 // // // jb SW1,isset1 setb SW1 clr SW2 MOV A,#'A' MOV SBUF,A JNB TI , $ CLR TI ljmp main isset1: clr SW1 ljmp main skip1: cjne a,#2,skip2 MOV A,#'B' MOV SBUF,A JNB TI , $ CLR TI ljmp main isset2: clr SW2 ljmp main END

;Check for SW1

;Check for SW2

;End of program

Rx Section:

# include <8052.h> # define M1_1 P2_0 # define M1_2 P2_1 unsigned char temp; main() { unsigned int i=0 ,j=0;

SCON = 0x50; TMOD = 0x20; TH1 = 0xFD; TR1 = 1; M1_1 = 0; M1_2 = 0; while (1) { while(!RI); RI = 0; temp = SBUF ; if(temp == 'A') { M1_1 = !M1_1; } if(temp == 'B') { M1_2 = !M1_2; } } }

/* mode 1, 8-bit uart, enable receiver */ /* timer 1, mode 2, 8-bit reload */ /* reload value for 2400 baud */ /* start the timer */

KEIL SOFTWARE
1. 2. Click on the Keil uVision Icon on DeskTop The following fig will appear

3. 4.

Click on the Project menu from the title bar Then Click on New Project

5.

Save the Project by typing suitable project name with no extension in u r own folder sited in either C:\ or D:\

6. 7. 8.

Then Click on Save button above. Select the component for u r project. i.e. Philips Click on the + Symbol beside of Philips

9.

Select AT89S52 as shown below

10. 11.

Then Click on OK The Following fig will appear

12.

Then Click either YES or NOmostly NO

13. 14.

Now your project is ready to USE Now double click on the Target1, you would get another option Source group 1 as shown in next page.

15.

Click on the file option from menu bar and select new

16.

The next screen will be as shown in next page, and just maximize it by double clicking on its blue boarder.

17. 18.

Now start writing program in either in C or ASM For a program written in Assembly, then save it with extension . asm and for C based program save it with extension .C

19.

Now right click on Source group 1 and click on Add files to Group Source

20.

Now you will get another window, on which by default C files will appear.

21. 22. 23.

Now select as per your file extension given while saving the file Click only one time on option ADD Now Press function key F7 to compile. Any error will appear if so happen.

24. 25.

If the file contains no error, then press Control+F5 simultaneously. The new window is as follows

26.

Then Click OK

27.

Now Click on the Peripherals from menu bar, and check your required port as shown in fig below

28.

Drag the port a side and click in the program file.

29. 30.

Now keep Pressing function key F11 slowly and observe. You are running your program successfully

CONCLUSION
The project ZIG-BEE BASED HOME AUTOMATION CONTROL has been successfully designed and tested. Integrating features of all the hardware components used have developed it. Presence of every module has been reasoned out and placed carefully thus contributing to the best working of the unit. Secondly, using highly advanced technology and with the help of growing technology the project has been successfully implemented.

BIBLIOGRAPHY

The 8051 Micro controller and Embedded Systems -Muhammad Ali Mazidi Janice Gillispie Mazidi The 8051 Micro controller Architecture, Programming & Applications
-Kenneth J.Ayala

Fundamentals Of Micro processors and Micro computers

-B.Ram

Micro processor Architecture, Programming & Applications

-Ramesh S.Gaonkar

Electronic Components -D.V.Prasad Wireless Communications - Theodore S. Rappaport Mobile Tele Communications - William C.Y. Lee

References on the Web:

www.national.com www.nxp.com www.8052.com www.microsoftsearch.com www.geocities.com