HEF4013B

Dual D-type ip-op

Rev. 06 27 October 2009 Product data sheet

1. General description
The HEF4013B is a dual D-type ip-op that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW and is transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs. The outputs are buffered for best system performance. The clock inputs Schmitt-trigger action makes the circuit highly tolerant of slower clock rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. The device is suitable for use over both the industrial (40 C to +85 C) and automotive (40 C to +125 C) temperature ranges.

2. Features
I I I I I I Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range from 40 C to +125 C Complies with JEDEC standard JESD 13-B

3. Applications
I I I I Automotive and industrial Counters and dividers Registers Toggle ip-ops

4. Ordering information
Table 1. Ordering information All types operate from 40 C to +125 C Type number HEF4013BP HEF4013BT HEF4013BTT Package Name DIP14 SO14 TSSOP14 Description plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT27-1 SOT108-1 SOT402-1

NXP Semiconductors

HEF4013B
Dual D-type ip-op

5. Functional diagram

1SD

6 SD D FF1 Q

1D

1Q

1CP

CP CD

1Q

1CD 2SD

4 8 SD D FF2 Q

2D

13

2Q

2CP

11

CP CD

12

2Q

2CD

10
001aag084

Fig 1.

Functional diagram

CP

C C C C Q

C C D

C C

Q C SD

CD

001aag086

Fig 2.

Logic diagram (one ip-op)

HEF4013B_6

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Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

6. Pinning information
6.1 Pinning

1Q 1Q 1CP 1CD 1D 1SD VSS

1 2 3 4 5 6 7
001aag085

14 VDD 13 2Q 12 2Q

HEF4013B

11 2CP 10 2CD 9 8 2D 2SD

Fig 3.

Pin conguration

6.2 Pin description

Table 2. Symbol 1Q, 2Q 1Q, 2Q 1CP, 2CP 1CD, 2CD 1D, 2D 1SD, 2SD VSS VDD Pin description Pin 1, 13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 Description true output complement output clock input (LOW to HIGH edge-triggered) asynchronous clear-direct input (active HIGH) data input asynchronous set-direct input (active HIGH) ground (0 V) supply voltage

7. Functional description
Table 3. Control nSD H L H L L
[1]

Function table[1] Input nCD L H H L L nCP X X X nD X X X L H Output nQ H L H L H nQ L H H H L

H = HIGH voltage level; L = LOW voltage level; X = dont care; = LOW-to-HIGH clock transition.

HEF4013B_6

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Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation Tamb = 40 C to +125 C DIP14 SO14 TSSOP14 P
[1] [2] [3]
[1] [2] [3]

Conditions VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V

Min 0.5 0.5 65 40 -

Max +18 10 VDD + 0.5 10 10 50 +150 +125 750 500 500 100

Unit V mA V mA mA mA C C mW mW mW mW

power dissipation

per output

For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K. For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. For TSSOP14 packages: above Tamb = 60 C, Ptot derates linearly with 5.5 mW/K.

9. Recommended operating conditions

Table 5. Symbol VDD VI Tamb t/V Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 40 Max 15 VDD +125 3.75 0.5 0.08 Unit V V C s/V s/V s/V

HEF4013B_6

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Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

10. Static characteristics

Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specied. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 A VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 A 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 A 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 A 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current all valid input combinations; |IO| = 0 A 5V 5V 10 V 5V 10 V 15 V 15 V 5V 10 V 15 V Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit Min 3.5 7.0 11.0 4.95 9.95 14.95 1.7 0.64 1.6 4.2 0.64 1.6 4.2 Max 1.5 3.0 4.0 0.05 0.05 0.05 0.1 1.0 2.0 4.0 Min 3.5 7.0 11.0 4.95 9.95 14.95 1.4 0.5 1.3 3.4 0.5 1.3 3.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 0.1 1.0 2.0 4.0 7.5 Min 3.5 7.0 11.0 4.95 9.95 14.95 1.1 0.36 0.9 2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 1.0 30 60 120 Min 3.5 7.0 11.0 4.95 9.95 14.95 1.1 0.36 0.9 2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 1.0 30 60 120 V V V V V V V V V V V V mA mA mA mA mA mA mA A A A A pF

VO = 13.5 V 15 V

CI

input capacitance

HEF4013B_6

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

11. Dynamic characteristics

Table 7. Dynamic characteristics Tamb = 25 C; unless otherwise specied. For test circuit see Figure 6. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions nCP to nQ, nQ; see Figure 4 VDD 5V 10 V 15 V nSD to nQ 5V 10 V 15 V nCD to nQ 5V 10 V 15 V tPLH LOW to HIGH propagation delay nCP to nQ, nQ; see Figure 4 5V 10 V 15 V nSD to nQ 5V 10 V 15 V nCD to nQ 5V 10 V 15 V tt transition time see Figure 4 5V 10 V 15 V tsu set-up time nD to nCP; see Figure 4 5V 10 V 15 V th hold time nD to nCP; see Figure 4 5V 10 V 15 V tW pulse width nCP input LOW; see Figure 4 5V 10 V 15 V nSD input HIGH; see Figure 5 5V 10 V 15 V nCD input HIGH; see Figure 5 5V 10 V 15 V
[1] [1] [1] [1] [1] [1] [1]

Extrapolation formula Min 83 + 0.55 CL 34 + 0.23 CL 22 + 0.16 CL 73 + 0.55 CL 29 + 0.23 CL 22 + 0.16 CL 73 + 0.55 CL 29 + 0.23 CL 22 + 0.16 CL 68 + 0.55 CL 29 + 0.23 CL 22 + 0.16 CL 48 + 0.55 CL 24 + 0.23 CL 17 + 0.16 CL 33 + 0.55 CL 19 + 0.23 CL 12 + 0.16 CL 10 + 1.00 CL 9 + 0.42 CL 6 + 0.28 CL 40 25 15 20 20 15 60 30 20 50 24 20 50 24 20

Typ 110 45 30 100 40 30 100 40 30 95 40 30 75 35 25 60 30 20 60 30 20 20 10 5 0 0 0 30 15 10 25 12 10 25 12 10

Max 220 90 60 200 80 60 200 80 60 190 80 60 150 70 50 120 60 40 120 60 40 -

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

HEF4013B_6

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Product data sheet

Rev. 06 27 October 2009

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NXP Semiconductors

HEF4013B
Dual D-type ip-op

Table 7. Dynamic characteristics continued Tamb = 25 C; unless otherwise specied. For test circuit see Figure 6. Symbol Parameter trec recovery time Conditions nSD input; see Figure 5 VDD 5V 10 V 15 V nCD input; see Figure 5 5V 10 V 15 V fclk(max) maximum clock frequency see Figure 4 5V 10 V 15 V
[1]

Extrapolation formula Min +15 15 15 40 25 25 7 14 20

Typ 5 0 0 25 10 10 14 28 40

Max -

Unit ns ns ns ns ns ns MHz MHz MHz

Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas. CL is given in pF.

Table 8. Dynamic power dissipation VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation VDD Typical formula VDD2 W Where fi = input frequency in MHz; 5 V PD = 850 fi + (fo CL)

10 V PD = 3600 fi + (fo CL) VDD2 W fo = output frequency in MHz; 15 V PD = 9000 fi + (fo CL) VDD2 W CL = output load capacitance in pF; (fo CL) = sum of the outputs; VDD = supply voltage in V.

12. Waveforms
1/fclk(max) VI input nCP 0V tsu th VI input nD 0V tPLH tt VOH output nQ VOL VY VM VX
001aah016

tW

VM

tsu th

tf

tr

VM

tPHL tt

Set-up and hold times are shown as positive values but may be specied as negative values. The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 9.

Fig 4.
HEF4013B_6

Set-up time, hold time, minimum clock pulse width, propagation delays and transition times
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Product data sheet

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HEF4013B
Dual D-type ip-op

VI input nCP 0V trec VI input nSD 0V VI input nCD 0V VOH output nQ VOL
001aag088

VM trec

VM tW

VM tW

Recovery times are shown as positive values but may be specied as negative values. Measurement points are given in Table 9.

Fig 5. Table 9. VDD

nSD, nCD recovery time and pulse width Measurement points Input VM 0.5VDD Output VM 0.5VDD VX 0.1VDD VY 0.9VDD

Supply voltage 5 V to 15 V

VDD VI G
RT

VO DUT
CL

001aag182

Test and measurement data is given in Table 10; Denitions test circuit: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance.

Fig 6. Table 10. VDD

Test circuit for measuring switching times Test data Input VI VSS or VDD tr, tf 20 ns Load CL 50 pF

Supply voltage 5 V to 15 V

HEF4013B_6

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Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

13. Application information

D FF 1 CP

D FF 2

D FF n

CP

CP

Q
001aag089

clock

Fig 7.

N-stage shift register

D FF 1 clock CP

D FF 2

D FF n

CP

CP

T-type flip-flop

001aag090

Fig 8.

Binary ripple up-counter; divide-by-2n

D FF 1 CP clock

D FF 2

D FF n

CP

CP

001aag091

Fig 9.

Modied ring counter; divide-by-(n + 1)

HEF4013B_6

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

14. Package outline

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

D seating plane

ME

A2

A1

c Z e b1 b 14 8 MH w M (e 1)

pin 1 index E

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-13

Fig 10. Package outline SOT27-1 (DIP14)

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Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

A X

c y HE v M A

Z 14 8

Q A2 pin 1 index Lp 1 e bp 7 w M L detail X A1 (A 3) A

2.5 scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012

inches 0.069

0.010 0.057 0.004 0.049

0.019 0.0100 0.35 0.014 0.0075 0.34

0.244 0.039 0.041 0.228 0.016

8 o 0

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

Fig 11. Package outline SOT108-1 (SO14)

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Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

c y HE v M A

14

Q A2 pin 1 index A1 Lp L (A 3) A

1
e bp

7
w M detail X

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o

Fig 12. Package outline SOT402-1 (TSSOP14)

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Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

15. Revision history

Table 11. Revision history Release date 20091027 Data sheet status Product data sheet Product data sheet Product data sheet Product specication Product specication Change notice Supersedes HEF4013B_5 HEF4013B_4 HEF4013B_CNV_3 HEF4013B_CNV_2 Document ID HEF4013B_6 Modications: HEF4013B_5 HEF4013B_4 HEF4013B_CNV_3 HEF4013B_CNV_2

Table 5 Recommended operating conditions t/V values updated.

20090619 20080515 19950101 19950101

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Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

16. Legal information

16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]

Product status[3] Development Qualication Production

Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.

Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

16.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental

16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com For sales ofce addresses, please send an email to: salesaddresses@nxp.com

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Product data sheet

Rev. 06 27 October 2009

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HEF4013B
Dual D-type ip-op

18. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.

NXP B.V. 2009.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 October 2009 Document identifier: HEF4013B_6