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1, JANUARY 2009


Multilevel Inverter For Grid-Connected PV System Employing Digital PI Controller

Jeyraj Selvaraj and Nasrudin A. Rahim, Senior Member, IEEE
AbstractThis paper presents a single-phase ve-level photovoltaic (PV) inverter topology for grid-connected PV systems with a novel pulsewidth-modulated (PWM) control scheme. Two reference signals identical to each other with an offset equivalent to the amplitude of the triangular carrier signal were used to generate PWM signals for the switches. A digital proportionalintegral current control algorithm is implemented in DSP TMS320F2812 to keep the current injected into the grid sinusoidal and to have high dynamic performance with rapidly changing atmospheric conditions. The inverter offers much less total harmonic distortion and can operate at near-unity power factor. The proposed system is veried through simulation and is implemented in a prototype, and the experimental results are compared with that with the conventional single-phase three-level grid-connected PWM inverter. Index TermsDSP TMS320F2812, grid connected, photovoltaic (PV), proportionalintegral (PI) current control, pulsewidthmodulated (PWM) inverter.

Fig. 1. Carrier and reference signals.

I. I NTRODUCTION HE DEMAND for renewable energy has increased signicantly over the years because of shortage of fossil fuels and greenhouse effect. Among various types of renewable energy sources, solar energy and wind energy have become very popular and demanding due to advancement in power electronics techniques. Photovoltaic (PV) sources are used today in many applications as they have the advantages of being maintenance and pollution free. Solar-electric-energy demand has grown consistently by 20%25% per annum over the past 20 years, which is mainly due to the decreasing costs and prices. This decline has been driven by the following factors: 1) an increasing efciency of solar cells; 2) manufacturingtechnology improvements; and 3) economies of scale [1]. PV inverter, which is the heart of a PV system, is used to convert dc power obtained from PV modules into ac power to be fed into the grid. Improving the output waveform of the inverter reduces its respective harmonic content and, hence, the size of the lter used and the level of electromagnetic interference (EMI) generated by switching operation of the inverter [2]. In recent years, multilevel inverters have become more attractive for researchers and manufacturers due to their advantages over

Manuscript received January 8, 2008; revised June 23, 2008. First published July 9, 2008; current version published December 30, 2008. The authors are with the Center of Research for Power Electronics, Drives, Automation and Control (UMPEDAC), Department of Electrical Engineering, University Malaya, 50603 Kuala Lumpur, Malaysia (e-mail: jeyraj95@um. Color versions of one or more of the gures in this paper are available online at Digital Object Identier 10.1109/TIE.2008.928116

conventional three-level pulsewidth-modulated (PWM) inverters. They offer improved output waveforms, smaller lter size, lower EMI, lower total harmonic distortion (THD), and others [3][8]. The three common topologies for multilevel inverters are as follows: 1) diode clamped (neutral clamped) [9][11]; 2) capacitor clamped (ying capacitors) [12][14]; and 3) cascaded H-bridge inverter [15][17]. In addition, several modulation and control strategies have been developed or adopted for multilevel inverters, including the following: multilevel sinusoidal (PWM), multilevel selective harmonic elimination, and spacevector modulation [3], [18]. A typical single-phase three-level inverter adopts full-bridge conguration by using approximate sinusoidal modulation technique as the power circuits. The output voltage then has the following three values: zero, positive (+Vdc), and negative (Vdc) supply dc voltage (assuming that Vdc is the supply voltage). The harmonic components of the output voltage are determined by the carrier frequency and switching functions. Therefore, their harmonic reduction is limited to a certain degree [4]. To overcome this limitation, this paper presents a ve-level PWM inverter whose output voltage can be represented in the following ve levels: zero, +1/2Vdc, Vdc, 1/2Vdc, and Vdc. As the number of output levels increases, the harmonic content can be reduced. This inverter topology uses two reference signals, instead of one reference signal, to generate PWM signals for the switches. Both the reference signals Vref1 and Vref2 are identical to each other, except for an offset value equivalent to the amplitude of the carrier signal Vcarrier , as shown in Fig. 1. Because the inverter is used in a PV system, a proportional integral (PI) current control scheme is employed to keep the output current sinusoidal and to have high dynamic performance under rapidly changing atmospheric conditions and to maintain the power factor at near unity. Simulation and experimental results are presented to validate the proposed inverter conguration.

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Fig. 4. Fig. 2. Single-phase ve-level inverter topology.

Basis of equivalence for sinusoidal PWM: voltseconds.

Fig. 3. Sinusoidal PWM signal.

Fig. 5.

Characterization of pulse.

II. F IVE -L EVEL I NVERTER T OPOLOGY AND PWM L AW The proposed single-phase ve-level inverter topology is shown in Fig. 2. The inverter adopts a full-bridge conguration with an auxiliary circuit [4]. PV arrays are connected to the inverter via a dcdc boost converter. Because the proposed inverter is used in a grid-connected PV system, utility grid is used instead of load. The dcdc boost converter is used to step up inverter output voltage Vinv to be more than 2 of grid voltage Vg to ensure power ow from the PV arrays into the grid [19]. A ltering inductance Lf is used to lter the current injected into the grid. The injected current must be sinusoidal with low harmonic distortion. In order to generate sinusoidal current, sinusoidal PWM is used because it is one of the most effective methods. Sinusoidal PWM is obtained by comparing a high-frequency carrier with a low-frequency sinusoid, which is the modulating or reference signal. The carrier has a constant period; therefore, the switches have constant switching frequency. The switching instant is determined from the crossing of the carrier and the modulating signal. A. Sinusoidal PWM Law A fundamental period in Fig. 3 consists of p pulses whose widths vary sinusoidally throughout the cycle to give the fundamental component of frequency. The basis of equivalence between the desired sinusoid and the actual pulsed waveform is taken to be voltseconds, as shown in Fig. 4, i.e., As1 = Ap1 and As2 = Ap2 . One of these pulses, the general kth pulse, is characterized in detail in Fig. 5.

The switching period and the frequency modulation ratio p are, respectively, given by = 2/p p = fs /f1 (1) (2)

where fs is the switching frequency and f1 is the fundamental frequency. The quarter period of pulse 0 is given as 0 = /4. (3)

k is the position from the origin of the fundamental period of the midpoint of the period . The angles 1k and 2k are the modulating angles which vary throughout the cycle, and it is to calculate these angles that a modulation law must be derived. Consider rst the average voltages V 1k and V 2k during the two halves of the modulating pulse V 1k = (Vs ) {1k (20 1k )} /20 V 1k = (Vs )(1k 0 )/0 = (Vs )1k where 1k = (1k 0 )/0 and, similarly V 2k = (Vs )2k (8) (7) (4) (5) (6)



where 2k = (2k 0 )/0 . (9)

The voltsecond As1 is the half-pulsewidth of the sine wave and is given according to Fig. 4 by

As1 =
k 20

Vm sin d

(10) (11)

= 2Vm sin 0 sin(k 0 ). However, sin 0 0 when 0 is small As1 = 20 Vm sin(k 0 ) and, similarly, As2 = 20 Vm sin(k + 0 ).



For the corresponding voltsecond Ap1 , in the PWM waveform, Ap1 = 20 V 1k Ap1 = 20 1k (Vs ) and, similarly, Ap2 = 20 2k (Vs ). (16) (14) (15)

For equivalence of voltseconds from which the modulation law can be derived, we require that As1 = Ap1 As2 = Ap2 . By equating (12) and (14), and (13) and (16) 1k = M sin(k 0 ) and, similarly, 2k = M sin(k + 0 ) where M is the modulation index and Vm . M= Vs (21) (20) (19) commonly expressed in terms of 1k and 2k , by substituting from (7) and (9) to give 1k = 0 [1 + M sin(k 0 )] 2k = 0 [1 + M sin(k + 0 )] . (22) (23) (17) (18)
Fig. 6. Carrier and reference signals for different values of modulation index M . (a) M = 0.3. (b) M = 0.5. (c) M = 0.7. (d) M = 1.2.

Thus, the switching angles 1k and 2k for the kth pulse can be calculated from (22) and (23) in terms of modulation index M and angles k and 0 which depend upon the fundamental frequency and frequency ratio.

Equation (21) can be expressed in terms of amplitude of carrier signal Vc by replacing Vs with Vc . Because, in this topology, two identical reference signals are used, Vs = 2Vc and Vm = Vref1 = Vref2 . If M > 1, higher harmonics in the phase waveform are obtained. Therefore, M is maintained between zero and one. If the amplitude of the reference signal is increased to be higher than the amplitude of the carrier signal, i.e., M > 1, this will lead to overmodulation. Large values of M in sinusoidal PWM techniques lead to full overmodulation [20]. Fig. 6 shows the carrier and reference signals for different values of M . Equations (19) and (20) dene the modulation law, which is more

B. Harmonic Spectrum of Sinusoidal PWM Waveform The voltage harmonics produced by the sinusoidal PWM can be computed by rst calculating the harmonics due to the kth pulse alone, Ank , and then summating the harmonic contributions of all p pulses 1 = 2
k +20


V ()ejn d
k 20




Fig. 7. Ideal ve-level inverter output voltage Vinv .

where V () is the voltage pulse shown in Fig. 5 k +2k k 1k 1 jn Vs e d + Vs ejn d Ank = 2 k 20 k 1k k +20 Vs ejn d (25)
k +2k

Fig. 8.

Switching pattern for the single-phase ve-level inverter.


= (Vs )

1 2


2 jn ejn1k + j sin 2n0 }ejnk .


Equation (25) cannot be readily simplied. Therefore, for the harmonic amplitudes due to all p pulses in a fundamental cycle

An =

Ank .


III. O PERATIONAL P RINCIPLE OF THE P ROPOSED I NVERTER Because PV arrays are used as input voltage sources, the voltage produced by the arrays is known as Varrays . Varrays is boosted by a dcdc boost converter to exceed 2Vg . The voltage across the dc-bus capacitors is known as Vpv . The operational principle of the proposed inverter is to generate velevel output voltage, i.e., 0, +Vpv /2, +Vpv , Vpv /2, and Vpv as in Fig. 7. As shown in Fig. 2, an auxiliary circuit which consists of four diodes and a switch S1 is used between the dc-bus capacitors and the full-bridge inverter. Proper switching control of the auxiliary circuit can generate half level of PV supply voltage, i.e., +Vpv /2 and Vpv /2 [4]. Two reference signals Vref1 and Vref2 will take turns to be compared with the carrier signal at a time. If Vref1 exceeds the peak amplitude of the carrier signal Vcarrier , Vref2 will be compared with the carrier signal until it reaches zero. At this point onward, Vref1 takes over the comparison process until it exceeds Vcarrier . This will lead to a switching pattern, as shown in Fig. 8. Switches S1 S3 will be switching at the rate of the carrier signal frequency, whereas S4 and S5 will operate at a frequency equivalent to the fundamental frequency. Table I illustrates the level of Vinv during S1 S5 switch on and off. IV. C ONTROL S YSTEM A LGORITHM AND I MPLEMENTATION The feedback controller used in this application utilizes the PI algorithm. As shown in Fig. 9, the current injected into the

grid, also known as grid current Ig , is sensed and fed back to a comparator which compares it with the reference current Iref . Iref is obtained by sensing the grid voltage and converting it to reference current and multiplying it with constant m. This is to ensure that Ig is in phase with grid voltage Vg and always at near-unity power factor. One of the problems in the PV generation systems is the amount of the electric power generated by solar arrays always changing with weather conditions, i.e., the intensity of the solar radiation. A maximum power point tracking (MPPT) method or algorithm, which has quick-response characteristics and is able to make good use of the electric power generated in any weather, is needed to solve the aforementioned problem [21]. Various MPPT control methods have been discussed in detail in [22]. Constant m is derived from the MPPT algorithm. The perturb-and-observe algorithm is used to extract maximum power from PV arrays and deliver it to the inverter [23], [24]. The instantaneous current error is fed to a PI controller. The integral term in the PI controller improves the tracking by reducing the instantaneous error between the reference and the actual current. The resulting error signal u which forms Vref1 and Vref2 is compared with a triangular carrier signal, and intersections are sought to produce PWM signals for the inverter switches. A. Mathematical Formulation The PI algorithm can be expressed in the continuous time domain as

u(t) = Kp e(t) + Ki

e( )d




Fig. 9.

Five-level inverter with control algorithm implemented in DSP TMS320F2812.

where u(t) control signal; e(t) error signal; t continuous-time-domain time variable; calculus variable of integration; proportional-mode control gain; Kp integral-mode control gain. Ki Implementing this algorithm using a DSP requires one to transform it into the discrete-time domain. Trapezoidal sum approximation is used to transform the integral term into the discrete-time domain because it is the most straightforward technique. The proportional term is directly used without approximation. P term : I term : Kp e(t) = Kp e(k).

Fig. 10. PI control algorithm implemented in DSP TMS320F2812.

To eliminate the need to calculate the full summation at each time step (which would require an ever-increasing amount of computation as time goes on), the summation is expressed as a running sum sum(k) = sum(k 1) + [e(k) + e(k 1)] u(k) = Kp e(k) + Ki sum(k). (33) (34)



e( )d Ki =


h [e(i) + e(i 1)] . 2 (30)

These two equations, which represent the discrete-time PI control law, are implemented in DSP TMS320F2812 to control the overall operation of the inverter. B. Algorithm Implementation Control signal saturation and integral-mode antiwindup limiting are easily implemented in software. In this work, the control signal itself takes the form of PWM outputs from the DSP. Therefore, the control signal is saturated at the value that corresponds to 100% duty cycle for the PWM. An undesirable side effect of saturating the controller output is the integral-mode windup. When the control output saturates, the integral-mode control term (i.e., the summation) will continue to increase but will not produce a corresponding increase in controller output (and hence will not produce any additional increase in plant response). The integral can become quite large, and it can take a long time before the controller is able to reduce it once the error signal changes sign. The effects of windup

Time relationship: t = k h where h sampling period; k discrete-time index: k = 0, 1, 2, . . .. For simplication, it is convenient to dene new controller gains as K i = Ki h 2 (31)

from which one can construct the discrete-time PI control law as


u(k) = Kp e(t) + Ki

[e(i) + e(i 1)] .




Fig. 11. PWM switching strategy.

Fig. 12. Inverter output voltage (Vinv ) and grid current (Ig ) for different values of M . (a) Vinv for M < 0.5. (b) Ig for M < 0.5. (c) Vinv for M > 1.0. (d) Ig for M > 1.0. (e) Vinv for 0.5 M 1.0. (f) Ig for 0.5 M 1.0.



on the closed-loop output are larger transient overshoot and undershoot and longer settling times. One approach for overcoming the integral-mode windup is to simply limit in software the maximum absolute value allowed for the integral, independent of the controller output saturation [25], as shown in Fig. 10. V. S IMULATION AND E XPERIMENTAL R ESULTS A. Simulation Results In order to verify that the proposed inverter can be practically implemented in a PV system, simulations were performed by using MATLAB SIMULINK. It also helps to conrm the PWM switching strategy which then can be implemented in a DSP. Fig. 11 shows the PWM switching strategy used in this paper. It consists of two reference signals and a triangular carrier signal. Both the reference signals are compared with the triangular carrier signal to produce PWM switching signals for switches S1 S5 as in Fig. 8. Note that one leg of the inverter is operating at a high switching rate equivalent to the frequency of the carrier signal, whereas the other leg is operating at the rate of fundamental frequency (i.e., 50 Hz). The switch at the auxiliary circuit S1 also operates at the rate of the carrier signal. As mentioned earlier, the modulation index M will determine the shape of the inverter output voltage Vinv and the grid current Ig . Fig. 12 shows Vinv and Ig for different values of M . The dc-bus voltage is set at 400 V (> 2Vg ; in this case, Vg is 240 V) in order to inject current into the grid. Fig. 12(a) shows that Vinv is less than 2Vg due to M being less than 0.5. The inverter should not operate at this condition because the current will be injected from the grid into the inverter, rather than the PV system injecting the current into the grid, as shown in Fig. 12(b). Overmodulation condition, which happens when M > 1.0, is shown in Fig. 12(c). It has a at top at the peak of the positive and negative cycles because both the reference signals exceed the maximum amplitude of the carrier signal. This will cause Ig to have a at portion at the peak of the sine waveform, as shown in Fig. 12(d). To optimize the power transferred from PV arrays to the grid, it is recommended to operate at 0.5 M 1.0. Vinv and Ig for optimal operating condition are shown in Fig. 12(e) and (f), respectively. As Ig is almost a pure sinewave, the THD can be reduced compared with that under other values of M . To analyze the performance of the PI current control scheme, a sudden step change is applied to the simulation process. This step change is similar to real-time environment condition (for example, the sun is emerging from the clouds). The step response is monitored, as shown in Fig. 13. B. Experimental Results The simulation results are veried experimentally by using a DSP TMS320F2812. The proposed inverter is tested with a PV array of 750 W. The modules ratings are shown in Table II, whereas Table III shows the PV multilevel inverter specications and its controller parameters. Ten modules are connected in series to produce 750 W of peak power. Fig. 14

Fig. 13. Step response of the PI current control scheme. TABLE II PV MODULE CHARACTERISTICS


Fig. 14. Prototype of the ve-level PWM inverter.

shows the prototype of the ve-level PWM inverter. PWM switching signals for the switches are generated by comparing a triangular carrier signal with two reference signals, as shown in Fig. 15. Fig. 16 shows the experimental results for Vinv and Ig , whereas Fig. 17 shows a zoom-in view of both the waveforms. It can be seen that Vinv consists of ve levels of output voltage, and Ig has been ltered to resemble a pure sinewave. The modulation index M is 0.8. For M that is less than 0.5, Vinv is



Fig. 16.

Experimental result of Vinv and Ig for M = 0.8.

Fig. 17.

Zoom-in view of Fig. 16.

Fig. 15. and S5 .

PWM switching signals for S1 S5 . (a) S1 . (b) S2 and S3 . (c) S4

Fig. 18.

Experimental result of Vinv and Ig for M = 0.2.

less than 2Vgrid . Therefore, current will be injected from the grid into the PV system, as shown in Fig. 18. This condition should be avoided to protect the PV system from damage. For the case of M being more than 1.0, the results are not shown because the PV system is designed to operate at condition of M being less than one. This is done by calculating the input current and voltage corresponding to the output voltage and current. Then, M is varied accordingly for the inverter to

operate at minimum and maximum power conditions. Below the minimum power condition (for example, during heavy clouds or nighttime) or above the maximum power condition (for example, over rating of PV arrays which exceeds the rating of the inverter), the inverter should not operate to ensure the safety of the PV system and the environment. THD and power factor measurements for the proposed inverter are measured by using FLUKE 43B Power Quality



Fig. 19. THD result of the proposed multilevel PV inverter voltage waveform shown in Fig. 17. Fig. 21. Conventional three-level PWM inverter for PV application.

Fig. 20. Grid voltage Vg and grid current Ig at near-unity power factor.

Fig. 22. Experimental result of Vinv and Ig for the three-level PWM inverter.

Analyzer. The THD is shown in Fig. 19. This result is measured corresponding to Fig. 16 where the M value is 0.8. The corresponding power factor is measured, and the result is shown in Fig. 20. It is notable that both the grid voltage Vg and the current injected into the grid Ig are in phase with a power factor of 0.96. The results from the ve-level PWM inverter are compared with those from the three-level PWM inverter in terms of THD. Fig. 21 shows the conventional three-level PWM inverter for grid-connected PV application. The same current control techniques were used to control the overall performance of the inverter. The only difference between Fig. 21 and Fig. 9 is the elimination of auxiliary circuit, and therefore, only one dc-bus capacitor is used. The resulting waveform of Vinv and Ig is shown in Fig. 22. The results were taken at almost the same environmental conditions to ensure that Ig is similar to the measurement made for the ve-level inverter. As shown in Fig. 23, THD measurement for the three-level inverter is much higher when compared with that for the ve-level inverter. This proves that multilevel inverters can reduce the THD which is an essential criterion for grid-connected PV systems.

Fig. 23. THD result of the three-level PV inverter.

Efciency measurement has been carried out to compare the efciency of the three-level PWM inverter with that of the ve-level PWM inverter for PV application. The measured



efciency of the three-level PWM inverter is approximately 90%, whereas that of the ve-level PWM inverter is 86%. As expected, the efciency of the ve-level PWM inverter is lower compared with that with the conventional three-level PWM inverter. The main reason is the addition of the auxiliary circuit between the dcdc boost converter and the full-bridge inverter conguration. Switching losses of switch S1 in the auxiliary circuit have caused the efciency of the ve-level PWM inverter to be approximately 4% less than that of the three-level PWM inverter. However, simulation and experimental results show that the THD of the proposed inverter is lower when compared to that of the conventional three-level PWM inverter, which is an important element for grid-connected PV systems.

VI. C ONCLUSION This paper presented a single-phase multilevel inverter for PV application. It utilizes two reference signals and a carrier signal to generate PWM switching signals. The circuit topology, modulation law, and operational principle of the proposed inverter were analyzed in detail. A digital PI current control algorithm is implemented in DSP TMS320F2812 to optimize the performance of the inverter. Experimental results indicate that the THD of the ve-level inverter is much lesser than that of the conventional three-level inverter. Furthermore, both the grid voltage and the grid current are in phase at near-unity power factor. R EFERENCES
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Jeyraj Selvaraj was born in Kedah, Malaysia, in 1980. He received the B.Eng. (Hons) degree from Multimedia University, Cyberjaya, Malaysia, and the M.Sc. degree in power electronics and drives from the University of Birmingham, Birmingham, U.K., and University of Nottingham, Nottingham, U.K., in 2002 and 2004, respectively. He is currently working toward the Ph.D. degree at the Center of Research for Power Electronics, Drives, Automation and Control (UMPEDAC), Department of Electrical Engineering, University Malaya, Kuala Lumpur, Malaysia. His research interests include single- and three-phase multilevel inverters, digital proportionalintegral current control techniques, photovoltaic inverters, and dcdc converters.

Nasrudin A. Rahim (M89SM08) was born in Johor, Malaysia, in 1960. He received the B.Sc. (Hons.) and M.Sc. degrees from the University of Strathclyde, Glasgow, U.K., and the Ph.D. degree from HeriotWatt University, Edinburgh, U.K., in 1995. He is currently a Professor in the Department of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia, and the Director of the Center of Research for Power Electronics, Drives, Automation and Control (UMPEDAC). Prof. Rahim is the Chairman of the working group WG-8 covering reluctance motors of the IEEE Motor Subcommittee under the IEEE-PES Electric Machinery Committee. His research interests include power electronics, realtime control systems, and electrical drives.