PIC18F8720/8620/6720/6620

PIC18F8720/8620/6720/6620 Rev. A4 Silicon/Data Sheet Errata

The PIC18F8720/8620/6720/6620 Rev. A4 parts you have received conform functionally to the Device Data Sheet (DS39609A), except for the anomalies described below. Revision A4 Silicon can be identified by the following: Revision ID: 0x04

3. Module: I/O Ports (Parallel Slave Port)

While operating in Parallel Slave Port mode, the OBF bit (PSPCON<6>) is supposed to be set when a byte is written to either PORTD or LATD. It has been noted that OBF may not be correctly set when a byte is written to LATD. If the byte is written to PORTD, then the OBF bit is set correctly. Work around To ensure the OBF bit is set correctly, write to PORTD rather than LATD.

1. Module: Core (Program Memory Space)

Performing table read operations above the user program memory space (addresses over 1FFFFFh) may yield erroneous results at the extreme low end of the devices rated temperature range (-40C). This applies specifically to addresses above 1FFFFFh, including the user ID locations (200000h-200007h), the configuration bytes (300000h-30000Dh) and the device ID locations (3FFFFEh and 3FFFFFh). User program memory is unaffected. Work around Two possible work arounds are presented. Other solutions may exist. 1. Do not perform table read operations on areas above the user memory space at -40C. 2. Insert NOP instructions (specifically, literal FFFFh) around any table read instructions. The suggested optimal number is 4 instructions before and 8 instructions after each table read. This may vary depending upon the particular application and should be optimized by the user. Date Codes that pertain to this issue: All engineering and production devices.

4. Module: A/D (External Voltage Reference) and Comparator Voltage Reference

When the external voltage reference, VREF-, is selected for use with either the A/D or comparator voltage reference, AVSS is connected to VREF- in the comparator module. If VREF- is a voltage other than AVSS (which must be tied externally to VSS), excessive current will flow into the VREF- pin. Work around If external VREF- is used with a voltage other than 0V, enable the comparator voltage reference by setting the CVREN bit in the CVRCON register. This disconnects VREF- and AVSS within the comparator module.

2. Module: External Memory Interface (PIC18F8620 only)

In Extended Microcontroller mode, or Microprocessor mode, the external memory interface is inactive from 20000h to 2FFFFh. ALE and WRL signals are inactive between 20000h and 2FFFFh. Work around Shift RAM space to 30000h and above, or as an alternate solution, the PIC18F8720 device can be used. This issue will be resolved in a future version of silicon.

2003 Microchip Technology Inc.

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PIC18F8720/8620/6720/6620
5. Module: DAW Instruction
The DAW instruction may improperly clear the CARRY bit (STATUS<0>) when executed. Work around Test the CARRY bit state before executing the DAW instruction. If the CARRY bit is set, increment the next higher byte to be added, using an instruction such as INCFSZ (this instruction does not affect any Status flags and will not overflow a BCD nibble). After the DAW instruction has been executed, process the CARRY bit normally (see Example 1). Work around All work arounds will involve setting the contents of BSR<3:0> to some value other than 0Fh. In addition to those proposed below, other solutions may exist. 1. When developing or modifying code, keep these guidelines in mind: Assign 12-bit addresses to all variables. This allows the assembler to know when Access Banking can be used. Do not set the BSR to point to Bank 15 (BSR = 0Fh). Allow the assembler to manipulate the access bit present in most instructions. Accessing the SFRs in Bank 15 will be done through the Access Bank. Continue to use the BSR to select all GPR Banks. 2. If accessing a part of Bank 15 is required and the use of Access Banking is not possible, consider using indirect addressing. 3. If pointing the BSR to Bank 15 is unavoidable, review the absolute file listing. Verify that no instructions contain C9h in the 8 Least Significant bits while the BSR points to Bank 15 (BSR = 0Fh). Date Codes that pertain to this issue: All engineering and production devices.

EXAMPLE 1:
MOVLW ADDLW BTFSC INCFSZ DAW BTFSC INCFSZ 0x80 0x80 STATUS,C byte2 STATUS,C byte2

PROCESSING THE CARRY BIT DURING BCD ADDITIONS

; .80 (BCD) ; .80 (BCD) ; test C ; inc next higher LSB ; test C ; inc next higher LSB

This is repeated for each DAW instruction

6. Module: External Memory Interface (PIC18F8720 and PIC18F8620 only)

When performing writes on the external memory interface, a short glitch is present on the LB and UB lines. The length of the glitch is proportional to FOSC and also may vary with process, voltage and temperature. The glitch occurs well before the WRH line is asserted and no adverse affect on the operation of the external memory interface has been observed. Work around None

8. Module: MSSP (SPI, Slave Mode)

In its current implementation, the SS (Slave Select) control signal generated by an external master processor may not be successfully recognized by the PIC microcontroller operating in Slave Select mode (SSPM3:SSPM0 = 0100). In particular, it has been observed that faster transitions (those with shorter fall-times) are more likely to be missed than than slower transitions. Work around

7. Module:

MSSP (All I2C and SPI Modes)

The Buffer Full (BF) flag bit of the SSPSTAT register (SSPSTAT<0>) may be inadvertently cleared even when the SSPBUF register has not been read. This will occur only when the following two conditions occur simultaneously: The four Least Significant bits of the BSR register are equal to 0Fh (BSR<3:0> = 1111) and Any instruction that contains C9h in its 8 Least Significant bits (i.e., register file addresses, literal data, address offsets, etc.) is executed.

Insert a series resistor between the source of the SS signal and the corresponding SS input line of the microcontroller. The value of the resistor is dependent on both the application systems characteristics and process variations between microcontrollers. Experimentation and thorough testing is encouraged. This is a recommended solution. Others may exist. Date Codes that pertain to this issue: All engineering and production devices.

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PIC18F8720/8620/6720/6620
Clarifications/Corrections to the Data Sheet:
In the Device Data Sheet (DS39609A), the following clarifications and corrections should be noted.

3. Module: Data EEPROM (Reset Values)

In Table 3-3, the entries for the EECON1 and EECON2 registers are reversed; this reflects the actual order of these registers in the SFR memory map. The device Reset values (listed in the last three columns) displayed for EECON1 are actually those for EECON2 and vice versa. They are listed correctly in all other occurrences throughout the data sheet.

1. Module: Comparator Voltage Reference

The selection of the comparators voltage reference source is clarified as follows: setting the CVRSS bit (CVRCON<4>) is not sufficient to select (VREF+ VREF-) as the comparator reference source (CVRSRC). The existing text implies that this is all that is necessary. To select (VREF+ VREF-) as the Comparator Voltage Reference source, the Voltage Reference Configuration bits in the ADCON1 register (ADCON1<5:4>) must also be set to 11.

4. Module: Memory (SFR Summary)

In Table 4-3, the POR/BOR Reset Value (next to last column) of EECON1 should read as xx-0 x000, not 00-0 x000 as shown.

5. Module: Timer0 2. Module: A/D (VREF+ and VREFReferences)

The operation of the module is clarified by the addition of the following note to the end of Section 19.1 A/D Acquisition Requirements: Note: When using external voltage references with the A/D converter, the source impedance of the external voltage references must be less than 20 to obtain the A/D performance specified in parameters A01-A06. Higher reference source impedances will increase both offset and gain errors. Resistive voltage dividers will not provide a sufficiently low source impedance. To maintain the best possible performance in A/D conversions, external VREF inputs should be buffered with an operational amplifier or other low output impedance circuit. If deviating from the operating conditions specified for parameters A03-A06, the effect of parameter A50 (VREF input current) must be considered. In Section 11.3 (Timer0 Interrupt), the fourth sentence begins The TMR0IE bit must be cleared in software.... This is amended to read, The TMR0IF bit must be cleared in software....

6. Module: Pin Diagrams

In the Pin Diagrams on pages 2 and 3 of the Data Sheet, the Timer1/Timer3 clock source input/ oscillator output pin is labelled as T1OSO/T13CLK. The correct designation is T1OSO/T13CKI, which is used in all other references to this pin throughout the data sheet.

2003 Microchip Technology Inc.

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PIC18F8720/8620/6720/6620
7. Module: Voltage-Frequency Graph
In Section 26.0 Electrical Characteristics, the following figure has been updated to include the voltage frequency for Extended devices.

FIGURE 26-3:

PIC18F6620/6720/8620/8720 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED)

6.0V 5.5V 5.0V PIC18FX620/X720 4.2V

Voltage

4.5V 4.0V 3.5V 3.0V 2.5V 2.0V

16 MHz (Extended)

25 MHz (Industrial)

Frequency

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PIC18F8720/8620/6720/6620
8. Module: Table 26-25: A/D Converter Characteristics
In Section 26.0 Electrical Characteristics, Table 26-25 should be replaced by the following table.

TABLE 1:
Param Symbol No. A01 A03 A04 A05 A06 A10 A20 A20A A21 A22 A25 A30 A50 NR EIL EDL EG EOFF VREF VREFH VREFL VAIN ZAIN IREF

A/D CONVERTER CHARACTERISTICS: PIC18FXX20 (INDUSTRIAL, EXTENDED) PIC18LFXX20 (INDUSTRIAL)

Characteristic Resolution Integral Linearity Error Differential Linearity Error Gain Error Offset Error Monotonicity Reference Voltage (VREFH VREFL) Reference Voltage High Reference Voltage Low Analog Input Voltage Recommended impedance of Analog Voltage source VREF Input Current (Note 1) 1.8V 3V AVSS AVSS 0.3V AVSS 0.3V Min Typ guaranteed
(2)

Max 10 <1 <1 <1 <1.5

Units bit

Conditions

LSb VREF = VDD = 5.0V LSb VREF = VDD = 5.0V LSb VREF = VDD = 5.0V LSb VREF = VDD = 5.0V VSS VAIN VREF VDD < 3.0V VDD 3.0V

AVDD + 0.3V VREFH AVDD + 0.3V 2.5 5 150

V V V V V k A A

VDD 2.5V (Note 3) (Note 4) During VAIN acquisition During A/D conversion cycle

Note 1: 2: 3: 4:

Vss VAIN VREF The A/D conversion result never decreases with an increase in the Input Voltage and has no missing codes. For VDD < 2.5V, VAIN should be limited to < .5 VDD. Maximum allowed impedance for analog voltage source is 10 k. This requires higher acquisition times.

9. Module: Electrical Characteristics

In Section 26.0 Electrical Characteristics, page 307, Maximum voltage on RA4 with respect to VSS should be 8.5V (not 12.0V).

2003 Microchip Technology Inc.

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PIC18F8720/8620/6720/6620
REVISION HISTORY
Rev A Document (10/2003) First revision of this document. Listed silicon issue 1 (Core Program Memory Space), 2 (External Memory Interface), 3 (I/O Ports), 4 (A/D), 5 (DAW Instruction), 6 (External Memory Interface), 7 (MSSP All I2C and SPI Modes) and 8 (MSSP SPI, Slave Mode). Listed Data Sheet Clarification issue 1 (Comparator Voltage Reference), 2 (A/D), 3 (Data EEPROM), 4 (Memory), 5 (Timer0), 6 (Pin Diagrams), 7 (Voltage-Frequency Graph), 8 (A/D Converter Characteristics) and 9 (Electrical Characteristics).

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2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.

Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Companys quality system processes and procedures are QS-9000 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001 certified.

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