MISRIMAL NAVAJEE MUNOTH JAIN ENGINEERING COLLEGE

(Managed by Tamilnadu, Educational and Medical Trust)

Thorapakkam, Chennai- 600 097.

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MISRIMAL NAVAJEE MUNOTH JAIN ENGINEERING COLLEGE

(Managed by Tamil Nadu, Educational and Medical Trust)

Thoraipakkam, Chennai 600 097

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Ex. No.: 1

STUDY OF XILINX ISE 9.1i

Date:
AIM: To study XILINX ISE 9.1i. PROCEDURE:

Starting the ISE Software

To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting: Start All Programs Xilinx ISE 9.1i Project Navigator Note: Your start-up path is set during the installation process and may differ from the one
above.

Accessing Help
At any time during the tutorial, you can access online help for additional information about the ISE software and related tools. To open Help, do either of the following:

Press F1 to view Help for the specific tool or function that you have selected or highlighted.

Launch the ISE Help Contents from the Help menu. It contains information about creating and maintaining your complete design flow in ISE.

Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board. To create a new project:

1. Select File > New Project... The New Project Wizard appears. 2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically.

4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page.

6. Fill in the properties in the table as shown

below: Product Category: All

Family: Spartan3

Device:

XC3S200 Package: FT256 Speed Grade: -4

Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: Verilog (or VHDL) Verify that Enable Enhanced Design Summary is selected.

Leave the default values in the remaining fields. When the table is complete, your project properties will look like the following:

7. Click Next to proceed to the Create New Source window in the New Project Wizard.
At the end of the next section, your new project will be complete.

Create an HDL Source

In this section, you will create the top-level HDL file for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the Creating a VHDL Source section below, or skip to the Creating a Verilog Source section.

Creating a VHDL Source

Create a VHDL source file for the project as follows:

1. Click the New Source button in the New Project Wizard. 2. Select VHDL Module as the source type. 3. Type in the file name counter. 4. Verify that the Add to project checkbox is selected. 5. Click Next.

6. Declare the ports for the counter design by filling in the port information as shown below:

7. Click Next, then Finish in the New Source Wizard - Summary dialog box to
complete the new source file template.

8. Click Next, then Next, then Finish.

The source file containing the entity/architecture pair displays in the Workspace, and the counter displays in the Source tab, as shown below:

Using Language Templates (VHDL)

The next step in creating the new source is to add the behavioral description for the counter. To do this you will use a simple counter code example from the ISE Language Templates and customize it for the counter design. 1. Place the cursor just below the begin statement within the counter architecture. 2. Open the Language Templates by selecting Edit Language Templates

Note: You can tile the Language Templates and the counter file by selecting Window
Tile Vertically to make them both visible.

3. Using the + symbol, browse to the following code example:

VHDL Synthesis Constructs Coding Examples Binary Up/Down Counters Simple Counter Counters

4. With Simple Counter selected, select Edit Use in File, or select the Use
Template in File toolbar button. This step copies the template into the counter source file. 5. Close the Language Templates.

Final Editing of the VHDL Source

1. Add the following signal declaration to handle the feedback of the counter output below the architecture declaration and above the first begin statement:
signal "0000"; count_int : std_logic_vector(3 downto 0) :=

2. Customize the source file for the counter design by replacing the port and signal name placeholders with the actual ones as follows:

replace all occurrences of <clock> with CLOCK

replace all occurrences of <count_direction> with DIRECTION replace all occurrences of <count> with count_int

3.

Add the following line below the end process; statement: <= count_int;

COUNT_OUT

4. Save the file by selecting File Save.

When you are finished, the counter source file will look like the following: library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use

IEEE.STD_LOGIC_UNSIGNED.ALL;

Uncomment instantiating

the

following

library

declaration

if

any Xilinx primitive --library UNISIM; --use UNISIM.VComponents.all;

in

this

code.

entity counter is Port ( CLOCK : in STD_LOGIC; DIRECTION : in STD_LOGIC; COUNT_OUT : out STD_LOGIC_VECTOR end counter;

(3

downto

0));

architecture Behavioral of counter is signal count_int : std_logic_vector(3 downto 0) := "0000"; begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int <= count_int + 1; else count_int <= count_int 1; end if;
end if; end

process; COUNT_OUT <= count_int; end Behavioral;

Creating a Verilog Source

Create the top-level Verilog source file for the project as follows:

1. Click New Source in the New Project dialog box. 2. Select Verilog Module as the source type in the New Source dialog box. 3. Type in the file name counter. 4. Verify that the Add to Project checkbox is selected. 5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown below:

7. Click Next, then Finish in the New Source Information dialog box to complete the
new source file template.

8. Click Next, then Next, then Finish.

The source file containing the counter module displays in the Workspace, and the counter displays in the Sources tab, as shown below:

Using Language Templates (Verilog)

The next step in creating the new source is to add the behavioral description for counter. Use a simple counter code example from the ISE Language Templates and customize it for the counter design. 1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement.

2. Open the Language Templates by selecting Edit Language Templates

Note: You can tile the Language Templates and the counter file by selecting Window
Tile Vertically to make them both visible.

3. Using the + symbol, browse to the following code example:

Up/Down Counters Simple Counter

Verilog Synthesis Constructs Coding Examples Counters Binary

4. With Simple Counter selected, select Edit Use in File, or select the Use
Template in File toolbar button. This step copies the template into the counter source file. 5. Close the Language Templates.

Final Editing of the Verilog Source

1. To declare and initialize the register that stores the counter value, modify
the declaration statement in the first line of the template as follows: replace: <reg_name>; reg with: [<upper>:0] reg [3:0]

count_int = 0; 2. Customize the template for the counter design by replacing the port and signal name placeholders with the actual ones as follows:

replace all occurrences of <clock> with CLOCK

replace all occurrences of <up_down> with DIRECTION replace all occurrences of <reg_name> with count_int

3. Add the following line just above the endmodule statement to assign the register
value to the output port: assign COUNT_OUT = count_int;

4. Save the file by selecting File Save.

When you are finished, the code for the counter will look like the following: module counter(CLOCK, DIRECTION, COUNT_OUT); input CLOCK; input DIRECTION; output [3:0] COUNT_OUT;
reg [3:0] count_int = 0; always @(posedge CLOCK)

if

(DIRECTION) count_int <= count_int + 1; else count_int <= count_int

1;

assign COUNT_OUT = count_int; endmodule You have now created the Verilog source for the tutorial project.

Checking the Syntax of the New Counter Module

When the source files are complete, check the syntax of the design to find errors and typos.

1. Verify that Synthesis/Implementation is selected from the drop-down list in

the Sources window. 2. Select the counter design source in the Sources window to display the related processes in the Processes window.

3. Click the + next to the Synthesize-XST process to expand the process group. 4. Double-click the Check Syntax process.
Note: You must correct any errors found in your source files. You can check for errors in
the Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design.

5.

Close the HDL file.

Design Simulation
Verifying Functionality using Behavioral Simulation
Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench. Create the test bench waveform as follows:

1. Select the counter HDL file in the Sources window. 2. Create a new test bench source by selecting Project New Source. 3. In the New Source Wizard, select Test Bench WaveForm as the source type, and
type counter_tbw in the File Name field.

4. Click Next. 5. The Associated Source page shows that you are associating the test bench
waveform with the source file counter. Click Next.

6. The Summary page shows that the source will be added to the project, and it displays
the source directory, type and name. Click Finish. 7. You need to set the clock frequency, setup time and output delay times in the Initialize Timing dialog box before the test bench waveform editing window opens. The requirements for this design are the following:
The counter must operate correctly with an input clock frequency = 25 MHz.

The DIRECTION input will be valid 10 ns before the rising edge of CLOCK.
The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. The

design requirements correspond with the values below. Fill in the fields in the Initialize Timing dialog box with the following information:
Clock High Time: 20

ns. Clock Low Time: 20 ns. Input Setup Time: 10 ns.

Output Valid Delay: 10 ns. Offset: 0 ns.

Global Signals: GSR (FPGA)

Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically.

Initial Length of Test Bench: 1500 ns.

8. Click Finish to complete the timing initialization. 9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the
Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for the counter design as follows:
Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that

the counter will count up.

Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that

the counter will count down.

10. Save the waveform.

11. In the Sources window, select the Behavioral Simulation view to see that the
test bench waveform file is automatically added to your project.

12. Close the test bench waveform.

Simulating Design Functionality

Verify that the counter design functions as you expect by performing behavior simulation as follows:

1. Verify that Behavioral Simulation and counter_tbw are selected in the

Sources window.

2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process
and double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation to the end of the test bench.

3. To view your simulation results, select the Simulation tab and zoom in on
the transitions. 4. Verify that the counter is counting up and down as expected.

5. Close the simulation view. If you are prompted with the following message, You
have an active simulation open. Are you sure you want to close it?, click Yes to continue. You have now completed simulation of your design using the ISE Simulator.

Create Timing Constraints

Specify the timing between the FPGA and its surrounding logic as well as the frequency the design must operate at internal to the FPGA. The timing is specified by entering constraints that guide the placement and routing of the design. It is recommended that you enter global constraints. The clock period constraint specifies the clock frequency at which your design must operate inside the FPGA. The offset constraints specify when to expect valid data at the FPGA inputs and when valid data will be available at the FPGA outputs.

Entering Timing Constraints

To constrain the design do the following:

1. Select Synthesis/Implementation from the drop-down list in the Sources

window.

2. Select the counter HDL source file.

3. Click the + sign next to the User Constraints processes group, and double-click the
Create Timing Constraints process. ISE runs the Synthesis and Translate steps and automatically creates a User Constraints File (UCF). You will be prompted with the following message:

4. Click Yes to add the UCF file to your project.

The counter.ucf file is added to your project and is visible in the Sources window. The Xilinx Constraints Editor opens automatically. Note: You can also create a UCF file for your project by selecting Project Create
New Source.

In the next step, enter values in the fields associated with CLOCK in the Constraints Editor Global tab.

5. Select CLOCK in the Clock Net Name field, then select the Period toolbar button
or double-click the empty Period field to display the Clock Period dialog box.

6.

Enter 40 ns in the Time field.

7. Click OK. 8. Select the Pad to Setup toolbar button or double-click the empty Pad to Setup
field to display the Pad to Setup dialog box.

9. Enter 10 ns in the OFFSET field to set the input offset constraint.

10. Click OK.

11. Select the Clock to Pad toolbar button or double-click the empty Clock to Pad
field to display the Clock to Pad dialog box.

12. Enter 10 ns in the OFFSET field to set the output delay constraint.

13. Click OK.

The constraints are displayed in the Constraints (

14. Save the timing constraints. If you are prompted to rerun the TRANSLATE or
XST step, click OK to continue. 15. Close the Constraints Editor.

Implement Design and Verify Constraints

R

Implement the design and verify that it meets the timing constraints specified in the previous section.

Implementing the Design

1. Select the counter source file in the Sources window. 2. Open the Design Summary by double-clicking the View Design Summary
process in the Processes tab.

3. Double-click the Implement Design process in the Processes tab.

4. Notice that after Implementation is complete, the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings. Locate the Performance Summary table near the bottom of the Design Summary.

5.
R

6. Click the All Constraints Met link in the Timing Constraints field to view the
Timing Constraints report. Verify that the design meets the specified timing requirements.

7.

Close the Design Summary.

Assigning Pin Location Constraints

Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan-3 Startup Kit demo board. To constrain the design ports to package pins, do the following:

1. Verify that counter is selected in the Sources window. 2. Double-click the Assign Package Pins process found in the User Constraints
process group. The Xilinx Pinout and Area Constraints Editor (PACE) opens. 3. Select the Package View tab. 4. In the Design Object List window, enter a pin location for each pin in the Loc column using the following information: CLOCK input port connects to FPGA pin T9 (GCK0 signal on board)
COUNT_OUT<0> output port connects to FPGA pin K12 (LD0 signal on board)

COUNT_OUT<1> output port connects to FPGA pin P14 (LD1 signal on board) COUNT_OUT<2> output port connects to FPGA pin L12 (LD2 signal on board) COUNT_OUT<3> output port connects to FPGA pin N14 (LD3 signal on board)

DIRECTION input port connects to FPGA pin K13 (SW7 signal on board) 5. Select File Save. You are prompted to select the bus delimiter type based on the synthesis tool you are using. Select XST Default <> and click OK. 6. Close PACE.

Reimplement Design and Verify Pin Locations

Reimplement the design and verify that the ports of the counter design are routed to the package pins specified in the previous section. First, review the Pinout Report from the previous implementation by doing the following:

1. Open the Design Summary by double-clicking the View Design Summary

process in the Processes window.

2. Select the Pinout Report and select the Signal Name column header to sort the
signal names. Notice the Pin Numbers assigned to the design ports in the absence of location constraints.

3. Reimplement the design by double-clicking the Implement Design process. 4. Select the Pinout Report again and select the Signal Name column header to sort
the signal names. 5. Verify that signals are now being routed to the correct package pins.

6.

Close the Design Summary.

Download Design to the Spartan-3 Demo Board

This is the last step in the design verification process. This section provides simple instructions for downloading the counter design to the Spartan-3 Starter Kit demo board.

1. Connect the 5V DC power cable to the power input on the demo board (J4).
2. Connect the download cable between the PC and demo board (J7).

3. Select Synthesis/Implementation from the drop-down list in the Sources

window. 4. Select counter in the Sources window.

5. In the Processes window, click the + sign to expand the Generate

Programming File processes.

6. Double-click the Configure Device (iMPACT) process. 7. The Xilinx WebTalk Dialog box may open during this process. Click Decline. 8. Select Disable the collection of device usage statistics for this project
only and click OK. iMPACT opens and the Configure Devices dialog box is displayed.

9. In the Welcome dialog box, select Configure devices using Boundary-Scan

(JTAG).

10. Verify that Automatically connect to a cable and identify Boundary-Scan

chain is selected.

11. Click Finish. 12. If you get a message saying that there are two devices found, click OK to continue.
The devices connected to the JTAG chain on the board will be detected and displayed in the IMPACT window 13. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200 device in the JTAG chain, select the counter.bit file and click Open.

14. If you get a Warning message, click OK. 15. Select Bypass to skip any remaining devices. 16. Right-click on the xc3s200 device image, and select Program... The
Programming Properties dialog box opens.

17. Click OK to program the device.

When programming is complete, the Program Succeeded message is displayed.

On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running. 18. Close IMPACT without saving.

Ex. No.: 2 Date: AIM:

STUDY OF XC3S400- XILINX SPARTAN 3 FPGA

To study XC3S400 XILINX Spartan 3 Field Programmable Gate Array (FPGA) INTRODUCTION: A field programmable gate array (FPGA) is a semiconductor device containing programmable logic components called configurable logic blocks and programmable interconnects. Logic blocks can be programmed to perform the logic functioning ranging from basic gates to more complex logic function. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. A hierarchy of programmable interconnects allows logic blocks to be interconnected as needed by the system engineer (designer). These can be programmed by the designer, after FPGA is manufactured, to implement any logical function hence the name FIELD PROGRAMMABLE. FPGA DESIGN AND PROGRAMMING To define the behaviour of the FPGA the user provides a hardware description language (HDL) or a schematic design. Common HDLs are VHDL and Verilog. Then, using an electronic design automation tool, a technology netlist is generated. This can be then fitted to the actual FPGA architecture using a process called place-and-route. The user will validate the map, place and route results via timing analysis, simulation and other verification methodologies. Once the design and validation process is complete, the bit file is generated is used to configure the FPGA. XILINX XC3S400 SPARTAN 3 FPGA

It is specifically designed as very low cost, high performance logic solution for high volume, consumer-oriented applications. ARCHITECTURE OF XC3S400 This consists of 5 fundamental programmable functionable elements 1. Configurable logic blocks (CLB) contain RAM based look-up-tables (LUTs) to implement logic and storage elements that can be used as flip flops or latches. CLBs can be programmed to perform a wide variety of logical functions as well as to store data. 2. I/O Blocks (IOBs) control the flow of data between the I/O pin and the internal logic of the device. Each IOB supports bidirectional data flow plus 2-state operations. Double Data rate (DDR) registers are included. The digitally controlled impedance (DCI) feature provides automatic on-chip terminations, simplifying board designs. 3. Block RAM provides data storage in the form of 18-10 bit dual port blocks 4. Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the products 5. Digital clock manager (DCM) blocks provide self calibrating, fully digital solution for distributing, delaying, multiplying, dividing and phase shifting clock signals.

These elements are organized as shown in the diagram. A ring of IOBs surrounds a regular array of CLBs. It has 4 RAM columns. Each column is made up of several 18kbit RAM blocks; each block is associated with a delicate multiplier. The DCMs are positioned at the ends of the outer block RAM columns. XC3S400 consists of rich network of traces and switches that interconnect all functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections as routing.

RESULT: Thus XC3S400 XILINX SPARTAN 3 field programmable gate array (FPGA) was studied.

Ex. No.: 3 Date:

FPGA DESIGN FLOW

AIM To study FPGA design flow using XILINX ISE 9.1 i INTRODUCTION: The integrated software environment (ISE) is the Xilinx design software that allows to take the design from design entry through Xilinx device programming. The ISE design flow comprises the following steps, design entry, design synthesis, design implementation, and Xilinx device programming. Design verification which includes both function verification and timing verification, takes place at different points during the design flow. DESIGN ENTRY: Design entry is the first step in the ISE design flow. During design entry, sources files are created based on the design objectives. The top-level design file can be created using a Hardware Description Language (HDL), such as VHDL, Verilog or using a schematic. SYNTHESIS: After design entry and optional simulation, the synthesis step is run. During this step, VHDL, verilog, or mixed language designs become netlist files that are accepted as input to the implementation step. IMPLEMENTATION: After synthesis, the design implementation is executed, which converts the logical design into a physical file format that can be downloaded to the selected target device. From project Navigator, the implementation process can be run in one step, or each of the implementation processes can be run separately. BACK ANNOTATION:

Back annotation is the translation of a routed or fitted design to a timing simulation netlist. VERIFICATION: The functionality of the design can be verified at several points is the design flow. The simulator software can be used to verify the functionality and timing of the design or a portion of the design. The simulator interprets VHDL or verilog code into circuit functionality and displays logical results of the described HDL to determine correct circuit operation. Simulation allows to create and verify complex functions in a relatively small amount of time. The in-circuit verification can also be run after programming the device. DEVICE CONFIGURATION: After generating a programming file, the target device is configured. During configuration files are generated and the programming files are downloaded from a host computer to a Xilinx device. RESULT Thus the FPGA design flow was studied using Xilinx ISE 9.1i.

Ex. No.: 4 Date: AIM:

STUDY OF SIMULATION USING XILINX ISE-9.1.i

To study the simulation of a digital circuit using Xilinx ISE 9.1.i INTRODUCTION: During HDL simulation, the simulator software verified the functionality, the timing of the design or portion of the design. The simulator interprets VHDL or Verilog code into circuit functionality and displays the logical result of the desired HDL to determine correct circuit operation. Simulation allows to create and verify complex functions in a relatively small amount of time. Simulation takes place at several points in the design flow. It is one of the first steps after design entry and one of the last steps after implementation. As part of verifying the end functionality and performance of the design. Simulation is an iterative process, which may require repeating until both design functionality and performance timing is met. For a typical design, simulation libraries 1. Compilation of the simulation libraries 2. Creation of the designs test bench 3. Functional simulation 4. Implementation of the design and creation of the timing simulation netlist 5. Timing simulation SIMULATION LIBRARIES Most designs are built with gentle code, so device specific components are not necessary. However in certain cases if may be required or beneficial to use device specification components in the code to achieve the desired circuit implementation and results when the component is instantiated

in the design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation, XILINX provides simulation libraries for simulation primitives. UNISIM library for functional simulation of XILINX primitives XILINX core library for functional simulation of linx primitives SIMPRIM lib for timing simulation of XILINX primitives TEST BENCH To simulate your design you need both the design under test (DUT) or unit under test (UUT) and the stimulus provided by the test bench. A test bench is HDL code that allows to provide a documental, repeatable set of stimuli that is portable across different simulator. A test bench can be as simple as a file with clock and input data or a more complicated file that includes error checking, file input and output and conditional testing. The test bench can be created using either of the following methods. (i) TEXT EDITOR This is the recommended method for verifying complex designs. It allows using all the features available in the HDL language and gives you flexibility in verifying design. Although this method may be more challenging in that one must create this code, the advantage is that it may produce more precise & accurate results than using the bench waveform editor.

(ii) XILINX TEST BENCH WAVEFORM EDITOR This is the recommended method for verifying less complicated simulation tasks, and is recommended if the designer is new to HDL simulation. It allows to graphically enter the test bench to drive the stimulus to the design. The same test bench can be used for both functions and timing simulation FUNCTIONAL SIMULATION After the simulation libraries & create the test bench & design code are compiled, one can perform functional simulation on the design. Functional simulation is an iterative process, which may require multiple simulations to achieve the desired end functionality of the design. RESULT Thus the Simulation using XILINX ISE-9.1.i was studied.

Ex. No.: 5 Date: AIM

STUDY OF SCHEMATIC ENTRY USING XILINX ISE 9.1i

To study the schematic entry of a digital circuit using XILINX ISE9.1i. INTRODUCTION Schematics are used for top level or lower level design files. It allows to have a visual representation of the design. TOP LEVEL SCHEMATIC Schematics are used in the top level and low level modules are created using any of the following source types. To instantiate a lower level module in the top level design and the schematic symbol is instantiated. LOWER LEVEL SCHEMATIC Schematics can be used to define the lower level modules of the design. If the top level design is schematic symbol is created and it is instantiated in the top level. If the top level design file is an HDL file a template is created. All schematics are ultimately converted either VHDL or verilog structural netlist before being passed. SCHEMATIC DESIGN METHODS When using a schematic the top level design either of the following method is used to describe the lower level modules. i) TOP-DOWN SCHEMATIC DESIGN METHOD

Using this method a top level block diagram description of the design is created using a schematic. Then each symbol pushed down and its behaviour is defined using HDL or schematic file. 1) SCHEMATIC: The schematic contains input markers that correspond to the pins in the block symbol created. The schematic is built by adding symbols ad described in adding a symbol. 2) VHDL (OR) VERILOG: The template contains HDC port descriptions that correspond to the pins in the block symbol created. The behavior of the module can be then added. The ISE language template provides a convenient method to insert. ii) BOTTON-UP SCHEMATIC DESIGN METHOD: Using this method a top level schematic design is created and lower level functional blocks is then created to instantiate. RESULT: Thus the schematic entry of a digital circuit was studied using XILINX ISE 9.1i.

3 Ex. No.: 6 Date: SIMULATION AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS I

AIM To Simulate and Implement Half Adder, Full Adder, Half Subtractor and Full Subtractor using XC3S400 FPGA trainer kit. APPARATUS REQUIRED 1. PC with Xilinx ISE 9.1i 2. XC3S400 FPGA kit PROGRAM

HALF ADDER module half_adder(a,b,sum,carry); input a,b; output sum,carry;

xor (sum,a,b); and (carry,a,b); endmodule

WAVEFORM

FULL ADDER module full_adder(a,b,c,sum,carry); input a,b,c; output sum,carry; assign sum = a^b^c; assign carry = (a&b)|(b&c)|(c&a); endmodule 4

WAVEFORM

HALF SUBTRACTOR module half_subtractor (x,y,difference,borrow); input x,y; output difference,borrow ;

assign difference = (x^y), borrow =(~x&y); endmodule

WAVEFORM

FULL SUBTRACTOR module full_subtractor (x,y,bin,d,bout); input x,y,bin; output d,bout; assign d = (x^y^bin), bout =(~x&y)|(~x&bin)|(y&bin); endmodule WAVEFORM

PROCEDURE 1. Open the Xilinx software and click the menu option file and select the new project from the sub menu 2. In the process tab, click on create new source->verilog module. Then give a file name for it and select the respective inputs and outputs from it. 3. Enter the given code respectively. 4. Go to process tab, click on synthesise XST->check syntax for checking the program.

5. From the process tab, click on create new source->test bench waveform and give a file name to it. 6. Select combinational in initial timing and clock wizard. 7. Give the input in the waveform module 8. In the sources tab change to behavioural simulation and click the test bench file you have created. 9. Click on the XILINX ISE Simulator from the process tab and select the simulate behavioural model. 10. The output will be obtained in the wave form module.

IMPLEMENTATION 1. Select the source file in the sources window 2. Open the design summary by clicking the view design process in the processes tab. 3. DOUBLE Click the implement design process in the process tab. 4. Notice that after implementation is complete, the implementation processes have a green check mark next to them indicating that they are completed successfully without any errors or warnings. 5. Locate the performance summary table near the bottom of the design summary. 6. Click the all constraints met link in the timing constraints report. Verify that the design meets the specified timing requirements. 7. Close the design summary.

RESULT Thus Half Adder, Full Adder, Half subtractor and Full subtractor circuits are simulated and implemented using XC3S400 FPGA Kit.

5 Ex. No.: 7 Date: SIMULATION AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS II

AIM To simulate and Implement 8 bit Adder, 4 bit Multiplier, 8:3 Encoder, 3:8 Decoder, 1:8 Demultiplexer and 4:1 Mulitiplexer. APPARATUS REQUIRED 1. PC with Xilinx ISE 9.1i 2. XC3S400 FPGA kit PROGRAMS 8 BIT ADDER module bit_8_adder(A,B,Cin,S,Cout); input [7:0] A,B;

input Cin; output [7:0] S; output Cout; wire C0,C1,C2,C3,C4,C5,C6; full_add FA0(A[0],B[0],Cin, S[0], C0); full_add FA1(A[1],B[1],C0, S[1], C1); full_add FA2(A[2],B[2],C1, S[2], C2); full_add FA3(A[3],B[3],C2, S[3], C3); full_add FA4(A[4],B[4],C3, S[4], C4); full_add FA5(A[5],B[5],C4, S[5], C5); full_add FA6(A[6],B[6],C5, S[6], C6); full_add FA7(A[7],B[7],C6, S[7], Cout); endmodule module full_add(a,b,c,sum,carry); input a,b,c; output sum,carry; assign sum = a^b^c; assign carry = (a&b)|(b&c)|(c&a); endmodule 6

WAVEFORM

4 BIT MULTIPLIER

module multiplier_4_bit (A,B,C); input [3:0] A; input [3:0] B; output [7:0] C; assign C[7:0] =A[3:0] * B[3:0]; endmodule WAVEFORM

7 8 :3 ENCODER module encoder8_to_3(D0,D1,D2,D3,D4,D5,D6,D7,X,Y,Z); input D0,D1,D2,D3,D4,D5,D6,D7; output X,Y,Z; or (X,D4,D5,D6,D7); or(Y,D2,D3,D6,D7); or (Z,D1,D3,D5,D7); endmodule WAVEFORM

3:8 DECODER module decoder3_to_8(X,Y,Z, D0,D1,D2,D3,D4,D5,D6,D7); input X,Y,Z; output D0,D1,D2,D3,D4,D5,D6,D7; assign D0 = (~X & ~Y&~Z), D1 = (~X & ~Y&Z ), D2 = (~X & Y&~Z ), D3 = (~X & Y&Z ), D4 = (X & ~Y&~Z ), D5 = (X & ~Y&Z ), D6 = (X & Y&~Z ), D7 = (X &Y&Z ); Endmodule 8 WAVEFORM

1:8 DEMULTIPLEXER module demux1_to_8(i,S0,S1,S2, D0,D1,D2,D3,D4,D5,D6,D7); input I,S0,S1,S2; output D0,D1,D2,D3,D4,D5,D6,D7; assign D0 = (i & ~S2 & ~S1 & ~S0), D1 = (i& ~S2 & ~S1 & S0), D2 = (i & ~S2 & S1 & ~S0), D3 = (i & ~S2 & S1 & S0), D4 = (i & S2 & ~S1 & ~S0), D5 = (i & S2 & ~S1 & S0), D6 = (i & S2 & S1 & ~S0), D7 = (i & S2 & S1 & S0); Endmodule WAVEFORM

9 4:1 MULTIPLEXER module mux4_to_1(i0,i1,i2,i3,s0,s1,out); input i0,i1,i2,i3,s0,s1; output out; assign out = (i0 & ~s1 & ~s0)|(i1 & ~s1 & s0)|(i2 & s1 & ~s0)|(i3 & s1 & s0); endmodule WAVEFORM

PROCEDURE 1. Open the Xilinx software and click the menu option file and select the new project from the sub menu 2. In the process tab, click on create new source->verilog module. Then give a file name for it and select the respective inputs and outputs from it. 3. Enter the given code respectively. 4. Go to process tab, click on synthesise XST->check syntax for checking the program. 5. From the process tab, click on create new source->test bench waveform and give a file name to it. 6. Select combinational in initial timing and clock wizard. 7. Give the input in the waveform module 8. In the sources tab change to behavioural simulation and click the test bench file you have created. 9. Click on the XILINX ISE Simulator from the process tab and select the simulate behavioural model. 10. The output will be obtained in the wave form module.

IMPLEMENTATION 1. Select the source file in the sources window 2. Open the design summary by clicking the view design process in the processes tab. 3. DOUBLE Click the implement design process in the process tab. 4. Notice that after implementation is complete, the implementation processes have a green check mark next to them indicating that they are completed successfully without any errors or warnings. 5. Locate the performance summary table near the bottom of the design summary. 6. Click the all constraints met link in the timing constraints report. Verify that the design meets the specified timing requirements. 7. Close the design summary. RESULT Thus 8 bit Adder, 4 bit Multiplier, 8:3 Encoder, 3:8 Decoder,1:8 Demultiplexer and 4:1 Multiplexer circuits are simulated and implemented.

10

Ex. No.: 8 Date:

SIMULATION AND IMPLEMENTATION OF SEQUENTIAL CIRCUITS I

AIM

To simulate and Implement Flip Flops, Universal Shift Register, Up down Counter and Serial Adder. APPARATUS REQUIRED 1. PC with Xilinx ISE 9.1i 2. XC3S400 FPGA kit PROGRAMS FLIPFLOPS

SR FLIP-FLOP module sr_flipflop(s,r,clk,q,qbar); input s,r,clk; output q,qbar; reg q,qbar; always@(posedge clk) begin case ({s,r}) 2'b00:q=q; 2'b01:q=1'b0; 2'b10:q=1'b1; 2'b11:q=1'bx; endcase qbar=~q; end endmodule

11 WAVEFORM

D FLIP-FLOP module D_FF (D,clk,reset,Q); input D,clk,reset; output Q; reg Q; always @ (posedge reset or negedge clk) if (reset) Q = 1'b0; else Q = D; endmodule

WAVEFORM

JK FLIP-FLOP module JK_FF (J,K,clk,reset,Q); input J,K,clk,reset; output Q; wire w; assign w = (J&~Q)|(~K&Q); D_FF dff1(w,clk,reset,Q); endmodule

module D_FF (D,clk,reset,Q);

input D,clk,reset; output Q; reg Q; always @ (posedge reset or negedge clk) if (reset) Q = 1'b0; else Q = D; endmodule WAVEFORM

T FLIP-FLOP module T_FF (T,clk,reset,Q); input T,clk,reset; output Q; wire w; assign w = T^Q; D_FF dff1(w,clk,reset,Q); endmodule

module D_FF (D,clk,reset,Q); input D,clk,reset; output Q; reg Q; always @ (posedge reset or negedge clk) if (reset)

12

Q = 1'b0; else Q = D; endmodule WAVEFORM

UNIVERSAL SHIFT REGISTER module unishft_reg(s1,s0,PIin,LFin,RTin,clk,reset,q3,q2,q1,q0); input s1,s0; input LFin,RTin; input clk,reset; input[3:0]PIin; output q3,q2,q1,q0; reg q3,q2,q1,q0; always @ (posedge clk or posedge reset) if (reset) {q3,q2,q1,q0}=4'b0000; else

case ({s1,s0}) 2'b00:{q3,q2,q1,q0}={q3,q2,q1,q0}; 2'b01:{q3,q2,q1,q0}={RTin,q3,q2,q1}; 2'b10:{q3,q2,q1,q0}={q2,q1,q0,LFin}; 2b11 :{q3,q2,q1,q0}=PIin; endcase endmodule 13

WAVEFORM

SYNCHRONOUS UP-DOWN COUNTER module updown_counter(up_down,clk,reset,count); input [1:0]up_down; input clk,reset; output [2:0]count; reg[2:0]count; always @(posedge clk or posedge reset) if (reset==1)count<=3'b000; else if(up_down==2'b00 ||up_down ==2'b11) count<=count; else if(up_down==2'b01) count<=count+1; else if(up_down==2'b10) count<=count-1; endmodule

WAVEFORM

PROCEDURE 1. Open the Xilinx software and click the menu option file and select the new project from the sub menu 2. In the process tab, click on create new source->verilog module. Then give a file name for it and select the respective inputs and outputs from it. 3. Enter the given code respectively. 4. Go to process tab, click on synthesise XST->check syntax for checking the program. 5. From the process tab, click on create new source->test bench waveform and give a file name to it. 6. Select combinational in initial timing and clock wizard. 7. Give the input in the waveform module 8. In the sources tab change to behavioural simulation and click the test bench file you have created. 9. Click on the XILINX ISE Simulator from the process tab and select the simulate behavioural model. 10. The output will be obtained in the wave form module.

IMPLEMENTATION 1. Select the source file in the sources window 2. Open the design summary by clicking the view design process in the processes tab. 3. DOUBLE Click the implement design process in the process tab. 4. Notice that after implementation is complete, the implementation processes have a green check mark next to them indicating that they are completed successfully without any errors or warnings. 5. Locate the performance summary table near the bottom of the design summary. 6. Click the all constraints met link in the timing constraints report. Verify that the design meets the specified timing requirements. 7. Close the design summary.

RESULT Thus Flip Flops, Universal Shift Register, Up down Counter and Serial Adder circuits are Simulated and Implemented.

Ex. No.: 9 Date:

SIMULATION AND IMPLEMENTATION OF SEQUENTIAL CIRCUITS II

AIM To Simulate and Implement PRBS generator and Accumulator.

APPARATUS REQUIRED 1. PC with Xilinx ISE 9.1i 2. XC3S400 FPGA kit PROGRAMS PRBS GENERATOR module prbsgen(clk, reset, en, q); input clk, reset, en; output [7:0] q; reg [7:0] q; always @(posedge clk or posedge reset) begin if (reset) q <= 8'd 1; else if (en) q <= {q[6:0], q[7] ^ q[5] ^ q[4] ^ q[3]}; end endmodule WAVEFORM

ACCUMULATOR module accumlator(Clk, CLR, D, Q); input Clk, CLR; input [3:0] D; output [7:0] Q; reg [7:0] tmp; always @(posedge Clk or posedge CLR) begin if (CLR) tmp = 4'b0000; else tmp = tmp + D; end assign Q = tmp; endmodule WAVEFORM

PROCEDURE 1. Open the Xilinx software and click the menu option file and select the new project from the sub menu 2. In the process tab, click on create new source->verilog module. Then give a file name for it and select the respective inputs and outputs from it. 3. Enter the given code respectively. 4. Go to process tab, click on synthesise XST->check syntax for checking the program. 5. From the process tab, click on create new source->test bench waveform and give a file name to it. 6. Select combinational in initial timing and clock wizard.

7. Give the input in the waveform module 8. In the sources tab change to behavioural simulation and click the test bench file you have created. 9. Click on the XILINX ISE Simulator from the process tab and select the simulate behavioural model. 10. The output will be obtained in the wave form module.

IMPLEMENTATION 1. Select the source file in the sources window 2. Open the design summary by clicking the view design process in the processes tab. 3. DOUBLE Click the implement design process in the process tab. 4. Notice that after implementation is complete, the implementation processes have a green check mark next to them indicating that they are completed successfully without any errors or warnings. 5. Locate the performance summary table near the bottom of the design summary. 6. Click the all constraints met link in the timing constraints report. Verify that the design meets the specified timing requirements. 7. Close the design summary.

RESULT Thus PRBS generator and Accumulator circuits are simulated and implemented.

Ex. No.13 Date

LAYOUT GENERATION AND SIMULATION OF CMOS INVERTER

Aim: To generate layout of CMOS inverter and to simulate it using Microwind and DSCH V2.0

Software tools required: Microwind and DSCH V2.0

Schematic diagram of CMOS Inverter:

The CMOS inverter The CMOS inverter design is detailed in the figure below. Here the p-channel MOS and the n-channel MOS transistors function as switches. When the input signal is logic 0 , the nMOS is switched off while PMOS passes VDD through the output. When the input signal is logic 1 Fig. the pMOS is switched off while the nMOS passes VSS to the output.

CMOS Inverter The fan out corresponds to the number of gates connected to the inverter output. Physically, a large fan out means a large number of connections that is a large load capacitance. If we simulate an inverter loaded with one single output, the switching delay is small. Now, if we load the inverter by

several outputs, the delay and the power consumption are increased. The power consumption linearly increases with the load capacitance. This is mainly due to the current needed to charge and discharge that capacitance.

Manual layout of the inverter

Click the icon MOS generator on the palette. The following window appears. By default the proposed length is the minimum length available in the technology (2 lambda), and the width is 10 lambda. In 0.12m technology, where lambda is 0.06m, the corresponding size is 0.12m for the length and 0.6m for the width. Simply click Generate Device, and click on the middle of the screen to fix the MOS device. Click again the icon MOS generator on the palette. Change the type of device by a tick on pchannel, and click Generate Device. Click on the top of the nMOS to fix the pMOS device.

Selecting the n- MOS device

Connection between Devices

Connections required to build the inverter

Within CMOS cells, metal and polysilicon are used as interconnects for signals. Metal is a much better conductor than polysilicon. Consequently, polysilicon is only used to interconnect gates, such as the bridge (1) between pMOS and nMOS gates, as described in the schematic diagram of figure. Polysilicon is rarely used for long interconnects, except if a huge resistance value is expected. In the layout shown in figure, the polysilicon bridge links the gate of the n-channel MOS with the gate of the p-channel MOS device. The polysilicon serves as the gate control and the bridge between MOS gates.

Polysilicon Bridge between pMOS and nMOS devices

Metal-to-poly

As polysilicon is a poor conductor, metal is preferred to interconnect signals and supplies. Consequently, the input connection of the inverter is made with metal. Metal and polysilicon are

separated by an oxide which prevents electrical connections. Therefore, a box of metal drawn across a box of polysilicon does not allow an electrical connection (Figure). To build an electrical connection, a physical contact is needed. The corresponding layer is called "contact". We may insert a metal-to-polysilicon contact in the layout using a direct macro situated in the palette.

Physical contact between metal and polysilicon

Adding a poly contact, poly and metal bridges to construct the CMOS inverter (InvSteps.MSK) The Process Simulator shows the vertical aspect of the layout, as when fabrication has been completed. This feature is a significant aid to understand the circuit structure and the way layers are stacked on top of each other. A click of the mouse on the left side of the n-channel device layout and the release of the mouse at the right side give the cross-section reported in figure.

The 2D process section of the inverter circuit near the nMOS device (InvSteps.MSK)

Supply Connections

The next design step consists in adding supply connections, that is the positive supply VDD and the ground supply VSS. We use the metal2 layer (Second level of metallization) to create horizontal supply connections. Enlarging the supply metal lines reduces the resistance and avoids electrical overstress. The simplest way to build the physical connection is to add a metal/Metal2 contact that may be found in the palette. The connection is created by a plug called "via" between metal2 and metal layers. The final layout design step consists in adding polarization contacts. These contacts convey the VSS and VDD voltage supply close to the bulk regions of the device. Remember that the n-well region should always be polarized to a high voltage to avoid short-circuit between VDD and VSS. Adding the VDD polarization in the n-well region is a very strict rule.

Adding polarization contacts

Inverter Simulation

The inverter simulation is conducted as follows. Firstly, a VDD supply source (1.2V) is fixed to the upper metal2 supply line, and a VSS supply source (0.0V) is fixed to the lower metal2 supply line. The properties are located in the palette menu. Simply click the desired property, and click on the desired location in the layout. Add a clock on the inverter input node

Adding simulation properties (InvSteps.MSK) The command Simulate Run Simulation gives access to the analog simulation. Select the simulation mode Voltage vs. Time. The analog simulation of the circuit is performed. The time domain waveform, proposed by default, details the evolution of the voltages in1 and out1 versus time. This mode is also called transient simulation, as shown in figure .

Transient simulation of the CMOS inverter (InvSteps.MSK) The truth-table is verified as follows. A logic zero corresponds to a zero voltage and a logic 1 to a 1.20V.When the input rises to 1, the output falls to 0, with a 6 Pico-second delay (6.10-12 second).

Result:

Thus layout of CMOS inverter was generated and simulated using Microwind and DSCH V2.0

Ex. No.14 Date:

SCHEMATIC ENTRY AND SPICE SIMULATION OF MOS DIFFERENTIAL AMPLIFIER

Aim: To generate schematic entry of MOS differential amplifier and to perform SPICE simulation of it using DSCH V2.0

Software tools required:

DSCH V2.0

Schematic diagram of MOS Differential amplifier:

The goal of the differential amplifier is to compare two analog signals, and to amplify their difference. The differential amplifier formulation is reported below . Usually, the gain K is high, ranging from 10 to 1000. The consequence is that the differential amplifier output saturates very rapidly, because of the supply voltage limits. Vout = K(Vp Vm) The schematic diagram of a basic differential amplifier is proposed . An nMOS device has been inserted between the differential pair and the ground to improve the gain. The gate voltage Vbias controls the amount of current that can flow on the two branches. This pass transistor permits the differential pair to operate at lower Vds, which means better analog performances and less saturation effects.

The best way to measure the input range is to connect the differential amplifier as a follower, that is Vout connect to Vm. The Vm property is simply removed, and a contact poly/metal is added at the appropriate Place to build the bridge between Vout and Vm.

GENERATION OF SPICE PROGRAM The conversion of the schematic diagram into a SPICE program is done by clicking GENERATE SPICE FILE from the SIMULATE menu.

SPICE PROGRAM

* MOS Diff Amp with Current Mirror Load *DC Transfer Characteristics vs VID

VID 7 0 DC 0V AC 1V E+ 1 10 7 0 0.5 E- 2 10 7 0 -0.5 VIC 10 0 DC 0.65V VDD 3 0 DC 2.5VOLT VSS 4 0 DC -2.5VOLT M1 5 1 8 8 NMOS1 W=9.6U L=5.4U M2 6 2 8 8 NMOS1 W=9.6U L=5.4U M3 5 5 3 3 PMOS1 W=25.8U L=5.4U M4 6 5 3 3 PMOS1 W=25.8U L=5.4U M5 8 9 4 4 NMOS1 W=21.6U L=1.2U M6 9 9 4 4 NMOS1 W=21.6U L=1.2U IB 3 9 220UA

.MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .DC VID -2.5 2.5 0.05V .TF V(6) VID .PROBE .END

SIMULATION OF Differential amplifier A slow ramp is applied on the input Vin and the result is observed on the output. We use again the Voltage vs. Voltage to draw the static characteristics of the follower.

As can be seen from the resulting simulation reported , a low Vbias features a larger voltage range, specifically at high voltage values. The follower works properly starting 0.4V, independently of the Vbias value. A high Vbias leads to a slightly faster response, but reduces the input range and consumes more power as the associated nMOS transistor drives an important current. The voltage Vbias is often fixed to a value a little higher than the threshold voltage Vtn. This corresponds to a good compromise between switching speed and input range.

Effect of Vbias on the differential amplifier performance

Result: Thus schematic entry of MOS differential amplifier was generated and SPICE simulation was done using DSCH V2.0.

Ex. No.15 Date:

AUTOMATIC LAYOUT GENERATION AND SIMULATION OF VOLTAGE CONTROLLED OSCILLATOR

Aim: To Simulate voltage controlled oscillator using Microwind and DSCH V2.0

Software tool required:

Microwind and DSCH V2.0

Schematic diagram of Voltage Controlled Oscillator The voltage controlled oscillator is able to produce a square wave with a frequency varying depending on an analog control Vc. Ideally, the frequency dependence with Vc should be linear. One example of voltage controlled oscillator is given below. It consists of a ring oscillator with three stages. Vc acts on the resistance of the supply path, which acts on the speed response of the inverters.

Schematic diagram of a voltage controlled oscillator using DSCH V2.0

GENERATION OF VERILOG PROGRAM

The conversion of the schematic diagram into a VERILOG description is done by clicking MAKE VERILOG FILE from the FILE menu DSCH V2.0

. VERILOG PROGRAM module VCOMos( Vcontrol,VoltageCtrOsc); input Vcontrol; output VoltageCtrOsc; nmos #(107) nmos(w2,vss,Vcontrol); // 2.0u 0.25u nmos #(135) nmos(w3,vss,Vcontrol); // 2.0u 0.25u

nmos #(128) nmos(VoltageCtrOsc,w2,w4); // 2.0u 0.25u pmos #(128) pmos(VoltageCtrOsc,w6,w4); // 2.0u 0.25u pmos #(107) pmos(w6,vdd,w3); // 2.0u 0.25u pmos #(135) pmos(w3,vdd,w3); // 2.0u 0.25u nmos #(107) nmos(w7,vss,Vcontrol); // 2.0u 0.25u nmos #(121) nmos(w8,w7,VoltageCtrOsc); // 2.0u 0.25u pmos #(121) pmos(w8,w9,VoltageCtrOsc); // 2.0u 0.25u pmos #(107) pmos(w9,vdd,w3); // 2.0u 0.25u pmos #(107) pmos(w10,vdd,w3); // 2.0u 0.25u pmos #(121) pmos(w4,w10,w8); // 2.0u 0.25u nmos #(121) nmos(w4,w11,w8); // 2.0u 0.25u nmos #(107) nmos(w11,vss,Vcontrol); // 2.0u 0.25u endmodule

Layout of Controlled Oscillator:

This verilog program is saved as a text file. It is compiled and converted into layout using Microwind V2.0. .

Simulation of the voltage controlled oscillator In the simulation , a specific mode "Frequency and Voltages" is used to plot the frequency variation with Vc. The VCO output is a frequency-varying square wave. Its dependence with Vc is not linear.

Simulation of the voltage controlled oscillator

In the simulation , a specific mode "Frequency and Voltages" is used to plot the frequency variation with Vc. The VCO output is a frequency-varying square wave. Its dependence with Vc is not linear.

Result:

Thus Voltage Controlled Oscillator was simulated using Microwind and DSCH V2.0