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Guide to L-edit v12.

6 Physical Design Tool for use in EE414 VLSI Design Department of Electrical and Computer Engineering Fall 2010
(last revised 11/1/10)

Summary: L-edit is an integrated circuit physical design tool from Tanner EDA. This tool allows you to draw the layout of an IC, look at cross-sections, perform DRC, and LVS. There are some design kits that come with L-edit including the AMI/On-Semiconductor 0.8um kit, which we will use in this document. Part 1: Launch L-edit, Start a design, and Setup the Technology 1) Log onto a computer in the digital lab (601 Cobleigh) and launch L-edit using: Start All Programs Tanner EDA Tanner Tools v12.6 L-Edit v12.6 2) Create a new layout design: - File New - select Layout - under Copy TDB, select <empty> from the bottom dialog - Click OK

3)

Load in the mamin08 design kit: - File Replace Setup Browse to: \Documents\Tanner EDA\Tanner Tools v12.6\L-Edit and LVS\Tech\Mosis and select the mamin08.tbd file (this stands for Mosis/AMI N-well 0.8um) - Click OK, and OK again. 2

Notice that all of the layers available in the 0.8um AMI design kit are now in the drawing palette on the left. 4) Verify the technology rule options: - Setup Design You should see the design setup options. If everything worked, you should see the following. Notice that Lambda is equal to 0.5um. This is important because the design rules for DRC are specified in terms of lambda.

5)

Save your design - Now you can click save and give your design a descriptive name and location. (i.e., Z:\EE414_Fall10\Ledit_Projects\HW7_CMOS_Inverter\inverter_amin08

Part 2: Inspect the design rules for the kit The design rules for this kit are located on the MOSIS website at: http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html Scroll down to Table 5. The layer rules for this kit are in the SCNPC row.

If you click on each of the layer names, you will see the layout rules given in terms of lambda. Our kit is the SCMOS column (standing for Scalable-CMOS). By specifying the rules in terms of lambda, the rules can be used across multiple technologies.

Part 3: Create your layout for the CMOS inverter Lets create a CMOS inverter with Ln=Lp=1um, Wn=3um, Wp=3um. We should write down the conversion between microns and Lambda so that the design rules make sense: Ln Lp Wn Wp = 1u = 2 = 1u = 2 = 3u = 6 = 3u = 6

NMOS The process that we are using is N-well CMOS. This means that the blank screen you see is p-type silicon. We explicitly draw active regions on the screen to open up the field-oxide to insert diffusion regions. This means you can think of the screen as p-type silicon with FOX everywhere on it to begin with. In order to create the NMOS structure, we use three layers: Active - This tell the process where to implant the n-type ions (P or As). Remember that we want to implant into the Poly to reduce its resistance. The Width of the N-Select dictates the width of the transistor (Wn) - This layer tell where the field-oxide should be opened up for the active regions. This layer must overlay the active region. - This specifies the gate of the device. Under the poly will be thin oxide forming MOS structure. The Length of the Poly dictates the length of transistor (Ln).

N-Select Poly

Display Notes - You can setup the default units to use (micron vs. lambda) in the upper corner of the screen. - You can setup the grid display and snap using the Setup Design menu and Grid tab Entry Notes: - You enter a rectangle by first selecting the layer and then clicking on the square icon. - You can enter rulers in your design to measure your rectangles as they are entered. You can set the display options of the ruler on the Setup Design menu on the Drawing tab.

1) Enter an N-select rectangle that is 9um x 5um 2) Enter an Active rectangle that is 7um x 3um centered within the N-select 3) Create a Poly rectangle that is 1um x 5um. Your design should look like this:

4) Run DRC to make sure your dimensions are not violating any design rules - Click on the DRC button in the upper left corner of the screen (little green play arrow). If everything checks out, you should see:

5) View the Cross Section of your layout: - Tools Cross-Section - You need to specify an *.xst file (if not already loaded). This can be found in the same directory as the original *.tbd file. The file is called mamin08.XST. Browse and select: \Documents\Tanner EDA\Tanner Tools v12.6\L-Edit and LVS\Tech\Mosis\mamin08.xst - In the dialog that comes up, you can specify the cross-section point using the up/down arrows or by selecting pick - Under Exaggeration, check the box that says center to window - Click OK, you should see the following figure. Notice the FOX that exists everywhere except in the active region. Also notice the thin oxide under the poly.

6) Enter the Body Diffusion point for the NMOS - In order to enter a body contact, we need to tell the tool that we are going to create a p+ diffusion region. We do this using the active and P-select layers. Put a substrate diffusion region next to your NMOS as follows:

7) Enter the contact windows for the NMOS - we do this using the Active Contact layer

8) Enter Metal 1 to connect the Source and Body of the NMOS together and put a little Metal1 over the Drain contact to connect to later.

PMOS A PMOS device is made in a similar manner as the NMOS except that we need to specify the N-well and use P-select instead of N-select. 1) Enter the PMOS N-well, P-select, Active, Poly, Active Contact, and Metal 1 as follows:

Connecting the Inverter Metal and Poly are connected together by simply drawing \rectangles that are adjacent to or overlap another rectangle of the same type (i.e., M1 to M1, Poly to Poly). Connect the inverter together as shown in the following figure: - We typically put horizontal strips across the chip to route VDD and VSS to multiple devices. These are called power supply rails. - Connect the gates together using Poly and then route the signal up to Metal 1 using a Poly Contact - Connect the drains together using Metal 1 - Label the 4-nodes of the inverter using the Drawing Ports button. (VDD, VSS, VIN, VOUT)

Perform a Final DRC on the Design

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Extract a SPICE Netlist of your Layout 1) Click on the Extract Connectivity button - in the Extract dialog that appears, specify the extract definition file at: \Documents\Tanner EDA\Tanner Tools v12.6\L-Edit and LVS\Tech\Mosis\mamin08.ext - specify the output name and location for the spice Netlist to be generated: Z:\EE414_Fall10\Ledit_Projects\HW7_CMOS_Inverter\inverter_amin08.spc - check the open spice file after extracting box - on the output tab, check the write node name aliases - click Run - in the dialog that appears saying that the area/fringe capacitance is set to zero, say Ignore All - you should see an extracted spice Netlist as follows:

Notice that the Length and Width of our transistors is what we wanted (W/L=3u/1u) Notice that the node name aliases show up as we wanted indicating that our inverter is connected correctly. 11