PCM block

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PCM block
A 4M or an 8M PCM interface to the Group switch is selected by using jumper setting in the PCU2-D. All PCM interfaces consist of two 4 Mbit/s or 8 Mbit/s PCM connections. One is connected to active the Group Switch an one to the redundant Group Switch. Switchover is done with CGSA and CGSB signals. PCM-MUX in 4M mode All incoming PCM lines are connected to the PCM-MUX. The PCM-MUX is a big CPLD. It connects incoming PCM lines to correct resources (PQIIs and DSPs). 4M connections (in use in the IP Trunk): PCM 1 <=> DSP block 0 PCM 2 <=> DSP block 1 PCM 3 <=> 4 Mbit/s line is de-multiplexed to two 2 Mbit/s lines => Even 2 Mbit/s PCM goes to PQII_0 and odd 2 Mbit/s goes to PQII_1 4M connections (in use in the BSC3i only): PCM 4 <=> Reserved for future use PCM 5 <=> 4 Mbit/s line is de-multiplexed to two 2 Mbit/s lines => Even 2 Mbit/s PCM goes to PQII_0 and odd 2 Mbit/s goes to PQII_1. In the receive direction, PCM 5 line needs to be de-interleaved (= de-muxed) from 4 Mbit/s line so that even 2 Mbit/s PCM data goes to the PQII_0 and odd 2 Mbit/s goes to the PQII_1. In the transmit direction data coming from the PQIIs needs be interleaved (= muxed) to one 4 Mbit/s line (PCM 5) so that data from the PQII_0 is even part of 4 Mbit/s line and data from the PQII_1 is odd part of the same 4 Mbit/s line (PCM 5). This is needed in the BSC3i only. The PCM 3 line also needs the same function of the PCM-MUX as the PCM 5, but function is used in IP Trunk. THe PCM-MUX also needs this network ID bit information, because PCM connections are different in the BSC3i and IP Trunk (Network ID bit affects only in 4 M PCM mode, in 8 M mode cables are connected at the same way regardless of network element). PCM-MUX in 8M PCM mode The 4M and 8M PCM interfaces differ from each other regarding the multiplexing method. The 8M PCM interface multiplexes timeslot by timeslot (TSL by TSL) four 2M PCMs, whereas the 4M PCM interface multiplexes bit-by-bit two 2M PCMs. Connections are the following: 8M PCM1 is multiplexed/demultiplexed from/to two 4M PCMs, first of these 4M PCMs contains 2M PCM0 and PCM1 and this 4M PCM is connected to DSP block 0. The last 4M PCM contains 2M PCM2 and PCM3 and this 4M PCM is connected to DSP block 1. 8M PCM2 is multiplexed/demultiplexed from/to four 2M PCMs. These 2M PCMs are connected as follows: Internal 2M Internal 2M Internal 2M Internal 2M PCM0 <=> PCM1 <=> PCM2 <=> PCM3 <=> the TDMC1 port the TDMC1 port the TDMD1 port the TDMD1 port of of of of PQII_0 PQII_1 PQII_0 PQII_1.

The PCM connections of the DSPs and the PQIIs are the same regardless of the network element ID when the 8M PCM interface is used. THe network element ID bit affects still PCM connections if the 4M PCM interface is used. Clock generation and clock supervision Clock and synchronisation signals for DSPs' and PQIIs' serial ports are generated from 8 MHz and 8 kHz basic timing signals. These basic timing signals are also supervised. If a clock error occurs, an interrupt is generated to the PQIIs and the PCM transmit drivers are disabled. Also the PCU2-D's external alarm _AL pin is driven low during the clock alarm. PCM side selection (switchover to redundant GSW1KB/GSWB/GSW) CGSA and CGSB signals are used to make the PCM side selection. These signals are connected to the LM311 comparato whose output controls receiver and transfer buffers.

DN0414339

Id: 0900d805804852f7

2010 Nokia Siemens Netw orks

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9/30/2010 8:24 PM