Scheduler for ARM processor

By, Biju Daniel Jennis Thomas Linju Baby John Nibas P P Tony Lijo Jose Government Engineering College Sreekrishnapuram 4th July 2011

Contents

Introduction General view of an OS ARM Architecture Implementation and Design Conclusion Future Scope References

INTRODUCTION

Embedded System and its Components. Three main components are there.
1. It has a hardware. 2. It has a main application software. 3. It has a real time operating system that supervises the application software.

Advantages of embedded systems. ARM Processor

Project work ow

Real Time Operating Sysyem

A real-time operating system (RTOS) is an operating system (OS) intended to serve real-time application requests A key characteristic of a RTOS is the level of its consistency concerning the amount of time it takes to accept and complete an applications task A real-time OS has an advanced algorithm for scheduling A variant of OS that operates in constrained environment in which computer memory and processing power is limited

Scheduling

Two types of scheduling: Non Preemptive

First come rst serve: Assigns the priority in the order in which they request the processor. Shortest job next: Scheduling algorithm chooses the process requiring minimum service time as its next one.

Preemptive
Round Robin: Distribution of processing time equitably among all processes requesting the processor.

Interrupts
Steps in handling Interrupts

1. Disable further interrupts. 2. Store current state of program. 3. Execute appropriate interrupt handling routine. 4. Restore state of program. 5. Enable interrupts. 6. Resume program execution.

ARM Architecture

Architectural simplicity of ARM processors (RISC) Low power consumption Load store architecture Uniform and xed length instruction elds to simplify decode instructions ARM Register set ARM has 31 general-purpose 32-bit registers Only 16 registers are visible at a time Two registers in the visible set have special functions
Link Register r14 Program Counter r15

Registers in the ARM set

ARM Architecture contd..

ARM architecture data path

ARM Architecture contd..

ARM instruction set

Data processing instructions. Branch instructions. Load store instructions. Software interrupt instruction. Program status register instruction.

Implementation and Design 1

The LPC2148 has the following memory regions

1. 512kb on-chip ash memory. This is where the load image of the program resides, including instructions and a read-only copy of the data section 2. 32kB SRAM. This is where the user stack, data, and bss are located. Each thread gets its own stack. 3. 8kB USB DMA SRAM. The LPC2148 contains an additional 8kB of SRAM which can be used by the USB DMA engine, or if DMA is not used, can be used as general purpose RAM. We use this memory region for the bootloader/supervisor. 4. Peripheral address space. On-chip hardware peripherals, such as timers, SPI interface, UART interface, USB interface, PWM block, and A/D converter are controlled through registers

TCB

The task array resides in the memory. TCB is a structure having an array of registers (unsigned int reg[16]), a CPSR(unsigned int), and tid (int). Static number of tasks, eg: dene MAXTASKS 10 Then the structure TCB is called., TCB threadtab[MAXTASKS]; Current index value is kept volatile. volatile int currindex;

Implementation and Design 1

Implementation and Design 2

when an interrupt occurs the arm core does the following.

(2)The current value of pc is copied to r14 irq The current value of cpsr is copied to spsr irq pc is loaded with the address 0x18 and the processor mode is changed to irq mode with irq interrupts disabled (to prevent interrupt from the interrupt.)

Implementation and Design 2

Implementation and Design 3

1. The IRQ vector at address 0x18 contains an LDR instruction that causes the PC to jump to the IRQ wrapper routine, called ARM irq, which is dened in the supervisor. 2. The IRQ wrapper routine saves registers r0-r3 and r12 to the IRQ scratch area. Remember that if a subroutine wants to use any of r4-r11, it must rst push the existing value to the stack. 3. The IRQ wrapper routine manually switches from IRQ mode to SYS mode. 4. The IRQ wrapper routine saves lr to the IRQ scratch area because it calls a subroutine. Recall that calling a subroutine, also called branch and link, modies the lr register, and that lr is a callee save register. Therefore the IRQ wrapper routine must save lr before calling any subroutines.

Implementation and Design 3

Implementation and Design 4

(6) The IRQ wrapper routine loads the address of the interrupt service routine from the vectored interrupt controller (VIC) and executes a branch and link to this address. We have provided code that congures the VIC to associate mythreadI SRwiththetimer 0interrupt. (7) timer isr() needs to save the state of task 0 to threadtab[0] before it can load the state of thread 1. The state of a thread consists of the values of r0-r15 and cpsr BEFORE the processor was interrupted by the IRQ exception. When timer isr() is called, the values of r4-r11,r13 have not been modied since before the interrupt occurred, so you may save these values directly to memory in the threadtab[0] structure. Also the r0-r3 and r12 is loaded to threadtab[0] from the irq scratch area.

Implementation and Design 4

(8) At this point, registers r0-r14 have been saved to the threadtab[0] structure. You still need to save pc and cpsr to memory. How do we do this? Recall that when the exception occurred, the ARM hardware copied pc to r14 irq and cpsr to SPSR irq. (9) Now that youre in IRQ mode, you can save the values of r14 and spsr to memory. The state of task0 is now saved to memory.

Implementation and Design 5

(10) Now you need to load the state of task1. Note that were still in IRQ mode, so load the values of pc and cpsr from memory into registers. (11) Switch back to SYS (12) Load r4-r11,r13 from memory into registers, and copy r0-r3,r12,lr from memory to the IRQ scratch area.

Implementation and Design 6

(13) return from the subroutine so that the execution will continue in the irq wrapper function. (14) The IRQ wrapper routine loads lr from the scratch area into r14. (15) The IRQ wrapper routine switches from SYS mode to IRQ mode. (16) The IRQ wrapper routine loads r0-r3,r12 from the scratch area to registers. (17) The IRQ wrapper routine executes the return from interrupt instruction (movs pc,lr), which resumes execution where task1 left o and copies spsr into cpsr in a single step.

Implementation and Design 7

CONCLUSION

Familiarized ARM architecture Studied how to develop a realtime operating system Studied the functions of a scheduler and its working also familiarized with the routines inside the operating system Major constraint- inside the ISR.

FUTURE SCOPE

Apart from task scheduling, process scheduling can be implemented if we have a better processor with memory management unit File system can be developed Device drivers for dierent real time applications can be developed Project can be extended to other platforms like atmel, avr, pic other arm platforms like arm cortex M 3, arm cortex A 8, stellaris etc..

REFERENCES
1. ARM System Developers guide. Designing and Optimizing System Software By Andrew N. Sloss, Dominic Symes and Chris Wright. 2. User manual of LPC 214X 3. ARM Assembly Language Fundamentals and Techniques. By William Hohl 4. C /OSTheRealTimeKernal, ByJeanJ.Labrosse 5. Embedded Systems. By Raj Kamal 6. http://en.kioskea.net/contents/pc/ on june 2011 7. http://infocenter.arm.com/help/topic/com.arm.doc.prd29genc-009492c/ 8. http://freertos.org ,on november 2010 9. http://linuxkernalcrossreference.com on november 2010 10. http://www.codesourcery.com/sgpp/lite/arm on January 2011 11. http://qemu.org on January 2011 12. https://sites.google.com/a/eng.ucsd.edu/ece30/lab-6

THANK YOU