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  • Lesson 2 CMOS Op Amp Design

    Hochgeladen von

    Ibrahim Muhammed
    155 Ansichten36 Seiten
    The document discusses the design of two-stage operational amplifiers, including their DC balance conditions, design relationships, and specifications. It provides procedures for unbuffered op amp design and worked examples. Additionally, it covers incorporating nulling resistors, compensation techniques, simulation, reducing parasitics, bias distribution, and modeling the positive and negative power supply rejection ratios of two-stage op amps.

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    The document discusses the design of two-stage operational amplifiers, including their DC balance conditions, design relationships, and specifications. It provides procedures for unbuffered op amp design and worked examples. Additionally, it covers incorporating nulling resistors, compensation techniques, simulation, reducing parasitics, bias distribution, and modeling the positive and negative power supply rejection ratios of two-stage op amps.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Als PDF, TXT herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    155 Ansichten36 Seiten

    Lesson 2 CMOS Op Amp Design

    Hochgeladen von

    Ibrahim Muhammed
    The document discusses the design of two-stage operational amplifiers, including their DC balance conditions, design relationships, and specifications. It provides procedures for unbuffered op amp design and worked examples. Additionally, it covers incorporating nulling resistors, compensation techniques, simulation, reducing parasitics, bias distribution, and modeling the positive and negative power supply rejection ratios of two-stage op amps.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Als PDF, TXT herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    von 36

    CMOS Operational Amplifier Design Lesson 2 pp.

    1-36

    13/11/2006

    D. De Venuto

    Two stage op amp design

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    DC Balance conditions for the two stage op amp

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    Design relationships for the two stage op amp

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    Op Amp specification

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    Unbuffered Op Amp Design Procedure

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    Unbuffered Op Amp Design Procedure

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    Unbuffered Op Amp Design Procedure

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    Example 1 Design of a two-stage op amp

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    Example 1

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    Example 1

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    Example 1

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    Example 1

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    Incorporating the nulling resistor into the Miller compensated two-stage op amp

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    Design of the nulling resistor (M8)

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    Example 2 RHP Zero Compensation

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    Example 2

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    An alternate form of nulling resistor

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    Programmability of the two-stage op amp

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    Simulation of the electrical design

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    5-to-1 Current Mirror with different physical performances

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    Reduction of Parasitics

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    Technique for reducing the overlap capacitance

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    Chip voltage bias distribution scheme

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    PSRR of the two-stage op amp

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    Positive PSRR of the two-stage op amp

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    Positive PSRR of the two-stage op amp

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    Positive PSRR of the two-stage op amp

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    Concept of the PSRR+ for the two-stage op amp

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    Negative PSRR of the two-stage op amp with Vbias, grounded

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    Negative PSRR of the two-stage op amp with Vbias grounded

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    Negative PSRR of the two-stage op amp with Vbias connected to VSS

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    Negative PSRR of the two-stage op amp with Vbias connected to VSS

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    Frequency response of the negative PSRR of the twostage op amp with VBias connected to VSS

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    Approximate model for negative PSRR with VBias connected to ground

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    Approximate model for negative PSRR with VBias connected to VSS

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