ICSE2004 Proc.

2004, Kuala Lumpur, Malaysia

Effect of Shallow Trench Isolation Induced Stress on CMOS Transistor Mismatch

Philip Beow Yew Tan' 2*, Albert Victor Kordesch' and Othman Sidek2 'Silterra Malaysia Sdn. Bhd. Kulim Hi-Tech Park,09000 Kulim, Kedah, Malaysia 2University Science Malaysia, 14300 Nibong Tebal, Pulau Pinang, Malaysia *Email: philip_tangsilterracom

Schaper et al. investigated the impact of Abstract - Mechanical compressive stress induced by shallow trench isolation (STI) and mechanical stress due to die packaging on both transistor mismatch are the two important transistor pair mismatch of directly neighboring effects that we should take into account when devices and the long distance mismatch of scaling down CMOS transistors. In this devices separated by distances of order of mm in paper, we study the relationship between these [4]. The mechanical stress is applied by using the two effects. Our finding shows that STI beam bending technique. Their findings show induced stress effect improves NMOS Id that pair mismatch is not affected by the applied matching but degrades PMOS Id matching. stress, while a weak effect is seen in case of long These effects become more obvious for small distance mismatch. They also found that changes size transistors. The STI stress effect has no due to beam bending mechanical stress are much smaller than the original long distance mismatch. significant effect on Vt mismatch. The results from this paper [4], does not I. INTRODUCTION necessary imply that STI mechanical stress has no effect on transistor mismatch. The reason is Shallow trench isolation (STI) induced because the applied stress by beam bending mechanical stress has caused transistors with the technique is in the range of lOOMPa but the STI same W/L behave differently due to the layout mechanical stress is four to five times greater shape of the active region. The distance between that the applied stress [5]. Probably the applied gate edge to active edge know as length of active stress was not strong enough to cause measurable (La) has been used to study the effect of STI differences in transistor mismatch. stress [1]. Smaller La means higher STI stress. II. EXPERIMENT STI compressive stress causes NMOS drain current (Id) to degrade and PMOS Id to increase The test structures used in this experiment are [2]. This information is very useful to analog when designing a matched transistor transistor pairs with different W/L ratios and designer pair. In order to make sure two transistors have different La sizes. Each transistor pair consists of the same Id, both the transistors should be two single-finger transistors with the same drain designed with identical WIL ratio and also orientation, with a common source but independent gate and drain pads. The two identical La. According to Pelgrom et al. [3], transistor transistors are placed adjacent to each other to mismatch is proportional to the inverse square avoid global mismatch effects. Also, we do not root of (W*L). This means that transistor pairs use dummy poly fingers in the test structures. In with larger W and L will have better matching. this study, 2560 pairs of transistors, which are Regarding La, we have yet to find any literature from 32 dice, one wafer (non-epi, 200mm in studying how La affects transistor mismatch or diameter and [100] orientation), are fabricated tells whether La does affect transistor mismatch using Silterra's 0.18 um Advanced Mixed Signal or not. In this paper, we investigate the CMOS technology. In our measurement setup, relationship between STI stress due to La and Vt was measured at Id = 0.luA*W/L, Vd-0.lV (linear) and Vd=1.8V (saturation). Id was transistor mismatch. Although no one has yet studied the effect of measured at Vg=1.8V, Vd=0.lV (linear) and STI stress due to La on transistor mismatch, we Vd= 1.8V (saturation). found a reference that studies beam bending mechanical stress on transistor mismatch.

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ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

III. RESULTS AND DISCUSSION

The summary of Vt mismatch and Id mismatch behaviors are shown in Table I.

Table I CMOS transistor matching behavior at larger La (higher STI stress)_. At larger La In Linear In Saturation Condition (higherSI Stress) Conditon NMOS Vt Matching Not Significant Not Significant NMOS Id Matching Statistically Statistically Improved Improved PMOS Vt Matching Not Significant Niot Sigiicant PMOS Id Matching Statistically Statisically Degraded Degraded I_________I____

significant effect on Vt mismatch; hence it is not

We found that the STI stress has no

discussed in detail here. Accordi-ng to the inverse square root law [3], if two transistors had infinite large gate areas, then they should have zero mismatch. In Fig. I to Fig. 4, by lookmg at the slope of the lines, we can statistically determine whether the matching is improved or degraded. Larger slope means matchin is degraded. Our reference point is La-5um- because at this active length, there will be practically no STI stress in the direction of La [1]. Fig. 1 to Fig. 4 show that NMOS Id matching is statistically improved and PMOS Id matching is statistically degraded at both linear and saturation conditions. NMOS Id matching statistically improves 11% (in the linear condition) and 5% (in the saturation condition). PMOS Id matching statistically degrades 27% (in the linear condition) and 26% (in the saturation condition). This improvement and degradation is not due to the fact that NMOS Id reduces and PMOS Id increases at higher STI stress [2] because the Id mismatches are calculated by taking the percentage differences and not the absolute values. The results from Fig. I to Fig. 4 only give us the statistical matching behavior of the transistor pairs. Hence, the accuracy of the results is dependent on the number of samples used. In this experiment, 32 pairs of transistor of each size are used to calculate the standard deviations. The Id matching improvement and degradation of NMOS and PMOS transistor pairs with narrow width and short channel length (W/L=0.6/0.18, where I/sqrt(Area)=3 and W/L=0.22/0.18, where 1/sqrt(Area)=5) are clearly seen in Fig. I to Fig. 4.

NMOS STI stress behavior can. be explained by the piezoresistive effect, where hi r STI stress causes higher resistance (due to positive piezoresistive coefficient) that re-duces NMOS Id. PMOS has a negative piezoresistive coefficient where the higher stress increases PMO-S Id. The negative piezoresistive effect is explained by the mobility modulation model based on defornation potential theor . In this model, with the band-splig due to strain stress, the redistributiOn f ls between heavyhole andd and lig l b leato ch*ange b of ;the effective hole m:obility. -The rootUcause of Id mismatch is process variations such as oxide thickness, channel doping and W/L fluctuations [7]. To explain why NMOS Id mathing improves with stress while PMOS Id matching degrades with stress, we would need a mechanism that counteracts the Id mismatch for NMOS but increases the Id mistch for PMOS. One of such possiblemechanism is poly: gate length fluctuation. Sppoe one of the transistors in a matched NMO air has lower poly gate lengh:due to a rxando process variation. The shorter poly gate transistor will have more stress than the longer one. More stress degrades Id, which partly counteracts the higher Id caused by the shorter poly gate. For example, if the poly gate is 5% shorter, the Id will be about 5% higher. The stress will be somewhat more in the shorter channel transistor, so the additional stress will cause Id to decrease. Hence, the net Id mismatch will be less than 5%.
4.0

y0.6135x La--tum 3y
3Y

0.6908x La-5um

22.5
0
v

2.0

1.50
0.5
0.0

-Linear (IDtIUN..Lai) -U-Lnear (IDNLIN..A5

3
4

Fig. 1 Plot of Idnlin mismatch versus inverse square root gate area for La=-lum and La-5um. Npair,=32 for each La.

lfsqrt(Area) ilium]

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ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

The percentage differences in slope between La-lum and La=5um are greater for L=O-.8um in comparison to L=lOum. These results show that the mismatch behaviors of short channel transistors are more sensitive to the STI stress compare to long channel transistors. This is because when transistor channel length, L decreases, STI stress effects on both electron and hole mobility will be more significant [2].
11sqrt(Area) [11um] Fig. 2 Plot of Idnsat mismatch versus inverse square root gate area for La=l um and La=5um. Npais=32 for each La.
3.5
3.0
2.0U
1

4.0 3.5 P 3.0 0 2.6 Slope Difference a 2.0

0 PI 1.0 0 .

y: .0.636Ln(x)+2.018 Lalum yx-0.7346Ln(x)+2.0766 La5um

yO0.6448XLa-1umrn
y:0.5077xLa=5umr

; 0.5

L25

00
*

I-Log. (La=5um)
0.1

-Log. (La=iurn)

-13A%

1.5

IDPUN_Lai
La5

X 1.0
0.0

It// O
0
1 2

//

-WLnear DPLN._La1) -Linear(iDPLN La5)

4

| IDPLIN

10 I Widtmurm] Fig. 5 Percentage of Stdev(IDNSAT) differences in slope for NMOS L=O. I 8um. Np,iX&=32 for each La.

11sqrt(Area) [I1um] Fig. 3 Plot of Idplin mismatch versus inverse square root gate area for La=lum and La=Sum. Npairs=32 for each La.
5.0 4.5
y
y

4.0
3.5 3.0

Q0.8527x La = Iumr
=

5U: 0,6749x La =

2.5

2.0
1.5

+ IDPSAT Lai I IDPSAT_La5

-

1.0

Unear(lDPSAT_La1)
Unear pDPSAT

Width [uml Fig. 6 Percentage of Stdev(IDNSAT) differences slope for NMOS L=lOum. Np,irs=32 for each La.
5.0 4.5 L*40
0)

0.1

10
in

0.5
0.0
0

La5)

11sqrt(Area) [hlum] Fig. 4 Plot of Idpsat mismatch versus inverse square root gate area for La- I um and La=Sum. Npairs=-32 for each La.

< 3.5 a. 3.0 2.5 <E 2.0

Q.1.5
1.0

We use plots of standard deviation versus width to further study the STI stress on Id matching of short and long channel length transistor pairs. From Fig. 5 and Fig. 6, NMOS Id matching decrement is 13.4% at L=0. 18um in comparison to 2.0% at L=lOum. While for PMOS is 56.8% at L=0.18um in comparison to 11.6% at L=lOum, as shown in Fig. 7 and Fig. 8.

(41

0.5

0.0

Widft [um] Fig. 7 Percentage of Stdev(IDPSAT) differences in slope for PMOS L=O. I 8um. Npairs=32 for each La.

0.1

10

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ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

0.7
j- G06

a
Slope Difference

0.6 L. 0.4
(

y=z0.0817Ln(x)+OA2 Lalum yv ..=05Ln()+OA641 L5um

[3]

0.3
a 0.2* lzlum X aOLa5um ; O.i - Log. "Ium)
0
0.1

8%

[4]

[5]
10

-Lol. (La4um)

Fig. 8 Percentage of Stdev(IDPSAT) differences in slope for PMOS L=lOum. Npairs=32 for each La. IV. CONCLUSION

Width lumi

[6]

At smaller La (lower STI compressive stressS), NMOS Id matching statistically improves b)Ut PMOS Id matching statistically degrades. MVe [7] believe the different mismatch behaviors of NMOS Id and PMOS Id are due to the changi,es of electron and hole mobility at higher STI stresSS. The NMOS Id degradation caused by STI steIss reduces the Id mismatch and the PMOS Id increment caused by STI stress increases Id mismatch. The STI stress has more significant effects on the Id mismatch of short channel transistcDrs compare to the long channel transistors. TI his because STI stress has higher effect on shl ort channel Id compare to long channel Id.
ACKNOWLEDGEMENT

M. J. M. Pelgrom, H. P. Tuinhout and M. Vertregt, "Matching Properties of MOS Transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp. 14331439 (1989). U. Schaper, C. Linnenbank, U. Koilmer, H. Mulatz, T. Mensing, R. Schmidt, R. Tilgner and R. Thewes, "Evaluation of the Impact of Mechanical Stress on CMOS Device Mismatch," IEEE Microelectronic Test Structures, ICMTS, pp. 1-5 (2001). C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud and H. Dansas, "Electrical Analysis of Mechanical Stress Induced by STI in Short MOSFETs Using Externally Applied Stress," IEEE Transactions on Electron Devices, vol. 51, no. 8, pp. 1254-1261 (2004). 0. Fujii, H. Yoshimura, R. Hasumi, T. Sanuki, H. Oyamatsu, F. Matsuoka and T. Noguchi, "Modeling of Stress Induced Layout Effect on Electrical Characteristics of Advanced MOSFETs," IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD),

Maxim and M. Gheorghe, "A Novel Physical Based Model of Deep-Submicron CMOS Transistors Mismatch for Monte Carlo SPICE Simulation," IEEE International Symposium on Circuits and Systems, vol. 5 (2001).
A.

(2004).

The authors would like to acknowledge all the members of Silterra Malaysia Sdn. Bhd. for supporting and contributing to the research work in this paper.
REFERENCES

[1]

R. A. Bianchi, G. Bouche and 0. Roux-dit-Buisson, "Accurate Modelling of Trench Isolation Induced Mechanical Stress effects on MOSFET Electrical

[21

Performance," International Electron Devices Meeting (IEDM), pp. 117-120 (2002). P. B. Y. Tan, A. V. Kordesch, Y. Mohd Yusof, N. Che May, H. S. Tan, P. Balasubramaniam, A. K. Kantimahanti and 0. Sidek, "Shallow Trench

Isolation Induced Mechanical Stress Effect on CMOS Transistor Electrical Perfonnance," 3rd on Advanced International Conference Manufacturing Technology (ICAMT2004), pp. 1433-

1439 (2004).

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