TOOLS UTILIZED Xilinx(ISE):

There are several EDA (Electronic Design Automation) tools available for circuit synthesis, implementation, and simulation using VHDL. Some tools (place and route, for example) are oered as part of a vendors design suite (e.g., Alteras Quartus II, which allows the synthesis of VHDL code onto Alteras CPLD/FPGA chips, or Xilinxs ISE suite, for Xilinxs CPLD/FPGA chips). Other tools (synthe-sizers, for example), besides being oered as part of the design suites, can also be provided by specialized EDA companies (Mentor Graphics, Synopsis, Synplicity,etc.). Examples of the latter group are Leonardo Spectrum (a synthesizer from Mentor Graphics), Synplify (a synthesizer from Synplicity), and ModelSim (a simulator from Model Technology, a Mentor Graphics company). The designs presented in the book were synthesized onto CPLD/FPGA devices (appendix A) either from Altera or Xilinx. The tools used were either ISE combined with ModelSim (for Xilinx chipsappendix B), MaxPlus II combined with Advanced Synthesis Software, or Quartus II. Leonardo Spectrum was also used occasionally. Although different EDA tools were used to implement and test the examples presented in the design, we decided to standardize the visual presentation of all simulation graphs. Due to its clean appearance, the waveform editor of MaxPlus II was employed. However, newer simulators, like ISE ModelSim and Quartus II, over a much broader set of features, which allow, for example, a more refined timing analysis. For that reason, those tools were adopted when examining the fine details of each design. The Xilinx Integrated Software Environment (ISE) is a powerful and complex set of tools. First, the HDL files are synthesized. Synthesis is the process of converting behavioral HDL descriptions into a network of logic gates. The synthesis engine takes as input the HDL design files and a library of primitives. Primitives are not necessarily just simple logic gates like AND and OR gates and D-registers, but can also include more complicated things such as shift registers and arithmetic units. Primitives also include specialized circuits such as DLLs that cannot be inferred by behavioral HDL code and must be explicitly instantiated. The libraries guide in the Xilinx documentation provides an complete description of every primitive available in the Xilinx library. (Note that, while there are occasions when it is helpful or even necessary to explicitly instantiate primitives, it is much better design practice to write behavioral code whenever possible.)

We will be using the Xilinx supplied synthesis engine known as XST. XST takes as input a verilog (.v) file and generates a .ngc file. A synthesis report file (.srp) is also generated, which describes the logic inferred for each part of the HDL file, and often includes helpful warning messages. The .ngc file is then converted to an .ngd file. (This step mostly seems to be necessary to accommodate different design entry methods, such as third-part synthesis tools or direct schematic entry. Whatever the design entry method, the result is an .ngd file.) The .ngd file is essentially a netlist of primitive gates, which could be implemented on any one of a number of types of FPGA devices Xilinx manufacturers. The next step is to map the primitives onto the types of resources (logic cells, i/o cells, etc.) available in the specific FPGA being targeted. The output of the Xilinx map tool is an .ncd file. The design is then placed and routed, meaning that the resources described in the .ncd file are then assigned specific locations on the FPGA, and the connections between the resources are mapped into the FPGAs interconnect network. The delays associated with interconnect on a large FPGA can be quite significant, so the place and route process has a large impact on the speed of the design. The place and route engine attempts to honor timing constraints that have been added to the design, but if the constraints are too tight, the engine will give up and generate an implementation that is functional, but not capable of operating as fast as desired. Be careful not to assume that just because a design was successfully placed and routed, that it will operate at the desired clock rate. The output of the place and route engine is an updated .ncd file, which contains all the information necessary to implement the design on the chosen FPGA. All that remains is to translate the .ncd file into a configuration bitstream in the format recognized by the FPGA programming tools. Then the programmer is used to download the design into the FPGA, or write the appropriate files to a compact flash card, which is then used to configure the FPGA. By itself, a Verilog model seldom captures all of the important attributes of a complete design. Details such as i/o pin mappings and timing constraints can't be expressed in Verilog, but are nonetheless important considerations when implementing the model on real hardware. The Xilinx tools allow these constraints to be defined in several places, the two most notable being a separate "universal constraints file" (.ucf) and special comments within the Verilog model. Xilinx has two main FPGA families: the high-performance Virtex series and the highvolume Spartan series, with a cheaper EasyPath option for ramping to volume production. It also manufactures two CPLD lines, the CoolRunner and the 9500 series. Each model series has been released in multiple generations since its launch.

The latest Virtex-6 and Spartan-6 FPGA families are said to consume 50 percent less power, cost 20 percent less, and have up to twice the logic capacity of previous generations of FPGAs.

4.1.1 Spartan Family:

The Spartan series targets applications with a low-power footprint, extreme cost sensitivity and high-volume such as displays, set-top boxes, wireless routers and other applications. The Spartan-6 family is built on a 45-nanometer (nm), 9-metal layer, dual-oxide process technology. The Spartan-6 was marketed in 2009 as a low-cost solution for automotive, wireless communications, flat-panel display and video surveillance applications. The Spartan-3A consumes more than 70-90 percent less power in suspend mode and 4050 percent less for static power compared to standard devices. Also, the integration of dedicated DSP circuitry in the Spartan series has inherent power advantages of approximately 25 percent over competing low-power FPGAs.

4.1.2 Virtex Family:

The Virtex series of FPGAs have integrated features such as wired and wireless infrastructure equipment, advanced medical equipment, test and measurement, and defense systems. In addition to FPGA logic, the Virtex series includes embedded fixed function hardware for commonly used functions such as multipliers, memories, serial transceivers and microprocessor cores. The Virtex-6 family is built on a 40-nm process for compute-intensive electronic systems, and the company claims it consumes 15 percent less power and has 15 percent improved performance over competing 40 nm FPGAs.Older-generation devices such as the Virtex, Virtex-II and Virtex-II Pro are also still available, although their functionality is largely superseded by the Virtex-4 and -5 FPGA families. The Virtex-II Pro family was the first to combine PowerPC embedded technology (including single and multiple PowerPC 405 processor cores) and integrated serial transceivers (up to 3.125 Gbit/s in Virtex-II Pro and up to 10.3125 in Virtex-II Pro X).The Virtex-4 series was introduced in 2004 and was manufactured on a 1.2V, 90-nm, triple-oxide process technology. The Virtex-4 family introduced the new Advanced Silicon Modular Block (ASMBL) architecture enabling FPGA platforms with a combination of features to support logic (LX), embedded processing and connectivity (FX), digital signal processing (SX).