Semi-Custom Design of Adiabatic Adder Circuits

V S Kanchana Bhaaskaran S Salivahanan SSN College of Engineering Chennai 603110 D.S.Emmanuel Vellore Institute of Technology Vellore 632006

Abstract
The paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs for carry lookahead adders and tree adders were designed. The simulations prove that the cell based design of tree adder circuits can save energy ranging from 2 to 100 over a frequency range of operation of 2MHz to 200MHz against the static CMOS circuit implementation. The Schematic Edit and T-Spice of Tanner tools formed the simulation environment.

1. Introduction
The power consumption is the principal criterion for the design and development of portable and high performance applications. Hence, the trend has been to search for techniques to reduce the power dissipation, low power operation, and designing for energy recovering and recycling. Energy recovery is proving a promising approach for the design of low power VLSI circuits. The primary advantage of adiabatic circuits results from its inherent nature of deriving a constant current from the power clock and the FETs working with minimum voltage between the source and drain terminals [1]. The adiabatic circuits are classified into fully adiabatic and quasi-adiabatic circuit based on whether full energy recovery or partial energy recovery is obtained. The former has no non-adiabatic energy loss, while the later suffers from both adiabatic and

non-adiabatic energy losses. The power supply switching noise is generated by the effective resistance(R) and inductance (Ldi/dt). When a number of nodes in the circuit switch at the same time, the effective switching current and hence, the rate of change of current (di/dt) on the supply line can prove very large. Since switching occurs with minimum voltage drop across devices and both the signal and power supply change slowly, very steep spikes are effectively removed from the supply current, and this results in appreciable reduction in switching noise. The literatures have brought out several types and genres of adiabatic circuits, namely, 2N-2P, 2N2N2P[2], PFAL [9], Pass Transistor Adiabatic Logic (PAL) [3], Clocked Adiabatic Logic (CAL) [4], Improved Pass-gate Adiabatic logic (IPGL) [5] and Adiabatic Differential Switch Logic (ADSL) [6]. They are designed for special functions with custom oriented designs. Design time is much longer and such a full custom design is needed only in performance critical applications. Standard cell-based designing is therefore preferred for faster design of circuits. Addition is one of the most commonly used arithmetic operations. This work aims at cell-based designing and comparison of 2N-2P, 2N-2N2P, PFAL, IPGL and ADSL based adiabatic adder circuits. Schematic designs are made for the individual AND, XOR, NOT and MULTIPLEXER modules and they are characterized. They are then employed in the full adder cell design. This paper presents the design, evaluation, performance analysis of 8-bit carry look ahead adders and tree adders constructed using the adder cells developed.
A

B
CO
CIN

Fig. 1 Schematic circuit of one bit full adder

Proceedings of the 19th International Conference on VLSI Design (VLSID06)

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CO

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(d) (e) Fig.2 Adiabatic circuit families (a) 2N2P (b) 2N2N2P (c) PFAL (d) IPGL (e) ADSL

A1
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2. Adiabatic Cell Design and Design Flow

The realization of full adder is done in a semiautomatic custom flow as depicted in Fig.1. Fig. 2 depicts the typical circuit arrangement of the adiabatic circuit families. The individual modules are constructed using the S-Edit and the designs are exported to the T-Spice circuit Simulator. The operational feasibility of the gate is studied for various frequency ranges and capacitive loads. The functional block diagram of the full adder circuit is shown in Fig.3.

Fig. 4. Schematic view of the 8-bit CLA architecture The literatures provide different one-bit adder topologies. For a logical evaluation, the same structural arrangement as followed for adiabatic adders, viz., by the use of XOR, AND and BUF gate modules was followed for CMOS adder also.

4. Performance Comparison

Evaluation

and

3. Adiabatic Adder Designs

The ripple carry adder design was not preferred due to its reduced speed of operation. Hence the carry lookahead adder (CLA) structure [7] that possesses faster carry computation ability and a tree-structured adder [8] were selected for our study. A cell generator in C++ program was developed to synthesize the architecture for structure of the CLA circuit. Fig.4 shows the general schematic arrangement of the adiabatic 8-bit CLA architecture. Fig.5 shows the schematic view of a tree adder. The adder highlighted with a star identifies the full adder driven by and driving a similar full adder with the respective sum and carry outputs. We designed a combinational CMOS one bit adder for comparison.
CO
A B ABAR BBAR
XOR

The results of the simulation are presented in this section. Each of the full adders was analyzed for energy consumption and the number of transistor devices employed in the design, which is an indication of the actual silicon area requirement for the circuit. The inputs A, B and Ci were supplied as per the three bit binary counting sequence for uniformity. The frequency of the power clock was varied from 100Hz to 200MHz. The energy dissipation measurement was done from the simulation outputs, by integrating the power over the specific period of simulation, which varied from 320ns to 640ms. The average power dissipation of the circuit was also observed. Fig.6 shows the energy comparisons made among the adiabatic families with
C4 B

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BUF

Fig.3 Adiabatic Full Adder Block Configuration

Fig.5 Schematic View of Tree Adder Structure

Proceedings of the 19th International Conference on VLSI Design (VLSID06)

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Energy, pJ

2N2P -0.10 -0.05

2N2N2P

IPGL

ADSL

CMOS

1 0.00

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Frequency, MHz

-8.E-07 -6.E-07 -4.E-07 -2.E-07 0.E+00

Energy,J

PFAL ADSL 0FF 2 4 8 10 14 16 Load Capacitance, fF

Fig. 6. Energy comparison of adiabatic adders with no load capacitances.

IPGL 2N2P -6.E-08 Energy, J -4.E-08 -2.E-08 0.E+00 0 10 20 30 40 50 60 70 80 Load Capacitance, fF 2N2N2P CMOS

Fig.8. Energy comparison of PFAL and ADSL adiabatic adders

2N2N2P Frequncy, MHz 100MEG 200MEG 300MEG 0 -1E-07 -2E-07 Energy, J -3E-07 2N2P PFAL ADSL

Frequency, MHz

Fig.7. Energy comparison of 2N2NP, 2N2N2P AND IPGL adiabatic adders no load at the sum and carry terminals. The negative sign indicates the energy dissipated in the circuit. Fig.7 gives the energy consumption for different capacitive loads for 2N2P, 2N2N2P and IPGL adiabatic adders. These adders were found to possess higher loaddriving capability than the PFAL and ADSL families, whose performance is shown in Fig.8. It is to be pointed out that the PFAL was reported in [9] as demonstrating the lowest power consumption. Our work shows that the PFAL adiabatic when driven by two-phase sinusoidal power clock is more energy consuming as depicted in Fig. 8 even for low capacity load conditions. Figs.9 and 10 show the energy comparisons made for the 8-bit carry lookahead adder and tree adder circuits of various adiabatic families The energy consumption comparisons [9] were made, and the concept of adiabatic gain G (the ratio between the energy dissipated by the CMOS gate and the equivalent adiabatic gate) is used. The Table 1 shows the transistor counts of the CLA and tree based adder circuits. The adiabatic gain, G for the case of tree adder is tabulated in the Table 2 for comparison. Table.1 Transistor counts for CLA and Tree Adders PFAL 2N2P 2N2N2P ADSL 8-BIT CLA 936 700 936 1440 TREE ADDER 648 504 648 936

Fig. 9. Energy comparisons made for 8-bit CLA for the 2N2P, 2N2N2P, PFAL and ADSL It can be noted that the adiabatic gain varies from 101.2 at 2MHz to 2.3 at 200MHz as against the CMOS tree adder.

5. Power Clock Generation

The power clocks used in adiabatic circuits provide the power for the circuit and behave as clock also. The resonant energy recovery topology based on synchronous clock generation is used for clock generation with the internal time base signals used as clock timing signals. Current charging as necessitated for adiabatic circuits is approximated using the sinusoidal power supply generated by the LC resonant
2MEG 20MEG 50MEG 100MEG 200MEG 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 2N2P 2N2N2P CMOS PFAL ADSL -0.8 -0.9 -1

Energy, pJ

Fig. 10. Energy comparisons made for the tree adders

Proceedings of the 19th International Conference on VLSI Design (VLSID06)

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Table.2 Energy consumption and adiabatic gain of the tree adders with respect to CMOS adders
2N2N2P 2N2P 200MEG -0.255 -0.229 2.081 2.320 100MEG -0.241 -0.127 2.208 4.183 50MEG -0.162 -0.093 3.283 5.711 20MEG -0.067 -0.048 7.942 10.973 2MEG -0.007 -0.005 72.432 101.218 ADSL -0.889 0.598 -0.555 0.958 -0.469 1.132 -0.384 1.383 -0.251 2.113 ADSLM -0.928 0.573 -0.619 0.859 -0.433 1.229 -0.310 1.712 -0.036 14.908 PFAL -0.604 0.879 -0.529 1.005 -0.302 1.761 -0.122 4.372 -0.010 50.873

Energy, J

-1.5E-10 -1E-10 -5E-11 0

2N2P 2N2N2P PFAL IPGL 2N CLK Adiabatic family

applications, and ADSL, 2N2P, 2N2N2P and IPGL are proved to be preferable. The results of Fig. 8 and 9 show that the 2N2P, 2N2N2P and IPGL are more suitable for operating under high load capacitance situations as against the ADSL and PFAL based circuits. It is also observed that the ADSL based adder is preferable for low voltage and low frequency high performance applications. The transients in the CMOS circuits are orders of magnitude higher in comparison with the adiabatic circuits. The sinusoidal frequency generates less noise and the skew does not dominate. Energy savings are achieved in the circuit, even taking into account the energy consumed for the clock generation circuitry. The results also show that the adiabatic circuits could be the most suitable choice, when the power consumption is considered the primary criteria for the given range of frequencies.

7. Reference
[1] [2]

Fig. 11. Power dissipation incurred in the adiabatic inverters and the clock generator circuit single phase power clock generator circuit of Fig 12. The circuit modeling was done initially. For a power
2 loss of PL , R= PL I L and C= 2 I L

[3]

V DD f c for a

particular frequency f c of the clock.

The power

[4]

conversion efficiency of the clock generator is defined as the ratio of the total dissipated load power to the total supply power delivered by the DC supply. It can be observed that the energy consumed by the clock generator for its power clock generation is comparatively less than that consumed by the inverters of various logic families as shown in Fig. 13.

[5]

[6]

6. Conclusion
[7]

This paper proves the feasibility of operating the adiabatic circuits by two-phase sinusoidal clock signals, and, the feasibility of semi custom modular design approaches for adiabatic designs. The work compares the adiabatic full adder circuits and multi bit adder circuits. For high frequency of operations, the IPGL could be employed though at higher transistor count and more area. The 2N-2P and 2N-2N2P circuits provide good performance at higher frequencies. The Full adder performance shows that the PFAL circuit experiences high-energy consumption in high frequency

[8]

Low power Design methodologies Jan.Rabaey & Massoud Pedram Kluwer Academic Publishers, 1996 V.S.Kanchana Bhaaskaran, Adiabatic Logic Circuit design with Integrated Power Clock Generator, Proceedings, Third International Conference on Signals, Systems & devices, March 21-24, 2005, Vol IV Vojin G Oklobdzija, Dragan Maksimovic and Fengcheng Lin, Pass-Transistor Adiabatic Logic Using Single Power-Clock Supply, IEEE Transactions on Circuits and Systems II:analog and Digital Signal Processing, Vol.44, No 10, Oct 1997 Dragan Maksimovic et al.,. Clocked CMOS adiabatic Logic with Integrated Single Phase Power Clock Supply, IEEE Transactions on VLSI Systems, Vol 8, No 4, Aug 2000, pp 460-463 L.Verga, F.Kovacs, G.Hosszu,An improved pass gate adiabatic logic, Proceedings, 14th Annual International ASIC/SOC Conference, pp 208-211, 2001 Y.Z.Zhang, H.H.Chen and J.B.Kuo, 0.8 V CMOS Differential Switch Logic Circuit using Bootstrap technique for Low Voltage Low Power VLSI Electronics Letters, 21st Nov 2002, Vol.38, No.24 Brent: R.P.Brent, and H.T.Kung, A regular layout for parallel adders, IEEE Trans. Comput., vol. C-31, pp.260-264, Mar. 1982. Chip: Chip-Hong Chang et al., A Review of 0.18 m Full Adder Performances for Tree Structured Arithmetic Circuits, IEEE Trans. On Very Large Scae Integrated Systems, vol.13, No.6, June 2005.
Antonio Blotti and Roberto Saletti, Ultralow-Power Adiabatic Circuit Semi-Custom Design, IEEE Trans. On VLSI Systems, vol.12, No.11, Nov 2004.

[9]

Proceedings of the 19th International Conference on VLSI Design (VLSID06)

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