This is a copy of the IEEE 1164 standard logic package.

It is used in all of the examples in the book and is listed here for reference. -- ---------------------------------------------------------- Title : std_logic_1164 multi-value logic system -- Library : This package shall be compiled into a -: library symbolically named IEEE. -: -- Developers : IEEE model standards group (par 1164) -- Purpose : This package defines a standard for -: designers to use in describing the -: interconnection data types used in vhdl -: modeling. -: -- Limitation : The logic system defined in this -: package may be insufficient for -: modeling switched transistors, since -: such a requirement is out of the scope -: of this effort. Furthermore, -: mathematics, primitives, timing -: standards, etc. are considered -: orthogonal issues as it relates to this -: package and are therefore beyond the -: scope of this effort. -: -- Note : No declarations or definitions shall be -: included in, or excluded from this -: package. The package declaration -: defines the types, subtypes and -: declarations of std_logic_1164. The -: std_logic_1164 package body shall be -: considered the formal definition of the -: semantics of this package. Tool -: developers may choose to implement the -: package body in the most efficient -: manner available to them. -: -- --------------------------------------------------------- modification history : -- --------------------------------------------------------- version mod. date: -- v4.200 01/02/92 -- -------------------------------------------------------In 1986, VHDL was proposed as an IEEE standard. It went through a number of revisions and changes until it was adopted as the IEEE 1076 standard in December 1987. The IEEE 1076-1987 standard VHDL is the VHDL used in this book. (Appendix D contains a brief description of VHDL 1076-1993.) All the examples have been described in IEEE 1076 VHDL, and compiled and simulated with the VHDL simulation environment from Model Technology Inc. The synthesis examples were synthesized with the Exemplar Logic Inc. synthesis tools. VHDL93 Updates Early in 1993 the VHDL language standard was updated to reflect a number of shortcomings with the VHDL 1076-1987 standard and to add some new features to the language. This new standard is called VHDL 1076-1993. In this appendix the 1987 standard will be referred to as VHDL87 and the 1993 standard as VHDL93. The goal of this appendix is not to give the user a complete description

of every new or changed feature, but to give the reader an idea of the scope of these changes and what effect they will have on future VHDL modeling efforts. The goal of the update was to remain compatible with VHDL87 so that VHDL87 models would work in a VHDL93 environment. This goal was not entirely achieved as some of the new features were no longer compatible.The main reason for the incompatibility was the use of new keywords in VHDL93, that may have been used as identifiers in VHDL87, and a major update of TEXTIO. The rest of this appendix includes discussions of the VHDL87 features that have either been added or changed. They are listed in alphabetical order for easier access. The std_logic Libraries The IEEE created the IEEE VHDL library and std_logic type in standard 1164. This was extended by Synopsys; their extensions are freely redistributable. Parts of the IEEE library can be included in an entity by inserting lines like t hese before your entity declaration: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; No attempt has been made here to be definitive or exhaustive. If you want real a nswers, read the source code. Links to the code or instructions on how to get it are provided for each section. The source is fairly readable to someone who kno ws some VHDL. Library information You can find information about the following libraries here: * * * * std_logic_1164 std_logic_arith std_logic_unsigned std_logic_signed

Missing parts Some more of the libraries will be added here eventually (hopefully). Until then , I will provide some source code: * * * * * * std_logic_entities std_logic_components std_logic_misc std_logic_textio gs_types cyclone_resolved