RS-232 Serial Protocol

The RS-232 serial communication protocol is a standard protocol used in asynchronous 232 serial communication. Figure 1 shows the relationship between the various components in a serial ink

Figure 1 : Asynchronous (RS-232) serial link The components are the UART, the serial channel, and the interface logic , An interface chip known as the universal asynchronous receiver/transmitter or UART is used to implement serial data transmission transmission. The UART sits between the host computer and the serial channel

FRAME FORMAT

A frame is a complete and nondivisible packet of bits A frame includes both information (e.g., data and characters) and overhead (e.g., start bit, error checking and stop bits) In asynchronous serial protocols such as RS-232, the frame consists of one start bit, seven or eight data bits, parity bits, and stop bits.

Figure 2 : RS-232 Frame (1 start bit, 7 data bits, 1 parity bits, and 2 stop bits) The start bit is used to signal the beginning of a frame The stop bit is used to signal the end of a frame Parity is used to detect transmission errors(Even and Odd parity is used) No clock signal is sent through serial line

IMPLEMENTATION ON FPGA
GENERAL RS232 STRUCTURE

Data_in

Uart Transmitter

TXD

Baud Control

sclk

Rate Genrator

Uart Data_out 8 Receiverer 1 RXD

FPGA It mainly consisting of a UART Transmitter, UART Receiver, Baud rate generator and a control mechanism UART Transmitter and UART Receiver is used for transmission and reception of data Baud rate generator is used to generate the clock signals for the UART Transmitter and UART Receiver Control mechanism is used to control the data transfer.

1. UART Transmitter
The UART Transmitter accepts the parallel data and converts it into serial data It performs the serializing action on the input data The block diagram is shown below

Data_in 8

1 TXINT
SERIALIZER

TXD

bclk

rst

It accepts the 8-bit data from the data bus and transmits a single bit in a single clock cycle The serializer first converts the 8-bit data into 10-bit by adding start and stop signal to the data bits The serializer is working on the input clock generated by the baud rate generator The transmission is possible only the Transmit Data Register(TDR) is empty After the completion of the transmission UART Transmitter generates an interrupt TXINT. It has a state reset signal to reset the serializer .

SERIALIZER

Data_in

TDR

TSR

TRANSMIT

bclk TXINT TDRE rst SCSR

TDRE 6 5 4 3 2 1 0

CONTROL

TXD

SERIALIZER

TDR TSR

Transmit Data Register (8-bit) Transmit Shift Register (9-bit)

SCSR Serial communication status Register(8-bit)

TDR is used to hold the input data TSR is used to hold the start, data, and stop bits TSR (0) TSR (1-8) TSR(9) Start bit Data bits Stop bit

SCSR stores the status of the transmitter SCSR(7) TDRE(Transmit Data Register Empty)

If TDRE=1 means TDR contains data and transmission is not possible If TDRE=0 means TDR doesnt contain any data and transmission is possible

SM CHART FOR UART TRAMSMITTER

RESET

sclk

1 IDLE

TDRE

0 TDR Data_in set TDRE

form TSR

SYNCH

sclk

clear TSR(0)

TXDATA inc TCNT

sclk

TXD TSR(Tcnt)

Set TXINT Clear tcnt

Tcnt=9

2. UART RECEIVER
The UART Receiver accepts the serial data and converts it into parallel data It performs the de-serializing action on the input data The block diagram is shown below

Data_out

RDRF RXINT

DESERIALIZER

RXD

sclk bclk

rst

It accepts the a set single bit from the input and convert it into a parallel(8-bit) data The reception is possible only RDRF signal is low After the reception of the 8-bit data, it generate an interrupt(RXINT) The oversampling method is used to ensure the start and data bits It has a reset signal to reset the system.

OVERSAMPLING METHOD The bit stream coming from the RXD pin is not synchronized with the clock(bclk) If we attempt to read the RXD at the rising edge of bclk we would have a problem if RXD changed near the clock edge We would have a setup and hold time problems

RXD

start bit *

1st data bit *

2nd data bit *

bclkx8

4clock

4 clock

4 clock

DE-SERIALIZER

Data_out

RDR

RSR

RDRF
RECEIVE

RXD

RXINT
CONTROL

bclk

rst SCSR
7 RDRF 5 4 3 2 1 0

DE-SERIALIZER

RSR RDR SCSR

Receiver Shift Register(8-bit) Receiver Data Register(8-bit) Serial Communication Status Register(8-bit)

SM CHART FOR UART RECEIVER

RESET

clk

IDLE

RXD

START_DETECT

clkx8

Clear cnt1

RXD

Clear cnt1

Cnt1=3

Inc cnt1

(Contd..)

RXDATA

clkx8

R
Inc cnt1

cnt1=7

Shift RSR Inc cnt2 Clear cnt1

Cnt2=8

1
RDR RSR

Generate TXINT Set RDRF Clr cnt1

INTERUPT

Clr cnt2

clk