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M.Tech. – I Semester Supplementary Examinations,
September, 2008
1.a) Draw the ASM chart to detect the overlapping sequence 1010 from
the incoming bit stream and output 1 for each detection.
Ex: x: 10101010110- - - - - - -
Z: 00010101000- - - - - - -
Implement the controller circuit using MUX method.
b) What is the difference between melay and moore state machine.
2.a) Draw the general structure of an FPGA and explain how a logic-
function can be realized on FPGA with a simple example.
b) Design and implement a BCD counter on PLD (PLA). Draw the
complete fuse-map circuit.
b) Draw the table giving the set of all possible single struck faults and
the faulty and fault-free responses and also construct the fault cover
table for the circuit shown in below.
Contd…2.,
Code No: 54111/MT ::2::
7.a) Explain the different types of fault models and fault types in a PLA.
b) Plot the following PLA on the map. Identify the undetectable faults.
Determine a minimal test set for an detectable faults.
x1 x2 x3 x4 Z1 Z 2
0 2 21 1 0
2 1 12 1 1
0 1 21 0 1
&_&_&_&