O Microcontrolador AT89S8252 Mdulo 1

Principais caractersticas do AT89S8252 Diagrama em Blocos do AT89S8252 Pinagem do AT89S8252 Circuito de Clock e Reset

Caractersticas
Microcontrolador de 8 bits Memria de programa interna de 8kBytes (FLASH), com capacidade de expanso para at 64kBytes com memria externa

Memria de dados no voltil interna de 2kBytes (EEPROM)

Memria RAM interna de 256 bytes com capacidade de expanso para at 64kBytes com memria externa

Gravao do chip on-board atravs de uma interface ISP (In-circuit Serial Programming)

Caractersticas
Possui 32 linhas para I/O distribudas em 4 portas Watchdog Timer (WDT) programvel de 16ms a 2048ms

Possui 3 Temporizadores/Contadores de 16 bits cada

Porta serial full duplex (UART) e Interface Serial SPI

Circuito oscilador interno, precisando apenas de um cristal e 2 capacitores externos

Dois modos de baixo consumo : IDLE e Power down

AT89S8252
Block Diagram
P0.0 - P0.7 P2.0 - P2.7

VCC PORT 0 DRIVERS GND PORT 2 DRIVERS

EEPROM

RAM ADDR. REGISTER

RAM

PORT 0 LATCH

PORT 2 LATCH

FLASH

B REGISTER

ACC

STACK POINTER

PROGRAM ADDRESS REGISTER

BUFFER TMP2 TMP1

ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS

PC INCREMENTER

PSW

PROGRAM COUNTER

PSEN ALE/PROG EA / VPP RST WATCH DOG PORT 3 LATCH TIMING AND CONTROL INSTRUCTION REGISTER DUAL DPTR

PORT 1 LATCH

SPI PORT

PROGRAM LOGIC

OSC PORT 3 DRIVERS PORT 1 DRIVERS

P3.0 - P3.7

P1.0 - P1.7

3
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Pin Configurations
PDIP
(T2) P1.0 (T2 EX) P1.1 P1.2 P1.3 (SS) P1.4 (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)

TQFP
P1.4 (SS) P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22

(MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5

1 2 3 4 5 6 7 8 9 10 11

P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)

PLCC
P1.4 (SS) P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3)

Pin Description
VCC GND Port 0 Supply voltage. Ground. Port 0 is an 8-bit open drain bi-didirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.

AT89S8252
0401FMICRO11/03

(WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4

18 19 20 21 22 23 24 25 26 27 28

(MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5

7 8 9 10 11 12 13 14 15 16 17

6 5 4 3 2 1 44 43 42 41 40

39 38 37 36 35 34 33 32 31 30 29

P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)

(WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4

Circuito de Clock
O Circuito de clock responsvel por gerar os pulsos para que o microcontrolador execute o programa armazenado na memria. A frequncia com que esses pulsos acontecem determina a velocidade de execuo do programa. O perodo do clock o inverso da frequncia do cristal. Para um clock de 1MHz o perodo 1/1MHz = 1us. O AT89S8252 possui um circuito amplificador inversor interno, necessitando apenas de 2 capacitores e o cristal para funcionar. Os pinos XTAL1 e XTAL2 so entrada e sada do amplificador inversor respectivamente. importante que os componentes do circuito de clock fiquem prximos ao controlador para evitar que rudos sejam inseridos no percurso. O valor de C1 e C2 deve ser 30pF 10pF quando for usado cristal e 40pF 10pF quando for usado ressonador cermico. Quando um clock externo for usado, o pino XTAL2 deve ficar desconectado e o sinal deve ser ligado ao pino XTAL1.

Circuito de Clock
Um ciclo de mquina o tempo necessrio para que o microcontrolador faa a busca de uma instruo na memria, decodifique a mesma e a execute. No AT89S8252 e na maioria dos controladores da famlia x51, um ciclo de mquina formado por 12 ciclos do clock. As instrues mais rpidas do AT89S8252 levam apenas um nico ciclo de mquina para serem executadas. As instrues mais lentas levam at 4 ciclos de mquina. Nos controladores mais avanados da famlia x51, o ciclo de mquina de apenas 4 ciclos de clock, o que faz com que o controlador seja 3 vezes mais rpido com a mesma frequncia de clock.

T C IC L O D E M Q U IN A 1 C M = 12 * T

A mxima frequncia de clock permitida no AT89S8252 24MHz.

Circuito de Reset
O circuito de reset responsvel pela inicializao de todos os registradores e memria RAM interna do microcontrolador, garantindo uma condio inicial para o seu correto funcionamento. Existem dois tipos de reset : o POR (Power On Reset), que acontece sempre que o microcontrolador energizado e o Reset Forado ou Reset Hardware, onde o estado de reset alcanado forando-se o nvel lgico alto no pino RST. No AT89S8252, enquanto a tenso em RST (pino 9) estiver acima de 70% de VCC, o estado de reset mantido. Para que o reset seja realizado corretamente, o nvel lgico alto deve ser aplicado ao pino RST por pelo menos 2 ciclos de mquina. Os valores de R e C so calculados com base nesta diretiva. Para um clock de 12MHz, os valores de R e C podem ser 10k e 10uF, respectivamente.
VCC C AT89S8252

RST

Circuito de Reset
Alguns controladores possuem o resistor internamente, fazendo-se necessrio apenas o capacitor. Neste caso, o datasheet dever ser consultado para saber o valor do resistor para que o capacitor possa ser calculado corretamente. O reset forado alcanado forando-se o nvel lgico alto no pino RST durante dois ciclos de mquina. Isto pode ser conseguido atravs de uma chave. No Datasheet do controlador indicado o valor de cada registrador e das portas aps o reset. No Datasheet do controlador indicado o valor de cada registrador e das portas aps o reset.
R VCC C AT89S8252

RST

VCC

AT89S8252

RST

Circuito de Reset
A figura a seguir mostra um exemplo de POR

AT89S8252
Z

Absolute Maximum Ratings*

Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V DC Output Current...................................................... 15.0 mA *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics
The values shown in this table are valid for TA = -40C to 85C and VCC = 5.0V 20%, unless otherwise noted.
Symbol VIL VIL1 VIH VIH1 VOL VOL1 VOH Parameter Input Low-voltage Input Low-voltage (EA) Input High-voltage Input High-voltage Output Low-voltage (Ports 1,2,3)
(1)

Condition (Except EA)

Min -0.5 -0.5

Max 0.2 VCC - 0.1 0.2 VCC - 0.3 VCC + 0.5 VCC + 0.5 0.5 0.5

Units V V V V V V V V V V V V

(Except XTAL1, RST) (XTAL1, RST) IOL = 1.6 mA IOL = 3.2 mA IOH = -60 A, VCC = 5V 10% IOH = -25 A IOH = -10 A

0.2 VCC + 0.9 0.7 VCC

Output Low-voltage (1) (Port 0, ALE, PSEN) Output High-voltage (Ports 1,2,3, ALE, PSEN)

2.4 0.75 VCC 0.9 VCC 2.4 0.75 VCC 0.9 VCC -50 -650 10 50 300 10 25 6.5 100 40

VOH1

Output High-voltage (Port 0 in External Bus Mode)

IOH = -800 A, VCC = 5V 10% IOH = -300 A IOH = -80 A

IIL ITL ILI RRST CIO ICC

Logical 0 Input Current (Ports 1,2,3) Logical 1 to 0 Transition Current (Ports 1,2,3) Input Leakage Current (Port 0, EA) Reset Pull-down Resistor Pin Capacitance Power Supply Current

VIN = 0.45V VIN = 2V, VCC = 5V 10% 0.45 < VIN < VCC

A A A K pF mA mA A A

Test Freq. = 1 MHz, TA = 25C Active Mode, 12 MHz Idle Mode, 12 MHz

Power-down Mode

(2)

VCC = 6V VCC = 3V

Notes:

1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA; Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power-down is 2V

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Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 9) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Table 1. AT89S8252 SFR Map and Reset Values

0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H 98H 90H 88H 80H IP XX000000 P3 11111111 IE 0X000000 P2 11111111 SCON 00000000 P1 11111111 TCON 00000000 P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DP0L 00000000 TL1 00000000 DP0H 00000000 TH0 00000000 DP1L 00000000 TH1 00000000 DP1H 00000000 SPDR XXXXXXXX PCON 0XXX0000 SBUF XXXXXXXX WMCON 00000010 SPSR 00XXXXXX PSW 00000000 T2CON 00000000 T2MOD XXXXXX00 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 SPCR 000001XX TH2 00000000 ACC 00000000 B 00000000 0FFH 0F7H 0EFH 0E7H 0DF H 0D7H 0CF H 0C7H 0BFH 0B7H 0AFH 0A7H 9FH 97H 8FH 87H

AT89S8252
0401FMICRO11/03