RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS

New Design of a MAP Decoder

Leila Sabeti

Advisor: Dr. M. Ahmadi Co-Advisor: Dr. K. Tepe

April 2004

University Of Windsor

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS

Outline
Objective

Digital Communication System Turbo Encoder Turbo Decoder Algorithms History Comparison BCJR/MAP Algorithm Max-Log-MAP Algorithm Comparison between previous implementations Proposed System Design Proposed quantization Metric normalization RTL simulation Synthesis Future works
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Objective
MAP/BCJR Decoder -can be used in communication systems (wireless, satellite, magnetic recording, digital video,) -Minimizes the bit error rate of received channel information -regenerates the original information Max-Log-MAP algorithm for implementation.

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Digital communication System

RSC 1/2 Information Source Source Encoder Information Source Source Encoder Channel Encoder Channel Encoder BPSK Digital Modulator Digital Modulator Transmitter Transmitter

AWGN

Channel Channel

Output information Source Decoder Output information Source Decoder

Channel Decoder Channel Decoder

Digital Demodulator Digital Demodulator

Receiver Receiver

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Turbo Encoder
Recursive Systematic Convolutional Codes (RSCC), two memory, code rate 1/2. Parallel or Serial concatenation of (RSCC) and a pseudo random interleaver
and/or more memories.

The encoding process represented by a state transition diagram.

0/00

1/11

00
1/10

1/11

10
0/00 0/01

01 11
1/10 0/01

RSC Encoder (Two Memory,Rate ,Generators (7,5))

State Diagram
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Turbo Encoder
Expanding the state transition diagram
Zero Transition K 00 11 One Transition

state
00

00 11 11

00 11

00 11 11 00 11

00

00

11

01 00 10 10 01 11 01 01 10 01 01 10 01

Trellis diagram for (7,5) convolutional code

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Turbo Decoder (SISO)

Important development in coding theory in recent years. Standard(Consultative Committee for Space Data Systems(CCSDS), and 3rd Generation Partnership Project (3GPP) ) Strong requirement for the efficient implementation

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Turbo Decoder
MAP/BCJR Decoders, interleavers and deinterleavers BCJR algorithm for received channel sequences Passing information to the next decoder at each iteration Reduction of Bit Error Rate (BER).
A Posteriori Probability

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Algorithms History

1948 : Shannon[6] 1967 : Viterbi Algorithm (VA)[6] 1972 : MAP/BCJR Algorithm[1] 1989 : Optimum Update (SOVA-SU)[7] 1990 : Max-Log-MAP[2] 1995 : Log-MAP[2] 1996 : SOVA[7] 2001 : Improved Max-Log-MAP [4][5]

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Performance of different Turbo decoders

1.E+00 1.E-01

Uuencoded

BER (Bit Error Rate)

1.E-02

MAP and Log-MAP have the best accuracy.

1.E-03 1.E-04
MAP SOVA

1.E-05
L-MAP ML-MAP

SOVA is the worst. ML-MAP is in between but it will be improved by iterative decoding and using scaling factor for APP.

1.E-06 1.E-07

0 0

1 1

Es/No (Signal to noise ratio)

2 2

3 3

3 10

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Complexity Comparison
MAP/BCJR Max-Log-MAP Log-MAP Sliding MAP SOVA

OM (n 2 ) Os (n 2 )

Oc(n 2 ) Os (n 2 )

Oc(n 2 ) Os (2n 2 )

OM (6n 2 ) Os (6n 2 )

Oc(0.5n 2 ) Os (0.5n 2 )

n: Number of states, M: Multiplications, S: Summations, C: Comparisons The differences of considered architecture in terms of power consumption is not significant. Improved ML-Map by using a scaling factor within the extrinsic calculation.

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BCJR/MAP Algorithm

State
0 1 2 3 4 5 6 7
0 k-1 k k +1 k +n- 1 k +n N

Trellis Length
0 1 2 3 4 5 6 7

The output of this algorithm (soft output) gives the probability of each received bit of information to be one or zero
Inputs

Soft Information

b)

Forward Backward recursion

Output
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BCJR/MAP Algorithm
t (m' , m) = pt (m | m' ).qt ( X t | m' , m).R(Yt | X t ).R(Yt | X t )
d p

t (m) = t 1 (m' ). t (m' , m)

m'

t (m' ) = t +1 (m). t +1 (m' , m)

m

( X t +1 ) = ln

t +1 ( m ', m ), X =1

t +1 ( m ', m ), X = 1

( m' , m). t +1 ( m ). t ( m' ) ( m ' , m). t +1 ( m ). t ( m ' )

Too difficult in practice, because of the numerical representation of

probabilities,nonlinear functions and mixed multiplications and additions of these values.

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Max-Log-Map Algorithm
work with the logarithms of the values using the following approximation: ln( e 1 + ... + e n ) max i
i{1 ... n }

Multipliers which make the design complex, huge and slow are changed to adders and comparators.

ln t( m ' , m ) =

2Y t d X t N0

2Y t p X t N0

+ ln AP t + K

ln t (m) = max[ t 1 (m' ) + t (m' , m)]

m'

ln t (m' ) = max[ t +1 (m' ) + t +1 (m' , m)]

m

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Max-Log-MAP Algorithm
Using Alpha, Beta and Gamma, Log-Likelihood Ratio (LLR) is computed which provides soft decision. Soft Output makes it possible to decide if each received Bit of information is zero or one.

Log-Likelihood Ratio (LLR)

ln t +1 = max [ln t +1 (m' , m) + ln t +1 (m) + lnt (m' , m)]

( m, m '), X =1

max [ln t +1 (m' , m) + ln t +1 (m) + lnt (m' , m)]

( m,m '), X = 1

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Previous implementations
Algorithm [4] [12] [8] Prp ML-MAP Log-MAP SL-MAP ML-MAP Speed High High Low High Area Medium High Low Accuracy High High High

Speed range about 20MHz~100MHz, needed for iterations Minimum area about 7mm2

Disadv. of [8]: Complex Control unit for synchronization of decoding steps Decreasing the memory size and increasing the accuracy in ML-MAP the lowest-complexity algorithm. Using the parallel calculation and LUTs, High speed

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Proposed System Specification

Encoder: Recursive Systematic Convolutional (RSC) Channel: Additive White Gaussian Noise (AWGN) Considered Modulation: Binary Phase Shift Keying (BPSK), which maps 1 to 1 and 0 to 1. Number Of Memories: 2. Code Rate: R=1/2 Block size: Flexible to the block size

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Proposed System Design

1. 2. 3. Gamma and Alpha are calculated together and stored in RAM . Beta and Landau are also calculated in parallel to give the soft output Faster, less memory and reduced area

Cal. Cal.
APP Ys Yp

RAM RAM

Cal. Cal.

RAM RAM

Soft Soft Output Output

Cal. Cal.

Soft Output

Cal. Cal.

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Proposed Gamma Unit

Logarithm of Gamma

ln t( m ' , m ) =

2Y t d X t N0

2Y t p X t N0

+ ln AP t + K

No sensitivity of Max-Log-MAP algorithm to the variance of the noise Eight nonzero Gammas but four different values.

ln t , 00 (m' , m) = (Ytd Yt p ) + ln APt (1) ln t , 01 (m' , m) = (Ytd + Yt p ) + ln APt (1) ln t ,10 (m' , m) = (+Ytd Yt p ) + ln APt (+1) ln t ,11 (m' , m) = (+Ytd + Yt p ) + ln APt (+1)
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Proposed Gamma Unit

Ys Yp

+ + + +
ln{P(1)} (Adders)

APP

LUT

ln{P(-1)}

00 10 11 01

Yd (systematic data) and Ys (Parity data) are added/subtracted.

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Alpha Calculation Unit

t (00, 01, 10,11)
Alpha recursion State 00 State
Alpha 0

Alpha: t+1 Alpha: t

Alpha 1 Alpha 0

In each Block Alpha is calculated using proper Gamma and previous calculated Alphas. Beta Calculation Unit Soft outputs

State 11 State

Alpha 1

Alpha 3 Alpha 2

To Memory

State 22 State

Alpha 2

Alpha 0 Alpha 1

State 33 State

Alpha 3

Alpha 2 Alpha 3

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Proposed quantization
Quantization of input,Gamma, Alpha,Beta,Output and Decreasing the number of bits->Lower accuracy Increasing->Larger memories for storage Crucial choosing Minimum quantization that still gives a reliable BER based on simulation results[4] .

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Proposed quantization
Decoder inputs [-4, 4], 90% covering. Integer value with one digit precision.
1 2
Integer

APP values between 8 and +8.

mantissa

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Proposed quantization
lnAP(1) and lnAP(-1) are quantized to integer values from 8 to 0. Also 8bits for , , and 8bits for output is considered.

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Metric Normalization
In forward or backward recursions, metric values can easily overflow or underflow. subtraction of the maximum or minimum node metrics at a specific time from all of the node metrics at that time

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RTL Simulation
Verilog Simvision

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Synopsys (Design analyzer) Modules

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Synopsys I/O wrapper

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Synthesis

Synopsys Area: 0.96 mm2 Speed: 150 MHz Fastest Implementation: 110MHz

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Partitioning and Floorplanning

Encounter

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Future Works
System Design System Design

Verilog Design analyzer Design analyzer Verilog

RTL Simulation RTL Simulation Synthesis Synthesis Scan Insertion Scan Insertion Gate-Level Simulation Gate-Level Simulation Floorplanning Floorplanning Placement Placement Clock Tree Generation Clock Tree Generation Routing & Timing Routing & Timing Verification Verification Physical Verification Physical Verification 31

Thank you

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