Principles of SMPS

Technical Information

Topologies

Topologies
Voltage Regulation
13022

Ferro-resonant Regulation Ferro-resonant techniques generate a line regulation by means of a resonant tank circuit and provide inherent isolation between primary and secondary windings. Ferro-resonant regulation is derived from a specially designed constant-voltage transformer. The semi-square wave output voltage of the transformer is well suited to rectification and filtering. The inherent current limitation in ferro-resonant regulated power supplies results from the collapse of output voltages as load current becomes excessive.
Unsaturated primary
13020

Ii

Vi+ T1

Vo+

Io

Ui

Control circuit

Uo

Gi

Go

Fig. 3 Linear regulator without input to output isolation

Switching Regulation Switching regulation is accomplished by the control of the on-time to off-time ratio of the pass transistor but in a fast switching technique. Advantages are a high efficiency and reliability and minimum heat generation. This control technique is known as Pulse Width Modulation (PWM) and is commonly working at switching frequencies far above 20 kHz.

AC input

Resonant tank circuit

CL

Saturated secondary

Regulated DC output

The active pulse width is narrow at high input voltage and is wide for low input voltage, but always remains within the envelope of the almost constant switching frequency. Switching regulators do not provide any isolation between the input and output circuits.
13023

Fig. 1 Ferro-resonant regulator, input to output isolated

Output voltage
13021

Ii

Vi+ T1 Control circuit

Vo+

Io

Ui

Ce

Uo

Gi

Go

Fig. 4 Switching regulator without input to output isolation

0% 100% 120% 140% Load current

Efficiency (calculated for regulators without input to output isolation). a) Linear regulator Po U o Io h = = Pi U i Ii b) Switching regulator 1 V collector-emitter saturation voltage, switching losses are not considered.

Fig. 2 Inherent current limitation

Linear Regulation Linear regulation is accomplished by the control of a voltage drop across a variable resistance element, the pass transistor. The difference between the unstable input voltage and the stabilized output voltage is generated across this pass transistor. The power loss is the product of its collector-emitter voltage and the input current. The input current and the output current are approximately equal. Linear regulators do not provide any isolation between the input and output circuits.

P loss I o 1 V Po Uo h = Pi (U o + 1)
h [%] 100 80 60 40 20 linear 2.6 3 Ui /Uo switching
13024

1 1.4 2 Fig. 5 Efficiency versus input voltage

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Principles of SMPS
Basic Switching Configurations
Buck Converter

Technical Information

Topologies

Advantages: FET drain-source U DS Ui, simple choke. No problems with magnetic coupling. Low loading of output capacitor. Duty cycle of TON / T = 1 is possible.
Lr T1
13025

Disadvantages: No isolation between input and output. The gate drive circuit must be in a floating configuration.
a) Ui 0 b) TON = 0.5 T T t d) 0 T t T t c) 0 T t
13026

Ui

Ci

D1

Co

Uo U i

Io 0

Fig. 6 Buck converter

a) Voltage across the transistor T1 b) Choke current c) Current across the input capacitor C i d) Current across the output capacitor C o

Boost Converter Advantages: Simple choke. No problems with magnetic coupling. Duty cycle TON / T = 0 is possible (U0 U i).
Lr D1
13027

Disadvantages: No isolation between input and output is provided. Medium loading of the output capacitor. High input start-up current.
TON = 0.5 T
13028

a) Ui

c) 0

Ui

Ci

T1

Co

Uo U i

0 b) Io 0

t d) 0

Fig. 7 Boost converter

a) Voltage across the transistor T1 b) Choke current c) Current across the input capacitor C i d) Current across the output capacitor C o

Buck-Boost Converter Advantages: Simple choke. No problems with magnetic coupling.

13029

T1 Ui

D1

Disadvantages: Power transistor drain-source voltage achieves approximately UDS Ui + Uo. No input to output isolation. Heavy loading of output capacitor. The gate drive circuit must be in a floating configuration. The polarity of the output voltage is negative in relation to the input voltage.
TON = 0.7 T
13030

Ci

Lr

Co

Uo

a) Ui 0 b)

c) 0

t d) 0

Fig. 8 Buck-Boost converter

Io 0

a) Voltage across the transistor T1 b) Choke current c) Current across the input capacitor C i d) Current across the output capacitor C o

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Principles of SMPS
Continuous Flyback Converter

Technical Information

Topologies

Advantages: Input to output isolation. Several output voltages can be regulated simultaneously. Wide control range for operation voltage changes (continuous transformer ratio).
n D1
13031

Disadvantages: Power transistor drain-source voltage U DS > U i + n Uo. Heavy loading to output capacitor and diode. Very good magnetic coupling necessary. Large core cross section with air gap required. Problems with stability and eddy currents. 13032 T
a) Ui 0 T t d) 0 = 0.5 T
ON

Ui

Ci

Co

Uo

c) 0 T t

D2

T1

b)

Fig. 9 Continuous flyback converter

T T (Trapezoidial current flow in transistor or primary winding)

a) Voltage across the transistor T1 b) Current across D1 c) Current across the input capacitor C i d) Current across the output capacitor C o

Discontinuous Flyback Converter Advantages: Galvanic isolation between input and output. Good stability and response times. Several output voltages can be regulated simultaneously.
n D1
13031

Disadvantages: Power transistor drain-source voltage U DS > U i + n Uo. Heavy loading to output capacitor and diode. Very good magnetic coupling necessary. Large core cross section with air gap required. Problems with eddy currents.
a) TON = 0.5 T
13034

c) 0

Ui

Ci

Co

Uo

Ui 0 b) T t

T d) 0

D2

T1
T T (Sawtooth current flow in transistor or primary winding) 0 t t

Fig. 10 Discontinuous flyback converter

a) Voltage across the transistor T1 b) Current across D1 c) Current across the input capacitor C i d) Current across the output capacitor C o

Single-Transistor Forward Converter Advantages: Core demagnetization is no problem. Simple design. Low output ripple current.
D1 Lr
13035

Disadvantages: Power transistor drain-source voltage U DS > 2 Ui. A demagnetization winding is necessary. Good magnetic coupling between primary and demagnetization winding is necessary.
a) Ui TON = 0.5 T
13036

D2 Ui D3 Ci T1

Co

Uo

c) 0

0 b) Io

t d) 0

Fig. 11 Single transistor forward converter

a) Voltage across the transistor T1 b) Current across the choke Lr c) Current across the input capacitor C i d) Current across the output capacitor C o

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Principles of SMPS
Push-Pull Converter Advantages: Small transformer. Low output ripple current.
D1 T1

Technical Information

Topologies

Lr

13037

Disadvantages: Power transistor drain-source voltage U DS > 2 Ui . Correction of the symmetry may cause problems. Good magnetic coupling between the two primary windings is necessary. Danger that both transistors may conduct simultaneously.
a) TON 0.45 T
13038

Co

Uo

c) 0

Ui

Ui

Ci

T2

D2

0 b)

t d) 0

Fig. 12 Push-pull converter

Io 0 T t

a) Voltage across the transistor T1 b) Current across the choke Lr c) Current across the input capacitor C i d) Current across the output capacitor C o

Half Bridge Push-Pull Converter Advantages: FET drain-source voltage U DS Ui. The transformer is very small and may have a high level of stray inductance. Low output ripple current.
D1 T1 Ci1 Ui Co Uo Lr
13039

Disadvantages: Danger that both transistors may conduct simultaneously. One galvanically isolated drive circuit is required.
a) Ui 0 b) Io 0 TON = 0.42 (2) T t d) 0 T t T t c) 0 T T t
13040

D2 Ci2 T2

Fig. 13 Single-ended push-pull converter

a) Voltage across the transistor T1 b) Current across the choke Lr c) Current across the input capacitor C i1 d) Current across the output capacitor C o

Two-Transistor Forward Converter Advantages: FET drain-source voltage U DS U i. Core demagnetization is not a problem. The transformer may have a high level of stray inductance. High efficiency. For higher input voltages. Low output ripple current.
T1

Disadvantages: One galvanically isolated drive circuit is required. Large transformer size.
a) Ui 0 TON = 0.5 T t d) 0 T t T t c) 0 T T t
13042

D3

D1

Lr

13041

b) Io 0

Ui

Ci D4 T2

D2

Co

Uo

a) Voltage across the transistor T1 b) Current across the output choke Lr c) Current across the input capacitor C i d) Current across the output capacitor C o

Fig. 14 Two-transistor forward converter

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Principles of SMPS
Full-Bridge Push-Pull Converter

Technical Information

Topologies

Advantages: FET drain-source voltage U DS Ui. The transformer may have a high level of stray inductance. For high power. Low output ripple current.
D1 T1 T2 Co Ui Ci D2 T4 T3 Uo Lr
13043

Disadvantages: Correction of symmetry may cause problems. Danger that two series transistors may conduct simultaneously. Two galvanically isolated drive circuitries are required. High component count.
TON = 0.42 (2) T t d) 0 T t T t c) 0 T T t
13044

a) Ui 0 b) Io 0

Fig. 15 Full bridge push-pull converter

a) Voltage across the transistor T1 b) Current across the choke Lr c) Current across the input capacitor C i d) Current across the output capacitor C o

Some Advanced Topologies

L
L1
13045

13046

D1

Io

Co

Uo

C1 Ui

D2

C0

Uo

Ui

D3 Ci T1

Fig. 16 Pseudo-resonant forward converter. High frequency variations.

L

Fig. 17 Synchronous rectifier (for low input voltages and high efficiency)

13047

Supply voltage
~

Input filter

T1

Co

Uo

Supply current

Io

Fig. 18 Boost converter (acting as power factor corrector)

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