Introduction

Data Organization and Addressing Capabilities

Instruction Set Summary

Signal Description

Bus Operation

Processing States

OnChlp Cache Memory

Coprocessor Interface Description

I nstruction Execution Timing

Electrical Specifications

Ordering Information and Mechanical Data

Condition Codes Computation

I nstruction Set

Instruction Format Survey

Advanced Topics

MC68020 Extensions to M68000 Family

MOTOROLA

MC68020
32-BIT MICROPROCESSOR USER'S MAN UAL
Second Edition

PRENTICE-HALL, Inc., Englewood Cliffs, N.J. 07632

 1 985, 1 984 by Motorola Inc. All rights reserved. No part of this book may be reproduced, in any form or by any means, without permission in writing from the publisher.

ISBN: 0-1 3-566860-3 (Prentice-Hall ed ition) ISBN: 0-1 3-566878-6 (Motorola edition)

Thi s document contains inform ation on a new product. S pec ificat ions and information herein are subject to change w ithout not i ce. Motorol a reserves the right to m ake changes to any products herein to i m prove functioning or design. Although the informat ion in th i s document has been carefu l l y reviewed and i s bel ieved t o be rel i able, Motorol a does not assume any l i ab i l ity ari sing out of the a p p l i cat ion or use of any product or c ircuit described herein; neither does it convey any l i cense under i t s patent rights nor the rights of others.
Motorola, Inc. general policy does not recommend the use of its components in life support ap plications where in a failure or malfunction of the component may directly threaten life or injury. Per Motorola Terms and Conditions of Sale, the user of Motorola components in li fe support ap plications assumes all risk of such use and indemni fies Motorola against all damages.

Printed in the United States of America 10 9 8 7

ISBN 0-13-566860-3 ISBN 0-13-566878-6

01 01

{PRENTICE-HALL {MOTOROLA ED.}

ED.}

Prentice-Hall International (UK) Limited, London Prentice-Hall Hispanoamericana, SA, Mexico Prentice-Hall of Japan, Inc., Tokyo Prentice-Hall of Australia Pty. Limited, Sydney Prentice-Hall Canada Inc., Toronto

Prentice-Hall of India Private Limited, New Delhi

Whitehall Books Limited, Wellington, New Zealand

Prentice-Hall Southeast Asia Pte. Ltd., Singapore

Editora Prentice-Hall do Brasil, Ltda., Rio de Janeiro

TABLE OF CONTENTS
Paragraph Number Page N umber

Title Section 1 Introduction Data Types and Address i n g M odes . . . . . I nstruct ion Set Overview . . . . . . . . . . . . . . V i rtual Memory/Mach i ne Concepts . . . . . V i rtual Memory . . . . . . . . . . . . . . . . . . V i rtual Mach i ne . . . . . . . . . . . . . . . . . . P i pe l i ned Architecture . . . . . . . . . . . . . . . .

1.1 1 .2 1 .3 1 .3 . 1 1 .3.2 1 .4

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1 -4 1 -5 1 -7 1 -7 1 -7 1 -8

2.1 2.2 2.2 . 1 2.2.2 2.2.3 2.3 2.4 2.5 2.6 2.7 2.8 2.8. 1 2.8. 1 . 1 2.8. 1 .2 2.8.2 2.8.2.1 2.8.2.2 2.8.2.3 2.8.2.4 2.8.3 2.8.3. 1 2.8.3.2 2.8.4 2.8.4. 1 2.8.4.2 2.8.5 2.8.6 2.8.6. 1

Section 2 Data Organization and Addressing Capabilities Operand Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Organ izat ion i n Reg isters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Reg isters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Reg isters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Organ izat ion in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nstruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ProgramlData References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers: N otation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reg i ster Di rect M odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Register D i rect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Register D i rect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register I nd i rect M odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Register I nd i rect . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Regi ster I n d i rect with Post increment . . . . . . . . . . Address Register I nd i rect with Predecrement . . . . . . . . . . . Address Regi ster I n d i rect with Displacement . . . . . . . . . . . Reg i ster I n d i rect with I ndex M odes . . . . . . . . . . . . . . . . . . . . . . . Address Regi ster I n d i rect with I ndex (8-Bit Disp lacement) Address Reg i ster I nd i rect with I ndex (Base Disp lacement) M emory I n d i rect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M emory I n d i rect Post-I ndexed . . . . . . . . . . . . . . . . . . . . . . . . Memory I nd i rect Pre-I ndexed . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter I nd i rect with Displacement M ode . . . . . . . . . . Program Counter I nd i rect with I ndex M odes . . . . . . . . . . . . . . . . PC I ndirect with I ndex (8-Bit Displacement) . . . . . . . . . . . . .
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2-1 2-1 2-1 2-2 2-2 2-2 2-4 2-5 2-5 2-5 2-6 2-6 2-6 2-7 2-7 2-7 2-7 2-8 2-8 2-8 2-9 2-9 2-1 0 2-1 1 2-1 2 2-1 3 2-1 3 2-1 4

TABLE OF CONTENTS (Continued)

Paragraph Number 2.8.6.2 2.8.7 2.8.7.1 2.8.7.2 2.8.8 2.8.8.1 2.8.8.2 2.8.9 2.9 2. 1 0 2.1 1 2.12 Page Number . . . . . . . . . . .
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Title PC I nd i rect with I ndex (Base D i splacement) . . . . Program Counter Memory I nd i rect M odes . . . . . . . . . . Program Counter Memory I nd i rect Postl ndexed Program Counter Memory I nd i rect Pre l ndexed . Absol ute Address M odes . . . . . . . . . . . . . . . . . . . . . . . . Absol ute Short Address . . . . . . . . . . . . . . . . . . . . . Absolute Long Address . . . . . . . . . . . . . . . . . . . . . I mmediate Data: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effective Address E ncod i ng Summary . . . . . . . . . . . . . . . . . System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . User Program Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q ueues
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3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10

Section 3 I nstruction Set Summary Data M ovement . . . . . . . . . . . . . . . . . . . . . . . . . . . I nteger Arithmetic Operations . . . . . . . . . . . . . . . Log ical Operat ions . . . . . . . . . . . . . . . . . . . . . . . . Shift and Rotate Operat ions . . . . . . . . . . . . . . . . B i t M a n i pu lation Operat ions . . . . . . . . . . . . . . . . Bit Field Operations . . . . . . . . . . . . . . . . . . . . . . . B i nary Coded Decimal Operat ions . . . . . . . . . . . Program Control Operat ions . . . . . . . . . . . . . . . . System Control Operat ions . . . . . . . . . . . . . . . . . M u lti processor Operat ions . . . . . . . . . . . . . . . . .

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32 32 3 4 34 35 36 36 37 38 39

4.1 4.2 4.3 4.4 4.5 4.5. 1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.6

Section 4 Signal Description Fu nction Code S i g na l s (FCO through FC2) . . . . . . . . . . . . . . . . . . Address Bus (AO through A31 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Bus (DO through 031 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Size (SilO, SIl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Bus Control Sig nals . . . . . . . . . . . . . . . . . . . . . . . External Cyc le Start (ECS) . . . . . . . . . . . . . . . . . . . . . . . . . . . Operand Cycle Start (OCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . Read M od i fyWrite Cyc le (RMC) . . . . . . . . . . . . . . . . . . . . . . Address Strobe (AS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Strobe (OS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read/Write (RIW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Buffer Enable (DB EN) . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer and Size Acknow ledge (DSACKO, DSACK1) . Cache Disable (C DIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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TABLE OF CONTENTS (Continued)

Paragraph Number 4.7 4.7. 1 4.7.2 4.7.3 4.8 4.8.1 4.8.2 4.8.3 4.9 4.9. 1 4.9.2 4.9.3 4.10 4.1 1 Page Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-4 4-4 4-4 4-4 4-4 4-4 4-5 4-5 4-5 4-5 4-5 4-6 4-6

Title I nterru pt Control S i g nals . . . . . . . . . . . . . . . . . I nterru pt Priority level (I PlO, I Pl1 , I Pl2) I nterru pt Pend ing (I PEN D) . . . . . . . . . . . . Autovector (AVEC) . . . . . . . . . . . . . . . . . . Bus Arbitration Signals . . . . . . . . . . . . . . . . . . Bus Req uest (BR) . . . . . . . . . . . . . . . . . . . Bus G rant (BG) . . . . . . . . . . . . . . . . . . . . . . Bus G rant Acknow ledge (BGACK) . . . . . . Bus Ex cept ion Control Signals . . . . . . . . . . . . Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . Halt (HALT) . . . . . . . . . . . . . . . . . . . . . . . . Bus Error (BERR) . . . . . . . . . . . . . . . . . . . . Clock (ClK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Summary . . . . . . . . . . . . . . . . . . . . . . . .

5.1 5.1 . 1 5 . 1 .2 5. 1 .3 5. 1 .4 5.2 5.2. 1 5.2.2 5.2.3 5.2.4 5.2.4. 1 5.2.4. 1 . 1 5.2.4. 1 .2 5.2.4. 1 .3 5.2.4. 1 .4 5.2.4. 1 .5 5.2.4.2 5.2.4.3 5.2.5 5.2.5. 1 5.2.5.2 5.2.5.3 5.2.5.4 5.2.6 5.2.7

Section 5 Bus Operation Operand Transfer Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynam i c Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M is a l i g n ment of B u s Transfers . . . . . . . . . . . . . . . . . . . . . . . . Effects of Dynamic Bus Sizing and Operand M isal ignment . Address, Size, and Data B u s Relationships . . . . . . . . . . . . . . B u s Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Cyc le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read-M od ify-Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Space Cyc les . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nterrupt Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nterru pt levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recog nition of I nterru pts . . . . . . . . . . . . . . . . . . . . . I nterrupt Acknow l edge Seq uence (l ACK) . . . . . . . . Spu rious I nterrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . lACK Generat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpo i nt Acknowledge Cyc le . . . . . . . . . . . . . . . . . . . Coprocessor Operations . . . . . . . . . . . . . . . . . . . . . . . . . Bus Error and Halt Operation . . . . . . . . . . . . . . . . . . . . . . . . . Bus Error Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Retry Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H alt Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double B u s Fau lts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitrat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5-2 5-2 5-1 0 5-1 4 5-1 6 5-1 8 5-1 8 5-22 5-22 5-26 5-26 5-26 5-27 5-27 5-31 5-31 5-31 5-34 5-34 5-34 5-35 5-39 5-39 5-41 5-42

TABLE OF CONTENTS (Continued)

Paragraph N umber 5.2.7.1 5.2.7.2 5.2.7.3 5.2.7.4 5.2.8 5.2.9 5.2.9.1 5.2.9.2 Page Number . .... . .... . ........... ........... . . . ........ ........... ........... . . . . . . . .... . . . . . . . . . . . . . . . . . . . 5-46 5-46 5-46 5-47 5-49 5-50 5-50 5-51

Title Request i n g the Bus . ....... . . . .. . ....... . Receivi n g the Bus G rant . . . . . . . . . . . . . . . . . . Acknowledgement of M astership . . . . . . . . . . Bus Arbitrat ion Control . . . . . . . . . . . . . . . . . . The Relat ionsh i p of DSACK, BERR, and HALT . . . Asynchronous versu s Synchronous Operation . . . Asynchronous Operation . . . . . . . . . . . . . . . . . Synchronous Operation . . . . . . . . . . . . . . . . . .

6.1 6. 1 . 1 6. 1 .2 6. 1 .3 6. 1 .4 6. 1 .5 6. 1 .6 6.2 6.2. 1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.3. 1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3. 1 0 6.3. 1 1 6.4 6.4.1 6.4.2 6.4.2 . 1 6.4.2.2 6.5

Section 6 Processing States Privilege States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use of Privilege States . . . . . . . . . . . . . . . . . . . . . . . . . . . Su pervisor States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Change of Privilege State . . . . . . . . . . . . . . . . . . . . . . . . . Address Space Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Proces s i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Except ion Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Processi n g Sequence . . . . . . . . . . . . . . . . . . . M u lt i ple Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Process i ng: Deta i l . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nstruction Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I l legal or U n i m plemented I nstructions . . . . . . . . . . . . . . Privilege V iolations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trac i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nterrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ret u rn From Exception . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Fau l t Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complet i n g the Bus Cyc le(s) . . . . . . . . . . . . . . . . . . . . . . Completing the Bus Cycl e(s) via Software . . . . . . . Completing the Bus Cycle(s) via RTE . . . . . . . . . . . M C68020 Exception Stack Frames . . . . . . . . . . . . . . . . . . . . .
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6-1 6-2 6-2 6-3 6-3 6-4 6-4 6-4 6-5 6-6 6-6 6-7 6-7 6-8 6-8 6-9 6-9 6-1 0 6-1 0 6-1 1 6-1 1 6-1 2 6-1 3 6-1 4 6-1 5 6-1 6 6-1 7 6-1 8 6-1 8 6-1 9 6- 1 9

TABLE O F CONTENTS (Continued)

Paragraph Number 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 Page N umber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6-20 6-20 6-21 6-22 6-23 6-24

Title N ormal Four Word Stack Frame . . . . . . . . . . . . . . . . . . Throwaway Four Word Stack Frame . . . . . . . . . . . . . . . N ormal S i x Word Stack Frame . . . . . . . . . . . . . . . . . . . Coprocessor M id-I nstruction Except ion Stack Frame Short B u s Cyc le Fault Stack Frame . . . . . . . . . . . . . . . Long Bus Cyc le Fault Stack Frame . . . . . . . . . . . . . . . . Stack Frame Summary . . . . . . . . . . . . . . . . . . . . . . . . . . Section 7 On-Chip Cache Memory Cache Des i g n and Operat ion . . . . . . . . . . . . . . . . On-Ch i p Cache Organ izat ion . . . . . . . . . . . . Cache Control . . . . . . . . . . . . . . . . . . . . . . . . Cache Control Register . . . . . . . . . . . . E - Enable Cache . . . . . . . . . . . . . . . . F - Freeze Cache . . . . . . . . . . . . . . . . . CE - Clear Entry . . . . . . . . . . . . . . . . . C - Clear Cache . . . . . . . . . . . . . . . . . . Cache Address Reg i ster . . . . . . . . . . . . . . . . . . . . Cache D i sable I n put . . . . . . . . . . . . . . . . . . . . . . . Cache I n itial ization . . . . . . . . . . . . . . . . . . . . . . . .

7.1 7. 1 . 1 7. 1 .2 7 . 1 .2.1 7 . 1 .2.2 7.1 .2.3 7 . 1 .2.4 7.1 .2.5 7.2 7.3 7.4

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7-1 7-1 7-2 7-2 7-3 7-3 7-3 7-3 7-3 7-4 7-4

Section 8 Coprocessor Interface Description I ntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 M C68000 Family Coprocessor I nterface Overview . . . . . . 8.2 I nterface Featu res . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2. 1 Concu rrent Cop rocessor Operat ion Support . . . . . . . 8.2.2 Cop rocessor I nstruct ion Format . . . . . . . . . . . . . . . . . 8.2.3 M68000 Coprocessor System I nterface . . . . . . . . . . . 8.2.4 M68000 Coprocessor Bus I nterface . . . . . . . . . . 8.2.4. 1 CPU Address Space . . . . . . . . . . . . . . . . . . . . . . . 8.2.4.2 Coprocessor I nterface Regi ster (CI R) Select ion 8.2.4.3 Coprocessor I nstruct i o n Types . . . . . . . . . . . . . . . . . . . . . . 8.3 Coprocessor General I nstructions . . . . . . . . . . . . . . . 8.3.1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3. 1 . 1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3. 1 . 2 Cond itional Coprocessor I nstructions . . . . . . . . . . . . 8.3.2 Branch On Coprocessor Cond ition I nstructions 8.3.2.1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2. 1 . 1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2. 1 . 2

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8-1 8-2 8-2 8-3 8-3 8-4 8-4 8-4 8-5 8-7 8-8 8-8 8-9 8-1 0 8-1 0 8-1 0 8-12

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Paragraph N umber Page Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8.3.2.2 Set On Coprocessor Cond ition . . . . . . . . . . . . . . . . . . . . . 8.3.2. 2 . 1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2.2.2 8.3.2.3 Test Coprocessor Condition, Decrement and Branch . . 8.3.2.3.1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2.3.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2.4 Trap On Coprocessor Cond ition . . . . . . . . . . . . . . . . . . . . 8.3.2.4. 1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2.4.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Coprocessor Contex t Save and Context Restore . . . . . . . . . . 8.3.3. 1 Coprocessor Context Save . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3. 1 . 1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3. 1 .2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3.2 Coprocessor Contex t Restore . . . . . . . . . . . . . . . . . . . . . . 8.3.3. 2 . 1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3.2.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3.3 Coprocessor I nternal State Frames . . . . . . . . . . . . . . . . . 8.3.3.4 Coprocessor Format Words . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3.4.1 Em pty/Reset Format Word . . . . . . . . . . . . . . . . . . . . . 8.3.3.4.2 Not Ready Format Word . . . . . . . . . . . . . . . . . . . . . . . 8.3.3.4.3 I nva l i d Format Words . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3.4.4 Valid Format Words . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Coprocessor I nterface Reg i ster (CI R) Set . . . . . . . . . . . . . . . . . . . . 8.4. 1 Response C I R ($00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Control ($02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 Control C I R ($04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4 Restore C I R ($06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.5 Operation Word C I R ($08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.6 Command C I R ($OA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.7 Cond ition C I R ($OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.8 Operand C I R ($1 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.9 Reg ister Select C I R ($1 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4. 1 0 I nstruction Address C I R ($1 8) . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4. 1 1 Operand Address C I R ($1 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Coprocessor Response Prim it ives I nt roduction . . . . . . . . . . . . . . . 8.5. 1 Coprocessor Response Prim itive Format . . . . . . . . . . . . . . . . Sca n PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.2 8.6 Coprocessor Response Pri m i t ive Set Description . . . . . . . . . . . . . 8.6. 1 B u sy 8.6. 1 . 1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6. 1 .2
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81 2 81 2 81 3 81 3 81 3 81 4 81 4 81 4 81 5 81 6 81 6 8 1 6 81 7 81 8 81 8 81 9 820 821 821 822 822 823 823 823 823 824 824 824 824 824 824 825 825 825 825 826 827 827 828 828 828

TABLE OF CONTENTS (Continued)

Paragraph N umber 8.6.2 8.6.2. 1 8.6.2.2 8.6.3 8.6.3. 1 8.6.3.2 8.6.4 8.6.4. 1 8.6.4.2 8.6.5 8.6.5. 1 8.6.5.2 8.6.6 8.6.6. 1 8.6.6.2 8.6.7 8.6.7 . 1 8.6.7.2 8.6.8 8.6.8. 1 8.6.8.2 8.6.9 8.6.9. 1 8.6.9.2 8.6. 1 0 8.6. 1 0. 1 8.6. 1 0.2 8.6. 1 1 8.6. 1 1 . 1 8.6. 1 1 .2 8.6. 1 2 8.6. 1 2. 1 8.6. 1 2.2 8.6. 1 3 8.6. 1 3. 1 8.6. 1 3.2 8.6. 1 4 8.6. 1 4 . 1 8.6. 1 4. 2 8.6. 1 5 8. 6. 1 5. 1 8.6. 1 5.2 Page N umber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. . . .. .. .. .. .. .. .. .. .. . . . . .. .. .. . . .. .. .. .. .. . . .. .. . . .. .. . . . . .. .. .. .. . . .. .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. . . .. .. .. .. .. .. .. .. .. . . .. .. .. .. . . .. .. .. .. .. .. .. .. .. .. .. . . . . . . .. .. .. . . .. .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 829 8-29 8-30 8-30 831 831 8-31 831 8-31 831 . 8-32 832 8-32 8-32 8-33 8-33 8-34 8-35 8-35 8-35 8-36 8-36 8-37 837 8-37 8-37 8-38 8-38 8-38 838 8-38 8-39 8-39 8-39 8-39 8-40 8-40 8-40 8-41 8-42 842

Title N u l l (No Operands) . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervisor Check . . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Operat ion Word . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer from I nstruction Stream . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eval uate and Transfer Effective Address . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eval uate Effective Address and Transfer Data . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write to Previously Eva luated Effective Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Take Address and Transfer Data . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer To/From Top of Stack . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer S i n g l e M a i n Processor Reg i ster . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer M a i n Processor Control Reg ister . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer M u lt i p le M a i n Processor Reg i sters . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tra nsfer M u lt i p l e Coprocessor Regi sters . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Status Regi ster and ScanPC . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Paragraph Number 8.6. 1 6 8.6. 1 6. 1 8.6. 1 6. 1 . 1 8.6. 1 6. 1 .2 8.6. 1 6.2 8.6. 1 6.2.1 8.6. 1 6.2.2 8.6. 1 6.3 8.6. 1 6.3.1 8.6. 1 6.3.2 8.7 8.8 8.8 . 1 8.8. 1 . 1 8.8. 1 .2 8.8.1 .3 8.8. 1 .4 8.8. 1 .5 8.8.2 8.8.2 . 1 8.8.2.2 8.8.2.3 8.8.2.4 8.8.2.5 8.8.2.6 8.8.2.7 8.8.2.8 8.8.3 8.9 8. 1 0 Page Number 8-43 8-43 8-43 8-43 8-45 8-45 8-45 8-46 8-46 8-46 8-47 8-48 8-48 8-48 8-49 8-50 8-50 8-50 8-50 8-5 1 8-5 1 8-52 8-53 8-53 8-54 8-54 8-55 8-55 8-56 8-56

Title

Ex cept ion Processing Req uest Primitives . . . . . . . . . . . . . . . . . . . Take Pre-I nstruct ion Ex cept ion . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Take M i d-I nstruct ion Ex cept ion . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Take Post-I nstruct ion Ex cept ion . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Classificatons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ex cept ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Detected Ex cept ions . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Detected Protocol Violations . . . . . . . . . . . . . . Coprocessor Detected I l legal Command or Cond ition Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . Coprocessor Data Processing Ex cept ions . . . . . . . . . . . . . . Coprocessor System Related Ex cept ions . . . . . . . . . . . . . . . Format Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M a i n Processor Detected Ex cept ions . . . . . . . . . . . . . . . . . . . . . . Protocol Violat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-Li ne Emu lator Ex cept ions . . . . . . . . . . . . . . . . . . . . . . . . . . Privi lege Violat i ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cpTRAPcc I nstruction Traps . . . . . . . . . . . . . . . . . . . . . . . . . . Trace Ex cept ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nterru pts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address and Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M a i n Processor Detected Format Errors . . . . . . . . . . . . . . . . . . . . Coprocessor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor I nstruction Format Summary . . . . . . . . . . . . . . . . . . . . . . Coprocessor Response Primit ive Format Sum mary . . . . . . . . . . . Section 9 I nstruction Execution T i m i n g Estimation Factors . . . . . . . . . . . . I n st ruction Cache and Prefetch . . . . Operand M isal i g n ment . . . . . . . . . . . . Concu rrency . . . . . . . . . . . . . . . . . . . . Overlap . . . . . . . . . . . . . . . . . . . . . . . . . I nstruction Stream T i m i n g Ex am ples I nstruction T i m i n g Tables . . . . . . . . . . . . . Fetch Effective Add ress . . . . . . . . . . . Timing ....... ....... ....... . ...... . . .. . .. .... . . . ....... .......

9.1 9.1 . 1 9. 1 .2 9. 1 .3 9. 1 .4 9. 1 .5 9.2 9.2.1

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TABLE O F CONTE NTS (Concluded)

Paragraph Number 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 9.2. 1 0 9.2. 1 1 9.2. 1 2 9.2. 1 3 9.2. 1 4 9.2. 1 5 9.2. 1 6 9.2 . 1 7 9.2 . 1 8 Title Fetch I m med iate Effective Address . . . . . . Calcu late Effective Address . . . . . . . . . . . . Calcu late I m mediate Effective Address . . . J u m p Effective Address . . . . . . . . . . . . . . . . MOVE I nstruction . . . . . . . . . . . . . . . . . . . . . Special Pu rpose MOVE I nstruction . . . . . . . Arithmet i c/Log ical Operat ions . . . . . . . . . . I m mediate Arithmetic/Log ical Operations . B i nary Coded Dec imal Operations . . . . . . . S i ngle Operand I nstructions . . . . . . . . . . . . Shift/Rotate I nstruct ions . . . . . . . . . . . . . . . Bit Manipu lation I nstructions . . . . . . . . . . . Bit Field Manipu lation I nstructions . . . . . . Condit ional B ranch I nstructions . . . . . . . . . Control I nstructions . . . . . . . . . . . . . . . . . . . Ex cept ion Related I nstructions . . . . . . . . . . Save and Restore Operat ions . . . . . . . . . . . .. . ... . . . ... ... ... ... ... ... ... ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . .. . .... .. . . .... .... .... .... .... .... .... .... .... ... . .... .... .... .... . . . . . . . . . . . . . . . . . ... . .... .... .... .... .... .... .... .... .... .... .... . . . . .... .... .... .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page N umber 9-1 1 9-1 3 9-1 3 9-1 5 9-1 5 9-21 9-22 9-22 9-23 9-24 9-24 9-25 9-26 9-26 9-27 9-28 9-28

1 0. 1 1 0.2 1 0.3 1 0.4 1 0.5 1 0.6 1 0.7

Section 1 0 Electrical Specifications Max i m u m Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics - PGA Package . . . . . . . . . . . . Power Considerat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Elect rical Characteristics . . . . . . . . . . . . . . . . . . . . . . AC Electrical Characteristics - C l ock I n put . . . . . . . . . . AC E lectrical Characterist ics - Read and Write Cyc les AC E lectrical Characteristics - Typical Capacitance Derat i n g C u rves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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1 0-1 1 0-1 1 0-1 1 0-2 1 0-3 1 0-4 1 0-6

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1 1 .1 1 1 .2 A B C D E

Section 1 1 Ordering Information and Mechanical Data Standard M C68020 Ordering I nformat ion . . . . . . . . . . . . . . . . . . . . . . . Package Dimensions and P i n Ass i g n ment . . . . . . . . . . . . . . . . . . . . . . APPEN DICES Condition Codes Com putat ion . . . . . . . . . I nstruction Set . . . . . . . . . . . . . . . . . . . . . . . I nstruction Format Summary . . . . . . . . . . Advanced Topics . . . . . . . . . . . . . . . . . . . . . M C68020 Extensions to M68000 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 -1 1 1 -2 A-1 B-1 C-1 D-1 E-1

xiii

LIST O F ILLUSTRATIONS
Figure Number 1 -1 1 -2 1 -3 1 -4 1 -5 2-1 2-2 2-3 2-4 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-1 0 5-1 1 5-1 2 5-1 3 5-1 4 5-1 5 5-1 6 5-1 7 5-1 8 5-1 9 5-20 5-21 5-22 5-23 5-24 5-25 Page Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -2 1 -3 1 -3 1 -4 1 -9 2-3 2-3 2-5 2-6 4-1 5-1 5-2 5-3 5-4 5-6 5-7 5-8 5-9 5-1 0 5-1 1 5-1 2 5-1 3 5-1 4 5-1 5 5-1 7 5-1 8 5-1 9 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-28

Title M C68020 B lock Diagram . . . . . . . . . . . . . . . . . User Progra m m i n g M odel . . . . . . . . . . . . . . . . Supervisor Prog ram m i n g M odel Su pplement Status Register . . . . . . . . . . . . . . . . . . . . . . . . . M C68020 Pipe l i ne . . . . . . . . . . . . . . . . . . . . . . .

Memory Operand Address ing . . . . . . . . . . . . . . . . . . . . Memory Data Organizat ion . . . . . . . . . . . . . . . . . . . . . . I nstruction Word G eneral Format . . . . . . . . . . . . . . . . . S i n g l e-Effect ive-Address I nstruction Operat ion Word

Fu nctional Signal G roups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relationship Between Ex ternal and I nternal Signals . . . . . . . . . Sample Wi ndow M C68020 I nterface to Various Port Sizes . . . . . . . . . . . . . . . . . . . I nternal Operand Representation . . . . . . . . . . . . . . . . . . . . . . . . . Ex ample of Long Word Transfer to Word Bus . . . . . . . . . . . . . . . Long Word Operand Write Timing ( 1 6- B it Data Port) . . . . . . . . . . Ex ample of Long Word Transfer to Byte Bus . . . . . . . . . . . . . . . . Long Word Operand Write Timing (8-Bit Data Port) . . . . . . . . . . . M isaligned Long Word Transfer to Word Bus Ex ample . . . . . . . M isaligned Long Word Transfer t o Word Bus . . . . . . . . . . . . . . . Ex ample of M isaligned Word Transfer to Word Bus . . . . . . . . . . M isaligned Word Transfer t o Word B u s . . . . . . . . . . . . . . . . . . . . M isalig ned Long Word Transfer t o Long Word B u s . . . . . . . . . . . M isalig ned Write Cycles to 32-Bit Data Port . . . . . . . . . . . . . . . . Byte Data Select Generat ion for 1 6- and 32-Bit Ports . . . . . . . . . Long Word Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . Long-Word Read Cycle Timing (32-Bit Data Port) . . . . . . . . . . . . Byte Read Cyc le Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte and Word Read Cycle Timing (32-Bit Data Port) . . . . . . . . . Write Cyc le Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte and Word Write Cycle Timing (32-Bit Data Port) . . . . . . . . . Read-Mod ify-Write Cyc le Flowchart . . . . . . . . . . . . . . . . . . . . . . . Read-Mod ify-Write Cyc le Timing (32-Bit Port, CAS I nstruction) . M C68020 CPU-Space Address Encod i n g . . . . . . . . . . . . . . . . . . . I nterrupt Acknowledge Sequence Flowchart . . . . . . . . . . . . . . . .
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xiv

LIST O F I L LUSTRATIONS (Continued)

Figure Number 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 7-1 7-2 7-3 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-1 0 Page Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5-30 5-31 5-32 5-33 5-35 5-36 5-37 5-38 5-40 5-41 5-4 3 5-44 5-45 5-47 5-48 6-6 6-1 7 6-20 6-20 6-21 6-21 6-22 6-23 6-24 7-2 7-3 7-3 8-3 8-5 8-6 8-6 8-7 8-8 8-9 8-1 1 8-1 1 8-1 1

Title I nterrupt Acknow l edge Cyc le Timing . . . . . . . . . . . . . . . . . . . . . Autovector Operat ion T i m i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . M C68020 B reakpo i nt Operat ion Flow . . . . . . . . . . . . . . . . . . . . . Breakpo i nt Acknow ledge Cyc le T i m i n g (Opcode Retu rned) . . . Breakpo i nt Acknowledge Cyc le T i m i n g (Ex ception S i g nal led) B u s Error Timing (Ex ception Taken) . . . . . . . . . . . . . . . . . . . . . . Delayed B u s Error (Ex ception Taken) . . . . . . . . . . . . . . . . . . . . . Delayed B u s Cyc le Retry T i m i n g . . . . . . . . . . . . . . . . . . . . . . . . . Retry Operat ion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H alt Operation T i m i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Operat ion T i m i n g . . . . . . . . . . . . . . . . . . . . . . . . Processor Generated Reset Operation . . . . . . . . . . . . . . . . . . . . B u s A rbitration F l owchart for S i ng le Req uest . . . . . . . . . . . . . . B u s A rbitration Operat ion T i m i n g . . . . . . . . . . . . . . . . . . . . . . . . B u s Arbitrat ion State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . B u s Arbitrat ion (Bus I nactiv e) . . . . . . . . . . . . . . . . . . . . . . . . . . . Ex ception Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spec ial Status Word (SSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format $0 - Four Word Stack Frame . . . . . . . . . . . . . . . . . . . Format $1 - Th rowaway Four Word Stack Frame . . . . . . . . . Format $2 - Six Word Stack Frame . . . . . . . . . . . . . . . . . . . . . Format $9 - Coprocessor M id-Instruction Except ion Stack Frame (1 0 Words) . . . . . . . . . . . . . . . . . . . . . . . . . . . Format $A - Short Bus Cyc le Fau lt Stack Frame (1 6 Words) Format $B - Long B u s Cyc le Fau l t Stack Frame (46 Words) Stack Frame Format Def i n itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M C68020 O n-C h i p Cache Organ izat ion . . . . . . . . . . . . . . . . . . . . . . . . . Cache Control Reg ister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Address Reg i ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F- Line Coprocessor I nstruction Operation Word . . . . . . . . . . . . . . . . . MC68020 CPU Space Address E ncod i ngs . . . . . . . Coprocessor I nterface Reg i ster Set Map Coprocessor Address Map i n MC68020 CPU Space M68000 Coprocessor I nterface Signal Usage Coprocessor G eneral I nstruction Format (cpG EN) Coprocessor I nterface Protocol for General Category I nstructions Coprocessor I nterface Protocol for Conditional Category I nstruct ions Branch on Coprocessor Cond ition I nstruction (cpBccoW) B ranch on Coprocessor Condition I nstruction (cp Bcco L)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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xv

LIST O F ILLUSTRATIONS (Continued)

Figure Number 8-1 1 8- 1 2 8- 1 3 8- 1 4 8- 1 5 8-1 6 8- 1 7 8-1 8 8- 1 9 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 8-28 8-29 8-30 8-31 8-32 8-33 8-34 8-35 8-36 8-37 8-38 8-39 8-40 8-41 8-42 8-43 8-44 8-45 8-46 9-1 9-2 9-3 Page N umber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8-1 3 8-1 5 8-1 6 8-1 7 8-1 8 8-1 9 8-20 8-23 8-24 8-25 8-26 8-28 8-29 8-30 8-31 8-32 8-32 8-33 8-35 8-36 8-37 8-38 8-38 8-39 8-40 8-40 8-41 8-42 8-43 8-44 8-45 8-45 8-46 8-46 8-56 9-2 9-3 9-4

Title Set on Coprocessor Cond ition (cpScc) . . . . . . . . . . . . . . . . . . . . . . . . . Test Coprocessor Condition, Decrement and Branch I nstruction Format (cpD Bcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trap o n Coprocessor Condition (cpTRAPcc) . . . . . . . . . . . . . . . . . . . . Coprocessor Context Save I n struction Format (cpSAVE) . . . . . . . . . Coprocessor Context Save I n struct ion Protocol . . . . . . . . . . . . . . . . . Coprocessor Context Restore I nstruct ion Format (cpR ESTORE) . . . Coprocessor Contex t Restore I nstruct ion Protocol . . . . . . . . . . . . . . Coprocessor State Frame Format i n Memory . . . . . . . . . . . . . . . . . . . Control C I R Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cond ition C I R Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operand A l i g n ment for Operand C I R Accesses . . . . . . . . . . . . . . . . . Coprocessor Response Primit ive Format . . . . . . . . . . . . . . . . . . . . . Busy Pri m i t ive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N u l l Pri m i t ive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervisor Check Primit ive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Operat ion Word P r i m itive Format . . . . . . . . . . . . . . . . . . . . . Transfer From I nstruct ion Stream Prim itive Format . . . . . . . . . . . . . . Eval uate and Transfer Effective Address Primitive Format . . . . . . . . Eval uate Effect ive Add ress and Transfer Data Prim it ive Format . . . Write to Previously Eva luated Effect ive Address Primit ive Format . . Take Address and Transfer Data Primit ive Format . . . . . . . . . . . . . . . Transfer S i n g le Top of Stack Primit ive Format . . . . . . . . . . . . . . . . . . Transfer M a i n Processor Reg i ster Primit ive Format . . . . . . . . . . . . . . Transfer M a i n Processor Control Reg ister Primit ive Format . . . . . . . Transfer M u lti ple M a i n Processor Reg i sters Primit ive Format . . . . . Reg i ster Select Mask Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer M u lt i ple Coprocessor Reg isters Pri m i t ive Format . . . . . . . . Operand Format Transfer M u lt i ple Coprocessor Reg i sters to - (An) Transfer Stat us Reg i ster and Scan PC Primit ive Format . . . . . . . . . . Pre-I nstruct ion Ex cept ion Pri m i t ive Format . . . . . . . . . . . . . . . . . . . . . MC68020 Pre-I nst ruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . Take M i d-I nstruction Ex cept ion Primit ive Format . . . . . . . . . . . . . . . . MC68020 M i d-I nstruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . Take Post-I nstruct ion Ex cept ion Primit ive Format . . . . . . . . . . . . . . M C68020 Post-I nst ruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . Coprocessor I nstruct ion Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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S i m u ltaneous I nstruction Ex ecution . . . . . . . . . . . . . . . . . . . . . . . . . . . I nstruction Ex ecut ion for I nstruct ion Timing Pu rposes . . . . . . . . . . . . Processor Activity for Ex ample 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xvi

LIST O F I L LUSTRATIONS (Concluded)

Figure N umber 9-4 9-5 9-6 1 0- 1 1 0-2 1 0-3 1 0-4 1 0-5 1 0-6 1 0-7 1 0-8 1 0-9 1 0-1 0 1 0-1 1 1 0- 1 2 1 0-1 3 Page Number 9-6 9-6 9-7
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Title Processor Activity for Example 2 Processor Activity for Example 3 Processor Activity for Example 4 RESET Test Load HALT Test Load . . . . . . . . . . . Test Loads . . . . . . . . . . . . . . . Clock I n put T i m i n g D iag ram Read Cyc le T i m i n g Diagram
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Write Cyc le T i m i n g Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitrat ion T i m i n g Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Capac ita nce Derat i n g Curve . . . . . . . . . . . . . . . . . OS, AS, I PE N D, and BG Capac i tance Derat i n g Curve . . . . . DBEN Capacitance Derat i n g Cu rve . . . . . . . . . . . . . . . . . . . ECS and OCS Capac itance Derating Curve . . . . . . . . . . . . . R/W, FC, SIZO-SIZ1 , a n d RMC Capac itance Derat i n g C u rve Data Capacitance Derat i n g C u rve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 0-2 . 1 0-2 . 1 0-3 . 1 0-3 . Foldout 1 . Foldout 2 . Foldout 3 . 1 0-6 1 0-6 . 1 0-7 . 1 0-7 . 1 0-8 . 1 0-8 .

xvii

LIST O F TABLES
Table Number 1 -1 1 -2 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-1 0 4-1 4-2 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 6-1 6-2 6-3 6-4 6-5 Page Number 1 -5 1 -6 2-1 9 2-20 2-20 3-2 3-3 3-4 3-5 3-5 3-6 3-6 3-7 3-8 3-9 4-2 4-6 5-4 5-4 5-5 5-5 5-1 4 5-1 6 5-27 5-49 6-4 6-5 6-8 6-1 2 6-1 3

Title Addressing M odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nstruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effective Address Specification Formats . . . . . . . . . . . . . . . . . . . . . . . I S-IllS Memory I nd i rection E ncodings . . . . . . . . . . . . . . . . . . . . . . . . . . Effective Address E ncoding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . Data M ovement Operations . . . . . . I nteger Arithmetic Operations . . . . Log ical Operations . . . . . . . . . . . . . Shift and Rotate Operations . . . . . Bit Manipulation Operations . . . . . Bit Field Operat ions . . . . . . . . . . . . B i na ry Coded Decimal Operations Program Control Operations . . . . . System Control Operat ions . . . . . . M u ltiprocessor Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fu nction Code Assig n ments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sig nal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIZE Output E ncod i ng s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Offset E ncodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M C68020 I nternal to External Data Bus M u lti plexor . . . . . . . . DSACK Codes and Res u lts . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory A l ig n ment and Port Size I n f l uence on Bus Cyc les . . Data B u s Activity for Byte, Word, and Long Word Ports . . . . . I nterrupt Control Line Status for Each Requested I nterrupt Corresponding I nterru pt Mask Levels . . . . . . . . . . . . a = B E R R, and H A LT Assertion Resu lts . . . . . . . . . . . . . . DSACK, Address Space Encod i ng s . . . . . Exception Vector Assi g nments . Exception Groups . . . . . . . . . . . . Privi l eged I nstructions . . . . . . . . Tracing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... ... .. .... . ..... .... . .... . Level .... . ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

.. .. . . . . . . . . . .

xviii

LIST O F TABLES (Concluded)

Table Number 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 9-3 Page Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 5 8-21 8-30 8-33 8-39 8-52 9-8 9-1 0 9-1 0

Title cpTRAPcc Opmode E ncod i ngs . . . . . . . . . . . . . . . . Coprocessor Format Word Encodings . . . . . . . . . . N u l l Coprocessor Response Primitive Encod i ngs . Valid Effective Address Codes . . . . . . . . . . . . . . . . Main Processor Control Reg i ster Selector Codes . Exceptions Related to Primitive Processing . . . . .

Example I nstruction Stream Execution Comparison . . . . . . . . . . . . . . I nstruction Timings for Ti ming Tables . . . . . . . . . . . . . . . . . . . . . . . . . . Observed I n struction Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xix/xx

S ECTI ON 1 I NTRODUCTION
T h e M C68020 is the first f u l l 32-bit im plementation o f t h e M68000 Family of micro processors from M otorola. Using V LSI tec h nology, the M C68020 is im plemented with 32-bit registers and data paths, 32-bit addresses, a rich instru ction set, and versatile ad d ressing modes. The M C68020 is object code com patible with the earlier members of the M68000 Family and has the added featu res of new addressing modes in su pport of high level lang uages, an on-chip instruction cache, and a flexible coprocessor i nterface with f u l l I EE E floating point su pport (the M C68881 ) . A lso, the internal operations of this microprocessor are designed to operate in paral lel, allowing m u l t i ple instructions to be executed concur rent ly. The execution time of an instruction can be completely absorbed by the execution time of su rrou nding instructions for a net execution time of zero c lock periods. The asynchronous bus structure of the M C68020 utilizes a non-multip lexed bus with 32 bits of address and 32 bits of data. The processor supports a dynamic bus sizing mechanism that al lows the processor to transfer operands to or from external devices w hile automatically determ i n i n g device port size on a cyc le-by-cycle basis. The dynamic bus interface al lows for s i mple, hig h ly effic ient access to devices of differing data bus widths, in addition to eliminating all data alig n ment restrictions. The resources available to the MC68020 u ser consist of the following: Virtual Memory/M achine Su pport Sixteen 32-Bit General-Pu rpose Data and Address Registers Two 32-Bit Supervisor Stack Pointers 32-Bit Program Counter Five Special Pu rpose Control Registers 4 Gigabyte Direct Addressing Range Two Processor Speeds: 12 and 16 M Hz 1 8 Addressing M odes Memory Mapped I/O Coprocessor I nterface H igh Performance On-Chip I nst ruction Cache 32-Bit Upgraded and New I nst ructions Operations on Seven Data Types Com plete Floating-Point Su pport via the MC68881 Coprocessor A block diagram of the M C68020 is shown in Figure 1 - 1 . The major blocks depicted operate in a h ig h ly i ndependent fashion that maximizes concu rrency of operation while managing t he essential synchronizat ion of instruction exec ution and bus operation. 1 -1


Sequencer Control Unit Instruction Prefetch and Decode

Address Bus

Execution Unit

Controller Instruction Cache

Bus Control Data Bus

Figure 1 1 . M C68020 Block Diagram The bus controller loads instructions from the data bus into the decode u n it and the on chip cache. The seq uencer and control u n it provide overal l chip control, managing the in ternal buses, registers, and fu nctions of the execution u n it. As shown in the program ming models (Fig u res 1 -2 and 1 -3), the M C68020 has 16 32bit general-pu rpose registers, a 32-bit program cou nter, a 1 6bit status register, a 32-bit vec tor base register, two 3bit alternate fu nction code registers, and two 32bit cache handl ing (address and control) registers. Registers 00-07 are used as data registers for bit and bit field (1 to 32 bits), byte (8-bit), word (1 6-bit), long word (32-bit), and quad word (64-bit) operations. Registers AO-A6 and the u ser, interru pt, and master stack pOinters are ad d ress registers that may be u sed as software stack pointers or base address registers. I n addition, the address registers may be u sed for word and long word operations. A l l of the 16 (00-07, AOA7) registers may be u sed as index registers. The vector base register is u sed to determine the l ocation of the exception vector table in memory to s u pport m u ltiple vector tables. The alternate function code registers al l ow the su pervisor to access any address space. The cache registers (control - CACR; address - CAAR) al low software manipulation of the on-chip instruction cache. Control and statu s accesses to the instruction cache are provided by the cache control register (CACR), w hile the cache address register (CAAR) holds the address for cache control fu nctions w hen required. The status register (Fig u re 1 4) contains the interru pt priority mask (three bits) as wel l as the condition codes: extend (X), negative (N), zero (Z), overflow (V), and carry (C). Addi tional control bits indicate t hat the processor is in the trace mode (T1 and TO), s u per visor/user state (8), and master/interrupt state (M).

1 -2

31

16 15

87

DO D1 D2 D3 D4 D6 D7
D5

Data Registers

31

16 15

AO A1 A2 A3 A4 A5 A6

Address Registers

31 31

16 15

0 0

I A7 IUSP) User Stack Pointer

Program Counter Condition Code Register

= >_ = _'r"----..:,I CCR

Figure 1 2. User Programming Model

15

I PC

LI LI

31 31

___ _____ ____

---I ____________ ---.J

1615

____________

_ ---I ___________

16 15

15

87

---.JI A7 " IMSP)

0
0

I A7 ' liSP) Interrupt Stack Pointer

Master Stack Pointer

31
r

ICCR)

I SR

Status Register Alternate Function Code Registers

I- - L.

31

31

2 a SFC DFC
0
0 0

I VBR Vector Base Register

31

I CACR Cache Control Register

I CAAR Cache Address Register

Figure 1 3. Supervisor Programming Model Supplement 1 3


15 14 13

-------- --------12 11 10 9
8

System Byte

User Byte (Condition Code Register)

5 4 3 2

Supervisor/User State Masterllnterrupt State

Figure 1 4. Status Register

Zero Overflow

Carry

1 .1 DATA TYPES AND ADDRESSI NG MODES Seven basic data types are su pported. These data types are: Bits B i t Fields (Field of consecu tive bits, 1 32 bits long) BCD Digits (Packed: 2 dig its/byte, U n packed: 1 digit/byte) Byte I ntegers (8 bits) Word I ntegers (1 6 bits) Long Word I n tegers (32 bits) Quad Word I n tegers (64 bits) In addition, operations on other data types such as memory addresses, status word data, etc., are supported in the i nstruction set. The coprocessor mechanism a l l ows direct sup port of floating-point operat ions with the M C68881 floating-point coprocessor, as well as specia l ized u ser-defined data types and fu nctions. The 18 addressing modes, shown i n Table 1 1 , incl ude nine basic types: Register Di rect Register I ndirect Register I nd i rect with I ndex Memory I nd i rect Program Counter I ndirect with Disp lacement Program Counter I ndirect with I ndex Program Counter Memory I ndirect Absolute I m mediate I ncl uded in the register indirect addressing modes are t he capabilities to postincrement, predecrement, offset, and index. The program counter re lative mode also has index and offset capab i l ities. Both modes are extended in the M C68020 to provide indirect reference throu g h memory. I n addition to t hese addressing modes, many instructions im pl icitly specify the use of the condition code register, stack pointer, and/or program counter. 1 -4

Table 1 -1 . Addressing Modes

Addressing Modes Syntax Register Direct Data Register Direct Dn Address Register Direct An Register Indirect Address Register Indirect IAnl Address Register Indirect with Postincrement IAnl + Address Register Indirect with Predecrement - IAnl Address Register Indirect with Displacement Id1 6,Anl Register Indirect with Index Ids,An,Xnl Address Register Indirect with Index IS-Bit Displacementl Ibd,An,Xnl Address Register Indirect with Index IBase Displacement! Memory Indirect II bd,Anl.Xn,odl Memory Indirect Post-Indexed Ilbd,An,Xnl.odl Memory Indirect Pre-Indexed Id 16 ,PCI Program Counter Indirect with Displacement Program Counter Indirect with Index Ids,PC,Xnl PC Indirect with Index IS-Bit Displacementl Ibd,PC,Xnl PC Indirect with Index IBase Displacement! Program Counter Memory Indirect Ilbd,PCI.Xn,odl PC Memory Indirect Post-Indexed Ilbd,PC,Xnl.odl PC Memory Indirect Pre-Indexed Absolute Ixxxl.W Absolute Short Ixxxi. L Absolute Long #<data> Immediate NOTES: Dn Data Register, DO-D7 An Address Register, AO-A7 dS , d 16 A twos-complement. or sign-extended displacement; added as part of the effective address calculation; size is S or 16 bits Id 16 and dS are 16- and S-bit displacementsl; when omitted, assemblers use a value of zero. Xn Address or data register used as an index register; form is Xn.SIZE* SCALE, where SIZE is .W or .L lindicates index register sizel and SCALE is 1 , 2, 4, or S lindex register is multiplied by SCALEI; use of SIZE and/or SCALE is optional. bd A twos-complement base displacement; when present, size can be 16 or 32 bits., ad Outer displacement, added as part of effective address calculation after any memory indirection; use is optional with a size of 16 or 32 bits. PC Program Counter < data> Immediate value of 8, 16, or 32 bits I Effective address I I Use as indirect address to long word address.
= = = = = =

= =

1 .2 I NSTRUCTION SET OVERVIEW The MC68020 instruction set is show n i n Table 1 -2. Special emphasis has been placed on the i n st ructio n s u pport of structured high-leve l languages and sophisticated operating systems, Each inst ruction, with few exceptions, operates on bytes, words, and long words and most instructions can u se any of the 18 addressing modes.

1 -5

emonic Description ABCD Add Decimal with Extend ADD Add ADDA Add Address ADDI Add Immediate ADDQ Add Quick ADDX Add with Extend AND Logical AND ANDI Logical AND Immediate ASL, ASR Arithmetic Shift Left and Right Branch Conditionally Bcc BCHG Test Bit and Change Test Bit and Clear BClR BFCHG Test Bit Field and Change BFCLR Test Bit Field and Clear Signed Bit Field Extract BFEXTS BFEXTU Unsigned Bit Field Extract BFFFO Bit Field Find First One Bit Field Insert BFINS BFSET Test Bit Field and Set BFTST Test Bit Field BKPT Breakpoint BRA Branch BSET Test Bit and Set BSR Branch to Subroutine Test Bit BTST Call Module CALLM Compare and Swap Operands CAS Compare and Swap Dual Operands CAS2 Check Register Against Bound CHK Check Register Against Upper and CHK2 Lower Bounds Clear CLR Compare CMP Compare Address CMPA Compare Immediate CMPI Compare Memory to Memory CMPM Compare Register Against Upper and CMP2 Lower Bounds DBcc Test Condition, Decrement and Branch DIVS, DIVSL Signed Divide DIVU, DIVUL Unsigned Divide EOR Logical Exclusive OR EORI logical Exclusive OR Immediate Exchange Registers EXG EXT,EXTB Sign Extend ILLEGAL Take Illegal Instruction Trap Jump JMP Jump to Subroutine JSR Load Effective Address LEA Link and Allocate LINK LSL, LSR Logical Shift Left and Right Move MOVE MOVEA Move Address MOVE CCR Move Condition Code Register MOVE SR Move Status Register MOVE USP Move User S tack Pointer Move Control Register MOVEC MOVEM Move Multiple Registers MOVEP Move Peripheral Move Quik MOVEO Move Alternate Address Space MOVES

Mn

Table 1 2. Instruction Set Summary

MULS MULU NBCD NEG NEGX NOP NOT OR ORI PACK PEA RESET ROL, ROR ROXL, ROXR RTD RTE RTM RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPcc TRAPV TST UNLK UNPK cpBcc cpDBcc cpGEN cpRESTORE cpS AVE cpScc cpTRAPcc

Mnemonic

Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend No Operation Logical Complement Logical Inclusive OR Logical Inclusive OR Immediate Pack BCD Push Effective Address Reset External Devices Rotate Left and Right Rotate with Extend Left and Right Return and Deallocate Return from Exception Return from Module Return and Restore Codes Return from Subroutine Subtract Decimal with Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words Test Operand and Set Trap Trap Conditionally Trap on Overflow Test Operand Unlink Unpack BCD Branch Conditionally Test Coprocessor Condition, Decrement, and Branch Coprocessor General Instruction Restore Internal State of Coprocessor Save Internal State of Coprocessor Set Conditionally Trap Conditionally

Description

COPROCESSOR INSTRUCTIONS

1 6

1 .3 VI RTUAL M EMO RY/MAC H I N E CONCEPTS The f u l l addressing range of the M C68020 is 4 gigabytes (4,294,967,296). H owever, most M C68020 systems i m p lement a smaller physical memory. N onetheless, by using virtual memory techniques, the system can be made to appear to have a full 4 g i gabytes of physical memory avai lable to each user program. These tec h n iq ues have been used for many years i n large mai nframe computers and more recently i n m i n icomputers. With the M C68020 (as with the M C6801 0 and M C6801 2), virtual memory can be f u l ly supported in microprocessorbased systems. In a virtual memory system, a u ser program can be w ritten as though it has a large amount of memory avai lable to it w hen actual ly, o n ly a smal ler amount of memory is physically present i n the system. In a s i m i lar fashion, a system can be designed i n such a manner as to al low user programs to access other types of devices that are not physi cally present in the system such as tape drives, d i sk drives, printers, or term inals. With proper software emu lation, a physical system can be made to appear to a u ser program as any other M68000 computer system and the program may be g iven f u l l access to a l l of the resou rces of t hat emu lated system. Such an emu lated system is cal led a virtual machi ne. 1 .3.1 Virtual Memory The basic mechanism for s u pport i n g virtual memory is to provide a l i m ited amount of h i g hspeed physical memory t hat can be accessed d i rect ly by the processor w h i l e main tai n i n g an i mage of a much larger "virtual" memory on secondary storage devices such as large capacity disk drives. When the processor attempts to access a location i n the virtual memory map that is not res ident i n physical memory (referred to as a page fau lt), the access to t hat l ocation is temporari ly suspended w h i l e the necessary data is fetched from secondary storage and placed in physical memory; the suspended access is then either restarted or conti n ued. The M C68020 u ses i nstruction cont i nuation to s u pport virtual memory. In order for the M C68020 to u se i nstruction cont i nuation, it stores its i nternal state on t he su pervisor stack w hen a bus cycle is termi nated with a bus error signal. It then loads the program cou nter with the address of the virtual memory bus error hand ler from the except ion vec tor table (entry n u m ber two) and resumes program execution at that new address. When the bus error exception handler routine has completed execution, an RTE i nstruction is executed which reloads the M C68020 with the i nternal state stored on the stack, reru ns the fau lted bus cycle (when req u i red), and cont i n ues the suspended i nstruction. I nstruction cont i n uation is crucial to the su pport of virtual I/O devices in memory mapped i n put/output systems. Si nce virtual reg isters may be simu lated in the memory map, an access to such a reg i ster w i l l cause a fault and the fu nction of the regi ster can be emulated by software. 1 .3.2 Virtual Machine A typical use for a virtual mac h i ne system is the development of software, such as an operating system, for a new mac h i ne also under development and not yet avai lable for programm i n g u se. In such a system, a govern i ng operating system emu lates the hard ware of the prototyped system and al lows t he new operating system to be executed and 1 7

debugged as though it were run ning on the new hardware. Since the new operating system is control led by the governing operating system, it is executed at a lower privilege level than the governing operating system. Thus, any attempts by the new operating system to use virt ual resources t hat are not physically present (and should be emulated) are t rapped to the governing operating system and hand led by its software. I n the M C68020, a virtual machine is f u l l y s u pported by ru n ning the new operating system in the u ser mode. The governing operating system executes in the su pervisor mode and any at tempt by the new operating system to access supervisor resou rces or execute privileged instructions wil l cause a t rap to the governing operating system. In order to f u l l y support a virt ual machine, the M C68020 m ust protect the su pervisor resou rces from access by u ser programs. The o n ly su pervisor resource that is not f u l l y protected on the M C68000 a n d M C68008 i s t h e system byte o f the status register. On the M C68000 and M C68008, the MOVE from SR instruction al lows user programs to test the S bit in the stat u s register (in addition to the T bits and interru pt mask) and thus determine that they are ru n n ing in t he u ser mode. For fu l l virtual machine su pport, an operating system m u st not be aware of the fact that it is running in the less privileged user mode and thus should not be al lowed direct access to the S bit. For this reason, the MOV E from SR instruction on the M C680 1 0, M C6801 2, and M C68020 is a privileged instruction and the MOVE from CCR (condition code register) instruction is available to a l l ow user pro g rams direct access to the condition codes. By making the MOVE from SR instruction privileged, when the new operating system attempts to access the system byte of the statu s register, a t rap to the governing operating system will occur, w here the operation can be emu lated. 1 _4 PIPELINED ARCH ITECTU RE The M C68020 uses a t h ree stage instruction pipe, as shown in Fig u re 1 -5, to implement a pipelined internal architecture. The pipeline is completely internal to the microprocessor. The benefit of the pipeline is to al low concu rrent operations to occu r for up to three word s of a single instruction or for u p to t h ree consecutive instructions. I nstructions are loaded from the on-chip cache or f rom external memory du ring inst ruc tion prefetch into stage B. The instructions are sequenced from stage B through stage C to D. Stage 0 presents a f u l ly decoded and validated instruction to the control u n it for execution. I nstructions with immediate data and extension words find these words a l ready loaded in stage C and ready for u se by the control and execution u n its.

1 -8

Instruction Fetch and Decode Sequencer

I I I I

..,

Stage D
-

Stage C
-

Stage B
-

I I I I

Control Unit

1- -

Instruction Flow from Cache and Memory Execution Unit

Figure 1 5. MC68020 Pipeline

1 9/1 1 0


SECTION 2 DATA ORGAN IZATION A N D ADD R ESS I N G CAPA B I L I TI ES
This section contains a descri ption of the registers and the data organization of the M C68020. 2.1 OPERAN D SIZE Operand sizes are defined as fol l ows: a byte eq uals 8 bits, a word eq uals 16 bits, a long word eq uals 32 bits, and a q uad word eq uals 64 bits. The operand size for each inst ruc tion is either explicitly encoded in the instruction or im plicit ly defined by the instru ction operation. The coprocessor interface a l l ows the su pport of any operand size from a bit to 256 bytes. 2.2 DATA O RGAN IZATION IN REG ISTERS The eig ht data registers su pport data operands of 1 , 8, 1 6, 32, and 64 bits, add resses of 1 6 o r 3 2 bits, and bit fields o f 1 t o 3 2 bits. The seven address registers and the stack pointers su pport add ress operands of 1 6 or 32 bits. The six control registers (SR, VBR, SFC, D FC, CACR, and CAAR) su pport various data sizes depending on the register specified. Coprocessors may define u n ique operand sizes, and su pport them with on-chip registers according ly. 2.2.1 Data Registers Each data register is 32 bits wide. Byte operands occu py the low order 8 bits, word operands the low order 16 bits, and the long word operands the entire 32 bits. The least sig n ificant bit of an integer is add ressed as bit zero and the most sig nificant bit is ad dressed as bit 31 . For bit fields, the most sig n ificant bit is add ressed as bit zero and the least sig nificant bit is add ressed as the width of the field m i n u s one. The q uad word data type is two long words and is used o n ly for 32-bit m u l tiply and divide (sig ned and unsigned) instructions. Quad words may be organ ized in any two data registers without restrictions on order or pairing. There are no explicit instructions for the management of this data type, although the MOVEM instruction can be used to move a q uad word into or out of the reg i sters. When a data reg ister is u sed as either a sou rce or destination operand, o n ly the ap propriate low order byte or word (in byte or word operations, respective ly) is u sed or changed; the remain i n g high order portion is neither u sed nor changed.

2-1

2.2.2 Address Registers

Each address register and stack pointer is 32 bits wide and holds a f u l l 32bit address. Address registers can not be u sed for byte-sized operands. Therefore, when an address register is u sed as a source operand, either the low order word or t he entire long word operand is u sed, depending u pon the operation size. When an address register is used as the destination operand, the entire register is affected regardless of t he operation size. If the operation size is word, operands are sig n extended to 32 bits before the operation is performed. Address registers may a l so be used to support some simple data operations. 2.2.3 Control Registers The statu s register (SR) is 1 6 bits wide with the lower byte accessed as the condition code register (GGR). Not a l 1 1 6 bits of the status register are defined, and u ndefined bits are read as zeros and ig nored when w ritten. Operations to the condition code register are word operations; however, the upper byte is read as a l l zeroes and ig nored when written. The cache control register (GAGR) provides control and stat us access to the on-chip in struction cache. The cache add ress register (GAAR) holds the necessary address for t hose cache control functions that req uire one. The vector base register (VBR) provides the starting address of the exception vector table. A l l operations involving the GAGR, GAAR, and V B R are long word operations regard less of whether these registers are used as the sou rce or destination operand. The alternate function code registers (SFG and D FC) are three bits wide and contain the address space val ues placed on FGO-FG2 d u ring the operand read or write of a MOVES in struction. Transfers to and from the alternate function code registers are accom plished using the M OV EG instruction and are long word, although the u pper 29 bits are read as zeroes and ig nored when w ritten. Accesses to the control registers are privileged operations and are avail able only in the su pervisor mode. 2.3 DATA ORGANIZATION IN M EM O RY Memory is organized on a byte-add ressable basis where lower addresses correspond to higher-order bytes. The address, N , of a long word datum corresponds to the address of the most sig n ificant byte of the higher-order word. The lower-order word is located at ad dress N + 2, leaving the least significant byte at address N + 3 (see Fig u re 2- 1 ). Notice t hat the MG68020 does not require data to be alig ned on even byte boundaries (see Fig ure 2-22) but the most efficient data transfers occu r when data is a l ig ned on the same byte boundary as its operand size. H owever, instruction words must be alig ned on even byte boundaries. The data types su pported in memory by the MG68020 are: bit and bit field data; i nteger data of 8, 1 6, or 32 bits; 32-bit addresses; and binary coded decimal data (packed and u n packed). These data types are organized in memory as shown in F i g ure 2-2. (The quad word is only an operand when located in the data registers.) N ote that a l l of these data types can be accessed at any byte address.

2-2

31

23

Word $000000 Word $00000002 B yle $000000 1 B yle $()()()()OO()1 Byte $()()()()oo()2 I Byte $00003 000 Long Word $00000004 Word $00000004 Word $00000006 B Yle $00000004 1 Byte $()()()()oo()5 Byte $<XXXlOOO6 I Byte $()()()()OO()7

15 Long Word $000000

'1

'1

Long Word $FFFFFFFC Word $FFFFFFFC Word $FFFFFFFE Byte $FFFFFFFC I Byte $FFFFFFFD Byte $FFFFFFFE I Byte $FFFFFFFF

Figure 21 . Memory Operand Addressing

o
7

Byte n - 1

Bit Data 6 5 4 Bit Number Bit Field Data Byte n+ 1 Base Bit

Byte n+ 2

Base Address Byte n - 1 I+- - -O;fset

o 7

Byte n -Offset2

. -3 -2 - 1 0

-+

- Width -

Base Address MSB Address

Byte Integer Data Byte n

o

Byte n - 1

LSB Word Integer Data

Byte n+ 1
o

Byte n + 2
o 7

Byte n - 1

o 7

Word Integer

Byte n+ 2

Byte n + 3

Address
Figure 22. Memory Data Organization (Sheet 1 of 2)

23

Long Word Integer Data Byte n - l

o 7 o 7

Address Byte n - l
o 7

Packed Binary-Coded Data MSD Byte n+ 1 Unpacked Binary-Coded Data

xx

Byte n + 2

Address Byte n - l
xx
=

o 7

Byte n+2

Address User-Defined Value

Figure 22. Memory Data Organization (Sheet 2 of 2) Coprocessors may i m plement any data types and lengths. For example, the MC68881 FloatingPo i nt Coprocessor su pports memory accesses for quadword sized items (doubleprecision floatingpoint val ues). A bit dat u m is specified by a base address that selects one byte in memory (base byte) and a bit n u mber that selects the one bit in t his byte. The most sig n ificant bit of the byte is bit n u mber seven. A bit field dat u m is specified by: 1) a base address that selects one byte in memory, 2) a bit field offset that indicates the leftmost (base) bit of the bit field in relation to the most significant bit of the base byte, and 3) a bit field width that determines how many bits to the right of the base bit are in the bit field. The most sig n ificant bit of the base byte is bit offset 0, the least significant bit of the base byte is bit offset 7, and t he least significant bit of the previous byte in memory is bit offset - 1 . Bit field offsets may have va lues in the range of - 231 to 231 - 1 and bit field widths may range between 1 and 32. 2.4 I NSTRUCTIO N FORMAT A l l instructions are at least one word and up to 1 1 words in length as shown in Fig ure 23. The length of the i n struction and the operat ion to be performed is determined by the first word of the i nstruction, the operation word. The remaining words, cal led extension words, furt her specify the instruction and operands. These words may be i m med iate operands, extensions to the effective address mode specified in the operation word, branch displacements, bit n u m ber or bit field specifications, special register specifica tions, trap operands, pack/ u n pack constants, argument counts, or coprocessor condition codes. 24

15

Operation Word lOne Word, Specifies Operation and Modes) Special Operand Specifiers IIf Any, One or Two Words) Immediate Operand or Source Effective Address Extension Ilf Any, One to Five Words) Destination Effective Address Extension IIf Any, One to Five Words)
Figure 23. Instruction Word General Format

2.5

P ROG RAM/DATA REFERENCES

The M C68020 separates memory references i nto two c l asses: program references and data references. Program references, as the name impl ies, are references to that section of memory that contains the program i nstructions. Data references refer to that section of memory that contains the program data. G eneral ly, operand reads are from the data space. A l l operand w rites are to the data space, except when caused by t he M OV ES i n st ruction.
2.6

ADDRESSI NG

I nstructions for the M C68020 contai n two kinds of i nformation: the function to be per formed and the location of the operand(s) on which that function is performed. The methods used to locate (or add ress) the operand(s) are explai ned in the follow i n g parag raphs. I nstruct ions specify an operand location in one of three ways: Reg i ster Spec ificat ion - The n u mber of the reg ister is g iven i n the reg i ster field of , the i nstruct ion. Effective Address Use of the various effective addressing modes. The def i n ition of certain i nstructions i m p l ies the u se of I m pl icit Reference specific registers.
2.7

REG ISTERS: N OTATION CONVENTIONS

Regi sters are ident ified by the follow i n g mnemonic description: An - Address reg i ster n (e.g . , A3 i s address reg ister 3) On - Data reg ister n (e.g., 05 is data reg ister 5) Rn - Address or Data Register n Xn - Denotes i ndex reg ister n (data or address) PC - The program cou nter SR - The statu s reg i ster CCR - The condit ion code register; part of the stat us reg ister SP - The act ive stack poi nter; S P and A7 are eq u i valent names. USP - The u ser stack poi nter (A7) ISP - The i nterru pt stack pOinter (A7')

25

MSP - The master stack poi nter (A7 ") SSP - The su pervisor stack poi nter, either the master (MSP) or i nterrupt (ISP) stack poi nter SFC - The sou rce function code reg ister D FC - The dest i nation function code reg ister VBR - The vector base reg ister CAC R - The cache control reg ister CAAR - The cache add ress reg i ster The reg i ster field w i t h i n an i nstruction spec ifies the reg ister to be used. Other fields w i t h i n the i nstruct ion specify w hether the reg ister selected i s an address or data reg i ster and how the reg i ster i s to be u sed. 2.8 EFFECTIVE ADDRESS M ost i nstructions specify the locat ion of an operand by u s i n g the effective address field (EA) i n the operat ion word. For example, F i g u re 24 shows the general format of the s i ng l e effective address i nstruction operat ion word. T h e effective address i s com posed o f two 3bit fields; the mode field and the reg ister field. The val ue in the mode field selects one of the addressi n g modes. The reg i ster field contai n s the number of a reg ister. The i n struct ion operand word for each i nstruction is located i n APPENDIX C.

15

14

13

12

11

10

4 3 2 Effective Address Register Mode

Figure 24. SlngleEffectlveAddress Instruction Operation Word The effective address field may req u i re add itional i nformat ion to f u l ly specify the operand address. This add i t i onal i nformat ion, cal led the effective address extension, i s contai ned i n fol lowi n g word or words a n d i s considered part o f the i nstruct ion, a s shown in F i g u re 23. Detai l s descri b i n g the format of the extension words can be found in 2.9 EF FECTIVE ADDRESS ENCODING S U M M ARY. 2.8.1 Register Direct Modes These effective addressi n g (EA) modes specify that t he operand is in one of s ixteen general pu rpose reg i sters or one of six control reg isters (S R, V B R, SFC, DFC, CACR, and CAAR). 2.8.1 .1 DATA REGISTER DIRECT. The operand is in the data reg i ster specified by the ef fective address reg i ster field. G eneration: Assembler Syntax: M ode: Regi ster: Data Register: EA = Dn On 000 n On

1
26

31 Operand

2.8.1 .2 ADDR ESS REG ISTER DIRECT. The operand is i n the address reg i ster specified by the effective address reg i ster field. Generation: Assembler Syntax: M ode: Regi ster: Address Reg ister: EA = An An 001 31 0 n __ __ __ __ __ __ __ ,__ --, __ __ __ __ An -- -- --. --o_ _ _p e ra n d _ _

__ __ __ __

__ __ __ __

2.8.2 Register Indirect Modes These effective address i n g modes specify that the operand is in memory and the con tents of a reg i ster is used to calcu late the address of the operand. 2.8.2.1 ADD RESS REG ISTER I N DI RECT. The address of the operand i s i n the address reg i ster spec if ied by the reg ister field. G enerat ion: Assem bler Syntax: M ode: Reg i ster: Address Regi ster: M emory Address:
2_8.2.2

EA = (An) (An) 010 31 n An --------+1 31

o Memory Address o Operand

ADDRESS REG ISTER I N DI RECT WITH POSTI NCREM ENT. The address of the operand is in the address reg ister specified by the reg i ster field. After the operand ad dress is u sed, it is i ncremented by one, two, or four depend i n g upon whether the s ize of the operand is byte, word, or long word. Coprocessors may su pport i ncrement ing for any s ize, up to 256 bytes, of operand. If the address reg i ster is the stack pointer and the operand size is byte, the address is i ncremented by two rather than one to keep the stack po inter on a word bou ndary. Generat ion: Assembler Syntax: M ode: Reg i ster: Address Reg i ster: EA = (An) A n = An + SIZE (An) + 01 1 n An

-.1

__ __ __ __ __ __ __ __ __ --J

31

Memory Address

Operand Length (1 , 2, or 4): -------- 31 Memory Address: Operand

2-7

2.8.2.3 ADDRESS REG ISTER I N DIRECT WITH P REDECREMENT. The address of the operand i s in the address reg ister specified by the reg i ster field. Before the operand ad d ress is used, it is decremented by one, two, or four depending u pon whether the operand s ize is byte, word, or long word. Coprocessors may su pport decrementing for any s ize, up to 256 bytes, of operand. If the address reg ister is the stack pointer and the operand s ize is byte, the address is decremented by two rather t han one to keep t he stack pointer on a word bou nary. Generation: Assem bler Syntax: M ode: Register: Address Regi ster: An = An - SIZE EA = (An) - (A n) 1 00 31 n A n ------+-t

o Memory Address

Operand Length (1 , 2, or 4): -------.{ 31 Memory Address: Operand

2.8.2.4 ADDRESS REGISTER I N DI RECT WITH DISPLACEM ENT. This addressing mode req u i res one word of extension. The address of the operand is the sum of the address i n the address reg i ster and t h e s i g nextended 1 6bit displacement i nteger i n the extension word. Displacements are always sign extended to 32 bits prior to bei n g u sed i n effective address calcu lations. Generation: Assem bler Syntax: M ode: Register: Address Register: D i splacement: Memory Address: EA = (An) + d 1 6 (d 1 6 ,An) 1 01 n An
- - -

31 r L

i n xedd_

- --

-,-------, -,_ _

L_ _ _ _ _ ._

31

M emory Address

15

I n t e_ _ _ ge r --, __ Operand

31

2.8.3 Register Indirect with Index Modes These effective address i n g modes specify that the contents of an address reg i ster are used in calculat i n g the fi nal effective address of the operand. I n add ition, an i ndex reg i ster and a d isplacement are also used in calculat i n g the final address (the val ues are both s i g n extended to 32 bits before the calcu lation). The variat ions avai lable for ad j ust i n g the i ndex reg ister cause the i ndex to be considered an " i ndex operand".

2-8

The format of the i ndex operand is "Xn.S IZE*SCALE". "Xn" selects any data or address reg i ster as the i ndex reg i ster. "SIZE" specifies the i ndex s ize and may be "W" for word s ize or " L" for long word s ize. "SCALE" al lows the i ndex reg i ster value to be m u lt i pl i ed by a value of one (no sca l i ng), two., four, or eight. Displacements and i ndex operands are always sign extended to 32 bits prior to bei n g u sed i n effective address calculations. 2.8.3.1 ADDRESS REGISTER I N DI RECT WITH I N DEX (8BIT DISPLACEM ENT). This ad d ressi n g mode req u i res one word of extension t hat conta i n s the i ndex reg ister i nd icator (with its s ize selector and sca l i n g mode), and an a-bit d i splacement. In this mode, the ad d ress of the operand is the sum of the address reg ister, the s i g n extended d isplacement val ue in the l ow order e i g ht bits of the extension word, and the s i g n extended contents of the i ndex reg i ster (possibly scaled). The u ser m ust specify t he displacement, the address reg i ster, and the i ndex reg i ster i n t h i s mode. Generat ion: Assembler Syntax: M ode: Reg i ster: Address Register: 31 D i splacement: I ndex Reg i ster: Scale: Memory Address: EA = (An) + (Xn) + da (da,An,Xn.S IZE * SCALE) 1 10 31 n +1 An
-

[ = = i xedd= = = -'--_-'--..,;----
31 S i g n Extended Value Scale Value 31 Operand

_ _ L- _ _ _ __ __ _ _ _ ,

M emory Address

2.8.3.2 ADDRESS REGISTER I N DI RECT WITH I N DEX (BASE DISPLACEM ENT). This form of address reg i ster i n d i rect with i ndex req u i res one, two, or three extens i on words that conta i n i ndex reg ister i nd i cation and an optional 1 6- or 32-bit base d isplacement (wh ich i s s i g n extended before it i s u sed in the effective address calcu lation). The address of the operand is the sum of the contents of the address reg i ster, the scaled contents of the s i g n-extended i ndex reg ister and the base d isp lacement. In this mode, spec i f icat ion of all t h ree addends i s optional. If none are spec ified, the pro cessor creates an effective address of zero.

2-9

N ote that if an i ndex reg i ster is specified, but not the address reg i ster, and a data reg i ster (On) is u sed as the i ndex reg i ster, then a "data reg i ster i n d i rect" access can be generated. Generat ion: Assembler Syntax: M ode: Reg ister: Address Register: EA = (An) + (Xn) + bd (bd,An,Xn.SIZE*SCALE) 1 10 31 n A n ------+t

o Memory Address

31 o Base S i g n E x t e nd e_a l u e _ dV _ _____ Disp lacem ent: '"-- _ _ _ _ _ _ _ _ _ _ --' 31 o I ndex S i g n Extended Value Reg i ster: Scale Value 31

Scale: Memory Address: 2.8.4 Memory Indirect

Operand

This addressi n g mode req u i res one to five words of extension, as deta i l ed in 2.9 EFFEC TIVE ADDRESS ENCODING S U M MA RY. Memory i n d i rect is d istingu i shed from address reg i ster i n d i rect by u se of sq uare brackets ([ ]) in the assembler notat ion. The assembler generates the appropriate i nd i cators in the extension words w hen this addressing mode i s selected. In t h i s case, four userspec ified val ues are used in the generat ion of the fi nal address of the operand. An address reg i ster is u sed as a base reg ister and its va lue can be adj usted by add i n g an optional base d isplacement. An i ndex reg i ster specifies an i ndex operand and final ly, an outer d isplacement can be added to the address operand, yielding the effective address. The locat ion of the sq uare brackets determ i nes the u serspec ified val ues to be used i n calculat i n g an i ntermediate memory address. An address operand i s then fetched from that i ntermed iate memory address and it is u sed in calculat i n g the effective address. The i ndex operand may be added in after the i ntermed iate memory access (posti ndexed) or before the i ntermed iate memory access (pre i ndexed). A l l fou r u serspec if ied va lues are optional. Both the base and outer disp lacements may be n u l l , word, or long word. When a d isplacement is n u l l , or an element is suppressed, its value i s taken as zero in t he effective address calcu lation.

21 0

2.8.4.1 M EM O RY I N DI RECT POSTIN DEXED. I n t h i s case, an i ntermed iate i nd i rect memory address is calcu lated u s i n g the base reg ister (An) and base displacement (bd). This address is used for an i n d i rect memory access of a long word, fol lowed by add i n g the i ndex operand (Xn.SIZE* SCALE) t o the fetched address. Final ly, the opt ional outer displacement (od) i s added to yield the effective address. G eneration: Assembler Syntax: M ode: Address Regi ster: Base Displacement: EA = (bd + An) + Xn.SIZE*SCALE + od ([bd,An),Xn.SIZE*SCALE,od) 1 10 31 -- -An Memory Address
---------

---

31 Sign Extended Value 31

I n d i rect Memory Address Points To 31 Value at I nd i rect Memory Address 31 I ndex Register: Scale: 31 Outer D isplacement: Effective Address: Sign Extended Value 31 Operand Sign Extended Value Scale Value

2-1 1

2.8.4.2 M EM O RY I N DI R ECT P R E I N DEXED. I n t h i s case, the i ndex operand (Xn.SIZE* SCALE) i s added to the base reg i ster (An) and base d i s placement (bd). This i n termed iate s u m i s then u sed as an i n d i rect address i nto the data space. Fol lowi n g the long word fetch of the operand address, the opt ional outer d i s placement (od) may be added to yield the effective address. Generat ion: Assembler Syntax: M ode: Address Regi ster: EA = (bd + A n + Xn.SIZE *SCALE) + od ([bd,An,Xn.SIZE* SCALE],od) 110 31 -- -- -- -- -- -- -; - -- -- --Address-- -An Memory
_ _ _ __ __ __

31 Base Displacement: 31 I ndex Register: Scale: 31 I n d i rect Memory Address Points To 31 Value at I nd i rect Memory Address 31 Outer D i splacement: Effective Address: S i g n Extended Value 31 Operand o S i g n Extended Value Scale Value Sign Extended Value o

2-1 2

2.8.5 Program Counter Indirect With Displacement Mode This address i n g mode req u i res one word of extension. The address of the operand is the sum of the address in the program counter and the sign extended 1 6bit d isp lacement i nteger in the extension word. The val ue i n the program cou nter is the address of the ex tension word. The reference is c lassified as a program reference. Generat ion: Assembler Syntax: M ode: Reg ister: Program Cou nter: Displacement: M emory Address: EA = (PC) + d 1 6 (d 1 6 , PC) 111 010 31

31 15 o - -----I nt e g e r .... --'I-- 31 Operand

[
g

2.8.6 Program Counter Indirect with Index Modes These addressi n g modes are analogous to t he reg ister i nd i rect with i ndex modes descri bed in 2.8.3, but the PC is u sed as t he base reg ister. As before, t he i ndex operand (sized and scaled) and a displ acement are u sed in the calcu lation of the effective address also. Displacements and i ndex operands are always s i g n extended to 32 bits prior to be i n g u sed in effective address calculations. PC relat ive accesses are always c lassif ied as program space references.

21 3

2.8.6.1 PC I N DI RECT WITH I N DEX (8 BIT DISPLACEM ENT). The address of the operand i s the sum of the address in the program cou nter, the sign extended displacement i nteger in the lower eight bits of the extension word, and the sized and scaled sign extended i ndex operand. The value i n the PC is the address of the extension word. This reference i s c lassif ied as a program space reference. The u ser must incl ude the displace ment, the PC, and the i ndex reg ister when specifying this address mode.

Generat ion: EA = (PC) + (Xn) + da Assembler Syntax: (da, PC,Xn.SIZE * SCALE) 111 M ode: 31 o 01 1 Reg i ster: Address of Extension Word Program Cou nter: ------- --------- 31 - - - - - - - - - - - 7 0 r Displacement:
L
_ _

in

I nteger f-----_+{ 0

31 Sign Extended Value Scale Value 31

I ndex Reg i ster: Scale: Memory Address:

Operand

2.8.6.2 PC I N DI RECT WITH I N DEX (BASE DISPLACEM ENT). Th i s address mode req u i res add itional extension words that conta i n the i ndex reg ister i nd i cation and an optional 1 6-or 32-bit base d isplacement (which i s sign extended to 32 bits before being used). The address of the operand is the sum of the contents of the PC, the scaled contents of the s i g nextended i ndex reg i ster, and the base d i sp lacement. In this mode, specification of all t h ree addends is opt ional. However, in order to d is t i n g u i s h this mode from address reg ister i n d i rect with i ndex (base d isplacement), when the u ser w ishes to s pecify no PC, the assem bler notation "ZPC" (zero value is taken for the PC) m u st be u sed. This al lows the u ser to access the program space, without necessarily using the PC i n calculat i n g the effective address. N ote that if ZPC and an i n dex reg i ster are s pec ified, and a data reg i ster (On) is u sed, then a "data reg ister i n d i rect" access can be made to the program s pace, without u s i n g the PC.

21 4

Generation: EA = (PC) + (Xn) + bd Assembler Syntax: (bd,PC,Xn.SIZE * SCALE) M ode: 111 31 Reg i ster: 01 1 Program Cou nter: ------- 31 Base Displacement: 31 I ndex Reg i ster: Scale: 31 M emory Address:

o Address of Extension Word

-------.--
o

S i g n Extended Va l ue S i g n Extended Value Scale Value Operand

2.8.7 Program Counter Memory Indirect Modes As in the memory i n d i rect modes (refer to 2.8.4 Memory Indirect) the square brackets ([ ]) i n d icate that an i ntermed iate access to memory is made as part of the fi nal effective ad d ress calculation. In this case, the PC i s u sed as a base reg i ster and its value can be adj u sted by add i n g an optional base d isplacement. A n i ndex reg ister specif ies an i ndex operand and fi nal ly, an outer displacement can be added to the address opera nd, yielding the effective address. The locat ion of the sq uare brackets determ i nes the user-specif ied val ues to be u sed i n calcu lat i n g an i ntermedi ate memory address. A n address operand i s t hen fetched from that i ntermediate address and it i s used in the final calcu lation. The i ndex operand may be added in after the i ntermed iate memory access (post-i ndexed) or before that access (pre-i ndexed). A l l four user-spec if ied val ues are optional. Both the base and outer d isp lacements may be n u l l , word, or long word. When u s i n g n u l l disp lacements, the value of zero is u sed i n the effective address calcu lation. I n order t o specify no P C but st i l l make program space references, the notat ion "ZPC" should be u sed in its place.

2-1 5

2.8.7.1 P ROG RAM COUNTER M EM O RY I N DI RECT POST I N DEXED. An i ntermedi ate i n d i rect memory address is calcu lated by add i n g the PC, used as a base reg i ster, and a base d i spl acement (bd). This address is used for an i n d i rect memory access i nto program s pace of a long word, followed by add i n g t he i ndex operand (Xn.SIZE *SCALE) with t he fetched address. F i nal ly, the opt ional outer d isplacement (od) is added to yield the effec tive address. Generat ion: EA = (bd + PC) + Xn.SIZE*SCALE + od Assem bler Syntax: ([bd, PGJ,Xn.SIZE*SCALE,od) M ode: 111 31 o 01 1 Reg i ster Field: Prog ram Cou nter: -------+1 ------.-- 31 o Base Displacement: S i g n Extended Value 31 I nd i rect M emory Address 31 Value at I nd i rect Memory Address in Program Space 31 I ndex Regi ster: S i g n Extended Value Scale Value 31 Outer Displacement: Effective Address: Sign Extended Value 31 Operand o

2-1 6

2.8.7.2 P ROG RAM COUNTER M EMORY I N DI RECT PRE I N DEXED. I n this case, the i ndex operand (Xn .SIZE* SCALE) is added to the prog ram counter and base displacement (bd). This i ntermed iate s u m is then u sed as an i n d i rect address i nto the program space. Follow i n g the long word fetch of the new effective address, the optional outer d i splace ment may be added to yield the effective address. Generat ion: . Assembler Syntax: M ode: Reg i ster Field: Prog ram Cou nter: EA = (bd + PC + Xn.SIZE* SCALE) + od ([bd, PC,Xn.SIZE * SCA LE],od) 111 31 01 1 _ _ _ _ _ _ _ _ _ 31 Base Displacement: 31 I ndex Reg ister: Sign Extended Value Scale Value 31
L_

_ -.

S i g n Extended Value

31 Value at I nd i rect Memory Address i n Program Space 31 Outer Displacement: Effect ive Address: S i g n Extended Value 31 Operand o

21 7

2.8.8

Absolute Address Modes

Absolute address modes have the address of the operand i n the extension word(s).
2.8.8.1

ABSOLUTE SH O RT ADDRESS. This addressing mode req u i res one word of exten sion. The address of the operand is in the extension word. The 1 6bit address is s i g n ex tended to 32 bits before it is u sed. Generat ion: EA g iven (xxx).w Assembler Syntax: 111 M ode: 31 000 Register: , - - - - - -------l.1 Si g n Exte nded Extension Word: L
_ _ _ _ _

-r------

Memory Address

31 Memory Address: Operand

2.8.8.2 ABSOLUTE LON G ADDRESS. This address i n g mode req u i res two words of exten sion. The address of the operand is developed by the concatenat ion of the extension words. The high order part of the address is the f i rst extension word; the l ow order part of the address is the second extension word.

G enerat ion: EA g iven (xxx). L Assembler Syntax: 111 M ode: o 15 001 Regi ster: F i rst Extension Word: ------- Address H i gh 15 Second Extension Word: 31 Concatenat ion 31 Memory Address: Operand

21 8

2.8.9 Immediate Data This addressing mode req u i res one or two words of extension, depen d i n g on the size of the operat ion. Byte Operat ion - Operand is in the low order byte of the extension word Word Operat ion - Operand is i n the extension word Long Word Operat ion - Operand is in two extension words; h i g h order 16 bits are in the f i rst extension word; low order 16 bits are in the se cond extension word. Coprocessors may provide s u pport for i m mediate data of any s ize with the i nstruct ion portion taking at least one word. G eneration: Assembler Syntax: M ode: Reg ister: Operand g iven #xxx 111 1 00

2.9 EFFECTIVE ADD RESS ENCODING S U M MARY Table 2-1 deta i l s effective address word formats. The i nstruct ion operand extension words fall i nto three categories: s i ng l eeffectiveaddress i nstruction, i ndexed/ i n d i rect (brief format), and i ndexedl i n d i rect (fu l l format). The l on gest i nstruction for the MC68020 contai n s ten extension words. They consist of both sou rce and dest i nation effective ad dresses u s i n g the f u l l format extension word, with both base d isplacements and outer d i s placements bei n g 32 bits. Table 21. Effective Address Specification Formats

11
13

Single Effective Address Instruction Format

10

2 4 Effective Address Register Mode

3

12 1 1 10 9 8 7 15 14 D/A I Register I W/L I Scale I I I

a

MC68020. Brief Format Extension Word

2 4 Displacement
a 3

15 14 D/A I Register Register D/A W/L Scale

Field

13

12

10 9 8 7 6 5 4 W/L I Scale I 1 I BS I IS I BD SIZE I I Base Displacement 10. 1 , or 2 Wordsl Outer Displacement la, 1 , or 2 Wordsl
MC68020. Full Format Extension Word(s)

11

I/IS

Index Register Number Index Register Type: O = Dn l = An Word/Long Word Index Size: = Sign Extended Word 1 = Long Word Scale Factor: 00= 1 01 = 2 10=4 11=8
a

Definition

BS IS

Field

B D SIZE IllS
2-1 9

Base Suppress: 0= Base Register Added 1 = Base Register Suppressed Index Suppress: Evaluate and Add Index Operand 1 Suppress Index Operand Base Displacement Size: 00 Reserved 01 Null Displacement 10= Word Displacement 1 1 = Long Displacement Index/Indirect Selection: Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress
a=
= = =

Definition

The i ndex su ppress (IS) and i ndex/i n d i rect select ion (I/IS) fields are combi ned to deter mine the type of i n d i rect ion to be performed u s i n g the i ndexli ndirect f u l l format address i n g mode_ The encod i n g s and su bseq uent operat ions are descri bed in Table 2-2. Table 2-2_ IS-IllS Memory Indirection Encodlngs

IS
0 0 0 0 0 0 0 0 1 1 1 1 1

Indirect ()()()
001 010 01 1 1 00 101 1 10 111

Index/

()()()
001 010 01 1 1 00- 1 1 1

Ope ration No Memory Indirection Indirect Pre-Indexed with Null Displacement Indirect Pre-Indexed with Word Displacement Indirect Pre-Indexed with Long Displacement Reserved Indirect Post-Indexed with Null Displacement Indirect Post-Indexed with Word Displacement Indirect Post-Indexed with Long Displacement No Memory Indirection Memory Indirect with Null Displacement Memory Indirect with Word Displacement Memory Indirect with Long Displacement Reserved

Table 2-3 is the encoding of the effective addressing modes d iscussed in the previous parag raphs. Table 2-3. Effective Address Encoding Summary

Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Address Register and Memory Indirect with Index Absolute Short Absolute Long Program Counter Indirect with Displacement Program Counter and Memory Indirect with Index Immediate Data Reserved for Future Motorola Use Reserved for Future Motorola Use Reserved for Future Motorola Use
2.1 0 SYSTEM STACK

Addressing Mode

Mode ()()()
001 010 01 1 1 00 101 1 10 111 111 111 111 111 111 111 111

Register

Reg # Reg # Reg # Reg # Reg # Reg # Reg #

()()()
001 010 01 1 1 00 101 1 10 111

Address reg i ster seven (A7) is used as the system stack pOinter (SP) where any one of t h ree system stack reg i sters is active at any one ti me. The M and S bits of the status reg i ster determ ine which stack poi nter i s used. If S = 0, the user stack poi nter (USP) is the active system stack poi nter and the master and i nterrupt stack poi nters cannot be referenced. If S = 1 and M = 1 , the master stack pOinter (MSP) is the active system stack poi nter and the u ser and i nterrupt stack pOi nters cannot be referenced as address reg i sters. If S = 1 and M = 0, the i nterrupt stack pointer (ISP) i s the active system stack pointer and the u ser and master stack pOi nters cannot be referenced as address reg i sters. (Th i s corresponds to the M C68000, M C68008, M C680 1 0, and MC680 1 2 su per visor mode.) The term s u pervisor stack poi nter (SSP) refers to the master or i nterru pt stack poi nters, depend i n g on the state of the M bit. Each system stack f i l l s from h i g h to low memory. 220

The act ive system stack po inter is i m p l icitly referenced by a l l i nstructions that use the system stack for l i n kage or storage al locat ion. The program counter i s saved on the active system stack on su brout i ne cal l s and restored from the active system stack on ret urns. During the processi n g of traps and i n terru pts, both the prog ram counter and the statu s reg ister are saved on the su pervisor stack (either master or i n terru pt). Thus, the execution of s u pervisor state code i s not dependent on the behavior of u ser code or cond ition of the user stack, and user programs may use the u ser stack pai nter i ndependent of s u pervisor stack req u i rements. In order to keep data on the system stack a l i g ned for max i m u m efficiency when byte data is pushed on to or pul led from the system stack, the stack poi nter is decremented or i n cremented by two as appropri ate. The efficiency of the M C68020 system stacking operat ions (e. g., stacking of except ion f rames, subrou t i ne cal ls, etc.) is S i g n if icantly i ncreased i n long word organ ized memory when the stack poi nter is long word a l i g ned.

2_1 1 USER P ROG RAM STACKS Add itional user program stacks can be i m plemented by employing the address reg i ster i n d i rect with post i ncrement and predecrement addressi n g modes. Using an address reg ister (AO t h rough A6), the user may i m p lement stacks which are f i l led e ither from h i g h memory t o l o w memory, or vice versa. T h e i m portant considerat ions are: u s i n g predecrement, the reg ister is decremented before its contents are used as the poi n ter to the stack; u s i n g post i ncrement, the reg i ster i s i ncremented after its contents are used as the pai nter to the stack. Care m ust be exercised w hen m i x i n g byte, word, and long word items in these stacks. Stack g rowth from h i g h to low memory i s i m plemented with - (An) to push data on the stack, (An) + to p u l l data from the stack. After either a push or a p u l l operat ion, reg ister A n paints to the top item on the stack. This is i l l u strated as:

An --+

Low Memory (Free) Top of Stack

Bottom of Stack H ig h Memory

2-21

Stack g rowth from low to h i g h memory is i m plemented with (An) + to push data on the stack, - (An) to p u l l data from the stack. After e ither a push or p u l l operat ion, reg i ster An pOints to the next avai lable space on the stack. This i s i l l u st rated as: Low Memory Bottom of Stack
L

A n -+

Top of Stack (Free) H i g h Memory

2.1 2 Q U E U ES User q ueues can also be i m p lemented with the address reg ister i n d i rect with post incre ment or predecrement addressing modes. Using a pai r of address registers (two of AD t h rough A6), the u ser may i m plement q ueues which are f i l led either from h i g h memory to low memory, or vice versa. Because queues are pu shed from one end and pul led from the other, tiNo reg i sters are u sed: the 'put' and ' get' pointers. Q ueue growth from low to h i g h memory i s implemented with (An) + to put data i nto the queue, (Am) + to get data from the q ueue. After a put operat ion, the 'put' add ress reg ister pOints to the next avai lable space in the queue and the u nchanged ' get' add ress reg i ster points to the next item to be removed from the q ueue. After a ' get' operat ion, the ' get' address reg ister points to the next item to be removed from the queue and the u nchanged 'put' address reg ister points to the next avai lable space in the q ueue. This i s i l l u st rated as: Low Memory Last Get (Free) N ext G et

G et (Am) +

-+

7 L Put (An) + -+

Last Put (Free) H igh Memory

2-22

If the queue is to be i m p lemented as a c i rcu lar buffer, the relevant address reg i ster should be checked and, if necessary, adju sted before the 'put' or 'get' operat ion is per formed. The add ress reg i ster is adj usted by su btract i n g the buffer length (in bytes), pro d u c i n g a "wrap-around." Queue growth from high to low memory i s i m plemented with - (An) to put data into the queue, - (Am) to get data from the queue. After a ' put' operat ion, the 'put' address reg ister poi nts to the last item put i n the queue and the u nchanged get address reg i ster poi nts to the last item removed from the queue. After a 'get' operat ion, the 'get' address reg i ster points to the last item removed from the queue and the u nchanged ' put' address reg i ster pOints to the last item put in the queue. This is i l l ustrated as: Low Memory (Free) Last Put

Put - (An)

-+

Get - (Am) -+

Next Get Last Get (F ree) H i gh Memory

If the q ueue is to be implemented as a c i rcu lar bu ffer, the 'get' or 'put' operation should be performed fi rst, and then the relevant address reg i ster should be checked and, if necessary, adju sted. The add ress reg i ster i s adj u sted by add i n g the buffer length ( i n bytes).

2-23/2-24

S ECTI ON 3 I NSTRU CTION S ET S U M MARY

This section contai ns an overview of the M C68020 i nstruction set. The i nstructions form a set of tool s to perform the fol low i ng operations: Data M ovement B i t Field M a n i pulation B i nary Coded Deci mal Arithmetic I nteger Arithmet i c Logical Program Control Shift and Rotate System Control Bit M a n i pulation M u l t i processor Commun icat ions The comp lete range of i nstruction capab i l ities combi ned with the flex i ble addressing modes descri bed previously provide a very flexible base for program development. The following notations w i l l be u sed throughout this sect ion. A n = any address reg ister, AO-A7 Dn = any data reg ister, DO-D7 Rn = any address or data reg i ster CCR = cond ition code reg ister (lower byte of statu s reg i ster) cc = cond ition codes from CCR SP = active stack poi nter USP = u ser stack poi nter SSP = s u pervisor stack pointer D FC = dest i nation fu nction code reg ister SFC = source fu nct ion code reg i ster Rc = control reg i ster (VBR, SFC, D FC, CACR, CAAR, USP, MSP, ISP) d = d i splacement; d 1 6 is a 1 6-bit d i splacement < ea > = effective address l i st = l i st of reg i sters, e.g., DO-D3 # < dat a > = i mmediate data; a l iteral i nteger ( offsetw idth] = bit field sel ect ion label = assem bly program label [7] = bit 7 of respective operand [31 :24] = bits 31 t hrough 24 of operand; i.e., high order byte of a reg ister X = extend (X) bit in CCR N = negative (N) bit in CCR Z = zero (Z) bit in CCR - = i nvert; operand i s log ica l ly comp lemented A = log ical A N D V = log ical O R e = logical excl u s ive O R

3-1

Dc Ou Dr, Oq Oh,OI

= =

data data data data

reg i ster, reg i ster, reg i ster, reg i ster,

00-07 used during compare 00-07 used during update remai nder or quotient of d ivide h i g h or l ow order 32 bits of m u lt i ply res u l t

3.1 DATA MOVEMENT The bas i c means of address and data manipu lation (transfer and storage) is accompl ish ed by the move (MOV E) i nstruction and its associated effective address i n g modes. Data movement i nstructions al low byte, word, and long word operands to be transferred from memory to memory, memory to reg i ster, reg i ster to memory, and reg ister to register. Ad d ress movement i nstructions (MOVE or M OV EA) a l l ow word and long word operand t ransfers to ensure t hat only legal address manipulations are executed. In add ition to the general MOVE i nstruction t here are several special data movement i nstruct ions: move m u l t iple reg i sters (MOVEM), move peri pheral data (MOV E P), move q u ick (MOV EO), ex change reg i sters (EXG), load effective address (lEA), push effective address (PEA), l i n k stack (LI N K), u n l i nk stack (UN lK). Table 3-1 i s a summary o f t h e data movement operations.

Table 31 . Data Movement Operations

Instruction Operand Syntax Operand Size Operation

EXG EA

MOVE MOVEA MOVEM MOVEP

L LINK

Rn, Rn < ea > ,An An,# < d > < ea > , < ea > < ea > , An list, < ea > < ea > , list Dn, (d 1 6 .Anl (d 16 ,Anl,Dn

32 32 1 6, 32 8 , 1 6, 32 16, 32 - 32 1 6, 32 16, 32 - 32 16, 32

Rn - Rn < ea > - An S P - 4 - S P ; An - ISPI; S P - An; S P source - destination

+ d - SP

UNLK

MOVEO PEA

# < data > ,Dn < ea > An

8 - 32 32 32

listed registers - destination source - listed registers Dn[31 : 24] - (An + dl ; Dn[23: 1 6] - (An + d + 21; Dn[15:8] - (An + d + 41; Dn[7 0] - (An + d + 61 (An + dl - Dn[31 :24] ; (An + d + 21 - Dn[23: 16]; (An + d + 41 - Dn[1 5:8]; IAn + d + 61 - Dn[7:0] immediate data - destination S P - 4 - SP; < ea > - (SPI An - SP; (SPI - An; S P + 4 - SP

3.2 I NTEG ER ARIT H M ETIC O PERATIONS The arithmet i c operat ions i nc l ude the four bas ic operat ions of add (ADD), subtract (SUB), m u lt i ply ( M U l), and d ivide (OIV) as well as arithmetic com pare (CM P, C M P M , CM P2), c lear (ClR), and negate (N EG). The ADD, C M P, and SUB i nstructions are available for both ad dress and data operat ions, with data operat i ons accept i n g a l l operand s izes. Add ress operat ions are l i m ited to legal address s ize operands ( 1 6 or 32 bits). The c lear and negate i nstructions may be u sed on a l l s izes of data operands,

3-2

The M U L and D I V operat ions are avai lable for s i g ned and u n s i g ned operands u s i n g word m u lt i ply to prod uce a long word prod uct, long word m u lt i ply to prod uce a long word or quad word prod uct; a long word d ividend with word d ivisor to produce a word q uotient with a word remai nder; and a long word or q uad word d ividend with long word d ivisor to prod uce long word q uotient and 'Iong word remai nder. M u l t i prec ision and m ixed s ize arithmet i c can be acco m p l i shed u s i n g a set of extended i nstructions. These instruct ions are: add extended (ADDX), su btract extended (SU BX), sign extend (EXT), and negate bi nary with extend (N EGX). Refer to Table 3-2 for a summary of the i nteger arith metic operat ions. Table 3-2. Integer Arithmetic Operations

Instruction ADD ADDA ADDI ADDO ADDX CLR CMP CMPA CMPI CMPM CMP2 DIVS/DIVU DIVSLlDIVUL EXT EXTB MULS/MULU NEG NEGX SUB SUBA SUBI SUBO SUBX

Operand Syntax Dn, <ea> <ea>, Dn <ea>, An #<data>, <ea> #<data>, <ea> Dn, Dn - IAnl, - IAnl <ea> <ea>, Dn <ea>, An #<data>, <ea> IAnl IAnl + <ea>, Rn < ea > , Dn < ea > , Dr:Dq <ea > , Dq <ea > , Dr:Dq Dn Dn Dn <ea>, Dn <ea>, DI <ea>, Dh:DI <ea> <ea> <ea>, Dn Dn, <ea> <ea>, An # < data> , < ea > # < data> , < ea > Dn, Dn - IAnl, - IAnl
+,

Operand Size 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 32116- 16:16 64/32 -32:32 32/32-32 32/32 -32:32 8 - 16 16-32 8-32 16x 16-32 32 x 32-32 32 x 32-64 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32

Operation source + destination - destination immediate data + destination - destination source + destination + X - destination o - destination destination - source destination - immediate data destination - source lower bound < = Rn < upper bound destination/source - destination Isigned or unsignedl
=

sign extended destination - destination source" destination - destination Isigned or unsignedl

o o

destination - destination destination - X - destination destination - source - destination

-

destination - immediate data - destination destination - source - X - destination

3-3

3.3 LOGICAL O PERATIONS Log ical operat ion i nstructions A N D, OR, EOR, and NOT are avai lable for all s izes of i n teger data operands. A simi lar set of i m med iate i nstructions (AN DI , ORI, and EORI) pro vide t hese logical operat ions with a l l s izes of immed iate data. TST is an arithmetic com parison of the operand with zero which i s then reflected in the condition codes. Table 33 is a summary of the log ical operat ions. Table 33. Logical Operations

AND

Instruction

ANDI EOR EORI NOT OR ORI

TST

< ea > , Dn Dn, < ea > # < data > , < ea > Dn, < ea > # < data > , < ea > < ea > < ea > , Dn Dn, < ea > # < data > , < ea > < ea >

Operand Syntax

8, 8, 8, 8, 8, 8, 8, 8, 8, 8,

Operand Size
16, 16, 16, 16, 16, 16, 16, 16, 16, 16,

32 32 32 32 32 32 32 32 32 32

immediate data A destination - destination source Ell destination - destination immediate data Ell destination - destination - destination - destination source V destination - destination immediate data V destination - destination source to set condition codes
-

source A destination - destination

Operation

3.4 S H I FT AND ROTATE OPERATIONS Shift operat ions i n both d i rect ions are provided by the arithmetic sh ift i nstruct ions ASR and ASL, and logical sh ift i nstructions LSR and LSL. The rotate i nstructions (with and without extend) avai lable are ROR, ROL, ROXR, and ROXL. A l l sh ift and rotate operat ions can be performed on either reg i sters or memory. Reg i ster sh ifts and rotates su pport a l l operand s izes and a l l ow a shift count (from one to eig ht) to be specified i n the i nstruct ion operation word or a sh ift count (modulo 64) to be specified in a register. M emory sh ifts and rotates are for word operands only and al low only s i n g lebit shifts or rotates. The SWAP i nstruction exchanges the 1 6bit halves of a register. Performance of shift/rotate i nstructions is enhanced so that use of the ROR or ROL i nstructions with a sh ift count of eight al lows fast byte swapping. Table 34 i s a su mmary of the sh ift and rotate operat ions.

34

Table 34. Shift and Rotate Operations

Instruction ASL ASR LSL LSR ROL ROR ROXL ROXR SWAP

On, On # < data > , On < ea > On, On # < data > , On < ea > On, On # < data > , On < ea > On, On # < data > , On < ea > On, On # < data > , On < ea > On, On # < data > , O n < ea > On, On # < data > , On < ea > On, On # < data > , On < ea > On

Operand Syntax

8, 1 6, 32 8, 1 6, 32 16 8, 16, 32 8, 1 6, 32 16 8, 16, 32 8, 16, 32 16 8, 1 6, 32 8, 16, 32 16 8, 16, 32 8, 16, 32 16 8, 1 6, 32 8, 1 6, 32 16 8, 16, 32 8, 16, 32 16 8, 16, 32 8, 16, 32 16 32

Operand Size

Operation

..

r-- O -
r-- O

r--l
o

.
--I

[0.. I I ..

Y
[0..
I

I I -[0

I"

C{H

I MW I LW I

I I -W

3.5 BIT MAN I P U LATION OPERATIONS Bit manipu lat ion operat ions are accomplished u s i n g the fol low ing i nstruct ions: bit test (BTST), bit test and set (BS ET), bit test and c lear (BC lR), and bit test and change (BCH G). A l l bit manipu lation operat ions can be performed on either reg isters or memory, with the bit nu mber specified as i m med iate data or by the contents of a data reg ister. Regi ster operands are always 32 bits, w h i l e memory operands are always 8 bits. Table 35 i s a summary of the bit manipulation operat ions, (Z is bit 2, the "zero" bit, of the status reg i ster.) Table 35. Bit Manipulation Operations

Instruction BCHG BCLR BSET BTST

On, < ea > # < data > , < ea > On, < ea > # < data > , < ea > On, < ea > # < data > , < ea > On, < ea > # < data > , < ea >

Operand Syntax

Operand Size
8, 8, 8, 8, 8, 8, 8, 8, 32 32 32 32 32 32 32 32

bit number> of destination) - Z - bit of destination Z bit number> of destination) o - bit of destination - bit number> of destination) - Z; 1 - bit of destination - bit number> of destination) - Z

Operation

35

3.6 BIT FIELD OPERATIONS The MC68020 su pports variable length bit field operations on fields of up to 32 bits. The bit field insert (BFI NS) i nserts a va lue i nto a bit field. Bit field extract u n s i g ned (BFEXTU) and bit field extract sig ned (BFEXTS) extracts a val ue from the field. Bit field f i nd f i rst one (BFFFO) f i nds the f i rst bit t hat i s set in a bit field. Also i ncl uded are i nstruct ions that are analagous to the bit manipu lation operations; bit field test (B FTST), bit field test and set (BFSET), bit field test and clear (B FCLR), and bit field test and change (BFC H G). Table 36 is a summary of the bit field operat ions. Table 36. Bit Field Operations

- Field - Field < ea > ! offset width BFCHG O's - Field < ea > !offsetwidthl BFCLR Field - Dn; Sign Extended < ea > !offsetwidthLDn BFEXTS Field - Dn; Zero Extended < ea > !offsetwidthL D n BFEXTU Scan for first bit set in Field; offset - Dn < ea > !offsetwidthLDn BFFFO Dn - Field Dn, < ea > !offsetwidthl BFINS l 's - Field < ea > loffsetwidthl BFSET - lOR of all bits in fieldl - Z Field MSB < ea > I offset width BFTST NOTE: All bit field instructions set the N and Z bits as shown for BFTST before performing the specified operallon.

Instruction

Operand Syntax

Operand Size 132 132 1-32 1-32 132 1-32 132 132

Operation

- N;

3.7 BI NARY CODED DECIMAL O PERATIONS M u lt i prec i s ion arithmetic operat ions on bi nary coded decimal nu mbers are accompl ish ed u s i n g the fol low i n g i nstructions: add decimal with extend (ABCD), su btract decimal with extend (SBCD), and negate decimal with extend (N BCD). PACK and UN PACK al low conversion of byte encoded n u meric data, such as ASCII or EBCDIC strings, to BCD data and vice versa. Table 37 is a sum mary of the b i nary coded dec i mal operat ions. Table 37. Binary Coded Decimal Operations

ABCD

Instruction

NBCD PACK SBCD UNPK

Operand Syntax Dn, Dn - IAni, - IAni

# < data > Dn, Dn, # < data > Dn, Dn # < data > Dn, Dn,# < data >

- IAni, - IAni,

< ea >

- IAni, - IAni - IAni, - IAni,

Operand Size 8 8 8 16-8 16-8 8 8 8 - 16 8-16

source l O + destination lO + X - destination

Operation

destination lO - X - destination unpacked source + immediate data - packed destination

destination l O - source l O - X - destination packed source - unpacked source unpacked source + immediate data unpacked destination

3-6

3.8 P ROG RAM CONTROL OPERATIONS Program control operations are accomplished u s i n g a set of conditional and uncondi tional branch i nstructions and return i nstruct ions. These i nstructions are summarized in Table 38. Table 38. Program Control Operations

Instruction
Bee OBcc S ec

Operand Syntax
< label> On, < label > < ea > 8, 16, 32 16 8

Operation Conditional n
if condition true, the PC + d - PC if condition false, then On - 1 - O if O 7- - 1 , then PC + d - PC if condition true, then 1 ' s - destination; else O' s - destination

BRA BSR CALLM JMP JSR NOP

< label > < label > # < data > , < ea > < ea > < ea > none

8, 16, 32 8, 16, 32 none none none none

Unconditional PC + d -

PC SP - 4 - S P ; PC - I S P I ; PC d - PC Save module state in stack frame; load new module state from destination destination - PC SP - 4 - SP; PC fSPI; destination PC PC PC + 2

RTO RTM RTR RTS

#<d> Rn none none

16 none none none

ISPI - PC; S P + 4 + d - S P Reload saved module state from stack frame: place module data area pointer in Rn I S PI - CCR; SP + 2 - SP; ISPI - PC; SP + 4 - S P I S PI - PC; SP + 4 - SP

Returns

The cond itional i nstruct ions provide test i n g CC - carry clear LS CS - carry set LT MI EO - equal F - never true NE PL GE - g reater or equal GT - g reater than T HI - high VC LE - less or eq ual VS

and branch i n g for the fol low i n g cond it ions: - l ow or same - less than - minus - not equal - plus - always true - overflow clear - overflow set

N ot available for the Bcc or cpBcc i nstructions.

3-7

3.9 SYSTEM CONTROL OPERATI O N S System control operat ions are accomplished b y u s i n g privi leged i nstructions, trap generati n g i nstruct ions, and i nstructions that u se or modify t he condition code reg i ster. These i nstructions are sum marized in Table 3-9. Table 39. System Control Operations

Instruction
ANDI EORI MOVE MOVE MOVEC MOVES ORI R ES ET RTE STOP

Operand Syntax
# < data > . SR # < data > . S R < ea > , S R S R , < ea > USP, An An, U S P Rc, Rn Rn, Rc Rn, < ea > < ea > , Rn # < data > , S R none none # < data > 16 16 16 16 32 32 32 32 8, 1 6, 32 16 none none 16

Operation Privileged
immediate data 1\ S R - S R immediate data e SR - SR source - S R S R - destination U S P - An An - U S P Rc - Rn Rn - Rc Rn - destination using DFC source using S FC - Rn immediate data V S R - SR assert R ESET line ( S P) - SR; SP 2 - SP; ( S P) - PC; S P Restore stack according to format immediate data - S R ; STOP

+ 4 - SP;

B KPT CHK CHK2 I LLEGAL

# < data > < ea > , Dn < ea > , Rn none

none 16, 32 8, 16, 32 none

Trap Generating

TRAP TRAPcc TRAPV

# < data > none # < data > none

none none 16, 32 none

if breakpoint cycle acknowledged, then execute returned operation word, else trap as illegal instruction if D n < O or D n > (ea), then C H K exception if R n < lower bound or R n > upper bound, then C H K exception S S P 2 - SSP; Vector Offset - I S SP); SSP - SSP; PC - I S SP); S S P 2 - SSP; SR - ( S S P) ; Illegal Instruction Vector Address - PC SSP 2 S S P; Format and Vector Offset - ( S SP); SSP - SSP; PC - ( S SP); S S P 2 - SSP; SR - I SSP); Vector Address - PC if cc true, then TRAP exception
-

if V then take overflow TRAP exception

ANDI EORI MOVE ORI

# < data > , CCR # < data > , CCR < ea > , CCR CCR, < ea > # < data > , CCR

8 8 16 16 8

Condition Code Register

immediate data 1\ CCR - CCR immediate data e CCR - CCR source CCR CCR - destination immediate data V CCR - CCR

3-8

3.1 0 M U LTIPROCESSOR OPERATIO N S Com m u n icat ion between the M C68020 a n d other processors i n the system i s ac compl i shed by u s i n g the TAS, CAS, CAS2 i nstructions (which execute i ndivisible read mod ifywrite bus cyc les), and coprocessor i nstructions. These i nstructions are sum marized i n Table 31 0. Table 31 0. M ultiprocessor Operations

Instruction CAS CAS2 TAS cpBcc cpDBcc cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc

Operand Syntax Dc, Du, < ea> Dcl:Dc2, Dul :Du2, IRn):IRn) < ea> < label> < label> , On User Defined < ea> < ea> < ea> none #<data> 8, 16, 32 16, 32 8

Operation Read-Modify-Write destination - Dc - CC; if Z then Du - destination else destination - Dc dual operand CAS destination - 0; set condition codes; 1 - destination (7J Coprocessor if cpcc true then PC + d - PC if cpcc false then On - 1 - On if On '" - " then PC + d - PC operand - coprocessor restore coprocessor state from < ea > save coprocessor state at < ea > if cpcc true, then l's - destination; elseO's - destination if cpcc true then TRAPcc exception

16, 32 16 User Defined none none 8 none 16, 32

3-9/31 0

SECTIO N 4
SIGNAL DESC R I PTION
This section contains a brief desciption of the i n put and output s i g nals by their fu nc tional g ro u ps, as shown in Figure 4-1 . Each signal is explai ned in a brief paragraph with reference (if applicable) to other sect ions that conta i n more detail about the function be i n g performed. N OTE The terms assertion and negation are u sed extensively. Th i s i s done to avoid confusion w hen deal i n g with a mixture of "act ive-low" and "active-h igh" s i g nals. The term assert or assertion i s u sed to indicate that a s i gnal is active or true, i ndependent of w hether that level i s represented by a h i g h or low voltage. The term negate or negation i s u sed to i n d i cate t hat a s ignal i s i nactive or false.

FCO-FC2 AO-A3 1 DOD3 1 Transfer Size

<Junction Codes
Address Bus Data BUS

/1

:)

terruPt Priority
MC68020 Microprocessor
irnm AVIT ID1"

E5iS

Cache Control Interrupt Control

SIZO SIZl OCS RMC

m AS

BG BGACK RESET HALT BERR ClK VCC (10) GND (15)

Asynchronous Bus Control

R/W DBEN DSACKO DSACKl

55

} }

Bus Arbitration Control Bus Exception Control

Figure 4-1 _ Functional Signal G roups

4-1

4.1 FUNCTION CODE SIG NALS (FCO through FC2) These threestate outputs ident ify the processor state (supervisor or u ser) and the ad dress space of the bus cycle cu rrently bei n g executed as defi ned in Table 4. 1 . Table 41 . Function Code Assignments

FC2
0 0 0

FC1
0 0

FCD
0

User Data Space User Program Space 1 I Undefined, Reservedl I Undefined, Reservedl 1 0 0 1 Supervisor Data Space 1 0 1 1 Supervisor Program Space 1 1 CPU Space 1 Address space 3 IS reserved for user definition, while 0 and 4 are reserved for future use Motorola.

1 1

I Undefined, Reservedl *

Cycle Type

by

By decod i n g the fu nction codes, a memory system can util ize the full 4 gigabyte address range for several add ress spaces, 4.2 ADDRESS BUS (AO through A31 ) These t h ree-state outputs provide the address for a bus t ransfer during all cu rrently def i ned cycles except CPU-space references. During CPU-space references the add ress bus provides CPU related i nformation. The address bus is capable of addressing 4 g igabytes (232) of data. 4.3 DATA BUS (DO through 031) These t h ree-state, b i d i rectional sig nals provide the general pu rpose data path between the MC68020 and all other devices. The data bus can transmit and accept data u s i n g the dynamic bus sizing capabilit ies of the MC68020. Refer to 4.4 TRANSFER SIZE (SIZO, SIZ1) for add it ional i nformation, 4.4 TRANSFER SIZE (SIZO, SIZ1) These threestate outputs are u sed in conj u nction with the dynamic bus SIZing capabilit ies of the M C68020. The SIZO and SIZ1 outputs i nd i cate the n u m ber of bytes of an operand rema i n i n g to be t ransferred d u r i n g a g iven bus cycle, 4.5 ASYNCH RONOUS BUS CONTROL SIG NALS The asynchronous bus control s i g nals for the MC68020 are descri bed in the follow i n g paragraphs. 4.5.1 External Cycle Sta rt (ECS) This output is asserted d u r i n g the fi rst one-half clock of every bus cycle to provide the earli est i nd icat ion t hat the M C68020 may be start i n g a bus cyc le. The use of this s ig nal

42

must be val idated later with address strobe, since the MC6S020 may start an i nstruction fetch cycle and then abort it if the i n struction word i s found i n the cache. The M C6S020 d rives only the address, s ize, and function code outputs (not address strobe) when it aborts a bus cyc le due to cache h i t. 4.5.2 Operand Cycle Start (OCS) This output s i gnal has the same t i m i n g as ECS, except that it is asserted only during the f i rst bus cyc le of an operand transfer or i nstruction prefetch. 4.5.3 Read-Modlfy-Wrlte Cycle (RMC) This th ree-state output s ignal provides an ind i cation t hat t he cu rrent bus operat ion is an i nd ivisible read-mod ify-write cycle. This s i g nal i s asserted for the duration of the read modify-write sequence. R M C should be u sed as a bus lock to insure i nteg rity of i nstruc tions which u se the read-mod ify-write operat ion. 4.5.4 Address Strobe (AS) This th ree-state output s ig nal ind i cates that valid fu nction code, address, s ize, and RIW state i nformation is on the bus. 4.5.5 Data Strobe (OS) I n a read cycle, t h i s t h ree-state output i nd icates t hat the s lave device should drive the data bus. In a w rite cycle, it i nd i cates that t he M C6S020 has placed valid data on the data bus. 4.5.6 ReadlWrlte (RIW) Th i s th ree-state output s i gnal defi nes t he d i rect ion of a data transfer. A h i g h level in d i cates a read f rom an external device, a low level i nd i cates a write to an external device. 4.5.7 Data Buffer Enable (DB EN) Th i s three-state output provides an enable to external data buffers. This signal allows the RIW signal to change without possible external buffer content ion. This pin i s not necessary i n all systems. 4.5.8 Data Transfer and Size Acknowledge (DSACKO, DSACK1) These i n puts i nd i cate that a data t ransfer is complete and the port size of the external device (S-, 1 6-, or 32-bits). During a read cyc le, when the processor recogn izes DSACKx, it latches the data and then term i n ates the bus cycle; during a write cyc le, when the pro cessor recogn izes DSACKx, the bus cycle i s term i n ated. See 5.1 .1 Dynamic, Bus Sizing for furt her i nformation on DSACKx encod i ngs. The processor w i l l synchron ize the DSACKx i nputs and al low skew between the two i n puts. See 1 0.6 AC ELECTRICAL SPECI FICATIONS- READ AND WRITE CYCLES for fur ther i nformation. 4-3

4.6 CAC H E DISAB LE (CDIS) Th i s i nput s ignal dynamically d i sables the onch i p cache. The cache is disabled i nternal ly after the cache d isable i n put i s asserted and synchron ized i nternally. The cache w i l l be reenabled i nternally after the i n put negat ion has been synch ron ized i nternally. See SEC TION 7 ONCHIP CAC H E M EM O RY for further i nformat ion. 4.7 I NTERRUPT CONTROL SIG NALS The follow i n g paragraphs descr i be t he i nterrupt control signals for the M C68020. Refer to 5.2.4.1 I NTER R U PT O PERATION for add itional i nformation. 4.7.1 Interrupt Priority Level (IPLO, IPL 1, I PL2) These i nputs i nd i cate the encoded priority level of the device req uest i n g an i nterrupt. Level seven i s the h i g hest priority and can not be masked; level zero i nd i cates that no i n terru pts are requested. The least s i g n i f icant bit is I P LO and the most s i g n i f i cant bit i s I P L2. 4.7.2 I nterrupt Pending (I PEND) This output i nd icates that the encoded i nterru pt priority level act ive on the I PLO-I PL2 i n puts is h i g her than the cu rrent level of the i nterrupt mask i n the status reg ister or that a non-maskable i nterru pt has been recogn ized. 4.7.3 Autovector (AVEC) The AVEC i n put is used to request i nternal generat ion of the vector n u mber d u r i n g an i n terrupt acknowledge cycle. 4.8 BUS ARBITRATIO N SIG NALS The follow i n g parag raphs desc ribe the three-w i re bus arbitration pins used to determ i ne which device i n a system w i l l be t he bus master. Refer to 5.2.7 BUS ARBITRATION for ad d itional i nformat ion. 4.8.1 Bus Request (BR) Th i s i n put is w i re-ORed w i t h all request s ig nals from all potential bus masters and i n d i cates that some device other than the M C68020 req u i res bus mastership. 4.8.2 Bus G rant (BG) Th i s output s ig nal i nd i cates to potential bus masters that the M C68020 w i l l release ownership of the bus w hen the cu rrent bus cyc le is completed .

4-4

4.8.3 Bus G rant Acknowledge (BGACK) Th i s i nput i nd i cates that some other device has become the bus master. Th i s s i gnal should not be asserted until the follow i n g cond i t i ons are met: 1) BG (bus g rant) has been received t h rough the bus arbitration process, 2) AS is negated, i ndicat i n g that the M C68020 is not u s i n g the bus, 3) DSACKO and DSACK1 are negated i nd icat i n g that the previous external device is not u s i n g the bus, and 4) BGACK is negated, w h i c h i nd i cates that no other device i s st i l l c l a i m i n g bus masters h i p. BGACK must rema i n asserted as long as any other device is bus master. 4.9 BUS EXCEPTIO N CONTROL SIG NALS The fol lowi n g paragraphs describe the bus exception control s i gnals for the M C68020. 4.9.1 Reset (RESEn This bidirect ional opendra i n s i g nal is used as the systems reset s ignal. If RESET is asserted as an i n put, the processor w i l l enter reset exception process i ng . As an output, the processor asserts R ESET to reset external devices, but i s not affected i nternally. Refer to 6.3.1 Reset for more i nformation. 4.9.2 Halt (HALn The assertion of this bidirectional, opendra i n s i g nal stops all processor bus act ivity at the completion of the cu rrent bus cycle. When the processor has been halted u s i n g this i n put, all control s i gnals will be placed i n their i nactive state, the R/w, fu nction code, and s ize S i gnals, and the add ress bus rema i n driven with the previous bus cycle i nformation. The RMC s ig nal will be driven i nact ive, if asserted. The data bus i s threestated. When the processor has stopped executing i nstruct ions, due to a double bus fault condi tion, the H A LT l i ne is driven by the processor to i n d i cate to external devices that the pro cessor has stopped. 4.9.3 Bus Error (BERR) This i n put s ignal i nforms the processor that there has been a problem with the bus cyc le cu rrently bei n g executed. These problems may be the result of: 1) Nonrespond i n g devices, 2) I nterrupt vector n u m ber acq u isition fai l u re, 3) I l legal accesses as determi ned by a memory management u n it, or 4) Various other appl i cation dependent errors. The bus error s ig nal i nteracts with the halt S i g nal to determ i ne if the cu rrent bus cycle should be re-run or aborted with a bus error. Refer to SECTION 5 BUS OPERATIO N for add i t i onal i nformat ion.

4-5

4.1 0 C LOCK (ClK) The M C68020 clock i n put is a TTLcompat i ble s i gnal that is i nternally buffered to develop i nternal clocks needed by the processor. The clock should not be gated off at any t i me and m ust conform to m i n i m u m and max i m u m period and pulse width t i mes. 4.1 1 SIG NAL S U M MARY

Table 42 provides a s u m mary of the electrical characteristics of the signals d i scu ssed i n t h e previous parag raphs. Table 42. Signal Summary

Signal Function Signal Name Function Codes FCO-FC2 Address Bus AO-A31 Data Bus DO-D31 Size SIZO-Sll l External Cycle Start ECS Operand Cycle Start OCS Read-Modify-Write Cycle RMC Address Strobe AS Data Strobe DS Read/Write R/W Data Buffer Enable DBEN Data Transfer and Size Acknowledge DSACKO-DSACK 1 Cache Disable CDIS Interrupt Priority Level IPLO-IPL2 Interrupt Pending IPEND Autovector AVEC Bus Request BR Bus Grant BG Bus Grant Acknowledge BGACK Reset RESET Halt HALT Bus Error BERR Clock CLK Power Supply VCC Ground GND *Open Drain

Input/Output Output Output Input/Output Output Output Output Output Output Output Output Output Input Input Input Output Input Input Output Input Input/Output Input/Output Input Input Input Input

Active State High High High H gh Low Low Low Low Low High/Low Low Low Low Low Low Low Low Low Low Low Low Low
i
-

Three-State Yes Yes Yes Yes No No Yes Yes Yes Yes Yes
-

No
-

No No* No*
-

4-6

S ECTION 5 BUS O P E RATION

T h i s section describes t h e control signal and b u s operation d u r i ng data t ransfer opera tions, bus arbitrat ion, bus error and halt conditions, and reset operat ion. N OTE I n the parag raphs dea l i ng w i t h bus transfers, a " port" refers to the external data bus width at the s lave device (memory, peri pheral, etc.). During a w rite cycle, the M C68020 always drives all sections of the data bus. The term "synchron izat ion" i s u sed repeated ly w hen d i scussing bus operat ion. This delay is t he t i me period req u i red for the M C68020 to sample an external asynchronous i n put S i gnal, determine w hether it is h i g h or low, and synchron ize t he i nput to the i nternal c l ocks of the processor. F i g u re 5-1 shows the rel ationship between the c lock signal, an external i nput, and its associated i nternal S i g nal that i s typical for all of the asyn chronous i n puts. Fu rthermore, for all i n puts, there is a sample w i ndow d u r i n g which t he processor latches the level of the i n put. This w i ndow i s i l l u st rated in F i g u re 5-2. In order to g uarantee the recog nition of a certai n level on a spec ific fal l i ng edge of the c lock, that level m u st be held stable on the input t hroug h the sample w i ndow. I f an i n put makes a transition during the sample w i ndow, the level recog nized by the processor i s not pred ictable; however, the processor w i l l always resolve the latc hed level to a logic h i g h or low before taking ac tion on it. One except ion to t h i s rule is for the late assert ion of BERR (see 5.2.5.1 BUS ERROR OPERATION), where the sig nal must be stable th roug h the w i ndow or the pro cessor may exh i bit errat ic behavior. I n add ition to meet i n g i n put setup and hold t i mes, a l l i n put Signals must obey t h e protocols descri bed later i n t h i s section (e.g., w hen DSACKx is asserted, it must remain asserted u nt i l AS is negated).

elK EXT
INT

!
I

---

---

I+-- Sync Delay

\--

Figure 51 . Relationship Between External and Internal Signals 5-1

tsu
elK

-.j

------------:'{-----------: EXT
I

I I I

I- I- th
I

Window

Sample

Figure 52. Sample Window 5.1 OPERAN D TRANSFER M ECHANISM The M C68020 arch itecture su pports byte, word, and long word operands al lowing access to 8, 1 6, and 32bit data ports t hroug h the u se of the data transfer and s ize acknowledge i n puts (DSACKO and DSACK 1 ). The DSACKx i nputs are control led by the s l ave device c u r rently bei n g accessed and are discussed further i n 5.1 .1 Dynamic Bus Sizing. The M C68020 places no restrictions on the a l i g n ment of operands in memory, that is, word and long word operands may be l ocated at any byte bou ndary. H owever, i nstruction a l i g n ment on word (even byte) boundaries i s enforced for max i m u m eff ic iency and i n order t o maintain compatibi l ity with earl ier mem bers o f the M68000 Fam i ly. The u ser should be aware that misa l i g n ment of word or long word operands may cause the M C68020 to perform mu ltiple bus cyc les for t he operand transfer and therefore, pro cessor performance is opt i m ized if word and long word memory operands are a l i g ned on word or long word bou ndaries, respect ively. Refer to 5.1 .3 Effects of Dynamic Bus Sizing and Operand Misalignment for a d i scussion of the i m pact of dynam ic bus sizing and operand a l i g n ment. 5.1 .1 Dynamic Bus Sizing The M C68020 a l l ows operand t ransfers to or from 8, 1 6, and 32bit ports by dynam ica l ly determ i n i ng the port s ize d u r i n g each bus cyc le. During an operand transfer cyc le, the slave device signals its port s ize (byte, word, or longword) and transfer status (com plete or not com plete) to the processor t hrough the u se of the DSACKx i n puts. The DSACKx i n puts perform the same t ransfer acknowledge function as does the DTACK i n put of other processors in the M68000 Fam i ly as well as i nform ing the M C68020 of the cu rrent port width. See Table 54 for DSACKx encod i ng s and assert ion resu lts. For exam ple, if the processor is executing an i nstruct ion that req u i res a read of a long word operand it w i l l attempt to read 32 bits during the fi rst bus cycle (refer to 5.1 .2 M is alignment of Bus Transfers). If the port responds that it is 32 bits w ide, the MC68020 latches a l l 32 bits of data and cont i n ues with the next operat ion. If the port responds that it is 1 6 bits wide, the M C68020 latches the 1 6 bits of val i d data and runs another cyc le to obtain the other 1 6 bits. An Bbit port is hand led s i m i larly, but with fou r read cyc les.

52

I t is i m portant to realize that the assert ion of OSACK, in add it ion to signal ling comp let ion of the bus cyc le, indicates the device port s ize not the transfer size. For example, a 32b it device always ret urns OSACK for a 32-bit port regard less of whether the bus cycle i s a byte, word, or long word operat ion. Each port i s fixed i n ass ignment to particu lar sect ions of the data bus. A 32-bit port is located on data bus bits 31 th rou g h 0, a 1 6-bit port i s located on data bus bits 31 th rou g h 1 6, a n d an 8-bit port is located on data bus b i t s 31 t h rough 2 4 . T h e MC68020 makes these assumptions in order to locate va lid data. This scheme m i n i m izes the nu mber of bus cycles needed to t ransfer data to the 8- and 1 6-bit ports. The M C68020 will always at tem pt to t ransfer the max i m u m amount of data on all bus cycles; i .e. for a long word operat ion, it always assumes that the port is 32 bits wide w hen beg i n n ing the bus cycle . F i g u re 5-3 shows the req u i red organ izat ion of data ports on the M C68020 bus for 8-, 1 6-, and 32-bit devices. The "OPn" labels in F i g u re 5-3 define the various operand bytes, with OPO bei n g the most s i g n i fi cant. Figure 5-4 shows the i nternal organ ization of byte, word, and long word operands. The fou r bytes shown in F i g u re 5-3 are routed to the external data bus via the data multi plex and dupl icat ion hardware which is also shown. Th i s hard ware provides t he basic mechanism through which the MC68020 su pports dynam ic bus sizing and operand misalig n ment. The m u ltiplexor operation, as detai led in Figure 5-3, shows the multip lexor con nect ions for d i fferent combi nations of add ress and data s izes. The multip lexor takes the four bytes of the 32-bit bus and routes them to their req u i red positions. For exam ple, OPO can be routed to 031 -024, as would be the normal case, or it can be routed to any other byte position in order to su pport a m isaligned transfer. The same is t rue for any of the operand bytes. The positioning of bytes is determ i ned by the s ize (SIZ1 and SIZO) and address (AO and A 1 ) outputs.
MC68020 I nternal Source/Destination Multiplexor External Data Bus OPO 0 OP1

D31-D24

I /

\ j 1 Routing and Duplication

D23-D16

OP2 2

OP3 3

I
I I

D 1 5-D8

D7-DO

Address xxxxxxxO I ncreasing Memory Addresses

Byte 0

Byte 1

Byte 2

Byte 3

32-Bit Port

xxxxxxxO 2 a xxxxxxxO

Byte 0 Byte 2 Byte 0 Byte 1 Byte 2 Byte 3

..

Byte 1 Byte 3

1 6-Bit Port

2 3

8-Bit Port

Figure 5-3. MC68020 Interface to Various Port Sizes 53

Long Word Operand Word Operand Byte Operand

31

oPo

OP1

OP2

OP3 OP3

I I I

15

OP2

OP3

Figure 54. I nternal Operand Representation The multi plexor routes and/or d u p l i cates the bytes of the bus to al low for any combi na tion of aligned or m i saligned transfers to take place. The SIZO and SIZ1 outputs i ndicate the remaining n u mber of bytes to be transferred during the next bus cycle . The n u mber of bytes transferred d u ring a bus cyc le w i l l be equal to or less than the operand s ize i nd i cated by the SIZO and SIZ1 outputs, depending on port width and operand a l i g n ment. For example, during the f i rst bus cyc le of a long word transfer to a word port, the size outputs w i l l i ndicate four bytes are to be transferred although only two bytes w i l l be moved on that cyc le. Table 51 shows the encod i ngs of SIZ1 and SIZO. Table 51 . SIZE Output Encodlngs

SIZI
0 1 1 0

SIZO
1 0 1 0

Byte Word 3 Byte Long Word

Size

The address l i nes AO and A 1 also effect operation of the data multip lexor. Ouring an operand transfer (instruction or data), A2A31 i ndicate the long word base address of that portion of the operand to be accessed, w h i l e AO and A 1 g ive t he byte offset from the base. For example, consider a word write to a long word address with an offset of one byte (A1 /AO = 01 ) . The M C68020 will i n it iate the transfer (SIZ1 /SIZO = 1 0, A1 /AO = 01 ) and the data multi plexor w i l l place OP2 and OP3 (see Figure 53 and 54) on 01 6023 and 0801 5 respectively. Table 52 shows t he encod i ngs of A 1 and AO and the correspond ing byte offsets from the long word base. Table 52. Address Offset Encodings

A1
0 0 1 1

AO
0 1 0 1

+0 +1 +2 +3

Offset

Bytes Byte Bytes Bytes

54

Table 5-3 describes the use of SIZ1 , SIZO, A 1 , and AO i n def i n i n g the transfer pattern from the MC68020' s i nternal m u l t i p lexor to the external data bus. Table 5-3_ MC68020 Internal to External Data Bus Multiplexor

Transfer Size
Byte

S IZ1
0 1

Size

S IZO
1 0 0 1 1 1 1 0 0 0 0

A1

Address

AO

031: 024

Source/ Destination External Data Bus Connection

023:016 015:08

07:00

x x x 0 0 1 1 0 0 1 1

x 0 1 0 1 0 1 0 1 0 1

OP3 OP2 OP2 OP1 OP1 OP1 OP1 OPO OPO OPO OPO

OP3 OP3 OP2 OP2 OP1 OP2 OP1 OP1 OPO OP1 OPO

OP3 OP2 OP3 OP3 OP2 OP1 OP2 OP2 OP1 OPO OP1 *

OP3 OP3 OP2 OPO OP3 OP2 OP1 OP3 OP2 OP1 OPO

Word 1 1 1 3 Byte 1 1 0 0 Long Word 0 0

*

On write cycles this byte is output, on read cycles this byte is ignored. x ; don ' t care. NOTE: The OP labels on the external data bus refer to a particular byte of the operand that will be read or written on that section of the data bus (see Figure 5-4).

Table 5-4 descri bes the encod i ng s of t he DSACKx pins to s i g nal cu rrent port s ize. Table 5-4. DSACK Codes and Results

DSACKl
H H L L

DSACKO
H L H L

Insert Wait S tates in Current Complete Cycle - Data Bus Complete Cycle - Data Bus Complete Cycle - Data Bus

Result

Bus Cycle Port Size is 8 Bits Port Size is 16 Bits Port Size is 32 Bits

5-5

F i g u re 55 shows the basi c control flow assoc iated with an a l i g ned long word transfer to a 1 6bit port. Refer to F i g u re 56 for t i m i ng relationships. The high order word of the long word (OPO and OP1) w i l l be t ransferred to the port located on 0 1 6031 during the fi rst bus operat ion. The s ize outputs w i l l i nd icate a long word operand and the lower address bits w i l l show a zero offset from the long word base (SIZ 1 /SIZO/A 1 IAO = 0000). The port res ponds to the processor by assert i n g the OSACK i n puts to i nd i cate comp let ion of a 1 6-bit transfer (OSACK1/0SACKO = LH). The M C68020 termi nates this cyc le and beg i n s a second cyc le to com plete the t ransfer. For the second cycle, the s ize and address out puts w i l l i nd i cate that a word t ransfer i s to occur on the upper data bus 0 1 6031 (SIZ1 /SIZO/A 1 /AO = 1 01 0). The base offset has been i ncremented by two in order to access the next h i g hest word l ocation. The processor a l so m u l t i plexes the lower word of the operand to 031 -0 1 6 and the port agai n responds by assert i n g the OSACKx i n puts (OSACK1 IDSACKO = LH).
Long Word Operand OPO 31

031

MSB

1 l Word Memory
Data Bus

OP1

OP2

OP3

I
Memory Control AO OSACKI OSACKO
o o L H H

016

LSB

SIZ1
o

MC68020 SIZO A 1
o o o

-- --

Figure 5-5. Exa mple of Long Word Transfer to Word Bus

56

ClK A2-A31 A1 AO FCO-FC2

so

S2

S4

so

S2

S4

=X ""\ ""\ =x

_ _ _ _ _ _ _

'X /

_ _ _ _ _ _ _ _ _

_ _ _ _ _ _ _ _

S IZ1 :00\ S ilO

--'---------' /

__' 'X

_ _ _ _ _ _ _ _

R/ W \ _ _ _ _ _ _ _ _ ____'_ _ _ _ _ _ _ _ _
_

-'_ \

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

ECS OCS

\'-------.J/ \ '-/ ---.J \'-------.Jr \'----O P2

_ _

\ D24-D31 ) >- --'DBEN D16-D23

_ _ _

_ _ _ _ _ _ _

_ _ _ _ _ _ OPO _ _ _ _ _ OP 1

...J )

____'_
(

_ _ _ _ ___

'_ _ _ _ _ _ _

)- ( >- ,---

word Write --l !.--- word Write .1... f.------ long Word Operand Write to 1 6-Bit port -----l

...J>----,--) -

_ _ _ _ _ _ O P3

Figure 56. Long Word Operand Write Timing (1 6 Bit Data Port)

5-7

The control flow for an a l i g ned long word transfer to an 8-bit port is shown i n Figure 5-7. Four bus cyc les w i l l be req u i red to t ransfer this operand, moving one byte per cycle. Similar to the previous example, the s ize outputs indicate a long word transfer d u r i n g the f i rst cycle, th ree byte d u r i n g the second, word d u ring the t h i rd, and byte during the fi nal cycle. See Table 5-3 for processor m u l t i plexor operat ion during this t ransfer. F i g u re 5-8 shows t i m i ng relationsh i ps for these t ransfers.
Long Word Operand OP2 OP1

OPO 31 Data Bus

OP3 0

Byte Memory
OPO OP1 OP2 OP3

SIZl
0 1 0

MC68020 SIZO Al
0 0 0 0

Memory Control AO DSACKl DSACKO

0 0 H H H H L

Figure 5-7_ Example of Long Word Transfer to Byte Bus

5-8

SO CLK A2-A31 A1

S2

S4

SO

S2

S4

SO

S2

S4

SO

S2

S4

=x

x / X / / V

x / \ X \ V

X / X \ / V / \ \ \

AD

FCO-FC2 =x
S IZ1 S IZO

R/W \
ECS \J

OCS \J
AS OS

OSACKO

5SAOO J
OBEN 024-031

\ =>----<

1\
OPO

1\

1\

I:-

Byte Write

>---< OP1 >---< OP2 >---< OP3 >1"" Byte Write 1"" Byte Write 1"" Byte Write
Long Word Operand Write to 8-Bit Port

=-:!

Figure 58. Long Word Operand Write Timing (8Bit Data Port)

5-9

5.1 .2 Misalignment of Bus Transfers I n the 32bit arch itecture of the M C68020, it is poss ible to execute an operand transfer on a memory address bou ndary t hat may not fal l on an equ i valent operand size bou ndary. Examples are words t ransferred to odd addresses and long words transferred to ad dresses other than long word boundaries. The M C68000, M C68008, and MC6801 0 im plementat ions a l l ow long word transfers on odd word boundaries but force an excep tion if word or long word operand t ransfers are attem pted at odd byte addresses. The M C68020 does not enforce any data a l i g n ment rest rictions. Some performance degradat ion can occur due to the m u ltiple bus accesses that the MC68020 must make when long word (word) operand accesses do not fal l on long word (word) boundaries . Note that i nstructions, and the i r associated (if any) extension words, are req u i red to fall on word address boundaries, but t h i s i s not req u i red for program space operand references. The M C68020 forces an address error except ion if an i nstruct ion prefetch is attempted at an odd address. This occu rs when an i nstruct ion (e.g., a branch with an odd offset) leaves the program counter set to an odd address. Dynam i c bus sizi ng also affects the t ransfer position of misalig n ment operands. N OTE In the following examp les for misaligned transfers, xxx in a byte denotes that the val ue is left u nchanged. F i g u re 5-9 shows the control associated with transferri ng a long word operand to an odd address in word organ ized memory. Figure 5-1 0 shows the t i m i n g relationship for this operat ion. Th is t ransfer req u i res that the M C68020 place a long word i n memory start i n g at the least s i g n i f icant byte of long word O. This transfer crosses two word boun daries and req u i res three bus cyc les to com plete. The f i rst cyc le executes with A2/A 1 /AO = 001 ) and the s ize outputs ind icat i n g a long word t ransfer (SIZ1/SIZO = 00). The word addressed d u r i n g t h i s t ransfer conta i n s o n ly one byte of the dest i nation and w i l l respond w i t h DSACK1/DSACKO = LH (port width = 1 6 bits). The system designer must en s u re that the u n u sed byte of the word accessed d u r i n g this cyc le does not receive an enable (refer to 5.1 _4 Address, Size, and Data Bus Relationships). The processor executes

OPO 31

Long Word Operand OP1 OP2

OP3 o

Data D31

Bus
D16

Word Memory MSB LSB

MC68020 SilO A1 AO

xxx OP1 OP3

OPO OP2 XXX

0 1 0

A2

Memory Control DSACK1 DSACKO

0 0

0 1 0

1 0 0

H H H

Figure 5-9. Misaligned Long Word Transfer to Word Bus Example

5-1 0

A2-A31 AO J Al

ClK

SO

S2

S4

SO

S2

S4

SO

S2

S4

X / \ X / / V

X \ X \

FCO-FC2 SIZ l

SIZO
R iw

OCS V AS OSACKO
l5Si'\CK'1

ECS V

OS

016-023

024-031

OBEN T\

/ r\

( OPl ) ( OPl ) ( OP2 ) 1\

( OP3
Byte Write

( OPO ) ( OPl )

08-015
00-07

( OPO )

( OP3

BYteWrite r

( OP2 )

Word Writ -I- Word Operande Wri-Ilong te

( OP2 )

( OP3 ( OP3
----:l

Figure 51 0. Misal igned Long Word Transfer to Word Bus

5-1 1

t he next transfer with A2/A 1 /AO = 0 1 0 and SIZ1 /SIZO = 1 1 (th ree bytes remaini ng). The memory accepts two bytes on this transfer and again asserts DSACK1 /DSACKO = LH. The final cycle is executed with t he t ransfer of a s i n g le byte (SIZ1 /SIZO = 0 1 ) to address A2tA1 /AO = 1 00. Figure 5-1 1 shows an example of a word transfer to an odd address i n word organ ized memory. This example is s i m i lar to t he one shown in F i g u re 5-9 except that the operand is of word size and req u i res o n ly two bus cyc les. Figure 5-1 2 shows the signal timing associated with this exam ple.
Word Operand OP2 OP3 15 Data Bus 031

Word Memory SIZl SIZO

016
M C68020

A2 o o

Memory Control Al

AO

OSACKl DSACKO

L L

H H

Figure 5-1 1 . Example of M isaligned Word Transfer to Word Bus

5-1 2

A2-A31 AO J A1 \

ClK

SO

S2

S4

SO

S2

S4

X / \ X \ / U \ / \ I

FCO-FC2 SIZO \
R/ W

SIZ1 J

OCS
AS

ECS OS

OSACKO OSACK1

016-023 00-07

024-031

OBEN 1\

\ ( ( ( (
OP2 OP2

/ /\ ) ) ) ( ( (
=

\
OP3 OP3

08-015

I:

OP2 OP3 ( ) Word Operand Write to All AO 01 Byte Write Word Write -I

OP3

OP3

:1

Figure 51 2. Misaligned Word Transfer to Word Bus

5-1 3

F i g u re 51 3 shows an example of a long word transfer to an odd address i n longword organ ized memory. I n this example, a long word access is attem pted beg i n n i ng at the least s i g n i f i cant byte of a longwordorgan ized memory. Thus, only one byte i s transfer red in the f i rst bus cyc le. The second bus cyc le then consists of a t h ree byte access to a long word bou ndary. Si nce the memory is long word organ ized, no further bus cyc les are necessary. F i g u re 51 4 shows the s i g nal t i m i n g associated with this example.

D31

31

OPO

Long Word Operand OP2 OP1 Data Bus

OP3

DO
SIZl
0

Long Word Memory

SIZO

MC68020

E
0

.E.
0

Memory Control DSACKl DSACKO

Figure 51 3. Misaligned Long Word Transfer to Long Word Bus 5.1 .3 Effects of Dynamic Bus Sizing and Operand Misalignment The combi nat ion of operand size, operand a l i g n ment, and port s ize affect the operat ion of the M C68020 operand transfer mechan ism by d ictat i n g the n u mber of bus cyc les reo q u i red to perform a particular memory access. Table 55 shows the n u mber of bus cyc les t hat are req u i red for d i fferent operand s izes through d i fferent port s izes based on the a l i g n ment of that operand. Table 55. Memory Alignment and Port Size Influence on Bus Cycles
N/A :2:4 Instruction* 1:1:1 1:1:1 Byte Operand :2:2 1 : 1 :2 Word Operand 2:3:4 1 :2:4 Long-Word Operand Data Port Size 32-8Its: 16-8Its: 8-Blts * Instruction prefetches are always two words from a long word boundary.

Al /AO

00

Number of Bus Cycles 01

1

1:1:1 1 : 1 :2 2:2:4
10 N/A

1:1:1 2:2:2 2:3:4

11 N/A

As can be seen in t h i s table, the M C68020 bus t hrou ghput can be s i g n i f icantly affected by port size and a l i g n ment. The M C68020 system des ig ner should be aware of and ac count for these effects, particu larly in t i me critical applications. Table 55 shows that the processor always prefetches i nstructions by read i n g two words from a long word boundary. When the MC68020 prefetches from the i nstruction stream, it always reads a long word f rom an even word address (A 1 /AO = 00), regard less of port s ize or a l i g n ment.

51 4

A2-A31 -y., AO J

ClK

SO

S2

S4

SO

S2

S4

A1 J

X \ \ X / / LI \ \ \ ( ( ( (
OPO OPl OPO

FCO-FC2 -y., SIZO \

R/W

SIZ l :\

"), '-J / "---/

m '-J
ocs AS

OSACKO ..J OSACKl ..J 016-023 ) 08-015 ) 00-07 ) 024-31 ) OBEN J\

os

\ \ / / \ \ ( ( (
OP2 OPl

I r

r\ ) ) )

Figure 51 4. Misaligned Write Cycles to 32Bit Data Port

I:

OPl OPO ( ) Byte Write -I 3-Bytes Write long Word Operand Write

OP3

:1

5-1 5

5.1 .4 Address, Size, and Data Bus Relationships The dynam ic bus capabi l ities of t he MC68020, coup led with the allowance for m isalig ned operands, create an extremely powerfu l and flexible bus structure. Correct external i n ter pretat ion of bus control signals is critical to ensure valid data transfer operat ion. The M C68020 system des i g ner should ensure t hat data ports are aligned as d iscu ssed in 5.1 .1 Dynamic Bus Sizing such that the MC68020 is able to route data to the correct l oca tions. It is also req u i red that the correct byte data strobes (fou r, for a long word memory) be generated which enable only t hose section of the data port(s) which are active d u r i n g the c u rrent bus cyc le. T h e M C68020 always drives a l l sections o f t h e data b u s d u r i n g a write cycle, so this necess itates carefu l control of the enable s i g nals for i ndependent bytes of a data port. For example, consider the bus transfer operat ion i l l ustrated in Figure 5-9. The transfer descri bed i s a long word w rite to an odd address in word-organ ized memory, req u i ri n g t h ree bus cyc les t o complete. Both t h e f i rst a n d the last transfers req u i re writing a s i n g l e byte t o a word address. I n order not t o overwrite those bytes which are not i nvolved i n t hese transfers, no byte data strobe should be asserted for t hose bytes. The req u i red act ive bytes of the data bus for any g iven bus transfer are a fu nction of the s ize (SIZ1 /SIZO) and l ower address (A1 /AO) outputs of the M C68020 and are shown i n Table 5-6. I ndividual data strobes for each byte o f t h e bus can b e generated by qual ifying the above enables with data strobe (OS). Devices residing on 8-bit ports can u t i l ize OS alone s i nce there i s o n ly one valid byte for any transfer. F i g u re 5-1 5 shows a logic d iag ram of one method of generat i n g byte data selects for 1 6 and 32-bit ports from the s ize and address encod i ngs. Table 56. Data Bus Activity for Byte, Word, and Long Word Ports
Oata Bus Active Sections Byte ( B ) - Word (W) - Long Word SIZl SIZO Al AD 031-024 023-016
-

Transfer Size

( L) Ports
07-00 -

0 1 5-08
-

Byte

Word

ThreeByte Long Word

0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

B B B B B B B B B B B B B B B B

W L W W L W W L W W L W

W L
-

W W W W W W W W W W W W W

L
-

L
-

L L L L L L

L L

L L
-

L L L
-

L L L
-

L L L L L L L

5-1 6

I
I

r--.

UUD
, " -...../

I "\ -../
IJ

UMD

r-

I -""""-

-../
I
-

l I l I

./

"

LMD

'"
./

LLD UD LD

JJ
"
./

AO

Al

S IZO

SIZl

Lc

UUD UMD LMD LLD UD LD

Upper Upper Data 132-Bit Port! Upper Middle Data 132-Bit Port) Lower Middle Data 132-Bit Port) Lower Lower Data 132-Bit Port) Upper Data 116-Bit Port) Lower Data 116-Bit Port)

Figure 51 5. Byte Data Select Generation for 1 6 and 32Bit Ports

51 7

5.2 BUS O PERATION Transfer of data between the processor and other devices i nvolves the following s i g nals: 1. Address Bus AO t h rough A31 , 2. Data B u s DO t hroug h 031 , and 3. Control S i g na l s. The address and data buses are paral lel, non-multiplexed buses used to transfer data with an asynchronous bus protocol. I n a l l bus cycl es, the bus master is responsible for deskewi n g a l l signals i ssued at both the start and t he end of the cyc le. I n add ition, the , bus master is responsible for deskew i n g the acknowledge and data Signals from the s l ave devices . The following sections explain the data t ransfer operat ions, bus arbitration fu nctions, and except ion processing. 5.2.1 Read Cycles During a read cycle, the processor receives data from a memory or peri pheral device. The processor reads bytes in a l l cases. The M C68020 w i l l read a byte, or bytes, as determi ned by the operand s ize and a l i g n ment. See 5.1 O PERAN D TRANSFER M ECHANISM. If the DSACKx i n puts or B E R R are not asserted d u ri n g the sample w i ndow of the fal l i n g edge of S2, wait cycles w i l l be i n serted in the bus cycle u n t i l either DSACK1 /DSACKO or B E R R i s recogn ized a s bei n g asserted. A flowchart of a long word read cycle is shown in F i g u re 5-1 6 with pos i t ional s i g nal i nfor mation shown in F i g u re 5-1 7. A flowchart of a byte read cyc le is shown i n F i g u re 5-1 8 with byte and word read cycle t i m i n g shown i n F i g u re 519. Actual read cycle timing diagrams specified in terms of c lock periods are shown i n SECTION 10 ELECTRICAL SPECI FICATIONS.

BUS MASTER Address Device 11 Set R/W to Read 21 Drive Function Code on FCO-FC2 31 Drive Address on AO-A31 41 Drive SilO-Sill I Four Bytesl 51 Assert ECS/OCS for One-Half Clock 61 Assert Address Strobe I AS I 71 Assert Data Strobe IDSI 81 Assert Data Buffer Enable IDBENI 11 Latch Data 21 Negate OS 31 Negate AS 41 Negate DBEN Acquire Data
,

SLAVE

Present Data 11 Decode Address 21 Place Data on 00-031 t-- 31 Assert Data Transfer and Size Acknowledge IDSACKxl
r-----.

Start Next Cycle

11 Remove Data fromTerminate Cycle 00-031

21 Negate DSACK

Figure 51 6. Long Word Read Cycle Flowchart

51 8

SO ClK A2-A31 Al AO FCO-FC2 S IZl S IZO R/W ECS OCS AS OS OSACKO OSACKl OBEN 00-031

S2

S4

Y \ ""\ Y ""\ ""\ J \ \ \ \ \ < r r r r r

Read

..

Figure 51 7. LongWord Read Cycle Timing (32Bit Data Port)

51 9

11 Set R/W to Read 21 Drive Function Code on FCO-FC2 31 Drive Address on AO-A31 41 Drive SIZO-SIZl lOne Bytel 51 Assert ECS/OCS for One-Half Clock 51 Assert Address Strobe lAS I 71 Assert Data Strobe IDSI BI Assert Data Buffer Enable IDBENI
BUS MASTER Address Device

S LAVE

r---

11 Latch Data 21 Negate OS 31 Negate AS 41 Negate DBEN

Acquire Data

f-----+I

1 1 Decode Address 21 Place Data on DO-D31 , D15-D23, D8-D15, or 00-07 Based on Transfer and Si Acknowl 31 IAssert DataAO, A 1 , and BuszeWidthl edge I)
Present Data

Start Next Cycle

'f

11 Remove Data from 00-031 2) Negate DSACK

Terminate Cycle

Figure 51 8. Byte Read Cycle Flowchart

520

A2-A31 =::x AO ---:\ A1 ---:\

CLK

SO

S2

S4

SO

S2

S4

x ! x \ I U U ! / \ \ \ ( (
OP3 OP2

FCO-FC2 =::x

SIZO ---:\
R/W

SIZ1

ECS -U AS

ocs -U
OSACKO OS

\ \

\ \ / / / ) ) (
OP3
Byte Read

r r \ \ \ r

DsAffi

016-023

024-031

08EN

08-015

Word Read

Figure 519. Byte and Word Read Cycle Timing (32Blt Data Port)

5-21

5.2.2 Write Cycle During a write cyc le, the processor sends data to memory or a peri pheral devi ce. The fu nction of the operand transfer mechanism d u r i n g a w rite cycle i s identi cal to that d u r i n g a read cyc le. See 5.1 OPERAN D TRANSFER M ECHANISM. A flowchart of w rite cyc le operat ion for words is shown i n F i g u re 5-20. Byte and word w rite cycle t i m i ng is shown in F i g u re 521 . The actual w rite cycle t i m i n g diagrams spec i fied in terms of c lock periods and details of both word and byte w rite cyc le opera tions are g iven in SECTIO N 10 ELECTRICAL SPECI FICATIONS.
BUS MASTER Address Device S LAVE

1 1 Set R/W to Write 21 Drive Function Code on FCOFC2 31 Drive Address on AO-A31 41 Drive Size on S IZO- S IZ1 ( Four Bytesl 51 Assert ECS/OCS for One-Half Clock 61 Assert Address Strobe (ASI 71 Assert Data Buffer Enable (oBENI 81 Place Data on Data Bus 91 Assert Data Strobes (oSI
Terminate Output Transfer

Present Data

1 1 Decode Address 21 Latch Data 31 Assert Data and Size Acknowledge ( oSACKI

11 Negate OS 21 Negate AS Remove Data from 41 Negate DBEN

31

00031

Start Next Cycle

1 1 Negate DSACK

Terminate Cycle

Figure 520. Write Cycle Flowchart 5.2.3 ReadModifyWrite Cycle The read-mod ify-write cyc le performs a read(s), modifies the data in the arit hmetic-log ic unit and writes the data back to the same add ress(es). I n the M68000 arch itectu re this process i s i ndivisi ble. During the entire readmod i fywrite seq uence the MC68020 asserts the RMC s i g nal to i nd i cate that an i nd ivisible operation is occurring. The M C68020 w i l l not issue a b u s g rant (BG) i n response t o a b u s req uest (BR) d u r i n g t h i s operation. The read-mod ify-write seq uence i s i m plemented to provide a means for sec ure inter task and/or i nter-processor com m u n i cation. The test and set (TAS) and com pare and swap (CAS and CAS2) i nstructions are the only MC68020 i nstructions which u t i l ize this feat u re.

522

A2-A31 X

CLK

SO

S2

S4

SO

S2

S4

FCO-FC2 X SIZO
SIZl R/W

AD \

Al }

X \ ! V U ! \ \ \ ( ( ( (
OP3 OP2

OCS \.J OSACKO J OSACKl J 016-023 ) 08-01 5 ) 00-07 ) 024-031 )

OBEN
os

ECS \.J

AS

\ \ / / 1\ ) ) ) ) ( ( ( ( \ \
OP3 OP3 OP3

r r

OP2
Word Write

OP3

OP3

I-

-I-

Byte Write

Figure 521 . Byte and Word Write Cycle Timing (32Bit Data Port)

5-23

A flowchart of the read-mod ify-write cyc le operat ion is shown i n F i g u re 5-22. For the CAS and CAS2 i nstruct ions, the operand read(s) and optional operand write(s) w i l l use the dynamic bus sizing and operand misal i g nment capab i l ities of the processor to transfer up to two or four long word operands respectively. Thus, w i t h i n both the read and write phases of the i ndivisible cycle, there may be u p to eight bus cycles to different ad d resses. Note that t h i s can i m pact bus arbitrat ion latency if CAS or CAS2 operands are not long word a l i g ned in a 32-bit port. Figure 5-23 depicts positional c lock i nformation for the read-modi fy-write operat ion. Act ual t i m i ng d iagrams specif ied in terms of c lock periods are g iven in SECTIO N 10 ELECTRICAL SPECI FICATIONS_
BUS MASTER Lock Bus S LAVE

11 Assert R M C

Start Input Transfer

11 21 31 41 51 61 71

Drive R/W to Read Drive Function Code on FCO-FC2 Drive Address on AO-A31 Drive SilO-Sill Assert ECS/OCS for One-Half Clock Assert Address Strobe IASI Assert Data Strobe IDSI 81 Assert D B EN

Present Data

Terminate Input Transfer

11 21 31 41 51

Latch Data Negate AS Negate D S Negate DBEN Start Data Modification

r.---

1 1 Decode Address 21 Place Data on DO-D31 31 Assert Data and Size Acknowledge I D SACKxl

I f CAS2 Instruction and Only One Operand Read, Then Go to ; If Operands Do Not Match Then go to ; Else Go to

f----.

Terminate Cycle

Start Output Transfer

1 1 Remove Data from DO-D31 21 Negate DSACK

r-

1 1 Set R/W to Write 21 Assert ECS/OCS for One-Half Clock 31 Assert AS 41 Assert D B EN 51 Place Data on DO-D31 61 Assert Data Strobe IDSI
Terminate Output Transfer

r---

Accept Data

11 21 31 41

Negate D S Negate AS Remove Data from DO-D31 Negate DBEN

--l

1 1 Store Data on DO-D31 21 Assert Data and Size Acknowlege I D SACKxl

Terminate Cycle

1 1 Negate DSACKx

Unlock Bus

r-. t

1 1 Negate R M C

Start Next Cycle

..

If CAS2 I nstruction and Only One Operand Written The Go to @ Else Go to CD

CD

Figure 5-22. ReadModify-Write Cycle Flowchart

5-24

SO CLK AO-A31 FCO-FC2 S llO-SIZ1

S2

S4

SO

S2

S4

=x =x =x " V "----J "----J "----J J---< \ \ \ / )

Indivisible Cycle

x x \ I V I / / / \ ( \ \ \ / "--I

R/W J
RMC ECS

AS
OS OSACKO OSACK1 OBEN 00-031
BG

lot

Figure 523. ReadModifyWrite Cycle Timing (32Bit Port, CAS Instruction)

525

5.2.4 CPU Space Cycles N ormal processor bus operat ions fal l i nto two d i st i nct classes: those which reference program areas and those which access data areas, as defined by the function code out puts. See 4.1 FU N CTION CODE SIG NALS (FCOFC2). A t h i rd c lass of operat ion i n cor porates those processor fu nct ions which do not properly fall i nto one of the above categories. These cyc les are c l ass ified as CPU space cycles (FCO-FC2 = 1 1 1 ) and i nc l ude i nterrupt acknowledge, breakpo i nt module operations, and coprocessor commun ica tions. The CPU space type is encoded on A 1 6-A1 9 d u r i n g a CPU space operat ion and i n d icates the fu nct ion that the processor is perform i ng. On the M C68020, four of the en cod i ngs are i m plemented as shown in F i g u re 5-24.

A l l u n u sed encod i ngs are reserved by M otorola for future extension of CPU space fu nctions. 5_2.4.1 I NTERRUPT O PERATION. The fol lowi n g paragraphs describe the recog nit ion and acknowledgement of i nterrupts for the M C68020. See 6.3.1 0 Interrupts for i nterrupt pro cess i n g deta i l s. 5.2.4. 1 .1 Interrupt Levels. The M68000 arch itectu re su pports seven levels of prioritized i nterru pts (level seven bei n g the h i ghest priority). Devices may be chai ned externally within i nterru pt priority levels, al low i n g an u n l i m ited n u m ber of devices to i nterru pt the processor. I nterru pt recog n ition and subsequent processing i s based on the encoded state of the I PLO-I PL2 control i nputs and the cu rrent processor priority set in the i nterrupt priority mask (12, 1 1 , 10) of M C68020 status reg i ster. I nterrupt req uest leve l zero (I PLO/i15'ITII PL2 = H H H) i nd i cates that no i nterru pt service is req uested. When an i nter rupt level one through s i x is requested via I PLO-I PL2, the processor compares the i n ter ru pt request leve l to the i nterru pt mask in order to determ i ne whether the i nterru pt should be processed. I nterru pt req u ests are ignored for all i nterru pt req uest leve l s that are less than or equal to the cu rrent processor priority determi ned by the i nterru pt mask. Level seven i nterrupts are non-maskable and are d iscussed further in 6.3. 1 0 Interrupts.

Function Code 2 31 Break pOi nt f"J11l 1 Acknowledge . Access Level 131 Control . 31 coprog::r I 31 InterruPt 1 1 Acknowledge
0 0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

: 23
I 0 0 0

Address Bus
19
0 0 0 0 0 0 0 0 0 1

0 0 0

0 0 0

0 0 0

16:

10

.
:

0 0

0 0

0 0 0

0 0 0

1 1 111 1 1 1 11 1 1 1 CPU S pace Type Field

, I

! CPID
.

10 : 15

13

10

MMU REG 4 1 CP REG 1 3 1 1 1 1 1 1 1 L EV EL 1 1 I

0 0 0 0 0

1
_

1 BKPT # 1 0

I.

Figure 524. MC68020 CPUSpace Address Encoding

5-26

Table 5-7 shows the relationship between the actual requested i nterrupt leve l , the i nter ru pt control l i nes (IPLO-I PL2), and the i nterrupt mask leve l s req u i red for recog n ition of the req uested i nterrupt. Table 5-7. Interrupt Control Line Status for Each Requested Interrupt Level and Corresponding Interrupt Mask Levels
Requested Interrupt Level Control Line Status L

IPl2 0* High High 1 2 High 3 High 4 Low 5 Low 6 Low 7 Low * Indicates that no i n terrupt is requested.

IP l High High Low Low High High Low Low

IP LO High Low High Low High Low High Low

Interrupt Mask Level Required for Recognition

N/A* 0 0-1 0-2 0-3 0-4 0-5 0-7

5.2.4. 1 .2 Recognition of Interrupts. To ensure t hat an i nterrupt w i l l be recog n ized, the fol lowi n g ru les should be followed : 1 ) The i ncom i n g i nterru pt req uest level must be at a h igher priority level than the mask level set in the status reg i ster (except for level seven, the non-maskable i nterru Pt). 2) The I PLO-I P L2 i nterrupt control l i nes must be held at the i nterrupt req uest level u n t i l the M C68020 acknow ledges the i nterru pt. See 5.2.4.1 .3 I nterrupt Acknowledge Sequence (lACK). The above ru les g uarantee t hat the i nterrupt w i l l be processed; however, the i nterru pt cou ld also be processed if the req uest is taken away before the l ACK bus cyc le. The M C68020 i n put synchron izat ion c i rcuitry for the I PLO-I PL2 control l i nes samples these i n puts on consecutive fal l i ng edges of the processor c lock in order to synchron ize and debou nce these s ig nals. An i nterrupt req uest that is held constant for two con secutive c lock periods i s considered a val i d i n put, and therefore it is possible that an i n terrupt req uest that is held for as short a period as two c lock cycles cou ld be recogn ized. I nterru pts recogn ized t hrough the process descri bed above do not force i m mediate ex cept ion processing but are made pend i n g . Only those i nterrupt req uests which exceed the cu rrent processor priority are made pend i ng, after the synchron izat ion and debounce delay, as described previou sly, and w i l l cause the assertion of I PE N D, s i g na l l i ng to exter nal devices that the M C68020 has an i nterrupt pend i ng . Exception process i n g for a pend i n g i nterrupt commences at the next i nstruction boundary, prov i d i ng that a h igher priority except ion is not also val id. See 4.7.2 Interrupt Pending (I PEND). 5.2.4. 1 .3 Interrupt Acknowledge Sequence (lAC K). When there is a pen d i n g i nterrupt at an i nstruction boundary, the M C68020 i n i t iates i nterru pt process i ng , provided that no h i g her priority exceptions are pendi ng. See 6.2 EXCEPTION PROCESSING. I n order to correct ly service an i nterru pt req uest, the processor m ust f i rst determ i ne the start i n g l ocat ion o f the i nterru pt service rou t i ne correspond i n g t o t h e requested service. The

5-27

M68000 Fam i ly s u pports acq u i sition of this i nformation with the i nterru pt acknowledge cyc le, d u r i n g which the processor acq u i res external ly, or generates i nterna l ly, the i nter rupt vector n u m ber. See 6.2.1 Exception Vectors. The M C68020 supports acq u isition of the i nterru pt vector n u mber by two methods. For those devices that have a vector reg i ster, the device may pass the vector to the processor over the data bus d u r i n g the l ACK cyc le. For those devices t hat can not supply an i nter rupt vector, the M C68020 u ses i nternally generated autovectors. The MC68020 l ACK seq uence i s the same for both cases, but the response of the i nterru pt i n g device d i ffers. At the beg i n n i ng of the l ACK cycle, the processor sets the function code and A 1 6-A1 9 to i n d icate CPU space seven , echoes the i nterrupt level bei n g acknow ledged on A1 -A3 and d rives the remai nder of the add ress bus high to i nd i cate that the CPU space access i s an i nterrupt acknow l edge cycle. The i nterru pt i n g device then either places an i nterrupt vec tor n u m ber on the least s i g n ificant byte of its data port and asserts DSACKO/DSACK1 to i nd i cate its port s ize, or it asserts AVEC to req uest that the processor i nternally generates the vector n u m ber correspond i n g to the requested i nterru pt leve l . F u rther deta i l of the lACK cycle i s provided in F i g u res 5-25, 5-26, and 5-27.
PROCESSOR Acknowledge Interrupt INTERRUPTING DEVICE Request Interrupt

1 1 Compare Interrupt Request Level with Interrupt Mask 2) Set R/W to Read 3) Set Function Code to CPU Space 4) Place Interrupt Level on A 1, A2, and and A3. Type Field lACK 5) Set Size to Byte 6) Assert Address Strobe (AS) and Data Strobe IDS)
=

Provide Vector Information

Acquire Vector Number

1 1 Place Vector N umber of Least Significant Byte of Data Port ( Depends on Port Size) 2) Assert DSACKx - or 1 1 Assert AVEC for Automatic Generation of Vector Number
Release

1 1 Latch Vector Number 2) Negate DS and AS

Start Interrupt Processing

1 ) Negate DSACKx

Figure 525. I nterrupt Acknowledge Sequence Flowchart

5-28

CLK A4-A31 A1 -A3 AO FCO-FC2 ' SIZ l SI ZO

so

S2

S4

so

S2

S4

so

S2

=>< '=>< ..J.. =>< =><

_ _ _ _

---J ! x 1
Interrupt Level

\'----X I... \
_ _ _ _

_ _ _

__ _ _ _ _

----' y \ .l......

...... _ _ _

_ _ _ _ _ _ _ _ _

_ _ _ _ _ _ _

=><

L.. /

---J I

'-__ \ \'---

DSACKO -.J r---\ __ \ _ DSACK1

/ \

'_ _ -'

/ \
Vector Number From 8-Bit Port

1 >--<= >--<= >--<=

D24-D31 D16-D23 DO-D7

ru-IPL2

J----<--""-\>--< )--{
v ;.:. _ _ ector _ ....;

J------<=:::::=:>--< \ >--<
0(

Vector Number From 16-Bit Port

.;.;., Number From 32-Bit Port

0(

..... _ _ _ _ _ _ _ _ _ _ __

I. Interrupt Acknowledge W" te Stac k

y -

Figure 526. Interrupt Acknowledge Cycle Timing

529

SO CLK A4-A31 Al -A3 AO FCO-FC2 SIZ l SIZO

S2

S4

SO

S2

S4

SO

S2

-y. -y. -y, ::::x -y. -y.

7 X 7 7 7
Interrupt Level

\ X \ \ L \ \

R /W J
ECS OCS AS OS OSACKO OSACK l

J\ /

/ / \ > X ..I_
Interrupt ACknOwledge Autovector

L / " \ / Write Stack

J\ ffiiEN =-oJ \ -< \ f.--- Read

00-031 I PLO-IPL2 AVEC

Figure 527. Autovector Operation Timing

530

5.2.4. 1 .4 Spurious Interrupt. I f, d u r i n g the i nterru pt acknowledge cycle, no device responds by assert i n g OSACKO/DSACK1 or AVEC, BERR should be asserted to term i n ate the vector acq u i sition. The processor separates the processing of t h i s error from a bus error by fetc h i n g the spurious i nterru pt vector i n stead of the bus error vector. The pro cessor then proceeds with the usual i nterru pt exception process ing. 5.2.4. 1 .5 lACK Generation. I n order to i nform external devices that the processor i s per form i n g an i nterru pt acknowledge cycle, it is normal to generate l ACK Signals for each of the seven i nterru pt leve l s. The l ACK signal for a part i c u l ar leve l can be derived by decod i n g the i nterru pt level from A 1 A3 and qual ifying t h i s with the function codes high (CPU space), the CPU space type (A1 6A 1 9) high (type $F), and address strobe (AS) asserted. 5.2.4.2 B R EAKPOINT ACKNOWLEDG E CYCLE. When a breakpoi nt i nstruct ion is exe cuted, the M C68020 performs a word read from the CPU space, type 0, at an address cor respon d i n g to the breakpoi nt n u m ber (bits [2:0] of the opcode). I f this bus cycle is termi nated by B E R R, the processor then proceeds to perform i l legal i nstruct ion except i on pro cessi ng. If the bus cyc le is term i nated by OSACKx, the processor uses the data retu rned on 0 1 6 031 (for 1 6bit or 32bit ports) or two reads from 024031 (for 8bit port) to rep lace the breakpoi nt i nstruct ion in the i nternal i nstruction p i pe l i ne, and beg ins execution of t hat i nstruct ion. The breakpoint operat ion f l ow is shown in F i g u re 528. Figures 529 and 530 show the t i m i ng diagrams for the breakpoint acknow ledge cyc le with the i n struction opcodes suppl ied on the cycl e and with an exception s i g naled, respectively.
PROCESSOR Breakpoint Acknowledge EXTERNAL DEVICE

1) 2) 3) 4) 5) 6)

Set R/W to Read Set Function Code to CPU Space Place CPU Space Type 0 on A 16-A 1 9 Place B reakpoint Number on A2-A4 Set S IZE to Word Assert AS and DS

If DSACK Asserted: 1 ) Latch Data 2) Negate AS and DS 3) Go to If BERR Asserted: 1 ) Negate AS and DS 2) Go to

1 1 Place Replacement Opcode on Data Bus 2) Assert DSACKx - or 1 1 Assert BERR to Initiate Exception Processing

1 1 Place Latched Data in I nstruction Pipeline 2) Continue Processing 1 1 Initiate Illegal Instruction Processing

Slave Negates DSACKx or B E R R

t
Figure 528. MC68020 Breakpoint Operation Flow

531

Figure 529. Breakpoint Acknowledge Cycle Tim ing (Opcode Returned)

532

ClK A20-A31 A16-A19

SLJLJLJ1S lJLJ ::::x

Breakpoint Encoding [0000]
....l _ _ '-_ _ _ _
_

SO

S2

S4

SO

S4

1SUL I I =x_ I := := =:J<_ I - --v-

_ _

::::x - ----....--- - \ '-Breakpoint Number A2-A15 =>< '--' 'X

_ _ _ _ _ _ _ _ _

_ _ _ _ _ _

A1-AO FCO-FC2 S IZ1 S IZO R/W ECS OCS AS OS OSACKO OSACK1

\ '::::x J

_ _ _ _ _ _ _ _ _ _ _

::::x '-::::x

_ _ _ _

_ _ _ _

...J y -' 7 \ ->--

CPU Space

Word

\------

_ _ _ _ _

_ _ _ _ _

V V

v V

- - --v-'-- --

/\ --\ '-

r--\ \ _ / '-- ---J /

....J>- - - - - - )- - - -- 024-031 --< ) 08-015 .J----<===J)f---

016-023
_ _ _

00-07 BERR HALT

.J----<===})--] ] Read
Breakpoint Acknowledge Bus Error Asserted I t(
_

_I

I Stacking
_

Exception

Figure 530. Breakpoint Acknowledge Cycle Timing (Exception Signalled) 5-33

5.2.4.3 COPROCESSOR OPERATIO NS. The MC68020 coprocessor i nterface al lows for i nstruct ionoriented com m u n icat ion between the processor and up to e i g ht coprocessors. The bus com m u n icat ion req u i red to support coprocessor operations i s carried o u t i n the M C68020 C P U space. Coprocessor accesses u t i l ize standard bus protocol except that the address bus sup pl ies access i nformat ion rather t han an address. The CPU space type field (A 1 6-A 1 9) for a coprocessor operat ion is 001 0. The coprocessor identif icat ion n u mber is encoded i n A 1 3-A 1 5 and AO-A5 ind icate the coprocessor i nterface reg i ster t o be accessed . The memory management u n i t of an M C68020 system i s always identif ied by coprocessor I D zero and has a n extended reg i ster select field (AO-A?) i n CPU space 0001 for use by the CALLM and RTM access level checking mechanism . 5.2.5 Bus Error a nd H alt Operation I n a bus arch itecture t hat req u i res a handshake from an external device to s i g nal that a bus cycle is com plete, the poss i b i l ity exists that the handshake m i g ht not occur. Si nce d ifferent systems req u i re different max i m u m response ti mes, a bus error i n put i s pro vided; see 4_9.3 Bus Error (B ERR)_ External c i rcu itry must be u sed to determ i ne the maxi mum d u ration between the assertion of address strobe (AS) and data t ransfer and s ize acknowledge (DSACKx) before issuing a bus error signal. When a BERR and/or HALT s i g nal is received, the processor i n it iates a bus error exception seq uence or ret ries the bus cyc le. In addition to a bus t i meout i nd icator, the BERR i n put i s u sed to i nd i cate an access fau lt in a protected memory scheme or a page/segment fau lt in a virtual memory system. When an external memory management unit detects an i nva l i d memory access, a bus error i s generated to su spend execution of the cu rrent i nstruction. 5.2.5_1 BUS E R RO R OPERATIO N . When the bus error s i gnal i s i ssued to term i nate a bus cyc le, the M C68020 may enter exception processing immed iately following the bus cycle, or may defer processing the exception u n t i l it needs the data that it was attempt i n g to access. Due to the h i g h l y pipeli ned arch itectu re of the M C68020, the processor attempts to prefetch i nstructions ahead of the cu rrent program cou nter. If the M C68020 en cou nters a bus error d u r i n g an i nstruction prefetch, the processor defers bus error excep tion processi n g u n t i l the fau lted data is act u a l ly needed for execution. It is poss ible that bus error processing w i l l not take place for a fau lted access if changes in program flow (e.g., branches) make u sage of the fau lted data u n n ecessary. The bus error s i g nal w i l l be recognized d u r i n g a bus cycle in either of the follow i n g cases: 1) DSACKx and HALT are negated and BEAR" is asserted. 2) H A LT and BERR are negated and DSACKx is asserted. BERR is then asserted w i t h i n one c lock cyc le. 3) BERR and HALT asserted. When the bus error cond ition i s recogn ized, the cu rrent bus cyc le i s termi nated i n the nor mal fash ion. F i g u res 5-31 and 5-32 show the t i m i ng d iagrams for both the normal and the delayed bus error s ig nals, ass u m i n g that the except ion is taken. See 6.3.3 Bus Error for except ion processing deta i l s .

5-34

5.2.5.2 RETRY OPERATION. When, d u r i n g a bus cyc le, the BERR and HALT i n puts are both asserted by an external device, the processor enters the retry seq uence. A delayed retry may be used, s i m i lar to the delayed bus error s i g nal descri bed above. F i g u res 5-33 and 5-34 show t i m i ng d iagrams for both methods of retrying the bus cycle.
Sw Sw Sw S4
_ _

_ _ _ _ _ _ _____

_ _ _ _ _

_____

x = = = )(

X::: x::: x= x:::

X = = = )(
-

_ _ _ _ _

_ _ _ _ -----l

= = = ==y X X - - - - )( \
-

- - -

'---

- -

'-----

_ _ _

_____

r-

- - -

_ _ _ _ '---

r -----'

- - -

\ f

DO-D31
HALT
BEAR

\ f - - - - - '-----

- __ -- _ _ _ _ _ _ = == }

---<'-----'I_I Stack Write

-

I..

Read Bus Error Detection

\'------/
-

-i .

1 Processing Internal

--

- -

Figure 531 . Bus Error Timing (Exception Taken)

5-35

Sw

Sw

S4

SO

S2

S4
_

_ _ _ _

_ _ _ _ _

'--' = = = = =:x X X n - - - =:x X - - - - - =x

-

_ _

X x

_ _ _ _

_ _ _ _ "_ _ _ _ _

-----' = = = = =x X

x x
_ _ _ _

----' - - - - \ 1 '
-- - - - - -

____ _ _ _ '---

r-- - --'----_---'r n ----/ \ \ / \ r---- - - - -

\
'-- -

I.- _ _ --- _ _ _ DO-D31 -

}_ ----' -

- u

_ _

}_

BE RR

III(-- Write Bus Error

_ _ ..

-.! I

Internal Processing

I- Stack Write --+l

Figure 532. Delayed Bus Error (Exception Taken)

536

SO ClK AO-A3l FCO-FC2 S IZl S IZO

S2

Sw

S4

SO

S2

S4

-y., -y., -:x =x-

x::: x::: x::: x::: V V / / \ \ \ \ ) \ / _I

Halt

R/W J
ECS

J J J--<

\ \ ! ! / / )

ocs V
AS DS
i5SACKO

DSACK l DO-D3l I P lO-IPl2

<

J BERR J

HAlT J

\- Read
\

_I

Rerun

Figure 533. Delayed Bus Cycle Retry Timing

537

SO ClK AO-A31 FCO-FC2 S IZl S IZO R/W ECS

S2

Sw

S4

SO

S2

S4

:J( :J( :J( Y V / / / / ) \

Read

' ' ' ' V V \ \ \ \ ( \ \ I I / / )

ocs V
AS OS OSACKO OSACKl

00-031 J------< J BERR J -.I

IPlO-IPl2

/ /
Halt

HALT

I_

_I_

_I_

Rerun

----....J

Figure 534. Retry Operation Timing

538

The processor term i nates the bus cyc le, places the control signals i n their i nactive state and does not run another bus cyc le u n t i l the BERR and HALT s i g nals are negated by external logic. The processor then ret ries the previous cyc le u s i n g the same access i n for mation (address, function code, s ize, etc.). The BERR s i gnal should be negated before or in conj unction with the HALT signal. The M C68020 i m poses no restrictions on retrying any type of bus cyc le. Spec if1cally, any read or write cyc le of a read-modify-write operation may be separately ret ried, si nce the RMC s i g nal w i l l remain asserted d u r i n g the ent i re retry seq uence. Systems des i g ners who u t i l ize the rel i nq u i s h and ret ry operat ion (BERR, HALT, and BR asserted) must g ive spec ial cons iderat ion to the read-mod ify-write operat ion s i nce the M C68020 w i l l not rel i nq u i s h the bus d u r i n g this operat ion. Any device req u i ri n g that the processor g ive up the bus and retry the bus operation during a read-mod i fy-write cycle must assert BERR and BR (HALT must not be i n c l uded). The bus error handler software should exam i n e the RM bit in the special status word (see 6.4.1 Special Status Word) and, if set, the handler can take the appropriate act ion to resolve the fau lt. 5.2.5.3 HALT O PERATION. The HALT i n put s i g nal to the MC68020 performs a halt/ru n/s i ng l e-step function. The halt and run modes are somewhat self explanatory i n that when the halt s i g nal is constantly asserted t h e processor "halts" (does noth i ng) and when the H A LT s i g nal i s constantly negated the processor "runs" (does somet h i n g). N ote that the HALT s i g nal o n ly halts the operat ion of the external bus, not the i nternal bus and execution u n it. Thus, a program that resides in the cache and does not req u i re use of the external bus w i l l not be affected by the H A LT signal. The s i n g le-step mode i s derived from correct ly ti med t ransitions on the HALT i n put. If HALT i s asserted when the processor beg i n s a bus cyc le and remains asserted, that bus cyc le w i l l com plete, but another cyc le w i l l not be a l l owed to start. When it is desi red to conti n ue, HALT i s then negated and re-asserted when the next bus cycle i s started. Thus, the s i n g le-cyc le mode al lows the u ser to proceed through (and debug) processor opera tions, one bus cyc le at a ti me. The t i m i ng req u i red for correct s i n g le-step operat ion i s detai led in F i g u re 5-35. Some care m u st be exerci sed to avoid harmfu l i nteractions between the BERR and the HALT s i g nals (see 5_2.5.2 RETRY OP ERATION) when u s i n g the s i n g le-cyc le mode as a debug g i n g tool. When the processor com pletes a bus cyc le after recog n izing that the HALT signal i s ac tive, the bus control s i g n a l s are placed in the i nactive state; but the address, fu nction code, s ize, and read/write l i nes rema i n driven. While the processor i s honori ng the halt req uest, bus arbitration performs as usual. See 5.2.7 Bus Arbitration. That is, halting has no effect on bus arbitration. The s i n g le-step operat ion described above and the software trace capabi l ity al low the system debugger to trace s i n g l e bus cycles, s i n g l e i nstructions, or changes in program flow. These processor capabi l i ties, along with a software debu g g i n g package, g ive com plete debu g g i n g flex i b i l ity. 5.2.5_4 DOU BLE BUS FAU LTS_ When a bus error except ion occu rs, the processor at tempts to stack several words contai n i n g i nformation about the state of the mach i ne. If a 5-39

SilO -Sil l :::x

R /W

FCO-FC2 :::x
A A31

O-

SO S2 S4 SO S2 S4 ClK JLJ1SlJl-.- I L

:::x

)- - ---\ )- - ---\

x= x=

ECS V

)- - -< x= '- _ ---.I --

\J

AS

OS '- -

-- '- - --\ I

\I...----JI
\.-._ _ __

00-031

-\--'I J---< --' - - - ---- >)_ _ __

\'---- - - \J \_
---l ... .

Read

\_J '-- Halt I.... .1...

(Arbitration permitted while the processor is haltedl

Read

----.j

Figure 535. H a lt Operation Timing bus error exception occurs d u r i n g the stacking operat ion, there have been two bus errors in a row. This is referred to as a double bus fault. When a double bus fau lt occu rs, the pro cessor halts and d rives the H A LT line low. Once a bus error exception has occu rred, any add itional bus error exception occu rri n g before the execut ion of the f i rst i nstruct ion of the bus error handler rou t i ne constitutes a double bus fau lt. 540

Note that a bus cyc le t hat is re-tried does not constitute a bus error exception and does not contribute to a double bus fault. N ote also that this means t hat as long as the exter nal hardware req uests it, the processor w i l l conti nue to retry the same bus cyc le. The occu rrance of an address error, simi lar to that of a bus error, is c lassified as an ex cept ion that may contribute to a double bus fau lt cond ition. See 6_3_2 Address Error_ The bus error i n put also has an effect on processor operation after the processor receives an external reset i n put. After reset, the processor reads the vector table to deter m i n e the address to start program execution and the i n itial value of the i nterrupt stack pointer. If a bus error or add ress error occurs while read i n g the vector table (or at any time before the first i nstruction i s executed), the processor reacts as if a double bus fau lt has occu rred and halts. O n ly an external reset can re-start a halted processor. From the above conditions a double bus fau lt is defined as the occu rrance of an address error or bus error d u ri n g the except ion processing for an address error, bus error, or reset except ion. 5_2_6 Reset Operation The RESET s i g nal is a bidirectional s i g nal that al lows either the processor or an external device to reset the system. Figure 5-36 is a t i m i n g d iagram for the power-up reset operat ion. When the RESET signal i s driven by an external device (for a m i n i m u m of 520 clock peri ods), it is recogn ized as an entire system reset, i nc l ud i n g the p rocessor. The pro cessor responds by com plet i n g any active bus cyc le in an orderly fash ion, and then

Plus 5 Vo i ts - - - - - - -I= - - - ==_::;:= r t >520 Clocks--\ ' '. l V CC - t<4 Clocks ---...l I - I r - - \ RESET -,L I- - - I- 4 Clocks ---...J '<'7r 7r7<C --r 1r1r '7'r7'< ._x7\ 1r 7t"7'r "l't'7'I r70 1 I BUS CYCleS nr. I<'7<" r 'I C ISP NOTES: Read Starts Bus State Unknown: All Control Signals Inactive Data Bus In Read Mode
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -

ClK

Figure 5-36_ Externa l Reset Operation Timing

5-41

read i n g the reset vector table entry (vector n u mber zero, address $00000000) and loads it i nto the i nterrupt stack pointer (ISP). Vector table entry n u m ber one at address $00000004 is then read and loaded i nto the program counter. The processor i n itial izes the status register to a mask level of seven with the T1 /TO and M bits cleared and the S bit set. The vector base reg i ster i s i n itial ized to $0000000 and the cache enable bit in the cache con t rol register i s cleared . No other reg i sters are affected by the reset seq uence.
When a reset i nstruction is executed, the processor drives the RESET pin for 5 1 2 clock cyc les. In this case, the processor i s resetting the rest of the system. Therefore, there is no effect on the i nternal state of the processor. A l l the i nternal reg isters of the processor and the status reg i sters are u naffected by the execut ion of a reset i nstruction. A l l exter nal devices con nected to the RESET l i ne are reset at the completion of the reset i nstruc tion. Figure 537 shows the t i m i n g i nformat ion for the i nstruction.

N ote that i n order to cause an external reset i n all cases, i ncluding when the processor is executing a reset i nstruction, the RESET s i g nal must be driven as an i n put for 520 c lock cycles. If the reset i nstruct ion w i l l not be executed, or external log ic can detect the asser tion of RESET by the processor and compensate for that cond i t ion, the shorter assert ion of R ESET of ten c lock cycles i s all that i s req u i red to reset the processor. 5.2.7 Bus Arbitration Bus arbitration is a tec h n ique used by bus master type devi ces to req uest, be g ranted, and acknowledge bus mastership. In its s i m p lest form, the bus arbitrat ion protocol con sists of the following: 1. an external device asserts a bus request to the M C68020, 2. the processor asserts bus g rant to i nd i cate that the bus w i l l be avai lable at the end of the cu rrent bus cyc le, and 3. the external device acknowledges that it has assu med bus masters h i p by assert i n g bus g rant acknow l edge.

542

CLK FCO-FC2 -y SIZO "Y.

R/W

AO-A31 Y
SIZl -:x

.J

=x== =x== =x== =x==

OCS 'J

ECS 'J AS i\ oS T\.

/ / / / / )

L "-

oSACKO oBEN

oSACK1

00-031
HALf

J----< /

\ ----<C J Resume \'--- Reset Interval I Normal -l 512 Clocks Operation

_

RESET

I-- Fetch--.j

Figure 537. Processor Generated Reset Operation

543

F i g u re 538 is a flowchart show i n g the deta i l i nvolved i n bus arbitration for a s i ng l e device. F i g u re 539 i s a t i m i ng d iag ram f o r t h e same operat ion. This tec h n ique al lows pro ces s i n g of bus req u ests d uring data t ransfer cyc les.
PROCESSOR REQUESTING DEVICE

Grant Bus Arbitration

1 1 Assert Bus G rant ( B G )

11 Assert Bus Request ( B RI

Request the Bus

Acknowledge Bus Mastership

I I

11 Negate BG and Wait for BGACK

to be Negated

Terminate Arbitration

I I

1 1 External Arbitration Determines Next Bus Master 21 Next Bus Master Waits for Current Cycle to Complete 31 Next Bus Master Asserts Bus Grant Acknowledge ( BGACKI to Become New Master 41 B us Master Negates B R
Operate a s Bus Master

1 1 Perform Data Transfers ( Read and Write Cyclesl

Release Bus Mastership

I I

Rs-Arbitrate or Resume Processor Operation

1 1 Negate BGACK

Figure 538. Bus Arbitration Flowchart for Single Request The t i m i ng diagram shows that the bus req uest (BR) is negated at the time t hat bus g rant acknowledge (BGACK) i s asserted. This type of operat ion i s true for a system consisting of the processor and one device capable of bus masters h i p. I n systems having a n u m ber of devices capable of bus masters h i p, the bus req u est l i ne from each device i s w i re ORed to the processor. In such a system, it is possible that there could be more than one bus req uest asserted s i m u ltaneously. The t i m i n g d iagram i s F i g u re 539 shows that the bus g rant (BG) signal i s negated a few c lock cycles after the transition of the bus g rant acknowledge s i g n a l . H owever, if bus reo q uests are sti l l pend i n g after the negation of bus g rant, the processor w i l l assert another bus g rant w i t h i n a few c l ock cycles after it was negated. This add i t i onal assertion of bus g rant al lows external arbitrat ion c i rcu itry to select the next bus master before the cu rrent bus master has completed u s i n g the bus. The following parag raphs provide add i t i onal i n formation about the th ree steps i n the arbitration process.

544

ClK AO-A31 FCO-FC2

=x

__ __ __

YO J

SIZO/ SIZl
R/IN ECS

=x

- -------------

-- -- -- c= ) -------- -- -- r-) c= c=
r__

V \ \
'--

ocs \J
AS DS DSACKO DSAC K 1

\.J \.J f' /" /

__ __ __ __ __ __ __ __ __ __ __

DO-D31

BR \

--------

/" ( -- ) -'

r__

\'-----/
Processor

4 1I""

. f---

\'-----/
DMA Device

---..J

I- Processor

Figure 539. Bus Arbitration Operation Timing

545

5.2.7.1 REQU ESTI NG T H E BUS. External devices capable of becom i ng bus masters re quest the bus by assert i n g the bus req uest (BR) signal. This is a wi re-ORed s i g nal (althoug h it need not be constructed from open-col lector devices) that i nd icates to the processor that some external device req u i res control of the bus. The processor is effec tively at a l ower bus priority level than the external device and re l i nqu i shes the bus after it has completed the cu rrent bus cyc le if one has started. If no acknowledge is received before the bus req uest s i g nal is negated, the processor cont i n ues execution once it detects that the bus req uest is negated. This al lows ord i nary process i n g to cont i n u e if the arbitration c i rc u i t ry i nadvertently responded to noise or an external device determ i nes t hat it no longer req u i res use of the bus before it has been g ranted masters h i p .

5.2.7.2 RECEIV I N G TH E BUS G RANT. The processor asserts bus g rant (BG) as soon as possi ble after recei pt of the bus req uest. N orma l ly t h i s is i m med iately follow i ng i nternal synchronization but there is one except ion to this ru le. The exception occu rs when a read-mod ify-w rite (RMW) cyc le i s i n progress. The processor w i l l not assert bus grant u n t i l the entire RMW cyc le i s comp lete. During the RMW operat ion, the RMC signal w i l l be asserted to i n d i cate that the bus is locked. The bus g rant s i g n a l may be routed through a daisy-chai ned network or th roug h a specific priority-encoded network. The processor is not affected by the external method of arbitration as long as the protocol is obeyed.

5.2.7.3 ACKNOWLEDG EM ENT OF MASTERSH I P. U pon receiving a bus g rant, the re questing device waits u n t i l address strobe, data transfer and s ize acknowledge, and bus g rant acknowledge are negated before assert i n g its own BGACK. The negation of the AS i n d i cates that the previous master has com pleted its cyc le; the negat ion of BGACK i n d i cates that the previous master has released the bus. The negation of DSACKx i nd i cates the previous s l ave has termi nated its connect ion to the previous master. N ote that i n some appl i cations DSACKx m ight not enter i nto this function. General pu rpose devices are then connected such that they are o n ly dependent on address strobe. When bus g rant acknow ledge i s asserted , the device i s the bus master u n t i l it negates BGACK. Bus g rant acknow l edge should not be negated u n t i l after a l l bus cycles req u i red by the alternate bus master are completed. B u s masters h i p i s termi nated at the negat ion of bus grant acknowledge. The bus req uest from the granted device should be negated after bus g rant acknowledge i s asserted . If a bus request i s sti l l pen d i n g after the assert ion of BGACK, another bus grant w i l l be asserted w i t h i n a few c locks of the negation of the bus grant. Refer to 5.2.7.4 BUS ARBITRATION CONTROL. N ote that the processor does not perform any external bus cyc les before it reasserts bus g rant.

5-46

5.2.7.4 BUS ARBITRATIO N CONTROL. The bus arbitration control u n i t i n the MC68020 i s implemented with a f i n ite state mac h i ne. As d iscussed previous ly, a l l asynchronous i n puts to the M C68020 are i nterna l ly synchron ized i n a max i m u m of two cyc les of the system c lock. As shown in F i g u re 5-40, i n put signals labeled R and A are i ntern a l ly synchronized ver sions of the bus request and bus grant acknowledge p i ns respectively. The bus grant out put is labeled G and the i nternal th reestate control s i gnal T. If T i s true, the address, data, and control buses are placed in the high i m pedance state when AS and RMC are negated. A l l S i g nals are shown in pos it ive logic (active h i g h) regardless of their true ac tive voltage leve l . State changes occur on t h e next riSing edge o f t h e c lock after t h e i nternal s i g n a l i s va l id. Outputs change on the fal l i ng edge of the clock after a state is reached. A t i m i ng diagram of the bus arbitration seq uence during a processor bus cyc le is shown in F i g u re 5-39. The bus arbitration seq uence w h i l e t he bus i s i n active (Le., executing i nter nal operat ions such as a m u lti ply i nstruction) is show n i n F i g u re 5-41 .

R Bus Request A - Bus Grant Acknowledge G - Bus G rant T Three-State Control to Bus Control Logic Dont Care NOTE: The BG output will not be asserted while R M C is asserted.
-

540. Bus Arbitration State Diagram

547

-------4C== >------<c==
__ __ __ __

r---- c==

----- __ __ __ __ __ __ r__

>------<L v v ------ '-------

__ __ __ __ __ __ __ __ __

__J I

------(
__ '--

-J /

-iI+t--- Alternate Master

'-----/

---+- Processor

Figure 541 . Bus Arbitration (Bus Inactive)

548

5.2.8 The Relationship of DSACK, BERR, and HALT I n order to properly control term i nation of a bus cyc le for a retry or a bus error cond it ion, DSACKx, B E R R, and H A LT should be asserted and negated on the rising edge of the MC68020 clock. This w i l l ass u re that when two signals are asserted s i m u ltaneously, the req u i red setup t i me (#47) and hold t i me (#53) for both of them w i l l be met during the same bus state. This, or some eq u ivalent precaution, should be desig ned external to the M C68020. The preferred bus cyc le term i nations may be sum marized as follows (case nu mbers refer to Table 5-8). N ormal Term i nation: DSACKx is asserted, BERR and H A LT remain negated (case 1 ). Halt Term i nation: H A LT is asserted at same ti me, or before DSACKx and BERR remains negated (case 2). Bus Error Term i nation: 'B'ERR i s asserted in l ieu of, at the same t i me, or before DSACKx (case 3) or after DSACKx (case 4) and HALT re mains negated; BERR is negated at the same t i me or after DSACKx. Retry Term i nation: H A LT and B'E'R'R are asserted i n l ieu of, at the same t i me, or before DSACKx (case 5) or after DSACKx (case 6); BERR is negated at the same t i me or after DSACKx, H A LT may be negated at the same t i me, or after BERR. Table 58. DSACK, BERR, and HALT Assertion Results
Asserted on Rising Edge of State N N +2 Result

Case No.

Control Signal

1 2 3 4 5 6 LEGEND: N A NA X S -

DSACKx BERR HALT DSACKx BERR HALT

HAIT

BE RR
BERR

DSACKx HALT DSACKx BERR HALT DSACKx EiEtiR" HALT

A NA NA A NA A/ S NA/A A NA A NA NA NA/A A A/ S A NA NA

S NA S NA S X S NA X A NA X S S A A

Normal cycle terminate and continue. Normal cycle terminate and halt. Continue when FIAIT removed. Terminate and take bus error trap. possibly deferred. Terminate and take bus error trap, possibly deferred. Terminate and retry when HALT removed. Terminate and retry when HALT removed.

the number of current even bus state (e. g . , S2, S4, etc.1 signal is asserted in this bus state signal is not asserted in this state don't care signal was asserted in previous state and remains asserted in this state

5-49

Table 5-8 deta i l s the res u l t i n g bus cycle term i nation u nder various com b i nations of con trol signal sequences. The correct t i m i ng for negation of BERR and HALT should also be ut i l ized to ensure pred i ctable operat ion. For the bus cyc le retry operat ion BERR must be negated prior to, or at the same time as HALT. DSACKx, BERR, and HALT may be negated when AS is negated. If DSACKx or BERR remain asserted i nto S2 of the next bus cyc le, this may cause i ncorrect bus operat ion. EXA M PLE A: A system u ses a watch-dog ti mer to termi nate accesses to an u n popu lated address space. The t i mer asserts BERR after t i me out (case 3). EXAM PLE B: A system u ses error detect ion and correct ion on RAM contents. Desig ner may: a) Delay DSACKx u n t i l data verified, and assert i3'ERR and H A LT. s i m u lta neou sly to retry error cyc le (case 5), or if val id assert DSACKx (case 1 ). b) Delay DSACKx u n t i l data verified, and assert BERR at same t i me as DSACKx if data i n error (case 3). c) Return DSACKx prior to data verification, as descri bed in the next section. If data i s inva l id, B E R R is asserted on next c lock cycle (case 4). d) Ret urn DSACKx prior to data verif icat ion, if data is i nva l i d assert BERR and H A LT on next c lock cycle (case 6). The memory controller may then correct the RAM prior to or during the retry. 5.2.9 Asynchronous Versus Synchronous Operation 5.2.9.1 ASYN C H RONOUS O PERATION. To achieve c lock freq uency i ndependence at a system level , the M C68020 can be u sed i n an asynchronous manner. This req u i res u s i n g only the bus handshake l i nes (AS, DS, DSACK1 , DSACKO, B E R R , a n d H A LT) to control the data transfer. U s i n g t h i s method, AS s i g na l s the start of a bus cycle and DS i s u sed as a cond ition for val id data on a w rite cyc le. Decode of the size outputs and lower address l i nes A 1 and AO provide strobes which i ndicate which portion of the data bus i s active. The s l ave device (memory or peri pheral) then responds by placing t he requested data on the correct portion of the data bus for a read cyc le or latch i n g the data on a w rite cycle and assert i n g data transfer and s ize acknowledge (DSACK 1 IDSACKO) correspond i n g to the port size to term i nate the cycle. If no slave responds, or the access is invalid, external control logic asserts the B E R R, or BERR and HALT signal(s) to abort or retry the bus cyc le. The DSACKx signals are al lowed to be asserted before the data from a slave device is val id on a read cyc le. The length of t i me that DSACKx may precede data is g iven as parameter #31 , and it m u st be met i n any asynchronous system to insure that va l i d data is latched i nto the processor. N otice t hat there is no max i m u m t i me spec ified from the assertion of AS to the assertion of DSACKx. This is because the M PU w i l l i n sert wait cycles in one c lock period increments u n t i l DSACKx is recogn ized as asserted.

5-50

The- BERR and/or H A LT signals are al lowed to be asserted after the DSACKx s i g nal is asserted. BERR and/or H A LT must be asserted w i t h i n the t i me g iven as parameter #48 after DSACKx is asserted i n any asynchronous system to i ns u re proper operat ion. If this max i m u m delay time i s violated, the processor may ex h i bit errat i c behavior. 5.2.9.2 SYNCH RONOUS O PERATION. To su pport those systems which use the system clock as a S i g nal to generate DSACKx and other asynchronous i n puts, the asynchronous i n put set up t i me is g iven (parameter #47), and the asynchronous i n put hold t i me i s g iven (parameter #53). If this set up and hold time is met for the assert ion or negat ion of an i n put, such as DSACKx, the processor is guaranteed to recog nize that signal level on that specific fal l i ng edge of the system clock. H owever, the converse is not true - if the i n put s i g nal does not meet the set u p and/or hold t i me, that level i s not guaranteed not to be recog n ized. In add ition, if the assert ion of DSACKx i s recogn ized on a fal l i ng edge of the c lock, val i d data w i l l be latc hed i nto the processor (on a read cycle) on the next fa l l i ng edge provided that the data meets the set u p time (parameter #27). G iven this situation, parameter #31 may be ignored. N ote t hat if DSACKx is asserted for the req u i red wi ndow around the fa l l i ng edge of S2 (and obeys the proper bus protocol), no wait states w i l l be i ncu rred and the bus cyc le w i l l run at its max i m u m speed of three clock periods. In order to assure proper operat ion i n a synchronous system when BERR and/or H A LT is asserted after DSACKx, BERR and/or H A LT m u st meet the setup time (parameter #27A) prior to the fal l i n g edge of the clock one clock cyc le are DSACKx is recog n ized as asserted. Th i s setup t i me is critical for proper operat ion, and the M C68020 may exh i bit er rat i c behavior if it is violated. The ECS (early cyc le start) s i g nal is provided on the MC68020 to provide the earl iest poss ible i nd i cation that t he processor is beg i n n i n g a bus cyc le. I n a sync h ronous system, the ECS output can be ut i l ized to i n i t iate address decode in order to provide i m proved memory access t i me. H owever, the ECS output i nd icates o n ly that the processor may be i n itiat i n g a bus cycle. The M C68020 may i n i t iate a bus cyc le by driving the address, size, and function code outputs and assert i n g ECS, but if the processor f i nds the data in the on-c h i p i nstruction cache, the cyc le w i l l be aborted before assert i n g AS.

5-51 /5-52

S ECTION 6 P ROCESS I N G STATES

Th i s section descri bes the behavior of the processor during i nstruction execution as governed by the processi n g state of the machi ne. The functions of the bits in the su per visor portion of the status reg i ster are explai ned, as well as the actions taken by the pro cessor i n response to exception cond itions. The processor i s always i n one of three processi n g states: normal, except ion, or halted . The normal process i n g state occurs during i nstruct ion execution, i nc l u d i n g the bus cyc les to fetch i nstructions and operands, and to store the results and comm u n i cate w i t h a coprocessor, if necessary. The stopped cond ition, which the processor enters when a STOP i nstruct ion is executed, is a special case of the normal state i n which no furt her bus cyc les are generated. The exception processi n g state is assoc iated with i nterru pts, trap i nstructions, traci ng, and other except ional cond i tions. The exception may be i ntern a l ly generated by an i n struction or by an u nusual cond ition ari s i n g during the execution of an i nstruction. Except ion processi n g can also be i n itiated by cond itions external to the processor such as an i nterru pt, a bus error, a reset, or a coprocessor pri m i t ive command. Exception pro ces s i n g i s desi g ned to provide an eff icient context switch so that t he processor may q u i ckly and g racefu l ly hand le u nusual cond itions. The halted process i n g state i s caused by a catastrophic system fai l u re. For examp le, if during the exception processi n g of a bus error another bus error occu rs, the processor assumes that the system is u n usable and halts. Only an external reset can restart a ha lted processor. N ote, a processor i n the stopped state is not i n t he halted state. 6.1 PRIVILEGE STATES The processor operates at one of two level s of privi lege: the user level or the su pervisor l evel. These l evels are ordered, with t he s u pervisor level bei n g of h i g her privi lege than the user level. N ot a l l processor i nstructions are permitted to execute i n the lower-privi leged user state, but all are avai lable in the su pervisor state. The privi lege level can be used by external memory management devices to control and translate accesses, and i nternally by the processor in order to choose between the user stack pOi nter and the su pervisor stack poi nter during operand references. The M C68020 provides a mechanism to a l l ow external hardware to enforce up to 256 privi lege level s w i t h i n the u ser level of privi l ege. This mechan ism is an opt ional part of the mod u l e cal l/return operat ions descri bed in APPENDIX D ADVANCED TOPICS.

6-1

6.1 .1 Use of Privilege States The privi lege level is a mechan i s m for providing secu rity in a computer system. User pro g rams may access only their own code and data areas, and can be restricted from ac cessing other i nformat ion. User program behavior is more easi ly g uaranteed when errors by other programs in the system cannot affect it. The privi lege mechanism provides secu rity by al low i n g most prog rams to execute i n user state. Here accesses are contro l led, and their effects on other parts of the system are l i m ited. The operat i n g system typica l ly executes in t he supervisor state, has access to a l l resou rces, performs the overhead tasks for the u ser state programs, a n d coord inates their activit ies. 6.1 .2 Supervisor States The su pervisor state is t he h i g her privi lege state. For i nstruction execution, the su per visor state is determi ned by the S bit of the statu s register; if the S bit is set, the pro cessor is in the s u pervisor state, and a l l i nstructions are executable. The bus cyc les generated by i nstructions that are executed in the su pervisor state are norma lly classified as su pervisor references, which i s reflected i n the va l ues placed on the fu nc tion code p i n s FCOFC2. The M C68020 al lows a m i nor d istinction of su pervisor act ivities, based on the M bit of the status register. The pu rpose of the M bit is to al low separation of task related and asyn chronous, I/O related su pervisor tasks, s i nce in a m u l t i-tasking operat i n g system it i s more effic ient to have a su pervisor stack space assoc iated with each user task a n d a separate stack space for i nterrupt assoc iated tasks. Thus, the master stack may be u sed to contain task control i nformation for the cu rrently executing u ser task w h i le the i nter ru pt stack is u sed for i nterru pt task control i nformation and temporary storage. When a user task switch is req u i red, the master stack pOinter is loaded with a new value that points to the new task context, w h i l e st i l l mainta i n i n g a val id, i ndependent stack space for i nterrupts. When the M bit is clear, the M C68020 i s in the i nterrupt state and operat ion is the same as the M C68000, M C68008, M C680 1 0, and MC6801 2 su pervisor state (this is the defau lt condition after reset). The processor uses the i nterrupt stack pointer (ISP) when it references the system stack poi nter (SSP). When the M bit i s set, the processor is in the master state and the processor u ses the master stack poi nter (MSP) when it references the system stack pointer (SSP). Whether the M bit is set or clear does not affect execu tion of privileged i nstruct ions. The M bit may be set or cleared by an i nstruction that modifies the status reg ister (MOVE to SR, A N D I to SR, EORI to SR, ORI to SR and RTE). A l so, the processor saves the M bit conf i g u ration and clears it in the SR as part of the ex cept ion processi n g for i nterru pts. A l l exception processi n g is done in the su pervisor state. The bus cyc les generated d u r i n g exception process i n g are c lassif ied a s su pervisor references. A l l stacking operat ions d u ri n g except ion processing use the active su pervisor stack pOi nter.

6-2

6.1 .3 User State The u ser state is the lower privi lege state. For i nstruction exec ution, the u ser state is determ i ned by the S bit of the status reg ister; if the S bit is clear, the processor is ex ecu t i n g i nstructions i n the u ser state. M ost i nstructions execute both in the u ser state and in the su pervisor state. However, some i nstru ctions which have i m portant system effects are made privi leged and are restri cted to use in the su pervisor state. For i nstance, user programs are not perm itted to execute t he STOP i nstruction or the RESET i nstruct ion. To i ns u re that a user program can not enter the privi leged su pervisor state, except in a control led man ner, the i nstruc tions which can mod ify the S bit in the stat u s reg ister are privi leged. The TRAP #n i n struction can be u sed to al low u ser program access to privi leged services performed by the operat i n g system i n the su pervisor state. The bus cycles generated by an i nstruction executed in the user state are classif ied as u ser state references, as reflected by the address space val ues placed on the fu nct ion code pins (FCO-FC2). This al lows an external memory management device to d istingu ish between user and s u pervisor activity, and to control access to protected portions of the address map. While the processor i s i n the user state, those references made to either the system stack poi nter i m p l i c it ly, or address reg i ster seven (A7) exp l icit ly, are always made relative to the u ser stack poi nter (USP). 6.1 _4 Change of Privilege State The o n ly way for the processor to change from the u ser to the supervisor privi lege level i s t h rough except ion process i ng, w h i c h cau ses a change f rom t h e user state to o n e o f the su pervisor states and can cause a change from the master state to the i nterru pt state. Except ion processing saves the c u rrent state of the S and M bits of the status reg i ster on the active supervisor stack, and the S bit is set, forc i n g the processor into the su pervisor state. A lso, if the except ion bei n g processed i s an i nterrupt and the M bit is set, it w i l l be cleared to put the processor i nto the i nterru pt state. I nstruct ion execution proceeds i n t h e su pervisor state t o hand le the exception cond ition. A t ransition from s u pervisor to user state can be caused by the following i nstructions: RTE, MOVE to SR, A N D I to SR, and EORI to SR. The M OVE, A N D I , and EORI to SR i nstruc tions execute at the su pervisor privi lege level, and then fetch the next i nstruct ion at the next sequential program cou nter address at the new privi lege level determ i ned by the new va lue of the S bit. The RTE i nstruction exami nes the su pervisor stack contents to determine which state restorat ions are req u i red. If the frame on top of the stack was created by an i nterrupt, t rap, or i nstruction except ion, the RTE i nstruction fetches the saved status reg i ster and program counter from the su pervisor stack, and restores each i nto its respective reg i ster. The processor then cont i n ues execution at the restored program counter address and at the privi lege level determi ned by the S bit of the restored statu s reg i ster. If the frame on top of the stack was created by a fau lted bus cyc le, the RTE i nstruction restores the ent i re saved mac h i ne state from the stack.

6-3

6.1 .5 Address Space Types Address space c lassification is generated by the processor accord i n g to the type of ac cess req u i red d u r i n g each bus cycle. This al lows external t ranslation of addresses, con trol of access, and d ifferentiation of speci a l processor states, such as i nterrupt acknowledge. Table 61 lists the types of accesses and their respective address space encod i ngs. Table 61 . Address Space Encodings
FC2 FC1 FCO Address Space
*

0 0 0 ( Undefined. Reserved) 1 User Data Space 0 0 1 User Program Space 0 0 1 1 ( Undefined. Reserved) 0 1 (Undefined. Reserved) 0 0 1 1 Supervisor Data Space 0 1 1 0 Supervisor Program Space 1 1 1 CPU Space * Address space 3 IS reserved for user definition. while 0 and 4 are reserved for future use by Motorola.
* *

U ser program and data accesses have no predefi ned memory locations. The su pervisor data space also has no predefi ned locat i ons. During reset, the f i rst two long words at memory locat ion zero in the su pervisor program space are u sed for processor i n itial iza tion. No other memory locat ions are ex pl icitly defi ned by the processor. 6.1 .6 CPU Space The CPU space is not intended for general i nstruct ion execution, but is reserved for pro cessor functions; that is, those bus cyc les in which the processor must com m u n i cate with external devices for reasons beyond normal data movement assoc iated with in structions. For exam p le, all M68000 processors u se the CPU space for i nterrupt acknowledge cyc les. The M C68020 also makes CPU space accesses for breakpoi nts, coprocessor operations, and to s u pport the module cal l/return mechan ism. Although the M OVES i nstruction can be used to generate CPU space bus cyc les, this may i nterfere with proper system operat ion. Thus, the use of M OV ES to access the CPU space should be done with caution. 6.2 EXCEPTIO N P ROCESSI NG A general description of exception process i n g is f i rst presented to i nt roduce the con cepts of i nterrupts, traps, and t rac i ng . Exception process i n g for coprocessor detected er rors is not discussed i n t h i s sect ion; refer to SECTION 8 COPROCESSOR INTERFACE DESCR I PTION for more deta i l s on coprocessor exception han d l i ng. The process i n g of an exception occurs i n fou r steps, with variations for d ifferent excep tion causes. During the f i rst step, a temporary i nternal copy of the status reg ister is made, and the status reg ister i s set for exception process i ng . In the second step, the ex cept ion vector is determ i ned, and in the t h i rd step, the cu rrent processor context i s saved. I n t h e fou rt h step a new context is obtai ned, a n d t h e processor then proceeds w i t h i nstruction process i ng. 64

6.2.1 Exception Vectors The vector base reg i ster points to the base of the 1 K byte exception vector table conta i n i n g the 256 exception vectors. Exception vectors are memory poi nters used by the pro cessor to fetch the address of routi nes which w i l l handle various except ions. A l l excep tion vectors are one long word in length, except for the reset vector, which is two long words i n length. Exception vectors are selected by 8bit vector n u mbers generated during exception pro cess i ng . This vector n u mber is m u l t i p l ied by four to form the vector offset, which is add ed to the vector base reg i ster to obtai n the address of the vector. A l l except ion vectors are located in s u pervisor data space, except the reset vector which is l ocated i n s u per visor program space. Vector n u mbers are generated i nternally or external ly, depending on the cause of the except ion. Table 62 provides the ass i g nments of the exception vectors.
Table 62. Exception Vector Assignments (Sheet
Vector Number(s)
a ()()()

of 2)

Vector Offset Space Assignment

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Through 23 24 25 26 27 28 29 30 31 32 Through 47
48

004

Hex

008 OOC 010 014 018 01C 020 024 028 02C 030 034 038 03C 040 05C 060
064

SP SP SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO SO

Reset: Initial Interrupt Stack Pointer Reset: Initial Program Counter Bus Error Address Error Illegal Instruction Zero Divide C H K , C H K 2 Instruction cpTRAPcc, T RAPcc, TRAPV Instructions Privilege Violation Trace Line 1 0 1 0 Emulator Line 1 1 1 1 Emulator (U nassigned, Reserved) Coprocessor Protocol Violation Format Error Uninitialized I nterrupt

068 06C 070 074 078 07C 080 aBC OCO OC4 OC8 OCC 000 004 008 OOC OEO OE4

Spurious Interrupt Level l Interrupt Auto Vector Level 2 Interrupt Auto Vector Level 3 Interrupt Auto Vector Level 4 Interrupt Auto Vector Level 5 Interrupt Auto Vector Level 6 Interrupt Auto Vector Level 7 Interrupt Auto Vector

( Unassigned, Reserved)

49 50 51 52 53
54

55 56 57

FPCP Branch o r Set o n U nordered Condition FPCP I nexact Result F P C P Divide b y Zero FPCP Underflow F P C P Operand Error FPCP Overflow FPCP Signaling NAN Unassigned, Reserved PMMU Configuration PMMU Illegal Operation

TRAP #0-1 5 Instruction Vectors

6-5

Table 62. Exception Vector Assignments (Sheet 2 of 2)

Vector Numberis)
58

Vector Offset Hex Space Assignment

59 Through 63

DES DEC DFC

SD SD SD

PMMU Access Level Violation Unassigned, Reserved User Defined Vectors 1 1921

64

100

SD
SD

Through 255
=

3FC

S P = Supervisor Program Space S D Supervisor Data Space

} }

As show n i n Tab le 6-2, 1 92 vectors are reserved for u ser defi nit ion as i nterrupt vectors and 64 are defi ned by the processor. H owever, there is no protection on the f i rst 64 vec tors, so that external devices may u se vectors reserved for i nternal pu rposes at the d i scret ion of the system desig ner. 6.2.2. Exception Stack Frame Except ion proces s i n g saves the most volat i l e portion of the cu rrent processor context on the top of the su pervisor stack. Th is context is organized in a format cal led the exception stack frame. This i nformation always incl udes the status reg i ster, the program cou nter, and the vector offset used to fetch the vector. The processor also marks the frame with a frame format. The format field a l l ows t he RTE i nstruct ion to ident ify what i nformat ion i s on the stack so t hat it may b e properly restored a n d t h e stack space dea l located. The general form of the except ion stack frame is i l l ustrated in Figure 6-1 . Refer to 6.5 MC68020 EXCEPTION STACK F RAM ES for a comp lete l ist of except ion stack frames.
SP 15 12 Status Register Program Counter Format D

Vector Offset Additional Processor State I nformation 12, 6, 12, or 42 Words, if Needed)

Figure 6-1 . Exception Stack Frame 6.2.3 Exception Types Exceptions can be generated by either i nternal or external causes. The externally generated except ions are i nterru pts, bus errors, reset, and coprocessor detected errors. I nterrupts are requests from peri pheral devices for processor action, w h i l e the bus error and reset p i n s are u sed for access control and processor restart. The i nternally generated except ions are caused by i nstruct ions, address errors, t raci ng, or breakpoi nts. The TRAP, TRAPcc, TRAPV, cpTRAPcc, CH K, CH K2, CALLM, RTM , RTE, and DIV i nstruc tions a l l can generate exceptions as part of their i nstruct ion execution. I n add ition, i l legal i nstructions, address error, privi lege violations, and coprocessor protocol viola tions cause exceptions. 66

6.2.4 Exception Processing Sequence Exception proces s i n g occurs in fou r ident ifiable steps. During the f i rst step, an i nternal copy i s made of the statu s reg i ster. After the copy i s made, the processor state bits in t he stat us reg i ster are changed. The S bit is set, putt i n g the processor i nto the supervisor privi l ege state. The T1 and TO bits are cleared, which al l ows the exception handler to ex ecute u n h i ndered by trac i n g . For the reset and i nterrupt excepti ons, the i nterrupt priority mask i s also u pdated. In the second step, the vector n u m ber of the exception i s determ i ned. For i nterrupts, the vector n u mber i s obtai ned by a processor read from CPU space $F, which i s def i ned as an i nterru pt acknowledge cycle. For coprocessor detected excepti ons, the vector n u m ber is i n c l uded in the coprocessor except ion primit ive response. (Refer to SECTION 8 COP ROCESSOR INTERFACE DESCR I PTION for a complete d i scussion of coprocessor except i ons.) For a l l other except ions, i nternal logic provides the vector n u m ber. This vec tor n u m ber is then used to generate the add ress of the except ion vector. For a l l except ions other than reset, the t h i rd step is to save the cu rrent processor con text. An exception stack f rame is created and f i l l ed on t he act ive su pervisor stack. Other i nformat ion may also be stacked, depend i n g on which exception i s be i n g processed and the context of the processor prior to the exception. I f the exception i s an i nterrupt and the M bit i s set, the M bit i s cleared, and a second stack frame i s created on the i nterrupt stack. The last step i s the same for a l l except ions. The exception vector offset i s determ i ned by m u l t iplying the vector n u m ber by fou r. This offset is then added to the contents of the vector base reg i ster to determine the memory address of the except ion vector. The pro gram counter value (and I S P for the reset except i on) is l oaded with the value in the excep t i on vector. The i nstruct ion at the address g iven in the exception vector is fetched, and normal i nstruct ion decod i n g and execution is resu med. 6.2.5 Multiple Exceptions The fol lowi n g parag raphs describe the processing that occu rs w hen m u lt i ple exceptions arise s i m u ltaneously. Exceptions can be g rou ped accord i ng to their characteristics and priority, as shown in Table 6-3. The priority relationship between two except ions determ i nes which is processed f i rst if both exceptions occur s i m u ltaneously. The term 'process' in this context means the ex ecution of the fou r steps previously defi ned: 1) change proces s i n g states if needed, 2) determ i n e exception vector, 3) save old context, and 4) load new context, i nc l u d i n g the f i rst three i nstruction words at the new program cou nter location. ' Process' i n this context does not i nc l ude the execution of the routine poi nted to by the fetched vector. As soon as the M C68020 has completed processi n g for an exception, it is then ready to beg i n execut ion of the except ion handler routi ne, or beg i n exception pro ceSS i n g for other pend i n g exceptions. Al so, a h i g her priority except ion can be processed before the completion of exception proces s i n g for lower priority except ions (for exam ple, 6-7

Table 63. Exception G roups

Groupl Priority

0
1

0.0

cp Mid-Instruction, Cp Protocol Violation, cpTRAPcc, Divide-byZero, RTE, RTM, TRAP #n, TRAPV 3 3.0 - lIlegal Instruction, Line A, U nimplemented Line F, Privilege Violation, cp Pre-Instruction cp Post-Instruction Trace - Interrupt is the highest priority, is the lowest.
C H K2 ,

0.0- Reset 1 .0- Address Error 1 . 1 - Bus Error 2.0- BKPT #n, CALLM, CHK,

Exception and Relative Priority

Characteristics

Aborts all processing !instruction or exception) and does not save old context. Suspends processing (instruction or exception) and saves internal context. Exception processing is part of instruction execution.

Exception processing begins before instruction is executed.

4.04.1 4.2

Exception processing begins when current instruction or previous exception processing is completed.

4.2

if a bus error occu rs during the processing for a t race exception, the bus error w i l l be pro cessed and hand led before the t race exception processing is com pleted). H owever, most exceptions can not occur during except ion processing. Fu rthermore, very few combi na tions of the exceptions shown in Table 6-3 can be pend ing s i m u ltaneously. This priority scheme is very i m portant i n determ i n ing the order i n which exception handlers are executed in m u ltiple exception situations. As a general ru le, the l ower the priority of an except ion, the more q u ickly the handler routine for that except ion w i l l be ex ecuted. For example, if s i m u ltaneous trap, t race, and i nterrupt exceptions are pend i ng, the t rap exception i s processed f i rst, fol lowed i m mediately by except ion process i n g for the trace and then the i nterru pt. Thus, when the processor finally resumes normal i n struction execution, it is i n the i nterrupt hand ler, which returns to the trace hand ler, which retu rns to the trap except ion handler. An exception to this ru le is the reset excep tion, which is the h i g hest priority and also the f i rst except ion handled, s i nce a l l other ex ceptions are cleared by t he reset condition. 6.3 EXCEPTION P ROCESSI NG: DETAIL Except ions have a n u m ber of sou rces, and each exception has characteristics which are u n ique to it. The follow i n g parag raphs detail the sou rces of except ions, how each arises, and how each i s processed. 6_3_1 Reset The RESET i n put provides the h i g hest level of exception. The RESET S ignal provides for system i n itializat ion and recovery from catastrophic fa i l u re. Any processing in progress at the t i me of the reset is aborted, and cannot be recovered. The stat us reg ister is i n itial ized: t rac i n g i s d i sabled (both trace bits are cleared), su pervisor interru pt state is entered (the su pervisor bit is set and the master bit i s cleared), and the processor inter ru pt priority mask is set to the h i g hest priority level (level seven). The vector base reg i ster and cache control reg i ster are i n itialized to zero ($00000000). A vector nu m ber i s i nter nally generated to reference the reset exception vector at offset zero in the su pervisor 6-8

program address space (which is two long words i n stead of the normal one long word). Because no assumptions can be made about the val id ity of any reg ister contents (in par ticular the su pervisor stack pointer) neither the program counter nor the status reg ister i s saved. The address contai ned i n t h e f i rst l o n g word o f t h e reset except ion vector i s fetched f o r u se a s the i n itial interrupt stack pointer, a n d the address i n t h e second long word of the reset exception vector i s fetched for use as the initial program cou nter. Pro g ram execution then starts at the address loaded i nto the program counter. The reset i nstruction does not affect any i nternal reg i sters, but it does assert t he RESET l i ne, thus resetting a l l external devices. This allows software to reset t he system to a known state and then cont inue processi n g at t he next i nstruction. 6.3_2 Address Error Address error exceptions occu r when the processor attempts to prefetch an i nstruction from an odd add ress. The affect i s much l i ke an internal ly generated bus error, so that the bus cycle is not executed and the processor beg i n s except ion processing. After excep tion processing commences, the sequence is the same as that for bus error except ions as described i n 6.3.3 Bus Error, except that the vector offset i n the stack frame refers to the address error vector. Also, if an address error occurs during the exception processing for a bus error, address error, or reset, the processor is halted. 6.3.3 Bus Error Bus error except ions occ u r d u ri n g a bus cyc le when external log ic aborts the cycle by assert i ng the BERR i nput. I f the aborted bus cycle i s a data space access, the processor i m mediately beg i n s exception processing. If the aborted bus cycle is an i nstruction prefetch, the processor delays taking the exception (the processor w i l l wait u n t i l the results of the aborted bus cyc le are req u i red for furt her instruction execut ion, and then takes the except ion). Except ion process i n g for a bus error fol lows the usual sequence of steps. The status reg i ster i s copied, the su pervisor state i s entered, and t racing is d isabled. A vector nu m ber is generated to refer to the bus error vector. The vector offset, program cou nter, and the copy of the statu s reg i ster are then saved on the stack, in add ition to i nformat ion describing the non-user visible i nternal reg i sters of the processor. This add itional i nfor mation is req u i red to recover f rom the bus fau lt, s i nce the processor may be in the m iddle of executing an i nstruction when the fau lt i s detected. The saved program cou nter va lue is the address of the i n st ruction that was executing at the time the fau lt was detected. This is not necessari ly the i n st ruction that generated the bus cyc le, due to the overlap ped execution al lowed by the processor. The i nternal state information incl uded in the stack frame contains sufficient i nformat ion to determine t he cause of the bus fault and recover from the error. For i m proved efficiency, the M C68020 su pports two d i fferent bus error stack frame for mats as shown i n F i g u res 6-7 and 6-8. If the bus error occ u rs in m id-instruction, the pro cessor saves its ent i re state in order to properly cont i nue execution of the i nstruct ion after the bus error i s corrected. If the bus error is taken as t he processor i s beg i n n i n g ex ecution of an i nstruction, the processor can save a much smal ler amount of i nformat ion

6-9

about the fai led cyc le i n order to cont i nue execution of that i nstruct ion when the excep tion handler returns. The two bus error stack frames are d istingu ished by the stack frame format code (refer to 6_5 MC68020 STACK FRAM ES for add it ional i nformat ion). If a bus error occ u rs d u r i ng the exception process i n g for a bus error, address error, or reset, or w h i l e the processor i s load i n g i nternal state i nformation from the stack d u r i n g t h e execution o f an RTE i nstruction, t h e processor enters t h e halted state. Th i s simpl ifies the detect ion of catastrophic system fai l u res, s i nce the processor removes itself from the system rather than modifying the c u rrent state of the stacks and memory. Only an ex ternal RESET can restart a processor halted due to a double bus fau lt. 6.3_4 Instruction Traps Traps are exceptions caused by i nstruction execution. They arise e ither from processor recog n it i on of abnormal cond it ions d u r i n g i nstruction execution, or from u se of the specific i nstructions w hose normal behavior is to cause an except ion. Except ion processing for traps fol l ows the same steps out l i ned previous ly. The statu s reg i ster i s copied i nternal ly, t h e s u pervisor state i s entered, a n d t h e trace b i t s are c leared. Thus, if trac i n g was enabled w hen the trap caus i n g i nstruct ion began execution, a t race except ion w i l l be generated by the i nstruct ion, but the trap handler rou t i ne wi l l not be t raced (the trap exception w i l l be processed f i rst, then the t race except i on). A vec tor n u mber is i nterna l ly generated; for the TRAP #n i nstruction, part of the vector n u mber comes from the i nstruct ion itself. The t rap vector offset, the program cou nter, and the copy of the status reg i ster are saved on the su pervisor stack. The saved value of the pro g ram counter is the address of the i nstruction after the i nstruction which generated the t rap. For a l l i nstruction t raps other than TRAP #n, a poi nter to the i nstruct ion which caus ed the trap is also saved. F i nal ly, i nstruct ion execution commences at the address con tai ned in the exception vector. Certain i nstructions are used specifically to generate traps. The TRAP #n i nstruct ion always forces an except ion, and i s usef u l for i m p lementing system cal l s for user pro g rams. The TRAPcc, TRAPV, cpTRAPcc, C H K, and C H K2 i nstructions force an except ion if t he user prog ram detects a ru ntime error, which may be an arithmetic overflow or a subscript value out of bou nds. The D I VS and DIVU i nstructions w i l l force an exception if a division operation i s attempted with a d ivisor of zero. The CALLM and RTM i nstructions w i l l cause a format error if an i l legal privi lege change i s requested or i nval i d parameters are present i n the type or opt i on fields. 6.3_5 Breakpoints I n order to u se the M C68020 in a hardware emu lator, it must provide a means of i nsert i n g breakpoi nts i nto t he target code, a n d then g ive a c lear annou ncement o f w h e n it has reached a breakpoint. For the M C68000 and M C68008, this can be done by i nsert i n g an i l l egal i nstruct ion at the breakpo i nt and detect i n g w hen t he processor fetches from the il legal i nstruction except ion vector locat ion. Si nce the vector base reg i ster on the M C6801 0, M C6801 2, and MC68020 al lows arbitrary relocat ion of the except ion vectors, the exception vector address cannot serve as a re l iable i n d icator that the processor i s tak i n g t h e breakpoint. On t h e M C680 1 0, M C680 1 2 , a n d M C68020, this function i s provided by exten d i n g the f u nctionality of a set of the i l legal i nstructions, $4848-$484F, to serve as 6-1 0

breakpo i nt i nstructions. The breakpoi nt fac i l ity also al lows external hardware to mon itor the execution of a program res i d i n g i n the on-chip cache, w ithout severe performance degradation. When a breakpoi nt i nstruction i s exec uted, the MC68020 performs a read from CPU space $0 at an address corresponding to the breakpoint number. Refer to Figure 5-24 for the CPU space $0 encod i ng. If this bus cycle is term inated by BERR, the processor then proceeds to perform i l legal i nstruction exception processing. If the bus cycle i s ter m i nated by DSACKx, the processor u ses the data returned to replace the breakpoi nt i n struction i n the i nternal i nstruction p i pe, and beg i n s execution of that i nstruction. 6.3.6 Format Error J u st as the processor checks that prefetched i nstructions are va l id, the processor (with t he aid of a coprocessor, if needed) also performs some checks of data values for control operat ions, i nc l u d i n g the type and option fields of the descriptor for CALLM , the coprocessor save area format for cpRESTORE, and the stack format for RTE and RTM . The RTE i nstruction checks the val i d ity of the stack format code, and i n the cases of the bus cycle fau lt formats, the va l i d ity of the data to be l oaded i nto the various i nternal reg i sters. The only data item checked for val i d ity is the version n u m ber of the processor that generated the f rame. This check ensures that the processor is not making erroneous assumptions about i nternal state i nformation in the stack f rame. The CALLM and RTM both check the val ues in the option and type fields in the module descri ptor and mod u l e stack frame, respectively. If these fields do not contain proper values, or if an i l legal access rig hts change request is detected by an external memory management u n it, then an i l legal c a l l or ret u rn i s bei n g requested and i s not executed. Refer to APPENDIX D.1 MODULE SU PPORT for more i nformation on the module cal l/return mechanism. The cpRESTO RE i nstruction passes the format field of the coprocessor save area to the coprocessor for validation. If the coprocessor does not recog n ize the format va lue, it i n d icates this to the main processor, and the M C68020 w i l l take a format error except ion. Refer to 8.1 5 EXCEPTION P ROCESSING for deta i l s of coprocessor related except ions. If any of these checks determine that the format of the control data i s i m proper, the pro cessor generates a format error except ion. This exception saves a short format excep tion frame, and then con t i n ues execution at the address contai ned in the format excep tion vector. The stacked program cou nter is the address of the i nstruction that detected the format error. 6.3.7 Illegal or Unimplemented I nstructions An i l legal i nstruct ion is any of the word bit patterns which do not correspond to the bit pattern of the fi rst word of a legal M C68020 i nstruction, or a MOVEC i nstruction with an u ndefi ned reg i ster spec i f icat ion field i n the f i rst extension word. The word patterns with bits [1 5: 1 2] eq ual to 1 0 1 0 are d is t i n g u i shed as u n i m p lemented i nstruct ions, referenced to as A-l i ne opcodes. D u ri n g i nstruction execution, when an attempt is made to execute an

6-1 1

i l legal i nstruction, an i l legal i nstruction except ion occu rs. U n i mplemented i nstructions u t i l ize separate except ion vectors, permitt i n g more efficient emu lation of u n i m ple mented i nstruct ions. The word patterns with bits [1 5: 1 2] equal to 1 1 1 1 (referred to as F-l i ne opcodes) are used for coprocessor i nstru ctions, but may generate an u n i m plemented i nstruction except ion. When the processor encou nters an F- l i ne i nstruction, it f i rst ru ns a bus cyc le referencing CPU space 2 and addressing one of eight coprocessors. If no coprocessor responds to the bus cycle and the access i s term i nated with a bus error, the processor w i l l proceed with u n i mplemented i nstruction except ion processing and fetch t he F-l i ne emulator vec tor. Thus, the fu nction of the coprocessor may be emu lated. Refer to SECTION 8 COPROCESSOR INTERFACE DESCR I PTION for more details. Except ion processi n g for i l legal and u n i mplemented i nstructions i s s i m i lar to that for t raps. After the i nstruction is fetched and decoded, the processor determ i nes that execu tion of an i l l egal or u n i m plemented i nstruction is bei n g attem pted and starts exception processing before executing the i nstruction. The status reg ister is copied, the su pervisor state is entered, and t rac i n g is d isabled. A vector n u mber is generated to refer to the i l legal i nstruction vector, or i n the case o f u n i m p lemented i nstructions, to t h e correspon d i n g emu lation vector. The i l legal or u n i m plemented i nstruction vector offset, cu rrent program cou nter, and copy of the stat u s reg ister are saved on the supervisor stack, with the saved value of the program cou nter bei n g the address of the i l legal or u n i m plemented i nstruction. Final ly, i nstruction execut ion res u mes at the address contained in the ex cept ion vector. 6_3.8 Privilege Violations In order to provide system sec u rity, certain i nstructions are privi leged (see Table 6-4). An attempt to execute one of the privi leged i nstructions while in the u ser privi lege state w i l l cause a n except ion. Also, a privilege violation may occu r if a coprocessor requests a privi lege check and the processor is in the user state. Table 6-4. Privileged Instructions
ANDI to S A EOAI to SA cpAESTOAE cpSAVE MOVE from SR MOVE to S A MOVE USP MOVEC MOVES OAI to SA A ESET RTE STOP

Except ion processing for privi lege violations i s sim i lar to that for i l legal i nstruct ions. After the i nstruction i s fetched and decoded, the processor determ i nes that a privi lege violation i s bei n g attempted, and the processor starts except ion process i n g before ex ecuting t he i nstruction. The status reg i ster is copied, the su pervisor state is entered, and t racing i s d i sabled. A vector n u m ber i s generated to reference the privi lege violation vec tor; the privi lege violation vector offset, cu rrent prog ram cou nter, and the stat us reg i ster are saved on the su pervisor stack. The saved value of the program counter i s the address of the f i rst word of the i nstruction which caused the privi lege violation. Fi nal ly, i nstruc tion execution resumes at the address conta i ned i n the privi lege violation exception vector. 61 2

6.3.9 Tracing To aid in program development, the M68000 processors i nclude a fac i l ity to al low i nstruct ion-by-i nstruction t rac i ng . The M C68020 also al lows tracing of i nstructions that change program flow. I n the trace mode, a t race exception is generated after an i nstruc tion i s executed, a l l ow i n g a debugger program to monitor the execution of a program u nder test. The trace fac i l ity u ses the T1 and TO b its in the s u pervisor portion of the status reg ister. If both T bits are clear, tracing is d i sabled, and i nstruction execution proceeds normal ly. I f t h e T 1 b i t is c lear a n d t h e TO b i t is set a t t h e beg i n n i n g o f t h e execution o f an i nstru ction, and that i nstruction causes the program cou nter to be u pdated i n a non-seq uential man ner, a t race exception w i l l be generated after its execution is comp leted. I nstructions that w i l l be t raced i n this mode i nc l ude all branches, j u m ps, i nstruct ion traps, returns, stat us reg ister manipulations (Si nce the processor must refetch any words that may have been prefetched from the su pervisor program space rather than user program space), and coprocessor general i nstructions that mod ify the program counter flow. If the T1 bit i s set and the TO bit i s c lear at the beg i n n i n g of the execut ion of any i nstruction, a t race except ion w i l l be generated after the execution of that i nstruct ion is completed. See Tabl e 6-5. Table 6-5. Tracing Control
TI TO Tracing Function

0 0 1 1

0 1 0 1

No Tracing Trace on Change of Flow ( B RA, J M P, etc.1 Trace on Instruction Execution (Any I nstructionl Undefined, Reserved

I n general terms, a t race except ion can be viewed as an extension to the function of any i nstruction. Thus, if a trace exception i s generated by an i nstruction, the execution of that i nstruction i s not com plete u n t i l the trace except ion process i n g associated with it is com pleted. If the i nstruction does not complete execution due to a bus error or address error exception, t race exception processi n g is deferred u n t i l after the execution of the s uspended i nstruct ion is resu med (by the associated RTE), and the i nstruction execution is com pleted normal ly. I f the i nstruction is executed and an i nterru pt is pend i n g on com pletion, the trace exception processing is completed before the interrupt exception pro cessing starts. If, during the execution of the i nstruction, an except ion is forced by that i nstruction, the forced except ion is processed before the t race except ion is processed, If the processor is in the trace mode when an attempt is made to execute an i l legal or u n i m plemented i nstruction, t hat i nstruction w i l l not cause a trace s i nce it i s not ex ecuted. Th i s i s of particu lar i m portance to an i nstruction emu lation rou t i ne that performs the i nstruction function, adju sts the stacked program counter to beyond the u n i m plemented i nstruct ion and then returns. Before t he return is executed, the stat us reg i ster on the stack should be checked to deter m i ne if tracing i s on; and if so, then the trace exception processing should also be emu lated in order for the trace except ion hand ler to accou nt for the emu lated i nstruction. The except ion processing for a t race starts at t he end of normal process i n g for the traced i nstruction, and before the start of the next i nstruction, An i nternal copy is made of the status reg i ster. The transition to s u pervisor state is made, and the T bits of the

6-1 3

status reg i ster are cleared, d i sab l i n g further t rac i ng . A vector n u m ber is generated to reference the t race exception vector. The address of the i nstruct ion that caused the trace except ion, the trace exception vector offset, program cou nter, and the copy of the status reg ister are saved on the su pervisor stack. The saved value of the program cou nter i s the address of the next i nstruction to be executed. I nstruction execution resumes at t he address contai ned in the t race exception vector. N ote that there is one case where trac i n g affects the normal operat ion of one i n struction. I f the STOP i nstruction beg i n s execut ion with T1 = 1, a trace exception w i l l be taken after the STOP i nstruction loads the statu s reg ister. Upon ret urn from the trace handler routi ne, execution w i l l conti nue with the i nstruction follow i n g the STOP, and the pro cessor w i l l never enter the stopped cond it ion. 6_3_1 0 I nterrupts Except ion processing can be cau sed by external devices req uest i n g service th roug h the i nterru pt mechan ism descri bed i n 5_2.4.1 I NTERRUPT O PERATION. I nterrupt requests ar rivi ng at the processor throu g h the I P LO-I PL2 pins do not force i m med iate except ion pro cessing, but may be made pend i n g . Pend i n g i nterru pts are serviced between i nstruction execution, at the end of exception process i ng , or when permitted during coprocessor i n structions. If the priority of the requested i nterru pt is less than or equal to the cu rrent i n terrupt mask level, execution continues with the next i nstruction and the i nterru pt re quest is ignored. (The recog nition of level seven is s l ightly d i fferent, as explai ned below.) If the priority of the requested i nterru pt i s g reater than the cu rrent i nterrupt mask level it is made pend i n g and exception processing w i l l beg i n at the next i nstruct ion bou ndary. Exception processing for i nterru pts fol l ows the same steps as previously out l i ned. F i rst, an i nternal copy of the status reg ister is made, the privi lege state i s set to su pervisor, trac i n g i s s u ppressed, and the processor i nterru pt mask level i s set to the level of the i n terrupt bei n g serviced . The processor fetches a vector number from the i nterrupti n g device, classifying t h e bus cyc le a s an i nterru pt acknowledge a n d d isplayi n g the level n u m ber of the i nterrupt bei n g acknowledged on pins A 1 -A3 of the address bus. If the vec tor nu mber is not generated by the i nterrupti n g device, external logic requests automat i c vectoring a n d t h e processor i nternally generates a vector n u m ber w h i c h is determ i ned by the i nterru pt level n u m ber. H owever, if external log ic ind icates a bus error, the i nterru pt i s taken to b e spurious, a n d the generated vector n u mber refers t o the spurious i nterrupt vector. Once the vector n u m ber is obtai ned, the processor proceeds with the usual exception processing, saving the exception vector offset, program cou nter, and status reg ister on the su pervisor stack. The saved value of the program counter i s the address of the i n struct ion which wou ld have been executed had t he i nterrupt not been present. I f the i nter rupt was recog nized d u ring the execution of a coprocessor i nstruction, further i nternal i nformat i on i s saved on the stack so that t he M C68020 can conti nue execut i n g the coprocessor i nstruction when the i nterru pt handler comp letes execution. If the M bit of the status reg i ster is set, the M bit is cleared and a t h rowaway except ion stack frame i s created on t o p o f t h e i nterrupt stack. T h i s second frame contains t h e same program cou nter and vector offset as the frame created on top of the master stack, but has a for mat n u mber of $1 i n stead of $0 or $9. The stat us reg ister w i l l be the same as that p laced on the master stack except that the M and S bits w i l l be set. The content of the except i on

6-1 4

vector correspond i n g to the vector n u m ber previously obtai ned is fetched and loaded i n to the program counter, and normal i nstruct ion execution resu mes i n the i nterrupt handler rou t i ne. Priority level seven i s a spec ial case. Level seven i nterru pts cannot be i n h i bited by the i n terru pt priority mask, thus, provid i ng a non-maskable i nterru pt capab i l ity. An i nterru pt re quest is generated each t i me t he i nterrupt request level changes from some lower level to level seven. N ote that a leve l seven i nterrupt may also be caused by level comparison if the req uest level and mask level are at seven and t he priority mask is then set to a lower level (e.g., with the MOVE to SA or ATE i nstruct ions). M ost M68000 Family peripherals provide for prog ram mable i nterrupt vector nu mbers to be u sed in the i nterru pt req uest/acknowledge mechanism of the system. If this vector n u m ber is not i n itial ized after reset and the peri pheral must acknowledge an i nterrupt re quest, the peri pheral ret urns the vector n u m ber for the u n i n itial ized i nterrupt vector, $OF .
6_3_ 1 1

Return From Exception

After exception stacki n g operat ions have been com pleted for a l l pend i n g except ions, the processor resu mes normal i nstruction execution at t he address contai ned in the vector referenced by the last exception to be processed. Once the except ion handler has com pleted execution, the processor must retu rn to the system context prior to the except ion (if possi ble). The mechanism used to accom p l i s h this retu rn for any except ion i s the ATE i nstruction. When the ATE i nstruct ion i s executed, the processor exami nes the stack frame on top of the act ive su pervisor stack to determ i ne i f it i s a val i d frame and what type of context restoration shou ld be performed. The actions taken by the processor for each of the stack frame types is descri bed below. Aefer to 6_5 M C68020 EXC EPTI O N STACK FRA M ES for the format of each frame type. For a normal four word frame, the processor u pdates the status reg ister and program counter with the data p u l led f rom the stack, i ncrements the stack pointer by eight, and resu mes normal i nstruction execution. For the throwaway four word stack, the processor reads the status reg i ster from the frame, i ncrements the active stack poi nter by eight, l oads the SA with the previously read value, and then beg i n s ATE processing aga i n . This means that the processor reads a new format word from the stack frame on top of the act ive stack (wh ich may or may not be the same stack u sed for the previous operat ion) and performs the proper operations cor respond i n g to that format. In most cases, t he throwaway frame w i l l be on the i nterru pt stack and when l oaded , the S and M bits w i l l be set. Then, there w i l l be a normal four word frame or a ten-word coprocessor m id-i nstruct ion frame on the master stack. H owever, the second frame may be any format ( i n c l u d i n g another throwaway frame) and may reside on any of the t h ree system stacks. For t he six word stack frame, the status reg i ster and program cou nter are updated from t he stack, the active su pervisor stack poi nter i s i ncremented by twelve, and normal in struction execution resu mes.

6-1 5

For the coprocessor m idi nstru ction stack frame the status reg ister, program cou nter, i n struction address, i nternal reg isters, and eva l uated effective add resses are p u l led from the stack and are restored to the correspond i n g i nternal reg i sters, and the stack poi nter is incremented by twenty. Then the processor reads from the response reg i ster of the coprocessor that generated the except ion to determ i ne the next operat ion to be perform ed. Refer to 8.1 5 EXC EPTIO N P ROCESSI NG for deta i l s of coprocessor related excep t i ons. For both the short and long bus fau l t stack frames, the format value on the stack i s f i rst checked for val i d ity. In add i t ion, for the long stack frame, the version nu mber contai ned in the stack must match the version number of the processor that is attem pting to read the stack frame. The vers ion n u m ber is located in the most s i g n i f icant n i bble (bits 1 2 through 1 5) of the word at location S P + 54 i n the long stack frame. Th is val i d i ty check is used to i ns u re that i n a dual processor system, the data w i l l be properly i nterpreted by the RTE i nstruction. I f the frame i s found to be inva l id or i naccessi ble, a format error or a bus error exception is taken, respectively. Otherw ise, the processor reads the entire frame i nto the proper i nternal reg i sters, dea l l ocates the proper stack, and resu mes nor mal process i ng . O nce the processor beg i n s to read the frame, a bus error must not occ u r or t h e processor w i l l enter t he ha lted state. Refer to 6.4 BUS FAULT RECOVERY f o r more i nformation on the behavior of t he processor after the frame is read i nto the i nternal reg i sters. If a format error or bus error occurs d u r i n g the execut ion of the RTE i nstruction, either due to any of the errors descri bed above or due to an i l legal format code, the processor w i l l create a normal fou r word or a bus cycle fau lt stack frame above the frame that it was attem pting to use. In this way, the fau lty stack frame remains i ntact and may be exa m i n ed by the format error or bus error exception hand ler and repai red, or used by another processor of a d ifferent type (e.g . , an MC680 1 0, M C680 1 2, or a future M68000 processor) in a m u l t i processor system. 6.4 BUS FAU LT RECOVERY There are two facets to recovery from a bus cyc le fau lt: recognition of the fau lt and sav i n g the processor state, and restori ng the state at a later t i me. A memory fau l t i s i nd icated to the M C68020 by an address error (generated i nternal ly), or by a bus error (generated by external logic, genera l ly by a memory management device or su bsystem). The processor state is saved on the su pervisor stack as descri bed in 6.3.3 Bus Error, and the state may be later restored by the RTE i nstruction as descri bed i n 6.3.1 1 Return From Exception. The act ion taken by the processor after t h e ret urn can be control led, to some degree, by manipulating the data i n the bus fault stack frame as descri bed below. The M C68020 can have fau lts occur on either i nstruction stream or data accesses. Fa u l ts on data accesses are taken when the bus cyc le is termi nated. Faults on i nstruction stream accesses are delayed u nt i l the processor attempts to use the i nformation, if ever, which was not obtai ned due to the aborted bus cycle. Address error faults occur only on i nstruction stream accesses, and are taken before the bus cycle is attempted.

61 6

6.4.1 Spec i a l Status Word There are several spec ial reg i sters saved as part of the bus fau lt except ion stack frame i nformation, i nc l u d i n g the i nternal special stat us word (see F i g u re 6-2). This word is pl ac ed i n the stack frame, at offset $A, for both the short bus cycle fau lt format and the long bus cyc le fau lt format. Refer to 6.5.5 Short Bus Cycle Fault S t a c k F r a m e and 6.5.6 Long
Bus Cycle Fault Stack Frame.

15
FC

14
FB

13
RC

I RB I 0 I 0 I 0

12

11

10

8
DF

I RM I RW I

5
SIZ

FC - Fault on Stage C of the Instruction Pipe - Fault on Stage B of the Instruction Pipe FB - Rerun Flag for Stage C of the Instruction Pipe* RC - Rerun Flag for Stage B of the I nstruction Pipe* RB - Fault/Rerun Flag for Data Cycle* DF - Read-Modify-Write on Data Cycle RM - Read/Write for Data Cycle 1 = Read. 0 = Write RW SIZ - Size Code for Data Cycle FCO-FC2 - Address Space for Data Cycle * 1 = Rerun Faulted Bus Cycle. or Run Pending Prefetch 0 = Do Not Rerun Bus Cycle
-

3 0

FC2-FCO

Figure

6-2. Special Status Word (SSW)

The spec i a l status word (SSW) i nformation defines whether the fau lt was on the i nstruc t i on stream, data stream, or both. There are two status bits each for the S and C stages of the i nstruction p i pe. The rerun flag bits (RS and RC) i nd i cate that the processor w i l l rerun the bus cyc le for the correspond i n g stage during the RTE i nstruct ion. This can be due to either a prefetch that i s pend i n g or to a fau lt that occu rred w h i l e executing a prefetch. The fau l t bits (FS and FC) ind icate that the processor attem pted to use a stage and found it to be marked as i nva l i d due to a bus error on the prefetch for that stage. The fau l t bits are outputs only that can be u sed by a bus error hand ler to determ i ne the cause(s) of a bus error except ion; they are i g nored when the processor reads the stack frame d u r i ng an RTE. The rerun bits i n d i cate if an element of the i nstruction pipe is va l id, and can be u sed by a handler to repair the pipe due to a fault (either an address error or a bus error). RS and RC are used by the processor d u r i n g an RTE to control the execution of bus cyc les for each stage; if eit her, or bot h, of the rerun bits are set when the RTE i nstruction reads the frame, the processor w i l l rerun the previously fau lted prefetch cyc le (or execute a pend i n g prefetch for the f i rst t i me). I f a rerun bit is clear, it is assu med that there is no prefetch pen d i n g for the corresponding stage and that software has repai red or f i l led the i mage of the stage, if necessary. When the SSW is w ritten to the stack frame during ex ception process i ng, the RS and/or RC bits w i l l be set if the corresponding fau l t bit is set, or if a prefetch for the stage is pen d i n g , so that the defau l t (if the hand ler does not mod i fy RS and/or RC) is to have the processor execute the bus cycle(s). The address space for i n struction stream fau lts is not presented explicit ly, but is the program space for the privi lege level i nd i cated i n the status reg i ster of the stack frame. If an address error except ion occurs, the fau lt bits w ri tten to the stack frame w i l l not be set (S i nce t hey are only set due to a bus error, as described above), and the rerun bits must be used to determ i ne the cause of the except ion. Depending on the state of the pi pel i ne, either R S and RC w i l l bot h be set, or RS alone w i l l be set. I f it i s desi red to repa i r the pipe l i ne a n d cont i n u e execution o f the suspended i nstruction, software m u s t place the correct i nstruct ion stream data in the stage C and/or stage S i mages (and c lear the correspond i n g reru n b its), depe n d i n g on the state of the rerun bits. 6-1 7

I f the OF bit of the SSW is set, a data fau lt has occu rred. I f the OF bit is set when the pro cessor reads the stack frame, it w i l l reru n the fau lted data access; otherw i se, it assumes that no data fau lt occu rred, or software has corrected the fau lt. Other i nformat ion about the data access, such as read/w rite, read-mod i fy-write, the s ize of the operand access, and the add ress s pace for the access are present i n the SSW. Data and i nstruct ion stream fau lts may be pend i n g s i m u l taneously; thus, the fau lt handler should be able to hand le any combi nation of the FC, FB, RC, RB, and OF bits. 6.4.2 Completing the Bus Cyele(s) There are two methods of complet i n g fau lted bus cyc les. The first is to u se a software handler to e m u l ate the cycle and the second is to al low the processor to rerun the bus cy c l e(s) after the cause for the fau lt has been repaired. 6.4.2.1 COM PLETI NG THE BUS CYClE(S) VIA SOFTWARE. Based on the i nformation saved on the stack, the fau l t handler rou t i ne may emulate the fau lted bus cycle in a man ner that is transparent to the i nstruction that caused the fau lt. For i nstruction stream faults, there are separate i mages for the B and C stages of the i nstruction p i pe that may need repai r. If the fau lt i n d i cator for a part i c u lar stage i s set, the processor has fau lted because the fetch of the i nstruction word was aborted by an add ress error or a bus error. For the short format frame, the address of the stage B word is the value in the program counter plus fou r, and the add ress of the stage C word is the value in the program counter p l u s two. For the long format, the add ress of the stage B word is g iven expl i c it ly, and the address of the stage C word is the address of the stage B word m i n u s 2. For each fau lted stage, the software handler should fetch the i nstruction word from the proper ad d ress s pace as i n d icated by the S bit of the status reg i ster in the frame, and write i t to the i mage of the stage in the stack frame. In add it i on, the handler must c lear the rerun b i t associated with the stage that i t h a s com pleted. T h e fau l t bits f o r each stage s h o u l d not be c hanged. For data write operat ions, the handler must transfer the properly s ized data in the i mage of the data output buffer (OO B) to the l ocation i nd icated by the fau l t address in the ad d ress s pace defi ned by the SSW. For data read operat ions, the handler must transfer pro perly s ized data from the location i n d icated by the fau lt address and address space to the i mage of the data i n pu t buffer (OI B). Byte, word, and 3-byte operands appear rig ht j ustified w i t h i n the 4-byte i mage of the data buffers. I n add it ion, the software handler must c lear the O F b i t of the SSW to i nform the processor that the fau lted data bus cyc le has been completed. In order to e m u l ate a read-mod ify-write cycle, the exception handler must f i rst determ i ne what i nstruction, CAS, CAS2, or TAS, caused the fau lt. This may be accom p l ished by ex a m i n i n g the operation word at the add ress contai ned in the stack frame program counter. Then the handler must mod ify not o n ly the SSW of the stack frame, but also the status reg i ster image and the i mage of any data reg i ster(s} req u i red for the CAS and CAS2 i nstructions (presu mably, the user visible reg isters were saved upon entry to the handler with a MOVEM i nstruction and are restored later). In other words, the fau lt handler must emulate the entire i nstruction, rat her than j ust the faulted bus cycle. Th i s more detai led action i s req u i red due to the fact that the processor assumes that the en t i re read-mod ify-w rite operation (wh i c h may consist of up to fou r long word t ransfers), i n c l u d i n g condit ion code computat ions and reg i ster transfers, is com pleted by the handler 6-1 8

if the OF bit is clear and the RM bit is set when the frame is read by an RTE i nstruction. This i s true regard less of w hether the fau l t occu rred on the f i rst read cycle, or su bse quent read or write cyc les of the operat ion. After the handler has com pleted the software emu lation, the stack frame and the memory state represent the state of the system after the bus cyc le(s) has been suc cessf u l ly completed. N ote t hat the software met hod must be u sed for address error faults. To ensure proper operation of the processor, no modif ications to a bus cyc le fau l t stack frame other than those descri bed above should be made. 6.4.2.2 COM P LETI NG THE BUS CYCLE(S) VIA RTE. If it is not necessary to complete the fau lted bus cyc le via software emulation, the RTE i nstruction, as the last instruction to be exec uted in the except ion handler routi ne, i s able to complete the fau l ted bus cycle(s) . This is the default case and it is assu med that whatever caused the fau lt, such as a non resi dent page in a virtual memory system, has been repa i red or the fault w i l l occ u r agai n. I f a fault occu rs when the RTE i nstruction attempts to rerun the bus cycle(s), a new stack frame w i l l be created on the su pervisor stack after the previous f rame is deallocated; and address error or bus error exception processing w i l l start in the normal manner. The read-mod ify-write operat ions of the M C68020 provide for a special case of the bus fau l t recovery proceSSing. While the bus recovery processing for a l l read and write opera t i ons are strictly on a cyc le-by-cyc le basis, t hat for a read-mod ify-write operat ion is on an i nstruct ion basis. This means that d u ri n g an RTE f rom a bus error of a read-mod i fy-write operat ion, i f the O F bit in the SSW i s set, i n d icat i n g that the cycle should be rerun, then the processor w i l l rerun the ent i re operat ion from beg i n n i ng to completion regard less of which part of the operat ion caused the bus error. S i m i larly, if the OF bit is cleared, i n d i cat i n g that the operation has been com pleted in software, the processor assumes that the ent i re operat ion has been completed and w i l l i m med iately proceed with the next i nstruct ion. Systems prog rammers and des i g ners both should be aware of this facet of the processor and its i m p l i cations. Specifical ly, it is recommended that memory management mechanisms t reat any bus cyc le with RMC asserted as a w ri te operation for protection check i n g operat ions regardless of the state of the R/W signal. Ot herwise, the potential for part i a l ly destroying system pOi nters with the CAS and CAS2 i nstructions ex ists si nce one port ion of the w rite operation cou ld take place and the remai nder aborted by a bus error. 6.5 MC68020 EXCEPTIO N STACK F RAMES The M C68020 generates s i x d ifferent stack f rames. These frames consist of the normal fou r and six word stack frames, the fou r word th rowaway stack frame, the coprocessor m id-i nstruction except ion stack frame, and the short and long bus fau lt stack f rames. Whenever the MC68020 writes or reads a stack frame, it w i l l use long word operand t ransfers whenever possible. Thus, i f the stack area res ides in a 32-bit ported memory and the stack poi nter is long word a l i g ned, exception processing performance w i l l be

6-1 9

g reat ly enhanced. A l so, the order of the bus cycles used by the processor to write or read a stack frame may not fol l ow the order of the data in the frame. 6.5.1 Normal Four Word Stack Frame This frame (see F i g u re 63) is created by interrupts, format errors, TRAP #n i nstruct ions, i l legal i nstructions, Al i ne and Fl i n e emulator traps, privi lege violations, and coprocessor pre i nstruction exceptions. The program cou nter value is the address of the next i nstruction to be executed, or the i nstruction that caused the except ion, depen d i n g on t h e exception type.
SP+ $02 15 Status Register Program Counter 0 0 0 0 o

+ $06

Figure 63. Format $0 6.5.2 Throwaway Four Word Stack Frame

Vector Offset

Four Word Stack Frame

This stack frame (see Figure 64) is the throwaway frame that is created on the i nterrupt stack d u r i n g except ion processing for an i nterrupt when a transition from the master state to the i nterrupt state occu rs. The program cou nter value is equal to the value on the normal fou r word or coprocessor midi nstruction exception stack frame that was created on the master stack.
S P -15 Status Register Program Register 0 0 0 1 o

+ $02

+ $06

Figure 64. Format $1

Vector Offset
-

Throwaway Four Word Stack Frame

6.5.3 Normal Six Word Stack Frame Th i s stack frame (see F i gure 65) is created by i nstruct ion related except ions which i n c l ude coprocessor post i n st ruction except ions, C H K, C H K2, cpTRAPcc, TRAPcc, TRAPV trace, and zero d ivide. The i nstruction address va lue i s the address of the i nstruct ion that caused the except ion. The prog ram counter value is the address of the next i nstruct ion to be executed, and the address to which the RTE i nstruction w i l l retu rn.

620

S P -. + $02

15 Status Register Program Counter 0 0 1 0

+ $06 + $06

1
-

Vector Offset I nstruction Address

Figure 65. Format $2

Six Word Stack Frame

6.5.4 Coprocessor M idlnstruction Exception Stack Frame Th i s stack frame (see F i g u re 66) is created for three d i fferent except ions, a l l related to coprocessor operations. The f i rst occurs when the "take m idi nstruction except ion" pri m i t ive i s read while processing a coprocessor i nstruction. The second occurs when the m a i n processor detects a protocol violation d u r i n g process i n g of a coprocessor i n struction. The t h i rd occurs when a " n u l l , come agai n with i nterru pts al lowed" primit ive is received, and the processor detects a pend i n g i nterru pt. Refer to SECTION 8 COPROCESSOR I NTER FACE DESCRIPTION for furt her deta i ls. The program cou nter val ue i s the address of the next word to be fetched from the i nstruction tream. The i n struction address va lue is the address of the f i rst word of the i nstruct ion that was ex ecu t i n g w hen the exception occu rred.
S P -+ $02 15 Status Register Program Counter 1 0 0 1 o

+ $06

+ $ 08

I
Instruction Address Internal Registers, 4 Words

Vector Offset

+ $ OC

+ $12

Figure 66. Format $9 Coprocessor M idl nstruction Exception Stack Frame (10 Words)
-

6-21

6.5.5 Short Bus Cycle Fault Stack Frame This stack frame (see F i g u re 67) is created whenever a bus cyc le fau lt is detected, and the processor recogn izes that it is at an i nstruct ion bou ndary and can use this reduced version of the bus fau lt stack frame. The program cou nter value is the address of the next i nstruction to be executed.
SP + $02 + $06 + $ 04 1 0 1 0 15 Status Register Program Counter
o

+ $08 + $OA + $OC + $OE + $1 0 + $1 2 + $14 + $16 + $ 18 + $1 A + $1 C + $1 E

Vector Offset Internal Register Special Status Word Instruction Pipe Stage C Instruction Pipe Stage B Data Cycle Fault Address Internal Register Internal Register Data Output Buffer Internal Register Internal Register

Figure 67. Format $A

Short Bus Cycle Fault Stack Frame (16 Words)

6-22

6.5.6 Long Bus Cycle Fault Stack Frame Th i s stack frame (see F i g u re 68) is created whenever the processor detects a bus cyc le fau lt and recog n izes that it i s not on an i nstruct ion boundary. The program counter va lue i s the address of the i nstruction t hat was exec u t i n g when the fau lt occu rred (which may not be the i nstruction that generated the fau lted bus cyc le).
S P ---+ + $02
+ 1

15 Status Register Program Counter 1 0 1

$06

+ $08 + $0A + $0 C + $0 E + $1 0 + $12 + $ 14 + $ 18 + $1C

Vector Offset Internal Register Special Status Word Instruction Pipe Stage C Instruction Pipe Stage B Data Cycle Fault Address Internal Registers, 2 Words Data Output Buffer

Internal Registers, 4 Words + $22 + $ 24 + $ 28 + $2 A + $2 C + $ 30 Internal Registers, 22 Words + $5A Stage B Address Internal Registers, 2 Words Data Input Buffer

Figure 68. Format $B - Long Bus Cycle Fault Stack Frame (46 Words)

623

6.5.7 Stack Frame Summary F i g u re 69 shows a s u m mary of the M68000 Fam i ly defi ned stack frames.
Format Frame Type

0000 000 1 0010 001 1 -01 1 1 1000 1001 1010 101 1 1 100-1 1 1 1

Short Format (4 Words) Throwaway 14 Words) Instruction Exception 16 Words! ( Undefined, Reserved! MC68010 Bus Fault (29 Words) Coprocessor Midlnstruction ( 1 0 Words! MC68020 S hort Bus Fault ( 1 6 Words! MC68020 Long Bus Fau!t 146 Words! ( Undefined, Reserved!

Figure 69. Stack Frame Format Definitions

6-24

S ECTIO N 7 ONCH I P CACH E M EM O RY

The MC68020 incorporates an on-ch i p cache memory as a means of i m proving the perfor mance of the processor. The cache is i m p lemented as a CPU i nstruction cache and i s u sed to store t h e i nstruction stream prefetch accesses from the m a i n memory. Studies have show n that typical programs spend most of their execution t i me in a few main rout i nes or tight l oops. Therefore, once capt u red in the h i g h-speed cache, these ac t ive code segments can execute d i rect ly from the cache. Thus, the processor does not suffer any external memory de lays, and the total execut ion t i me of t he program is s i g n ificantly improved. The performance is also improved by al low i n g the M C68020 to make s i m u ltaneous accesses to i nstructions in the i nternal cache and to data in the external memory. Another of the major benefits of using the cache is that the processor's external bus activity i s g reatly red uced. Thus, i n a system with more than one bus master (such as a processor and DMA device) or a tightly-coup led mult i-processor system, more of the bus bandw idth i s avai lable to the alternate bus masters without a major deg radat ion i n the performance of the M C68020. 7_1 CAC H E DESIGN A N D O PERATION The follow i n g parag raphs desc ribe t he cache design and operat ion w i t h i n the MC68020. 7. 1 .1 On-Chip Cache Orga n ization The MC68020 on-c h i p i n struct ion cache i s a d i rect-mapped cache of 64 long word entries. Each cache entry consists of a tag field made u p of the upper 24 address bits and the FC2 va l ue, one va l id bit and 32 bits (two words) of i nstruct ion data. F i g u re 7-1 shows a block d iagram of the on-chip cache. Whenever an i nstruction fetch oc c u rs, the cache (if enabled) is f i rst checked to determ i ne if the word req u i red is in the cache. This is achieved by f i rst u s i n g the i ndex field (A2-A7) of the access address as an i ndex i nto the on-c h i p cache. Th is selects one of the 64 entries in the cache. Next, the ac cess address bits A8-A31 , and FC2 are com pared to the tag of the selected entry. If t here is a match and the val i d bit is set, a cache h i t occurs. Address bit A 1 is u sed to select the proper word from the cache entry and the cycle ends. If there is no match, or the val id bit i s clear, a cache m i ss occurs and the i nstruct ion i s fetched from external memory. This new i nstruction i s automatically written into the cache entry, and the va l i d bit is set, u n less the freeze cache bit has been set (see 7.1 .2_3 F- FREEZE CACH E) in the cache

7-1

A 3 1

--l 1- 1"

MC68020 Prefetch Address A A A A A A A A A A A A A A A A A A A A A A A A 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 3 2 1 0 Tag d ' '" " I t Select Word

4

Tag

Word

Word

Select Tag Replace

Comparator

Replacement Data To Instruction Path ::4-0--- Hit -----'- Cache Control

'---+----'-

Figure 71 . MC68020 OnChip Cache Organization control reg i ster. Since the processor always prefetches i nstructions external ly with long word, a l i g ned bus cycles, both words of the entry w i l l be updated, regardless of which word cau sed the m i ss. N OTE Data accesses are not cached, regard less of their associated address space. 7.1 .2 Cache Control The cache itself is accessable o n ly by t he i nternal M C68020 control u n it. The user has no d i rect method of accessing (read/write) i nd ividual entries (tag, data, etc.). To manipu late the cache entries, however, the u ser does have a set of control functions avai lable in the form of a cache control reg ister which i s descri bed below. 7.1 .2.1 CAC H E CONTROL REG ISTER. Access to the cache control reg ister (CACR) i s pro vided by means of the M ove Control Reg i ster (MOV EC) i nstruction. The M OV EC i nstruc tion is a privi leged i nstruction. The CACR is a 32bit reg ister which is organ ized as show n i n F i g u re 72. The u n u sed b i t s ( i n c l u d i n g bits [31 :8] which are not shown) are always read as zeros.

72

I0

31

C CE F E

= = = =

Clear Cache Clear Entry Freeze Cache Enable Cache

Figure 72. Cache Control Register

I 0 I 0 I 0 I 0 I C ICE I I E I

7.1 .2.2 E- ENABLE CACH E. The cache enable fu nction is necessary for system debug and emulation. This bit al lows the des ig ner to operate the processor with the cache d isabled. C leari ng this bit w i l l d isable t he cache (force cont i n uous m isses, and su ppress f i l l s) and force the processor to always access external memory. The cache w i l l remain d isabled as long as t h i s bit i s c leared. The u ser m u st set t h i s bit, which i s automatically c leared w henever the processor is reset, to enable the cache. 7.1 .2.3 F- FREEZE CAC H E. The freeze bit keeps t he cache enabled, but cache m isses are not a l l owed to replace val id cache data. This bit can be u sed by emulators to freeze the cache d u r i n g emu lat ion function execution. 7.1 .2.4 CE-CLEAR ENTRY. When t he c lear entry bit i s set, the processor takes the ad dress (i ndex field, bits 27) in the cache address reg i ster (CAAR) and i nvalidates the assoc iated entry (clears the va l i d b it) in the cache, regard less of whether or not it pro vides a hit; i.e., whether the tag field in t he cache address reg ister matches the cache tag or not. This function w i l l occ u r only w hen a w rite to the cache control reg ister is perform ed with t he CE bit set. This bit always reads as a zero and the operat ion is i ndependent of the state of the E or F bits, or the external Cache D i sable (CDIS) p i n . 7.1 .2.5 C- CLEAR CAC H E. The cache c lear bit i s used t o i nva l i date a l l entries i n the cache. This function is necessary for operati n g systems and other software which must c lear old data from the cache w heneve r a context switch is req u i red. The setti n g of the c lear cache bit i n the cache control reg i ster causes a l l va l i d bits i n the cache to be cleared, thus i nvalidat i n g a l l entries. This function occurs only when a w rite to the cache control reg ister is performed with the C bit set. This bit always reads as a zero. 7.2 CAC H E ADDRESS R EGISTER The cache address reg i ster (CAAR) i s a 32bit reg ister which provides an address for cache control functions (see F i g u re 73). The M C68020 only u ses this reg ister for t he clear entry (CE) function. Access to the CAAR is provided by t he M ove Control Reg i ster (MOVEC) i nstruction.
31 8 7 2 1 0

Cache Function Address

Figure 73. Cache Address Register

Index

I I

73

7.3 CAC H E DISABL E I N PUT The cache disable i n put is u sed to dynamica l l y d isable the cache. The i n put signal on this pin is synchron ized before bei n g u sed to control the i nternal cache. The cache is d isabled on the f i rst cache access after the synchron ized CDIS signal is recog n ized as being asserted. The cache w i l l be reenabled o n the first cache access after the syn chron ized CDIS signal is recog n ized as bei n g negated. Th is pin disables the cache i n dependent of the enable bit i n the Cache Control Register and, therefore, can be u sed by external emu lator hardware to force the M C68020 to make a l l accesses via the external bus. 7.4 CAC H E I N ITIALIZATION During processor reset, the cache is cleared by resetting a l l of the valid bits. The Cache Control Register (CACR) enable (E) and freeze (F) bits are a l so cleared.

7-4

SECTI ON 8 COP ROC ESSOR I NT E R FACE D ESC R I PTION

T h i s sect ion describes t h e M68000 coprocessor i nterface. It is intended f o r desig ners who are i m plement i n g a coprocessor to i nterface to the MC68020. M otorola coprocessors w i l l conform to the i nterface descri bed i n this section and their use does not req u i re a detai led know ledge of the M68000 coprocessor i n terface. These coprocessors w i l l execute M otorola defi ned i nstru ct ions that are descri bed in the respective coprocessor user manuals. 8.1 I N T R O D U CTION The M68000 Fami ly of general pu rpose microprocessors provide a level of performance which sat isfies a w ide range of computer appl ications. Spec ial pu rpose hardware, however, can often provide h i g her level s of performance for a spec ific appl ication. The coprocessor concept al lows the capab i l ities and performance of a general pu rpose pro cessor to be enhanced for a particu lar appl i cation without unduly encu mbering the main processor arch itect u re. A coprocessor can be des i g ned to eff iciently hand le any number of spec ific capabi l ity req u i rements that must typica lly be implemented in software by a general pu rpose processor. Thus, the processi n g capab i l i t ies of a system can be tail ored to a spec ific application by ut i l izing a general pu rpose main processor and the ap propriate coprocessor(s). It is i m portant to make the d isti nction between standard peri pheral hardware and a M68000 coprocessor. An M68000 coprocessor i s a device or set of devices that have the capabil ity of com m u n icat i n g with the main processor th rough the protocol def i ned as the M68000 coprocessor i n terface. A coprocessor d iffers from a peri pheral particu larly from the perspective of the main processor progra m m i n g model. This program m i ng model con sists of the i nstruction set, reg i ster set, and memory map available to the program mer. A coprocessor adds add i t ional i nstructions, and generally add itional reg i sters and data types which are not d i rect ly su pported by the main processor arc h itect ure. Dedicated coprocessor i nstructions are provided to u t i l ize the coprocessor capab i l it ies. The i nteract ions between the main processor and the coprocessor that are necessary for the coprocessor to provide a g iven service, are transparent to the prog ram mer. That is, no know ledge of the commun icat ion protocol between the main processor and the coprocessor is req u i red of the prog rammer s i nce this protocol is i m p l emented in hard ware. Thus, the coprocessor can provide capab i l ities to the user without appeari ng as hardware external to the main processor. In contrast, standard peri pheral hardware is generally accessed th rough the use of i nter face reg isters mapped i nto the memory space of the main processor. The prog rammer u ses standard processor i nstru ctions to access the peripheral i nterface reg i sters and

8-1

thus ut i l ize the services provided by the peripheral. Wh i l e a peri pheral cou ld conceivably p rovide capab i l ities eq uivalent to a coprocessor for many appl ications, the programmer must i m plement the com m u n i cation protocol between the main processor and the peri pheral necessary to use the peri pheral hardware. 8.2 M68000 FAM I LY COP ROCESSO R INTERFACE OVERVI EW The com m u n i cation protocol defi ned for the M68000 coprocessor i nterface w i l l be descri bed u nder 8.3 COPROCESSOR I NSTRUCTION TYPES. The algorithms necessary to i m p lement the M68000 coprocessor i n terface are provided in the m icrocode of the MC68020 and are com pletely transparent to the MC68020 programmer's model. For ex amp le, floati ng-point operat ions are not i m p lemented in the MC68020 hardware. In a system u t i l izing both the MC68020 and the M C68881 F loati ng,Po i nt Coprocessor, a pro g rammer can use any of the i nstructions def i ned for the M C68881 without the knowledge that the actual com putat ion is performed by the MC68881 hardware. A M68000 coprocessor may be coup led with a main processor which does not have a coprocessor i n terface such as an MG68000, MC68008, MC680 1 0 , or MC680 1 2. Th is is ac comp l i shed by providing i nstruction seq uences that emulate the protocol of the coprocessor interface descri bed i n this sect ion. The coprocessor w i l l appear as a peri pheral in the program m i ng model of these p rocessors. 8.2.1 Interface Features The M68000 coprocessor i nterface des i g n incorporates a number of flexible capabi l i t ies. The phys i cal coprocessor i n terface i s based on M68000 asynchronous bus cyc les which s i m p l ifies the i nterface s i nce there are no special pu rpose signals i nvolved. Si nce stan dard M68000 asynch ronous bus cyc les are used to transfer i nformat i on between the main processor and the coprocessor, the coprocessor can be implemented in the technology which i s ava i l able to the coprocessor des i g ner. A coprocessor can be im plemented as a V LSI devi ce, as a separate system board, or even as a separate com puter system. Si nce the main processor and a M68000 coprocessor com m u n i cate using an asyn chronous bus, they are not req u i red to operate at the same c l ock freq uency. This feature al lows the system des i g ner to optim ize the s peed of the various sections of the p rocess i n g hardware for a particular system appl icat ion. The deSig ner is free to choose the s peeds of a main processor and coprocessor which provide the opt i m u m performance for a g iven system. The M68000 coprocessor i nterface also fac i l itates the des i g n of coprocessors. The coprocessor des i g n need only conform to the coprocessor i nterface and does not req u i re extensive know ledge of the arch itect ure of the main processor. The coprocessor must reflect the arch itectu re of the main processor only to the extent that it mu st use the M68000 coprocessor i nterface p rotocol to com m u n i cate with the main processor. Also, the main processor can operate with a coprocessor without explicit provisions for the capabil it ies of that coprocessor bei n g made in the main processor arc h itecture. Si nce the capab i l ities of the coprocessor are not d ictated by the arc h itect ure of the main pro cessor, the coprocessor des i g ner has a great deal of freedom in the i m p lementat ion of a g iven coprocessor.

8-2

8.2.2 Concurrent Coprocessor Operation Su pport The program mers model for the M68000 Fam ily of m i c roprocessors is based on seq uen tial, non-concurrent i nstruction execution. Th is i m p l i es that the i n structions in a g iven se quence are executed i n the order which they occur and that a l l act ions performed by an i n struction w i l l be completed by the t i me the next i nstruction in the seq uence executes. In order to maintain a u n i form prog rammers model, any coprocessor extensions should also mainta i n the model of sequential, non-concurrent i nstruct i on execut ion at the user leve l . That is, the programmer may assume that all services provided by a g iven i nstruc t i on w i l l have been completed when the next i nstruction in the seq uence exec utes. The M68000 coprocessor i n terface i s des ig ned to provide f u l l support of all operat ions necessary for non-concu rrent operation between the main processor and its associ ated coprocessors. W h i le the M68000 coprocessor i n terface al lows concu rrency i n coprocessor execution, i t i s the responsibi l ity o f the coprocessor des i g ner t o i m plement this concu rrency w h i l e mainta i n i ng a progra m m i n g model based on sequential, non concu rrent i nstruction execution.

8.2.3 Coprocessor I nstruction Format The i nstruction set for a g iven coprocessor is defi ned by the design of that coprocessor. When a coprocessor i nstruct ion is encountered i n the main processor i nstruction stream, the MC68020 hardware i n i t i ates comm u n ication with the coprocessor and co ordi nates any i nteraction necessary for the i nstruction execution with the coprocessor. A prog rammer is req u i red to know o n ly the i nstruction set and reg ister set defi ned by the coprocessor in order to ut i l ize the fu nctions provided by the coprocessor hardware. The i n struct ion set of an M68000 coprocessor is implemented by using the F-l i ne opera tion words in the M68000 i nstruction set. The operation word is the f i rst word of any M68000 Fam i ly i nstruction. The F- l i ne operat ion word contains ones in bits 1 5 t h rough 1 2 ([1 5: 1 2) = (1 1 1 1 ) ; see F i g u re 8-1 ) and the rema i n i n g bits are used t o spec i fy the type of coprocessor i n struct i on that w i l l be executed. The F-l i ne operation word may be followed by a number of extension words which provide add it ional information necessary for the execut ion of the coprocessor i nstruction. B its 1 1 t h rough 9 of the F-l i ne operat ion word are used to encode the coprocessor iden t i f ication code (Cp-I O). The MC68020 uses the coprocessor ident ification field to i n d i cate which coprocessor it is accessing for a g iven coprocessor i nstruct i on.

15

14

13

12

11

10 Cp- I D

7 Type

3 Type Dependent

Figure

81 . F-line Coprocessor I nstruction

Operation Word

8-3

Cp-I D codes of 000- 1 0 1 are rese rved for cu rrent and future Motorola coprocessors and Cp- I D codes of 1 1 0-1 1 1 are reserved for user defi ned coprocessors. The Motorola Cp- I D codes w h i c h are cu rrently defi ned are: Cp1D Code 000 001 Motorola Coprocessor M C68851 Paged-Memory Management Unit M C68881 F l oating-Point Coprocessor

Thus, M otorola assemb lers w i l l by defau lt use the Cp- I D codes spec ified above when generat i n g the i nstruction operat ion codes for the MC68851 and MC68881 coprocessor i nstruct ions. The encod i n g of bits 8 t h rough 0 of the coprocessor i nstruction operat ion word i s depen dent on the particu lar i nstruct ion bei n g i m p lemented. These encod i ngs are d i scussed i n 8.3 COP ROCESSO R I NSTRUCTION TYPES. 8_2.4 M68000 Coprocessor System I nterface The com m u n i cation protocol between the main processor and coprocessor necessary to execute a coprocessor i nstruction is based on a group of i nterface reg i sters which are defi ned for the M68000 coprocessor i nterface. The MC68020 hardware i n i t iates a coprocessor i nstruction by accessing one of these reg isters. The coprocessor uses a set of response primit ive codes and format codes defi ned for the M68000 coprocessor inter face to com m u n i cate status and service requests to the main processor. The coprocessor i nterface reg i sters are also used to pass opera nds between the main processor and the coprocessor. The coprocessor i nterface reg i ster set, response pri m i t ives, and format codes wi l l be d i scussed in 8.4 COP ROCESSOR I NTERFACE REGISTER (CI R) SET and 8_6 COPROCESSO R RESPONSE PRIMITIVE SET DESC R I PTION. 8_2.4.1 M68000 COP ROCESSOR BUS I NTERFACE. The M C68020 uses standard M68000 asynchronous bus cycles to access the registers i n the coprocessor i nterface reg i ster set. Thus, the bus i nterface i m p lemented by a coprocessor for its i nterface reg i ster set must only sati sfy the M C68020 address, data, and control signal t i m i n g to g uarantee proper com m u n i cation with the main processor. The MC68020 t i m i n g i nformation for read and w rite bus cycles i s i l l ustrated in Fig ures 1 0-5 and 1 0-6 found on foldout pages i n the back o f t h i s manual. A detai led discussion o f the MC68020 async h ronous bus opera tion is contai ned in SECTION 5 BUS OPERATIO N . 8.2.4.2 CPU ADD RESS SPACE. D u r i n g coprocessor i nstruct ion execution, t h e M C68020 executes bus cycles in CPU space to access the i nterface reg ister set of a coprocessor. The M C68020 ind icates that it is acceSSing CPU space by driving the three function code outputs h i g h d u r i n g a CPU space bus cycle (FC2-FCO = 1 1 1 ; see 5.2.4 CPU Space Cycles). Thus, the coprocessor i nterface reg ister set is mapped i nto CPU space in the same manner that a peri pheral i nterface reg i ster set is genera l ly mapped into data space. The i nformation encoded on the function code l i nes and address bus of the

8-4

MC68020 d u r i n g a coprocessor access is used to generate the c h i p sel ect s i g nal for the coprocessor bei n g accessed. The address l i nes of the M C68020 are also used to spec ify which reg i ster i n the i nterface set is be ing accessed d u ri n g operand transfers between the main processor and the coprocessor. The i nformat ion that is encoded on the fu nction code and address l i nes of the M C68020 during a coprocessor access is i l l ustrated in F i g u re 8-2.

Function Code
1 1 1

Address Bus

11

31 0 0 0 0 0 0 0 0 0 0 0 0

19 15 0 0 1 0

CPU ISpace Type Field

1 Cp-ID 1 0

12 0 0 0 0 0 0 0

1 CIR Register
4

Figure 82. M C68020 CPU Space Address Encodings

Address signals A 1 9-A 1 6 specify the CPU space cycle type during a CPU space bus cyc le. The types of CPU space cycles cu rrently def i ned for the M C68020 are i nterru pt acknowledge, breakpo int acknowledge, mod u le su pport operat ions, and coprocessor access cycl es. CPU space type 2 (A 1 9-A 1 6 = 001 0) specif ies a coprocessor access cyc le. A 1 5-A1 3 of the M C68020 address bus spec ify the coprocessor ident if icat ion code (Cp-ID) for the coprocessor bei n g accessed. This code is extracted from bits 1 1 -9 of the coprocessor i nstruct ion operat ion word (see F i g u re 8-1 ) and placed on the address bus d u ri n g each coprocessor access. Thus, a chip sel ect s i g nal for a g iven coprocessor can be generated by decod i n g the M C68020 fu nction code signals and bits A 1 9-A 1 3 of the address bus. The fu nction code signals and A1 9-A 1 6 i ndicate a coprocessor access in CPU space, w h i l e A 1 5-A1 3 i nd i cate which of the poss ible eight coprocessors assoc iated with the main processor is bei n g accessed. Bits A31 -A20 and A1 2-A5 of the MC68020 address bus are always zero d u r i n g a coprocessor access generated in conj u nction with the execution of a coprocessor i n struction. The MC6801 0 and MC6801 2 can emu late coprocessor access cycles i n CPU space u s i n g the MOVES i nstruction. 8.2.4.3 COPROCESSOR I NTER FACE REGISTER (CIR) SE LECTION. The MC68020 must access the reg isters defi ned i n the coprocessor interface reg ister (CI R) set to com m u n icate with the coprocessor d u r i n g the exeuct ion of a coprocessor i nstruction. During coprocessor access bus cycles, A4-AO of the MC68020 address bus are used to spec ify which reg i ster i n the C I R set is bei n g referenced. The reg i ster map for the M68000 coprocessor i nterface is depicted i n F i g u re 8-3. A detai led descr i pt ion of the i nd ividual reg i sters i s provided in 8.4 COP ROCESSOR INTERFACE REG ISTER (CIR) SET.

8-5

31
00

08 OC 10 14 18 1C

04

Response" Save* Operation Word (Reservedl

15

Register Select

Instruction Address

Operand Address

Operand"

Control" Restore* Command" Condition* (Reservedl

Figure 83. Coprocessor Interface Register Set Map

As a resu l t of the va l ues encoded on the MC68020 address bus duri ng a coprocessor access, each coprocessor in a system is mapped i nto a u n i q u e reg ion of the main pro cessor's logical CPU add ress space. An add ress map for the coprocessor access port ion of the MC68020 CPU space i s presented in F i g u re 84. A4AO i nd icate the i nterface reg i ster offset from the coprocessor base address in CPU space.

2EOOO I-------i 2E01 F

1-------1
------

Interface Register Set Reserved

Figure 84. Coprocessor Address Map in MC68020 CPU Space

Address Space for Coprocessor with Cp-ID = 7

A block leve l diagram of the signals i n volved in the M68000 coprocessor i nterface is pro vided in F i g u re 85. S i n ce the c h i p select for a g ive n coprocessor is based in part on the Cp- I D encoded on A1 5A 1 3 of the M C68020 address bus, the system des i g ner is free to use m u lt i ple coprocessors of the same type by s i m ply ass i g n i n g a u n ique Cp I D to each one.

86

Main Processor MC68020

FCO-FC2 ,. A19-A13 AS DS Riw

Coprocessor Decode Logi c DSACK

CS

Coprocessor

A4-Al D31-DO

.S2 8'
Ul

g $ ,; >

.c -

0 c o

-' OJ u ro
c

Chip select logic may be Integrated into the coprocessor Address lines not specified above are "0" during coprocessor access.
1
=

FC2-FCO 1 1 1 __ CPU Space Cycle A19-A16=OO10 __ Coprocessor Access in CPU Space A 15-A 13 = xxx __ Coprocessor Identification A4-A rrrr Coprocessor Interface Register Selector
__

Figure 85. M68000 Coprocessor Interface Signal Usage The MC68851 Paged-M emory M anagement U n it, however, uses FC2-FCO and A31 -AO as i n puts to perform add ress t ranslations. Thus, the MC68851 decodes the i nformat ion on the MC68020 add ress bus and fu nction code l i nes i nterna l ly to determ i ne when an access is made to one of its coprocessor i nterface reg isters. Si nce the MC68851 decodes the address and fu nction code p i n s i nterna l ly, it req u i res no external chip select logic and thus must be assig ned the Cp- I D 000. 8.3 COP ROCESSO R I N STRUCTION TYPES Fou r categories of coprocessor i nstructions are defi ned for the M68000 coprocessor i n terface: general, cond i t ional, context save, and context restore. These fou r categories are d i s t i n g u i shed by the type of operat ions provided by the coprocessor i nst ruct ions con tai ned in each. The i nstruction category also determ i nes the coprocessor i n terface reg i ster accessed by the MC68020 to i n i t iate the coprocessor i nstruction and the com m u n i cat ion protocol between the main processor and the coprocessor necessary for in struct ion com pletion. During the execution of i n structions i n the general or cond it ional categories, the coprocessor can req uest services from and i n d i cate status to the main processor using the set of coprocessor response pri m i t ive codes defi ned for the M68000 coprocessor i n terface. During the execution of the i nst ruct ion in the context save and context restore categories, the coprocessor i n d i cates its stat us to the main processor by uti l izing the set of coprocessor format codes defi ned for the M68000 coprocessor i n terface.

8-7

8.3.1 Coprocessor General Instructions The general coprocessor i n struction category is u sed to i m p lement data processing i n structions and other general pu rpose i nstructions defi ned for a g iven coprocessor. 8.3.1 .1 FORMAT. The format of a general type i nstruct ion is i l l ustrated in Figure 8-6.

15 1

14

13 1

12 1

Coprocessor Command Optional Effective Address or Coprocessor Defined Extension Words

11

10 Cp-ID

6
0

3 Effective Address

Figure 86. Coprocessor General Instruction Format (cpG EN)

For the pu rpose of this d i scussion, all coprocessor i nstructions in the general i nstruct ion category w i l l be referred to using the cpGEN m nemonic. The actual m nemon ic and syn tax used to represent a coprocessor i nstruction is determ i ned by the syntax of the assembler or compi ler which generates the object code for the coprocessor i n structions . The coprocessor general type i nstruct ions always consists of at least two words. As i n a l l coprocessor i n structions, the f i rst word o f the i nstruct ion i s a n F- line operat ion code (bits [1 5-1 2] = 1 1 1 1 ). The Cp-I D field of the F-I ine operat ion code is used by the MC68020 during the coprocessor access to i nd i cate which of the coprocessors i n the system w i l l execute the coprocessor i nstruct ion. The Cp- I D is placed on A 1 5-A 1 3 during accesses to the coprocessor i nterface reg i sters (see 8.2.4.2 CPU ADDRESS SPACE).

Bits [8-6] = 000 i n d i cate that the i nstruct ion is in the general i n struction category. B i ts 5-0 of the F-l i ne operat ion code may be used to encode a standard M68000 effective address specifier (see 2.8 EFFECTIVE ADDRESS). During the execution of a cpGEN i n struction, the coprocessor can use a coprocessor response primit ive to request that the M C68020 perform an effective address cal culat ion necessary for that i n struction. If the MC68020 receives one of these primit ives, the processor w i l l then u t i l ize the effective address spec i fier field of the F- l i ne operat ion code to determ ine the effective add ress i n g mode bei n g requested. The second word of the general type i nstruct ion i s the coprocessor command word. Th is command word i s w ritten to the command coprocessor i nterface reg i ster (command CI R) to i n i tiate the coprocessor i nstruction.

An i nstruction i n the coprocessor general i n struction category may opt iona l ly i n c l ude a nu mber of extension words which fol low the coprocessor command word in the i n struc tion format. Add itional i nformat ion req u i red for the coprocessor i nstruction execution can be i n c l uded as coprocessor def i ned extension words. If the coprocessor requests that the MC68020 calcu late an effective address during coprocessor i nstruct ion execu tion, i nformation req u i red for the calc u l at ion must be i nc l uded in the i nstruction format as effective address exte nsion words.

8-8

Main Processor Coprocessor M1 Recognize Coprocessor Instruction F-Line Operation Word M2 Write Coprocessor Command Word to Command CIR _ f.!. Decode Command Word and Initiate Command Execution C2 While (Main Processor Service is Requiredl do Steps 1 1 and 21 below M3 Read Coprocessor Response Primitive 1 1 Request Service by Placing Appropriate Response Primitive Code in Response CIR Code from Response CIR 11 Perform Service Requested by Response 21 Receive Service from Main Processor Primitive 21 If (Coprocessor Response Primitive Indicates "Come Again"l go to M3 (see Note 1) C3 Reflect " No Come Again" in Response CI R C4 Complete Command Execution C5 Reflect "Processing Finished" Status in Response CIR M4 Proceed with Execution of Next Instruction (see Note 21 NOTES 1 "Come Again" indicates that further service of the mai n processor is being requested by the coprocessor. 2. The next instruction should be the operation word pointed to by the ScanPC at this point. The operation of the MC68020 ScanPC is discussed in 8.5.2 ScanPC.
-

8.3.1 .2 P ROTOCOL. The execution of cpGEN i nstructions fol l ows the protocol presented in F i g u re 8-7. The m a i n processor i n i t iates com m u n i cation with the coprocessor by writing the i nstruction command word to the command G I R. The coprocessor then decodes the command word to beg i n processing assoc iated with the execution of the cpG EN i nstruct ion. The i nterpretat ion of the coprocessor command word is spec i f ied by the coprocessor des i g n and the M G68020 does not attempt to decode the i nformat i on conta i ned i n this command word.

Figure 87. Coprocessor Interface Protocol for General Category Instructions

After writing to the command GIR, the main processor wi l l read the response G I R to determine its next action. W h i l e the coprocessor is executing an i n struct ion, it may re q uest services from and com m u n i cate status to the main processor by placing the ap propri ate coprocessor response primit ive codes i n the response G I R. When the coprocessor has comp leted the execution of an i nstruct ion or no longer needs the ser vices of the main processor to execute the i nstru ction, it w i l l reflect this status in the response G I R . The main processor w i l l then proceed to the next i nstruct ion i n the instruc t i on stream. If a trace exception is pend ing, however, the MG68020 w i l l not termi nate com m u n i cation with the coprocessor u n t i l the coprocessor i n d icates that it has com pleted a l l processing associated with the cpGEN i nstruction (see 8.8.2.5 TRACE EXCEp TIO NS).

8-9

The coprocessor i nterface protocol i l l ustrated in F i g u re 8-7 al lows the operat ion of a g iven general category i nstruction to be def i ned by the coprocessor. That is, the main processor s i mply i n i t iates the i nstruction by writing the i nstruction command word to the command C I R and then reads the response C I R to determ i ne its next action. The execu t ion of the coprocessor i nstruction is then defi ned by the i nternal operat ion of the coprocessor and its use of response pri mit ives to request services from the main proc essor. This i nstruction protocol al lows a wide range of operat ions to be impl emented i n t h e general i nstruct ion category. 8.3.2 Conditional Coprocessor Instructions The cond itional i nstruction category al lows program contro l , based on the operat ions of the coprocessor, to be i m p lemented in a u n i form manner. The execution of i nstructions i n this category i s i n herently d ivided between the main processor and the coprocessor. The coprocessor is responsible for eva l uating a condition and retu r n i n g a true/fa lse i nd io cator to the main processor. The completion of the i n struction execution is then hand led by the main processor based on this true/false cond ition i nd i cator. The i m p lementation of i nstructions in the cond itional category promotes eff ic ient u t i l iza t ion of the hardware provided by design in the main processor and the coprocessor. The cond ition on w h i c h the i n struction execution is based is related to the coprocessor operat ion and is therefore eva luated by the coprocessor. The i nstruct ion completion follow i n g the cond ition eval uation is, however, d i rect ly related to the operat ion of the main processor. The port i on of the i nstruction i nvolving change of flow, sett i n g a data alterable byte, or TRAP operat ions is executed by the main processor s i nce its architec t u re i n herently i m p lements these operat ions to su pport its i nstruct ion set. The protocol u sed to execute a conditional category coprocessor i n struction is i l l u s t rated in F i g u re 8-8. The main processor i n i t iates an i nstruct ion in t h i s category by writing a cond ition selector to the cond it ion C I R . The cond it ion selector is decoded by the coprocessor to determ i ne w hat cond ition it should eva luate. The coprocessor can use response primit ives to request that the main processor provide services req u i red for the cond ition evaluation. Upon completion of the cond ition evaluation, the coprocessor returns a true/fa lse i n d i cator to the main processor th rough the response C I R u s i n g the N u l l primit ive (see 8.6.2 Null (No Operands . The main processor completes the coprocessor i nstruct ion execution when it receives the cond ition i n d icator from the coprocessor. 8.3.2.1 B RANCH ON COP ROCESSO R CON DITION IN STRUCTIONS. There are two for mats of the M68000 Fam ily branch i nstruction provided in the cond it ional i nstruct ion category. These i nstructions al low the control of flow of i n struction execution to be based on cond i t ions related to the coprocessor operat ion. The execution of these i n struct ions is based on the condit ional branch i n structions provided in the M68000 Fam ily i nstru ction set. 8.3.2.1 .1 Format. The two formats of the branch on coprocessor cond ition i n structions are i l l ustrated in F i g u res 8-9 and 8-1 0.

81 0

Main Processor M1 Recognize Coprocessor Instruction F-Line Operation Word M2 Write Coprocessor Condition Selector to Condition _ C1 CIR M3 Read Coprocessor Response Primitive Code from Response CI R 11 Perform Service Requested by Response Primitive 21 If (Coprocessor Response Primitive Indicates "Come Again"l go to M3 Isee Note 1 )
-

Coprocessor

M4 Complete Execution of Instruction Based on the True/False Condition Indicator Returned in the Response CI R NOTES 1. All coprocessor response primitives, except the Null primitive, that allow the "Come Again" primitive attribute must indicate "Come Again" when used during the execution of a conditional category instruction. If a "Come Again" attribute is not indicated in one of these primitives, the main processor wil initiate protocol violation exception processing Isee 8.8.2. 1 PROTOCOL
VIOLATIONSI.

Decode Condition Selector and Initiate Condition Evaluation C2 While (Main Processor Service is Requiredl do Steps 11 and 21 Below 1 1 Request Servi c e by Placing Appropri a te Response Primitive Code in Response CIR 21 Receive Service from Main Processor C3 Complete Condition Evaluation C4 Reflect "No Come Again" Status with True/False Condition Indicator in Response CIR

Figure 88. Coprocessor Interface Protocol for Conditional Category Instructions

15 1

14 1 3 12 1 1 1 0 9 8 7 6 5 4 3 2 Condition Selector Cp-ID I 0 I 1 I 0 I I 1 I 1 I 1 I Optional Coprocessor Defined Extension Words Displacement

Figure 89. Branch On Coprocessor Condition Instruction (cpBcc.W)

15
1

6 4 3 2 5 13 12 11 10 9 8 0 I 1 I 1 I Condition Selector Cp-ID 1 I 1 I 1 I I I Optional Coprocessor Defined Extension Words Displacement - High Displacement - Low
14

Figure 81 0. Branch On Coprocessor Condition Instruction (cpBcc.L)

81 1

The fi rst word of the branch on coprocessor cond ition i nstruction is the F- l i ne operat ion word. As with all coprocessor i nst ruct ions, bits [1 5-1 2) = 1 1 1 1 and bits [1 1 -9) conta i n the identificat ion code of the coprocessor that w i l l evaluate the cond ition. Bits [8-6) are used to d istingu ish between the word and long word d i splacement formats of the i n struction, which are denoted by the cpBcc.W and cpBcc. L m nemon ics respect ively. Bits [5-0) of the F- l i ne operation word contain the coprocessor cond ition selector field. The MC68020 writes the ent i re operat ion word to the condition CIR to i n i t iate the branch i nstruction. The coprocessor should then use bits [5-0) to determine the cond ition which it should evau late. If the coprocessor req u i res add itional i nformat ion to eva l uate the cond it ion, this i n forma tion can be i n c l uded in the branch i nstruction format u s i n g coprocessor defi ned exten sion words. These extension words fol low the F-l i ne operation word and the nu mber re q u i red for a g iven coprocessor i nstruction is determi ned by the coprocessor des i g n . The final word(s) of the cpBcc i nstruction format contains the disp lacement used by the main processor to calcu late the dest i nation address when the branch is taken. 8.3.2. 1 .2 Protocol. The protocol used to i m plement the cpBcc. L and cpBcc.W i nst ruc tions i s depicted in F i g u re 8-8. The main processor transfers the cond ition selector to the coprocessor by writing the F-l i ne operat ion word to the condit ion C I R to i n i t iate the i n struction. The main processor then reads the response C I R to determ i ne its next act ion . The coprocessor can use the res ponse prim itive set to request services necessary to eval uate the cond ition. I f the coprocessor ret urns the false condition i nd i cator, the main processor proceeds with the execut ion of the next i n struction i n the i nstruction stream. If the coprocessor returns the true condition i nd i cator, the d i s placement is added to the M C68020 scan PC (see 8.5.2 ScanPC) to determ i ne the dest ination address at which the main processor cont i n ues i nstruction execution. The scanPC must be po i nt i n g to the locat ion of the fi rst word of the disp lacement in the i nstruction stream when the dest i na t ion address is calcu lated. The disp lacement is a two's complement i nteger that can be either a 1 6-bit word or a 32-bit long word. The 1 6-bit d i splacement i s s i g n extended to a long word va lue before the dest i nation address is calcu lated. 8.3.2.2 SET ON COP ROCESSOR CONDITION. The set on coprocessor cond ition instruc tions are u sed to set or reset a flag (a data alterable byte) based on a cond it ion eva luated by the coprocessor. The operat ion of t h i s i nstruct ion is patterned after the operat ion of the Scc i nstruction i n the M68000 Fam i l y i nstruction set. W h i l e the Scc i nstruction does not i n herently cause a change of program flow, it is often used to set flags u pon which prog ram flow i s based. 8.3.2.2.1 Format. The format for the set on coprocessor cond ition i nstruction, denoted by the cpScc mnemonic, is i l l ustrated in F i g u re 8-1 1 .
15
1

14 1

13 1

12 1

3 Effective Address Condition Selector Optional Coprocessor Defined Extension Words Optional Effective Address Extension Words (05 Words)

11

10 CpID

8 0

7 0

6 1

I I

Figure 81 1 . Set On Coprocessor Condition (cpScc)

8- 1 2

The f i rst word of the cpScc i nstruction is the F-l i ne operation word . Th is word contains the Cp- I D field i n bits [1 1 -9] and bits [8-6] = 001 to identify the cpScc instruction. The lower six bits of the F-l i ne operat ion word are u sed to encode an M68000 Fam ily effective address mode (see 2.8 EFFECTIVE ADDRESS). The second word of the cpScc i nstruction format contains the coprocessor condit ion selector in bits [5-0]. Sits [1 5-6] of this word are reserved and should be zero to i ns u re com pat i b i l ity with future M68000 prod ucts. This word is w ritten to the condition C I R to i n itiate the cpScc i n struction. I f the coprocessor req u i res add i t ional i nformation to eva l u ate the condition, this i nforma t ion can be incl uded in the cpScc i nstruction format u s i n g coprocessor defi ned exten sion words. These extension words fol low the word cont a i n i n g the coprocessor cond ition selector field, and the n u m ber of extension words req u i red for a g iven coprocessor i n struct ion is determ i ned by the coprocessor des i g n . T h e fi nal port i on o f the cpScc i nstruction format conta i n s zero to five effective address extension words. If the main processor req u i res add itional i nformation for the calcu la tion of the effect ive address specif ied by bits [5-0] of the F- l i ne operat ion word, t h i s i nfor mation is incl uded i n the effect ive add ress extension words. 8_3.2.2.2 Protocol. The protocol u sed to i m plement the cpScc i nstruction i s depicted in F i g u re 8-8. The MC68020 transfers the condition sel ector to the coprocessor by writing the word following the operat ion word to the cond ition CIR. The main processor then reads the res ponse C I R to determine' its next act ion. The coprocessor can use the response primit ive set to request services necessary to eva l uate the con d i t ion. The operation of the cpScc i nstruction depends on the cond ition evaluation ind icator ret u rn ed to the main processor by the coprocessor. I f the coprocessor ret urns the false condi t ion i nd i cator, the main processor eva l u ates the effective address spec i f ied by bits [5-0] of the F-l i ne operation word and sets the byte at that effective address to FALSE (al l bits to zero). I f the coprocessor ret u rns the true cond ition i nd i cator, the main processor sets the byte specif ied by the effective address to TRUE (al l bits set to one). 8.3.2_3 TEST COP ROCESSOR CON DITION, DECREM ENT AND BRANCH. The operation of the test coprocessor cond ition, decrement and bra nch i nstruction i s patterned after the DScc i nstructions provided in the M68000 Fam ily i nstruction set. This operation is based on a coprocessor eva l u ated condition and a loop counter provided in the main processor and i s usef u l i n i m plemen t i n g the DO-UNTIL type constructs used i n many h i g h leve l languages. 8.3.2.3.1 Format. The format of the test coprocessor cond it ion, decrement and branch i n struction, denoted by the cpDScc mnemonic, is i l l ustrated in Fig ure 8-1 2.
15 1
14

13

12 1

10 9 8 7 6 5 4 3 2 0 Register 0 I 0 I 1 I 0 I 0 I 1 I Cp-ID I I Condition Selector ( Reservedl Optional Coprocessor Defined Extension Words Displacement

11

Figure 8-1 2. Test Coprocessor Condition, Decrement and Branch Instruction Format (cpDBcc) 8- 1 3

The f i rst word of the cpOBcc i n st ruction is the F l i ne operat ion word. Bits [20] of this operat ion word denote the main processor data reg ister that will be used as the loop cou nter d u r i n g i nstruction execution. The second word of the cpOBcc i nstruction format contains the coprocessor cond ition selector i n bits [50] and should conta i n zeroes i n bits [1 56] to maintain compat i b i l ity with fut ure M68000 prod ucts. This word i s written to the condition C I R to i n i t iate the cpOBcc i nstruct ion. I f the coprocessor req u i res add itional i nformation to eva l uate the cond i t ion, this i n forma tion can be i n c l uded in the cpOBcc i nstruct ion format u s i n g coprocessor defi ned exten sion words. These extension words fo l low the word conta i n i ng the coprocessor cond ition selector field i n the cpOBcc i nstruct ion format. The displacement for the cpOBcc i nstruction is contai ned in the last word of the i nstruc t ion format. This disp lacement is a two's comp lement 1 6bit value that is s i g n extended to long word s ize when it is u sed for a desti nat ion address calculation. 8.3.2.3.2 Protocol. The protocol used to i m plement the cpOBcc i nstruct ions is depicted i n F i g u re 88. The M C68020 transfers the cond ition selector to the coprocessor by writing the word following the operat ion word to the cond ition CIR. The main processor then reads the response CIR to determ i ne its next action. The coprocessor can use the response primit ive set to req uest any services necessary to eval uate the cond ition. If the coprocessor ret urns the true cond ition i ndicator, the main processor proceeds with the execution of the next i nstruction in the i nstruction stream. I f the coprocessor retu rns the false condition i ndicator, the main processor decrements the loworder word of the reg i ster specif ied by bits [20] of the Fl i ne operation word. If this reg i ster is equal to m i n u s one ( - 1 ) after bei n g decremented, the main processor proceeds with the execu t ion of the next i nstruction in the i n struction stream. If the reg i ster is not eq ual to m i n u s o n e ( - 1 ) after be i n g decremented, the m a i n processor branches to the dest ination ad dress to cont i n ue i nstruction execution. The desti nat ion address calcu lation is identical to that used for the cpBcc.W i nstruct ion. That is, the d i splacement i s added to the M C68020 scanPC (see 8.5.2 ScanPC) to deter mine the dest i n ation address at which the main processor conti nu es i nstruct ion execu t ion. The scan PC must be pOinting to the location of the 1 6bit d isp lacement in the i nstruct ion stream when the dest i nation add ress is calcu lated.

8.3.2.4 TRAP ON COP ROCESSOR CON DITION. The operat ion of the trap on coprocessor condition i n struct ion al lows the prog rammer to i n it iate exception process i n g based on cond itions related to the coprocessor operation. 8.3.2.4.1 Format. The format for the t rap on coprocessor cond it ion i nstruction, denoted by the cpTRAPcc mnemonic, is i l l u strated in F i g u re 81 3.

8 1 4

15 1

14 1

13 1

12

6 7 5 4 3 8 o 10 9 Cp I D I 0 I 0 I 1 I 1 I 1 I 1 I Opmode Condition Selector (Reservedl Optional Coprocessor Defined Extension Words Optional Word or Long Word Operand 11

Figure 81 3. Trap On Coprocessor Condition (cpTRAPcc) Bits [2-0] of the cpTRAPcc F-l i ne operat ion word specify the number of optional operand words i nc l uded in the i n struction format. The i nst ruct ion format can i ncl ude zero, one, or two operand words. The second word of the cpTRAPcc i nst ruct ion format contains the coprocessor condi t i on selector i n bits [5-0] and should conta i n zeroes i n bits [1 5-6] to maintain compat i b i l ity with future M68000 prod ucts. This word is written to the condition C I R to i n itiate the cpTRAPcc instruct ion. If the coprocessor req u i res add itional i nformat ion to evaluate a condition, t h i s informa tion can be i n c l uded in coprocessor defi ned extension words. These extension words follow the word conta i n i n g the coprocessor cond ition selector field in the cpTRAPcc i n struction format. The number of operand words i n d i cated by bits [2-0] of the cpTRAPcc F-l i ne operat ion word fol low the coprocessor defi ned extension words. These operand words are not ex plic i t ly used by the M C68020, but can be u sed to encode i nformat ion referenced by the cpTRAPcc exception han d l i n g rout i nes. The legal encod i n gs for bits [2-0] are provided i n Table 8-1 . Other encod i ngs of these bits map t o the encod ings o f the cpScc i nst ruct ion or if u ndef i ned, cause an F-l i ne emu lator except ion (see APPENDIX B I NSTRUCTION SEn. Table 81 . cpTRAPcc Opmode Encodings
Opmode 010 01 1 100
Optional Words in

I nstruction Format One

Two

Zero

8.3.2.4.2 Protocol. The protocol u sed to i m plement the cpTRAPcc i nst ruct ions is depi cted i n F i g u re 8-8. The MC68020 transfers the cond ition sel ector to the coprocessor by wri t i n g the word fo l low i n g the operation word to the condition C I A. The main proc essor then reads the response C I R to determ ine its next action. The coprocessor can use the response pri m i t ive set to req uest any services necessary to eval u ate the cond i t ion. I f t h e coprocessor ret urns t h e true cond ition indi cator, the m a i n processor i n it i ates excep t ion processing for the cpTRAPcc except ion (see 8.8.2.4 cpTRAPcc IN ST RUCTION TRAPS). If the coprocessor returns the false cond ition i ndicator, the main processor pro ceeds w i t h the exception of the next instruction in the i nst ruct ion stream.

8-1 5

8.3.3 Coprocessor Context Save and Context Restore The coprocessor context save and context restore i nstruction categories are i n c l uded i n the M68000 coprocessor i nterface i n order t o su pport m u l t itasking program m i ng en vironments. In a mult itasking environ ment, the context of a coprocessor may need to be changed i n an asynchronous manner with respect to the operation of that coprocessor. That is, the coprocessor may be i n terru pted at any po i n t in the execution of an instruc t ion i n the general or cond itional category in order to commence context change operat ions. In contrast to the general and cond i t i on i nstruction categories, the context save and con text restore i nstruct ion categories do not use the coprocessor response primit ives d u r i n g the i nstruct ion execution. A set of format codes is def i ned for the M68000 coprocessor i nterface to al low the coprocessor to com m u n i cate status i nformation to the main processor d u r i n g the execution of i nst ruct ions i n the context save and context restore categories. These coprocessor format codes are d i scu ssed in detail in 8.3.3.4 COPROCESSOR FOR MAT WO R DS. 8.3.3.1 COP ROCESSO R CONTEXT SAVE. There is one i nstruction defi ned for the M68000 coprocessor context save i nstruction category. The coprocessor context save i nstruc t i on, denoted by the cpSAV E mnemo n i c, al lows the context of a coprocessor to be saved in an asynchronous manner with respect to the exec ution of coprocessor i nstructions i n the general o r cond i t ional i n struction categori es. During the execution of a cpSAV E i n struction, the coprocessor can com m u n icate status i nformation to the main processor by using the coprocessor format codes. 8.3.3.1 .1 Format. The format of the cpSAV E i nstruction is i l l ustrated in Figure 8- 1 4.
15 14 13 12 11 10 Cp I O 9 8 6 5 4 3 2 Effective Address
o

Figure 8-1 4. Coprocessor Context Save Instruction Format (cpSAVE) The first word of the i nstruction is the F-l i ne operat ion code which contains the coprocessor identif ication spec i fier in bits [1 1 -9] and an M68000 effective address spec i fier in bits [5-0]. The effective address encoded in the cpSAVE i nstruction is used to determ i n e w here the state frame assoc iated with the cu rrent context of the coprocessor w i l l be saved in memory. The control alterable and pre-decrement addressing modes are legal w i t h the cpSAV E i n struction. Other address i n g modes encoded w i t h i n t h i s i nstruction w i l l cause the MC68020 to i n i t i ate F-l i ne emulator except .ion processing as descri bed in 8.8.2.2 F- L i N E E M U LATOR EXC EPTIO NS. There can be up to five effective address extension words following the cpSAV E i nstruc tion operation word. If the main processor req u i res add i t ional i nformation for the calcula tion of the effective add ress specif ied by bits [5-0] of the operat ion word, t h i s i n format ion i s i ncl uded in the effective address extension words.

8- 1 6

8.3.3. 1 .2 Protocol. The protocol for the coprocessor context save i nstruct ion i s i l l ustrated i n Figure 81 5. The m a i n processor i n itiates t h e cpSAV E i n struction by read i n g t h e save C I R. Thus, t h e cpSAV E i nstruction i s t h e o n l y coprocessor instruction that i s i n i t i ated by read i n g from (as opposed to writing to) a reg i ster i n the coprocessor i nterface reg i ster set. The coprocessor com m u n i cates status i nformation assoc iated with the con text save operat ion to the main processor by placing coprocessor format codes in the save C I A .
Main Processor M1 M2 M3 Recognize Coprocessor Instruction F-Line Operation Word Read Save CIR to I nitiate the cpSA V E Instruction If I Format = Not Readyl do Steps 1) and 21 Below 1 I Service Pending Interrupts 21 Go to M2
..

Coprocessor

C1

If I Not Ready to Begin Context Save Operationl do S teps 1 1 and 21 Below 11 Place Not Ready Format Code in Save CI R 21 Suspend or Complete Current Operations Place Appropriate Format Word in Save CI R Transfer Number of Bytes Indicated in Format Word Through Operand CI R

M3

Evaluate Effective Address Specified in F-Line Opword and Store Format Word at Effective Address If I Format = Emptyl go to M5 Else, Transfer Number of Bytes Indicated in Format Word From Operand CI R to Effective Address Proceed with Execution of Next Instruction

C2

Figure 81 5. Coprocessor Context Save Instruction Protocol If the coprocessor is not ready to i m med iately suspend its cu rrent operat ion when the main processor reads the save C I R, the coprocessor may ret urn a format code i nd i cat i n g " N ot Ready" t o t h e main processor, The main processor w i l l t h e n service a n y pen d i n g i n terrupts and ret urn to read the save C I R and thus re i n i t iate the cpSAV E i nstruction. After plac i n g the not ready format code in the save C I R, the coprocessor should proceed to either suspend or complete the operat ions assoc iated with the i nstruct ion it is cu rrently executing. Once the coprocessor has suspended or comp leted all operat ions associated with the i nstruction it i s execut ing, it w i l l place a format code i n the save C I R representing the i n ternal coprocessor state. When the main processor reads the save C I R, it transfers the format word to the effective address encoded in the cpSAV E i nstruction. The lower byte of the coprocessor format word specif ies the number of bytes of state i nformat ion, not i nc l u d i n g the format word, which w i l l be tran sferred from the coprocessor to the effective address spec if ied. If the state i nformation is not a m u lt i ple of four bytes in size, the M C68020 w i l l i n i t iate format error exception process ing (see 8.8.1 .5 FOR MAT ERRORS). The coprocessor and main processor coord i nate the transfer of the i nternal state of the coprocessor through the use of the operand CIR. The M C68020 completes the coprocessor context save by repeated ly read i n g the operand CIR and writing the i n forma tion obta i ned into memory u n t i l the nu mber of bytes specif ied in the coprocessor format word have been tran sferred. Following a cpSAV E i nstruct ion, the coprocessor should be in an idle state, that is, not executing any coprocessor i nstruct ions.

8-1 7

The cpSAV E i nstruction is a privi leged i nst ruct ion. Thus, when the main processor en cou nters the cpSAV E i nstruction, it checks the supervisor bit in the stat us reg ister to determine if it is operat i n g in the supervisor state. If the MC68020 attempts to exec ute a cpSAV E i nstruct ion whi le i n the user state (bit [1 3] = 0 in status reg ister), it w i l l i n itiate privi lege violation exception processing w i thout accessing any of the coprocessor i nter face reg i sters (see 8_8_2.3 PRIVI LEGE VIOLATIONS). The MC68020 w i l l i n itiate format error exception process ing if it reads an i nval i d format word of a val i d format word whose length field is not a m u lt i p le of four bytes f rom the save C I R d u ri n g the execution of a cpSAV E i nstruction (see 8.3.3.4.3. Invalid Format Words). The M C68020 w i l l write a $0001 to the control C I R to abort the coprocessor i n struction i n this situation prior to except ion processing. Th i s case is not i nc l uded i n F i g u re 8-1 5 s i nce a coprocessor should generally only ret u rn a not ready o r a va l i d format code in the context of the cpSAVE i nst ruct ion. The coprocessor may ret urn the i nva l i d format word, however, if a cpSAVE i s i n i t i ated w h i l e t h e coprocessor is executing a cpSAV E or cpRESTO R E i nstruction and the coprocessor is not able to su pport the suspension of these two i n structions.

8.3_3.2 COP ROCESSOR CONTEXT RESTO RE. There i s one i nst ruct ion def i ned for the M68000 coprocessor context restore i nstruction category. The coprocessor context restore i nstruction, denoted by the cpRESTO RE m nemoniC, provides a mechanism by which a coprocessor can be forced to term i n ate any cu rrent operat ions and restore a state assoc iated with a d i fferent context of execution. During the execution of a cpRESTOR E instruction, the coprocessor can com mun icate status i nformat ion to the main processor by plac i n g format codes in the restore CIR. 8.3.3.2.1 Format. The format of the cpRESTOR E i nst ruct ion i s i l l ustrated i n F i g u re 8-1 6.
15 14 13 12 11 10 9 8 6 5 4 3
2 o

Effective Address

Figure 8-1 6. Coprocessor Context Restore Instruction Format (cpRESTO RE) The f i rst word of the i nstruction is the F-l ine operat ion code which contains the coprocessor identif ication spec ifier in bits [1 1 -9] and an M68000 effective add ress spec ifier in bits [5-0]. The effective address encoded in the cpRESTORE i nst ruct ion i s used t o determ i ne where i n memory t h e coprocessor context i s stored. The effect ive address pOints to the coprocessor format word conta i n i n g i n formation related to the con text that w i l l be restored to the coprocessor. There can be up to five effective address extension words fol low ing the f i rst word in the cpRESTORE i n struction format. If the main processor req u i res add itional i nformat ion for the ca lcu lat ion of the effective address spec i f ied by bits [5-0] of the operat ion word, this i nformat ion i s i n c l uded i n the effective address extension words.

8-1 8

A l l memory addres s i n g modes except the pre-decrement address ing mode are legal. I l legal effective address encod i ng s cause the M C68020 to i n i t iate F-l i ne emu lator excep tion processing (see 8_8_2_2 F-L i N E EMU LATOR EXCEPTIONS). 8.3.3.2.2 Protocol. The protocol for the coprocessor context restore i nstruction i s i l l u strated i n F i g u re 8-1 7. W h e n t h e main processor encou nters a cpRESTO RE i nstruction it f i rst reads a coprocessor format word from the effective address spec ified in the i n struct ion. This format word conta i n s a format code and length field. The main processor reta i n s a copy of the length field to determ ine the n u m ber of bytes which w i l l be trans ferred to the coprocessor d u r i n g the cpRESTO R E operat ion and writes the format word to the restore C I R to i n it iate the coprocessor context restore.
Main Processor M1 M2 M3 Recognize Coprocessor Instruction F-line Operation Word Read Coprocessor Format Code from Effective Address Specified in Operation Word Write Coprocessor Format Word to Restore CI R Coprocessor

---!. l
.... .. I-- --I

M4 M5

Read Restore CIR If ( Forma t = Invalid Formatl Write $000 1 Abort Code to Control CIR and I nitiate Format Error Exception Processing (see Note 1 )

Terminate Current Operations and Evaluate Format Word If ( I nvalid Formatl Place Invalid Format Code in the Restore CIR

M6

If ( Forma t = Empty/Resetl go to M.? Else, Transfer Number of Bytes Specified by Format Word to Operand CI R (see Note 21 Proceed with Execution of Next Instruction

If ( V alid Format! Receive Number of Bytes Indicated in Format Word Through Operand CIR

M7

NOTES: 1 See S.S. 1 .5 2. The MC68020 uses the length field in the format word read during M2 to determine the number of bytes to read from memory and write to the operand CI R.

FORMAT ERROR.

Figure 8-1 7. Coprocessor Context Restore Instruction Protocol When the coprocessor receives the format word i n the restore C I R it mu st termi nate any cu rrent operat ions and eval u ate the format word. If the format word represents a val i d coprocessor context as determ i ned by the coprocessor des ign, the coprocessor w i l l ret urn the format word t o the m a i n processor th rou gh the restore C I R and prepare to receive the n u m ber of bytes specif ied in the format word through its operand C I R . The main processor follows i t s w rite o f t h e format word t o t h e restore C I R b y read i n g that same reg i ster, I f the coprocessor ret urns a val i d format word, the main processor w i l l proceed t o transfer the n u m ber o f bytes spec ified (by the format word read from the cp RESTORE effective address previous ly) t h rough the operand CIR.

8- 1 9

If the format word w ritten to the restore C I R does not represent a val i d coprocessor state frame, the coprocessor w i l l place an i nval i d format word in the restore C I R and term i n ate any cu rrent operat ions. Upon rece i pt of the inva l i d format code, the main processor acknowledges the format error by writing a $0001 to the control C I R and i n i t iating format error except ion processing (see 8.8.1 .5 FORMAT ERROR). The cpRESTO R E i nstruction i s a privi leged i nstruct ion. Thus, when the main processor encounters a cpR ESTO R E i nstruction, it checks the su pervisor bit in the status register to determ ine if it is operat i n g in the supervisor state. If the MC68020 attempts to exec ute a cpRESTORE i nstruct i o n w h i l e in the user state (bit[1 3] = 0 in status reg i ster), it w i l l i n itiate privi lege violat ion exception process i n g without accessing any of the coprocessor interface reg i sters (see 8.8.2.3 PRIVILEGE VIOLATIONS). 8.3.3.3 COP ROCESSOR I NTERNAL STATE FRAM ES. The cpSAVE and cpRESTORE i n structions t ransfer an i nternal coprocessor state frame between memory and a coprocessor. This i nternal coprocessor state frame represents the state of coprocessor operat ions. U s i n g the cpSAV E and cpRESTORE i nstruct ions it is poss i ble to i nterru pt coprocessor operat ion, save the context assoc iated with the current operation, and i n itiate coprocessor operat ions in a new context. A coprocessor's i nternal state frame i s stored as a sequence of long word entries i n memory a s a resu l t o f a cpSAV E i nstruction execution. The format o f a coprocessor state frame stored in memory is i l l u st rated in F i g u re 8-1 8.
Save Order o n n1 n2 Restore Order 31 0 2 3

Format

23

7 15 Length ( U nused, Reservedl Coprocessor Dependent Information

Figure 818. Coprocessor State Frame Format in Memory During the cpSAVE i nstruct ion, the effective address contai ned i n the operat ion word is calcu lated and the format word i s stored at this effective address. The long words that form the coprocessor state frame are then written to descending memory add resses beg i n n i ng with the address spec ified by the sum of the effective address and the format word length field x4. D u r i n g the cpRESTO R E i nstruction, the format word and long words that are contai ned in the state frame are read from ascending addresses beg i n n i ng with the effective add ress specif ied i n the i nstruction operat ion word. The coprocessor format word is stored at the lowest address of the state frame in memory and is the first word transferred for both the cpSAVE and the cpRESTO RE i n struc tions, The word follow i n g the format word does not conta i n i nformation relevant to the coprocessor state frame, but serves to keep the i nformat ion in the state frame a m u lt i p le

8-20

of four bytes i n size. The number of entries following the format word (at h i gher addresses) is determ i ned by the format word length for a g iven coprocessor state. The i nformat ion contai ned in a coprocessor state frame describes a context of operat ion for that coprocessor. This desc ription of a coprocessor context incl udes the program i n visible state i nformat ion and, optional ly, the program visible state i nformat ion. The pro gram i nvisible state i nformation is any i nternal reg i sters or status i n formation which cannot be accessed by the prog rammer, but i s st i l l necessary for the coprocessor to con t i n u e its operat ion at the point of suspension. Program visible state i nformat ion i ncl udes the contents of all reg i sters which appear in the coprocessor program m i n g model and which can be d i rect ly accessed u s i n g the coprocessor i nstruct ion set. The i nformation saved by the cpSAVE inst ruct ion must i ncl ude the program invisible state i nformat ion. I f cpGEN i nstructions are provided to save t h e program visible state o f the coprocessor, the cpSAVE and cp RESTO R E i nstructions should only transfer the program i nvisible state i nformation to m i n i m ize i nterru pt latency d u r i n g a save or restore operat ion. 8.3.3.4 COP ROCESSOR FO RMAT WO RDS. The coprocessor com m u n icates stat us i n for mation to the main processor during the cpSAVE and cpRESTOR E i nstructions by u t i l iz i n g coprocessor format words. The format words def ined for the M68000 coprocessor i nterface are l i sted in Table 82. Table 82. Coprocessor Format Word Encodings

Format Code
00 01 02 03-0F 10-FF

Length
xx xx xx xx

Length

Empty/Reset Not Ready. Come Again Invalid Format Undefined, Reserved Valid Format. Coprocessor Defined

Meaning

The upper byte of the coprocessor format word contains the code used to commun icate coprocessor statu s i nformat ion to t he main processor. The MC68020 recogn izes four types of format words: empty/reset, not ready, invalid format, and va lid format. The MC68020 i nterprets the reserved format codes ($03$OF) as i nval i d format words, The l ower byte of the coprocessor format word is u sed to spec ify the size in bytes (which must be a m u lt i p le of fou r) of the coprocessor state frame i n conj u nction with the val i d format code (see 8.3.3.4.4 Valid Format Words). 8.3.3.4.1 Empty/Reset Format Word. The empty/reset format code is returned by the coprocessor d u r i n g a cpSAV E i nstruct ion to ind icate that the coprocessor contains no user loaded i nformation. That is, no coprocessor i nstruct ions have been executed si nce either the previous cpRESTORE with the em pty/reset format code or the previous hard ware reset. If the main processor reads the empty/reset format word from the save C I R d u r i n g t h e i n itiation o f a cpSAV E i nstru ct ion, it w i l l si mply store t h e format word at t h e ef fective address specif ied i n the cpSAV E i nstruct ion, and proceed with the execution of the next i nstru ction. I f the main processor reads the em pty/reset format word from memory during the execu tion of the cpRESTO RE i n struction, it w i l l write the format word to the restore C I R . The main processor w i l l then read the restore C I R and if the empty/reset format word is

821

ret urned by the coprocessor, the main processor w i l l then cont inue with the execution of the next instruct ion. The main processor can i n itial ize the coprocessor by writing the empty/reset format code to the restore C I R. When the coprocessor receives the emp ty/reset format code, it w i l l term i nate any cu rrent operat ions and wait for the main pro cessor to i n itiate the next coprocessor i nstruction. I n particular, the cpRESTORE of the empty/reset format word should cause the coprocessor to ret urn this same format word if a cpSAVE i nstruct ion is executed before any other coprocessor i nstruct ions. Thus, an em pty/reset state frame consists only of the format word and the following reserved word i n memory (see F i g u re 8-1 8). 8.3.3.4.2 Not Ready Format Word. When the main processor i n i tiates a cpSAV E i n struc t ion by read i n g the save C I R, the coprocessor may ret urn a not ready format word. The main processor w i l l then service any pend i n g i nterrupts and return to re-read the save C I R. The not ready format word a l l ows the coprocessor to delay the save operat ion u n t i l it i s ready t o save i t s i nternal state. The cpSAV E i nstruct ion may cause the su spension of a coprocessor i nstruction in the general or cond itional category with the capabi l i ty of res u m i n g the suspended i nstruct ion at a later t i me. If no further main processor services are req u i red to complete coprocessor i nstruct ion execution, it may be more eff icient to complete the i nstruction and thus red uce the size of the saved state. The coprocessor deSigner should con sider the efficiency of i n struction completion versus i nstruct ion suspension and res u m ption when a cpSAV E i nstruct ion is i n itiated by the main pro cessor . When the main processor i n itiates a cpRESTORE i nstruction by writing a format word to the restore C I R, the coprocessor should genera l ly term inate any cu rrent operations and restore the state frame suppl ied by the main processor. Thus, the not ready format word shou ld generally not be retu rned by the coprocessor during the execut ion of a cpRESTORE i n st ruct ion. If the coprocessor must delay the cpRESTO RE operat ion for any reason, it can return the not ready format word when the main processor reads the restore C I A . If the m a i n processor does read the not ready format word from the restore C I R d u r i n g the cpRESTO RE i nstruction, it w i l l re-read the restore C I R without servicing any pend i n g i nterru pts. 8.3.3.4.3 I nvalid Format Words. A coprocessor may place the i nval i d format word in the restore C I R i n response to the main processor's i n itiation of the cpRESTORE i nstruct ion. This i nval i d format i nd icates that the format word written to the restore CIR does not describe a val id coprocessor state frame. If the main processor reads this format word d u r i n g the cpRESTOR E i nstruction, it w i l l write the abort mask ($0001 ) to the control CI R and i n itiate format error except ion process i ng. A coprocessor should genera l l y not place an i nval i d format word i n the save CIR when the main processor i n itiates a cpSAVE i nstruction. A coprocessor, however, may not be able to su pport the i n itiation of a cpSAV E i n struction w h i l e it is executing a previously i n it iated cpSAV E or cpRESTO RE i nstruction. I n t h i s Situation, the coprocessor can return the i nval i d format word when the main processor reads the save C I R to i n i t iate the cpSAVE i nstruction w h i le either another cpSAVE or cpRESTO RE i nstruct ion i s ex ecut i ng. If the main processor reads an inva l i d format word from the save C I R it w i l l write the abort mask to the control C I R and i n i tiate format error exception process i n g (see 8.8.1.5 Format Error).

8-22

8.3.3.4.4 Valid Format Words. Valid format words are the only type of format words i n w h i c h t h e length field, contai ned i n t h e lower eight bits, is re leva nt. When t h e m a i n pro cessor reads a val id format word from the save C I R duri ng the cpSAVE i nstruct ion, it w i l l use t h e length field t o determ i n e the size o f t h e coprocessor state frame t o save. D u r i n g the c pRESTORE i nstruct ion, t h e main processor uses t h e l e n g t h f i e l d i n the va l i d format word read from the effect ive add ress spec ified in the i nstruction to determ i ne the size of the coprocessor state frame that w i l l be restored. The length field of a va l id format word must be a m u l t i ple of four bytes in size. If the main processor detects a val id format length field that i s not a m u l t i ple of fou r bytes i n size d u ri n g the exec u t i on of a cpSAVE or cpRESTO RE i n struction, the main processor w i l l write t h e abort mask ($0001 ) t o t h e control C I R a n d i n i t iate format error exception pro cessing. 8.4 COP ROC ESSOR I NTERFACE R EG ISTER (CI R) SET The M68000 coprocessor i n terface is i m plemented using a protocol based on the coprocessor i nterface reg i ster set. During the exec ut ion of a coprocessor instruct ion, the M C68020 accesses the reg i sters defi ned in the CIR set to com m u n i cate with the coprocessor. It should be noted that the i nterface reg i ster set is not d i rectly re lated to the reg i ster set that appears i n the coprocessor's progra m m i n g model. A memory map of the coprocessor i nterface reg i ster set i s i l l ustrated in F i g u re 8-3. The reg isters denoted by an asterisk ( ) must be i n c l uded i n a coprocessor i nterface i n order to al low coprocessor i nstruct ions in a l l fou r categories to be i m plemented. The com plete reg i ster model must be i m p l emented if the system is to u t i l ize a l l of the coprocessor response primit ives defi ned for the M68000 coprocessor i nterface. A detai led description of each reg ister i n the CIR set is g iven i n the fol low i n g parag raphs. The hex idecimal va l ue i n parenthes i s fol low i n g each reg ister name in the follow i n g parag raph tit les is the reg ister offset from the base address of the CIR set.
*

8.4.1 Response C I R ($00) The response C I R is a 1 6-bit reg ister t h rough which the coprocessor com m u n i cates a l l service requests to t h e m a i n processor u s i n g t h e coprocessor response primit ives. The main processor reads the response C I R to receive the coprocessor response primit ives d u ri n g the execution of i nstructions in the general and condit ional i nstruct ion categories. 8.4.2 Control CIR ($02) The control C I R is a 1 6-bit reg i ster which is accessed by the main processor to acknow ledge coprocessor requested exception processing or to abort the execution of a coprocessor i nstruct ion. The format of t h i s reg i ster is i l l u strated in F i g u re 8-1 9.
15 14 13 12 11 10 9 8 7 (Undefined, Reservedl 6 5 4 3 2

I XA I AB I

Figure 819. Control C I R Format

8-23

The M C68020 writes the hexidecimal value $0002 to the control C I R to acknowledge the receipt of one of the three "Take Except ion" coprocessor response primit ives. The M C68020 writes the hexidecimal va lue $0001 to the control C I R to abort any coprocessor i nstruct ion that is in progress. The MC68020 w i l l abort a coprocessor i nstruct ion when it detects one of three except ion cond itions: F-l i ne emulator detected after a response primit ive is read, privi lege vio lat ion cau sed by the supervisor check pri m i tive, or a format error (see 8.8 EXCEPTIONS). 8.4.3 Save CIR ($04) The save C I R is a 1 6-bit reg i ster through which the coprocessor com m u n icates status and state frame format i nformat ion to the main processor during the execution of a cpSAV E i nstruct ion. The main processor reads the save C I R to i n itiate the cpSAV E i nstruction. 8.4.4 Restore CIR ($06) The restore C I R is a 1 6-bit reg i ster. The main processor i n i t iates the cpRESTORE i nstruc tion by wri t i n g a coprocessor format word read from memory i nto t h i s reg i ster. During the execution of the cp RESTO R E i nstruction, the coprocessor com m u n i cates stat us and state frame format i nformation to the main processor through the use of the restore C I R. 8.4.5 Operation Word C I R ($08) The operat ion word C I R is a 1 6-bit reg i ster to which the main processor writes the F-l i ne operat ion word of the coprocessor i nstruct ion in progress when it is requested by the t ransfer operat ion word coprocessor response primit ive (8.6.4 Transfer Operation Word). 8.4.6 Command C I R ($OA) The command C I R is a 1 6-bit reg i ster. The main processor i n i t iates an i nstruct ion i n the coprocessor general i nstruction category by writing the i nst ruct ion command word, which fol l ows the i nstruction F-l i ne operat ion word, to this reg i ster. 8.4.7 Condition C I R ($OE) The con d ition C I R is a 6-bit reg ister th rough which the main processor i n itiates an i nstruct ion in the coprocessor cond itional category by writing the cond it ion selector assoc iated with the i nstruction. The format of the con d ition C I R is i l lustrated in F i g u re 8-20.
15 14 13 12 11 10 9 Undefined Reserved 8 6 5 4 3 2 Condition Selector
o

Figure 8-20. Condition C I R Format 8.4.8 Operand C I R ($1 0) The operand C I R is a 32-bit reg ister. If the coprocessor requests the transfer of an operand necessary to execute an i n struction, the operand transfer is performed by the main processor reading from or writing to this reg ister.

8-24

The M C68020 transfers a l l operands to and from the operand C I R a l i g ned with the most s i g n i f i cant byte of this reg ister. Any operand larger than four bytes is read from or written to this reg i ster u s i n g a seq uence of long word transfers. If the operand i s not a m u l t i p l e o f fou r bytes i n size, t h e port i o n remai n i ng after the i n itial l o n g word transfers w i l l be a l i g ned with the most S i g n i f i cant byte of the operand C I R. F i g u re 821 i l l ustrates the operand a l i g n ment u sed by the M C68020 when accessing the operand C I R.

31

24

Byte Operand

23

16

15

N o Transfer

Word Operand Three Byte Operand Long Word Operand Ten Byte Operand

No Transfer No Transfer

No Transfer

Figure 821 . Operand Alignment for Operand C I R Accesses 8.4.9 Register Select CIR ($1 4) The reg i ster sel ect C I R is a 1 6bit reg ister. When the coprocessor uses a response primit ive to request the transfer of a main processor control reg i ster, multiple main proc essor reg i sters, or m u lt i ple coprocessor reg i sters, the main processor reads this reg i ster to ident ify the n u mber or type of reg isters to be transferred. 8.4. 1 0 I nstruction Address C I R ($1 8) The i nstruction address C I R i s a 32bit reg i ster. I f the coprocessor u ses a response primit ive to req uest the address of the i nstruct ion it is cu rrently executing, the main proc essor w i l l transfer t h i s address to the i nstruct ion address C I A. Any transfer of the scanPC i s also performed th rou gh the i nstruct ion address CIR (see 8.6. 1 5 Transfer Status Register and ScanPC). 8.4.1 1 Operand Address CIR ($1 C) The operand address C I R i s a 32bit reg ister. I f a coprocessor uses a response primit ive to request an operand address t ransfer between the main processor and the coprocessor, the address is transferred t h rough this reg i ster. 8.5 COP ROCESSO R RESPONSE PRIM ITIVES INTRODUCTION The response pri m i t ives are essent i a l ly primit ive i nstructions that the coprocessor issues to the main processor during the execut ion of a coprocessor i nstruction. The coprocessor can com m u n i cate status i nformation and service req uests to the main proc essor through the use of the coprocessor response primit ives. Within the general and cond it ional i nstruction categories, i nd ividual i nstructions are d istingu ished by the opera tion of the coprocessor hardware and the services spec ified by coprocessor response pri m i tives and provided by the main processor.

825

8.5.1 Coprocessor Response Primitive Format The M68000 coprocessor response primit ives are encoded in a 1 6bit word which i s tran sferred to t h e main processor t h rough t h e u se o f t h e response C I A. The format of the coprocessor response primit ives is i l l u strated i n Fig ure 822.

I CA I PC I D R I

15

14

13

12

11 10 Function

3 4 Parameter

Figure 822. Coprocessor Response Primitive Format The encod i n g of bits [1 20] of a coprocessor response pri m i t ive is dependent on the i nd i o vidual pri mit ive bei n g i m p l emented. B i ts [1 5-1 3], however, are used to spec ify part i cular att ributes of the response primit ive which can be u t i l ized i n most of the primit ives de fi ned for the M68000 coprocessor i nterface. B i t [1 5] in the coprocessor response pri m i t ive format, denoted by CA, is used to specify the come again operat ion of the main processor. Whenever the main processor rece ives a response primit ive from the response C I R with the come again bit set to one, it w i l l per form the service i nd i cated by the primit ive and then ret urn to read the response C I R. This protocol al lows a coprocessor to com m u n i cate multiple response primit ives to the main processor during the execution of a s i n gle coprocessor i nstruction . B i t [1 4] i n the coprocessor response primit ive format, denoted by PC, i s used to specify the pass prog ram counter operat ion. If the main processor reads a primit ive from the response CIR that has the PC bit set, the main processor w i l l i m mediately pass the cur rent va lue of its program counter to the i nstruction address C I R as the f i rst operation i n servi c i n g t h e primit ive request. The value o f the program cou nter passed f rom the main processor to the coprocessor i s the address of the operat ion word of the coprocessor i n struction executing when the primit ive is received. The PC bit is i m p lemented in a l l of the coprocessor response pri m i t ives cu rrently def i ned for the M68000 coprocessor i nterface. If an u ndefi ned pri mit ive or a primitive that reo quests an i l l egal operation is passed to the main processor, the main processor w i l l i n i t iate exception processing for either an F-l i ne emu lator or a protocol violation (see 8.8.2 Main Processor Detected Exceptions). If the PC bit is set in one of these response primit ives, however, the mai n processor w i l l pass the program counter to the i nstruction address CIR before it i n i t iates except ion processing. The PC bit w i l l genera l ly be set i n the first primit ive ret urned by the coprocessor after the main processor i n it i ates a cpG EN i nstruction that can be executed concu rrently by the coprocessor. Si nce the main processor may proceed with i nst ruct ion stream execution once the coprocessor releases it, the coprocessor must record the i n struct ion address to support any poss ible except ion processing related to the i nstruction operat ion. Excep tion processi n g related to concu rrent coprocessor instruction execut ion is d i scu ssed i n 8.6.16.1 TAKE P R EI NSTRUCTI ON EXC EPTION. B i t [ 1 3] of the coprocessor response primit ive format, denoted by DR, is the d i rection bit and i s u sed in conj u nction with operand transfers between the main processor and the

826

coprocessor. If DR = 0, the d i rect ion of transfer is from the main processor to the coprocessor (main processor write). If DR = 1 , the d i rect ion of transfer is from the coprocessor to the main processor (main processor read). I f the operat ion indicated by a g iven response pri m i t ive does not i nvolve an expl icit operand transfer, the val u e of this bit i s dependent on the part icu lar pri m i t ive encod ing. 8.5.2 Scan PC During the execution of a coprocessor i nstruct ion, the program cou nter in the MC68020 w i l l conta i n the add ress of the operat ion word of that i nstruction. A second reg i ster is used to seq uential ly add ress the words that com pose the rem a i n i n g portion of a g iven i n struction. Th i s second reg i ster is referred to as the scan PC, si nce it is used to scan the i nstruction stream d u ri n g the i nstruction execution. I f the main processor req u i res extension words i n order to calcu late an effective address or desti nation address of a branch operat ion, it uses the scanPC to address these exten sion words in the i nstruction stream. A l so, if a coprocessor req uests the transfer of infor mation contai ned i n the i nstruction stream, the scanPC is used to address coprocessor defi ned extension words (which are provided in the i nstruction format) d u r i n g the transfer. As each word i s referenced, the scan PC i s i ncremented to poi n t to the next word in the i nstruction stream. When an i nstruct ion is com pleted, the va lue contai ned in the scanPC i s transferred to the program cou nter to address the operat ion word of the next i n struction to be executed. The va l u e of the scanPC at the t i me that the main processor reads the f i rst response pri m itive after an i nstruction i n i t iation i s dependent on the i nstruction bei n g executed. For a cpGEN instruction, the scanPC poi nts to the word fo l lowi n g the coprocessor com mand word. For the cpBcc i nstructi ons, the scan PC poi nts to the word fol l ow i n g the in stru ct ion operat ion word. For the cpScc, cpTRAPcc, or cpDBcc i nstructions, the scanPC poi nts to the word following the coprocessor cond ition speci fier word . If a coprocessor i m plementation u ses optional i n st ruction extension words to define a general or condit ional i nstruction, these words m u st be used consistently during the i n struction execution. Specifical ly, during the execut ion of general category i nstruct ions, when the coprocessor termi nates the i nstruction protocol the MC68020 assu mes that the scanPC i s pointing to the operat ion word of the next i nstruction to be executed. During the execution of cond it ional category i nstruct ions, when the coprocessor term i n ates the i n st ruction protocol the M C68020 assu mes that the scanPC i s po i n t i n g to the word follow i n g the last of any coprocessor defi ned extension words in the i nstruction format. 8.6 COPROCESSOR RESPONSE P R I M ITIVE SET DESCRIPTION The following sect ions present a detai led description of the M68000 coprocessor response pri m it ives which are supported by the M C68020. Any response primit ive that the M C68020 does not recog n ize w i l l cause the M C68020 to i n i t iate protocol violation ex cept ion processing (see 8.8.2.1 PROTOCOL VIOLATI O NS). This method of hand l i ng u ndefi ned primit ives al lows the su pport of extensions to the M68000 coprocessor response primit ive set to be e m u l ated by the protocol violation except i on hand ler. Excep tion processi n g related to the coprocessor i nterface is d i scu ssed in 8.8 EXCEPTIONS.

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8.6.1 Busy The busy response pri m i t ive cau ses the main processor to re i n it i ate a coprocessor i n stru ct ion. This primit ive can be used with i nstructions in the general or cond i t ional category. 8.6.1 .1 FORMAT. The format of t h i s primit ive is i l l ustrated in F i g u re 8-23.
15
o 14 10 9 8 6 4 o

13
1

PC

12

11

Figure 823. Busy Prim itive Format The PC bit is a l lowed and is i nterpreted as descri bed i n 8.5.1 Coprocessor Response Primitive Format. 8.6.1 .2 O PERATION. The busy pri m i tive is u t i l ized by coproCessors which can operate concu rrently with the main processor but can not buffer writes to their command or con d it ion C I R. A coprocessor may execute a cpGEN i nstruction concu rrently with i nstruc tion execution i n the main processor. I f the main processor attempts to i n i t iate an i nstruct ion in the general or cond itional i nstruction category w h i le the coprocessor is concu rrently executing a cpGEN i nstruction, the coprocessor can place the busy primitive i n the response C I R. When the main processor reads this primit ive, it servi ces pen d i n g i nterru pts (using a pre- i nstruct ion exception stack frame, see F i g u re 8-4 1 ) and then restarts the general or cond i t ional coprocessor i nstruct ion which it had attempted to i n it iate earlier by writing to the command or cond ition C I R res pect ively. The busy primit ive should only be used as the f i rst primit ive retu rned after the main proc essor attempts to i n i t iate an i nstruction in the general or cond it ional category. Thus, t h i s pri m i t ive w i l l b e u sed o n ly i n response to a write to t h e command o r condition C I R . I n par ticu lar, the busy primit ive should not be i ssued at a poi n t i n i nstruction execution after program visible resou rces (coprocessor or main processor program visible reg isters or operands in memory) have been altered by that i nstruction operat ion. The restart of an i n struction after it has altered program visible resou rces w i l l cause those resou rces to have i nconsistent values when the i nstruction execution is rei n it i ated. The scanPC is not considered a program visible reg ister. A spec ial case of the operat ions of the M C68020 in response to the busy primit ive occurs i n re lation to breakpoi n t cyc les (see 6.3.5 Breakpoints). This special case occu rs when a coprocessor F-l i ne i nstruction is i n i t iated th rou gh a breakpo i n t cyc le, the busy primit ive is retu rned in res ponse to the i nstruction i n i t iation, and an i nterrupt is pend i n g . If these th ree cond it ions are met, the breakpo i n t cyc le is re-executed after the i nterru pt excep tion proces s i n g has been completed. This is of part icular i nterest to designers that i n tend to use breakpoi nts to i ncrement or decrement a cou nter i n order to monitor the number of passes t h rough a loop, s i nce this spec ial case may cause m u l t i ple breakpo i nt acknowledge cyc les to be executed during a S i n g l e pass t h rough a loop.

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8.6.2 Null (No Operands) The n u l l coprocessor response pri m i t ive is used to com m u n icate coprocessor status i n format ion to the main processor. This primit ive can be used in conj unction with i nstruc t i ons i n the general and cond it ional categories. 8.6.2.1 FORMAT. The format of the n u l l primit ive i s i l lustrated i n F i g u re 8-24.
15 14 13 0 12 0 II 10 9 5 4 3 2

I C A I PC I

I 1 I

IA

PF

TF

Figure 8-24. Null Prim itive Format The CA and PC bits are i m plemented and are i nterpreted as descri bed in 8.5.1 Coprocessor Response Primitive Format. Bit [8] of the primit ive format, denoted by lA, is used to i n d i cate the i nterrupts al lowed pri m itive attribute. This bit determ i nes whether the MC68020 w i l l service pend i n g i n ter rupts prior to re-read i n g the response C I R after rece iving a n u l l primit ive. B i t [ 1 ] in the n u l l primit ive format, denoted by PF, is u sed to ind icate the process i n g f i n is hed stat us of t h e coprocessor. That is, PF = 1 ind icates that t h e coprocessor has completed a l l processing associ ated with an i nstruct ion. Bit [0] of the pri m i t ive format, denoted by TF, i s u sed to provide the true/false condition i n d icator to the main processor d u r i n g the execution of a cond it ional category i n struction. TF = 1 is the true cond ition spec i f ier and TF = 0 is the false condition spec ifier. The TF bit is only re levant for n u l l pri m i t ives i n which CA = 0 that are used by the coprocessor d u r i n g the execution of a condit ional type i nstruction.

8.6.2.2 OPERATION. A n u l l primit ive with CA = 1 i s hand led i n the same man ner by the M C68020 whether executing a general or cond itional type coprocessor instruction. I f the n u l l pri m it i ve i s issued by the coprocessor with CA = 1 and IA = 1, the main processor w i l l service pend i n g i nterru pts (generating a m id-i nstruction stack frame, see F i g u re 8-43) and ret urn to read the response C I R . If the n u l l primit ive is issued with CA = 1 and IA = 0, the main processor wi l l s i m ply re-read the response C I R without servicing any pend i n g i nterru pts.

The main processor completes the execution of a cond it ional category coprocessor i n struction when it receives a n u l l , CA = 0 pri m i t ive. A n u l l , CA = 0 primit ive is used to com m u n i cate a cond ition eval uation indi cator to the main processor during the execution of a cond itional i n struct ion and thus end the d ialogue between the main processor and coprocessor for that i nstruction. The PF bit i s not re levant during cond itional i nstruction execution since there i s an i m p l ied "coprocessor process i n g f i n ish" by the n u l l , CA = 0 primit ive. The d i alogue between the m a i n processor and coprocessor for i nstruct ions in the general category i s normally term i nated after any primit ive which does not have CA = 1 . If a trace exception i s pend i ng, however, the i nstruction d i alogue i s not termi nated u n t i l the main processor reads a n u l l , CA = 0, PF = 1 primit ive from the response CIR (see 8.8.2.5 TRACE EXC EPTI ONS). Thus, the main processor w i l l cont i n ue to re-read the response

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C I R u n t i l it receives a n u l l , CA = 0, PF = 1 pri m i t ive, and w i l l then proceed with trace exception process i ng. Under these c i rcumstances, the main processor w i l l service pend i n g i nterru pts before re-read i n g the res ponse C I R if IA = 1 . A coprocessor may be able to execute a cpGEN i n struction concu rrently with the execu tion of main processor i nstructions and buffer one write to either its command or condi tion CIR. In this sit uat ion, a n u l l pri mit ive with CA = 1 can be i ssued when the coprocessor i s concurrently execut i ng a cpG E N i nstruction and the main processor i n i t i ates another general or cond itional coprocessor i nst ruct ion. This primit ive i ndi cates t hat the coprocessor is currently busy and the main processor shou ld re-read the response C I R without rei n it i at i n g the i n struction. The IA bit of t h i s n u l l primit ive should generally be set to m i n i m ize i nterrupt l atency while the main processor i s wai t i n g for the coprocessor to complete the general category i nst ruct ion. A summary of the encod i n g s of the n u l l pri m i t ive i s provided i n Table 8-3.

CA
x

PC
1
0

Table 8-3_ Null Coprocessor Response Prim itive Encodings

IA x
0

PF
x

TF
x

1
0 0 0

x
0 0

x x c c

0 0

General Pass Program Counter to Instruction Address C I R , Clear PC Bit and Proceed with Operation Specified by CA, lA, PF, and TF Bits ReRead Response C I R , Do Not Service Pending Interrupts Service Pending Interrupts and Re-Read the Response CIR If ITrace Pendingl Re-Read Response CI R Else, Execute Next Instruction If (Trace Pendingl Service Pending Interrupts and Re-Read Response CIR Else, Execute Next Instruction Coprocessor Instruction Completed; Service Pending Exceptions or Execute Next Instruction

Instructions

Same as General Category

Conditional Instructions

Same as General Category Same as General Category Main Processor Completes Instruction Execution Based on TF c Main Processor Completes Instruction Execution Based on TF c Main Processor Completes Instruction Execution Based on TF c
= = =

x Don ' t Care c 1 or 0 Depending on Coprocessor Condition Evaluation

= =

8.6_3 Supervisor Check The supervisor check primit ive a l lows the coprocessor to verify that the main processor is operat i n g in the su pervisor state during the coprocessor i nstruct ion execution. This primit ive can be used i n conj u nction with i nstru ct ions i n the general and cond it ional coprocessor i n struct ion categories. 8.6_3.1 FORMAT. The format of the supervisor check primit ive is i l l ustrated in F i g u re 8-25.
15
1

14 PC

13

12

11

10

Figure 8-25. Supervisor Check Primitive Format

8-30

The PC bit i s al lowed and is i nterpreted as descri bed i n 8.5.1 Coprocessor Response Prim itive Format. W h i l e bit [1 5] is shown as 1 , this bit is actually a "don't care" value for t h i s primit ive. That is, the primit ive w i l l result in the actions spec ified below regard less of the va lue of t h i s bit. If this p r i m i t ive is i ssued with bit [ 1 5] = 0 during a cond itional category i nstruction, however, the main processor w i l l i n itiate protocol violat i on excep tion processing. 8.6.3.2 OPERATION. When the main processor reads the su pervi sor check pri m i tive f rom the response C I R , it checks the va lue of the S bit in the status regi ster. I f S = 0 (main proc essor ope rat i n g in u ser mode), the main processor aborts the coprocessor i n struction ex ecution by writ i n g a $0001 mask to the control CIR. The main processor then i n i t i ates privi lege violation except ion processing (see 8.8.2.3 PRIVILEGE VIOLATIONS). If the main processor i s in the su pervisor mode when it receives this primit ive, it w i l l s i m ply reo read the res ponse C I R . T h e pu rpose o f t h e su pervisor check pri m i t ive i s t o al low t h e impleme ntat ion o f privi leged i nstructions in the coprocessor general and conditional i nstruction categories. Thus, this primit ive should be the f i rst one i ssued by the coprocessor during the d i alog for an i nstruction which is i m plemented as privi leged. 8.6.4 Transfer Operation Word The transfer operat i on word primi tive al lows the coprocessor to obta i n a copy of the coprocessor i nstruct ion operation word. This primit ive can be used with general or condi t ional category i nstruct ions. 8.6.4.1 FOR MAT. The format of the transfer operation word pri m i tive is i l l ustrated i n F i g u re 826.

I CA I

15

14 PC

13

12

11 0

10

Figure 826. Transfer Operation Word Primitive Format Both the CA and PC bits are al lowed and are i nterpreted as descri bed i n 8.5.1 Coprocessor Response Primitive Format. I f t h i s pri m i t ive i s i ssued with CA = 0 during a cond i t ional category i nstruct ion, the main processor w i l l i n i t iate protocol violat ion except ion process i n g . 8.6.4.2 OPERATION. After read i n g this primit ive f rom t h e response C I R, t h e main proc essor transfers the operation word of the cu rrently executing coprocessor i nstruct ion to the operat ion word C I R. The va l u e of the scanPC is not affected by this primit ive. 8.6.5 Transfer From Instruction Stream The main processor transfers operands from the i nstruction stream to the coprocessor. This pri m i t ive is al lowed with general and cond itional category i n struct ions. 8.6.5.1 FORMAT. The format of the transfer from i nstruction stream primit ive is i l l u s trated i n F i g u re 827.

83 1

15
CA

14
PC

13 0

12 0

11

10

Length

Figure 827. Transfer From I nstruction Stream Primitive Format Both the CA and PC bits are al lowed and are interpreted as descri bed in 8.5.1 Coprocessor Response Primitive Format. If this pri m i t ive is issued with CA = 0 during a cond it ional category i n struct ion, the main processor w i l l i n itiate protocol violation exception processing. Bits [70] of the primit ive format spec i fy the length, i n bytes, of the operand to be trans ferred from the i nstruction stream to the coprocessor. The length must be an even n u m ber of bytes. If an odd length is speci f ied, the main processor w i l l i n i tiate protocol violation exception processing (see 8.8.2.1 P ROTOCOL VIOLATIONS). 8.6.5.2 OPERATION. When the main processor reads t h i s pri m i tive from the response CIR it copies the number of bytes ind icated by the length field from the i n struction stream to the operand CIR. Thus, coprocessor defi ned extension words provided in the instruction format can be transferred to the coprocessor i n response to this pri m i tive. The f i rst word or long word tran sferred is at the locat ion poi nted to by the scanPC when the pri m i tive i s read by the main processor and the scan PC i s i ncremented by two after each word i s tran sferred. Thus, the scanPC is i n cremented by the total nu mber of bytes transferred and poi nts to the word follow i n g the last word transferred when the primit ive execut ion has completed. The main processor w i l l transfer the operands from the i n struction stream u s i n g a sequence of long word writes to the operand C I R. I f the length field is not an even m u lt i ple of four bytes, the last two bytes form the i nstruct ion stream are transferred u s i n g a word write to the operand CIR. 8.6.6 Evaluate and Transfer Effective Address The effective address specif ied in the coprocessor i nstruct ion operat ion word is eva luated by the main processor and transferred to the coprocessor. This primit ive is al lowed with general category i nstructions. I f this pri m i tive i s i ssued by the coprocessor d u r i n g the execut ion of a condi tional category i nstruct ion, the main processor w i l l i n iti ate protocol violat ion except ion processi n g . 8.6.6.1 FORMAT. T h e format o f t h e eval u ate a n d t ransfer effective address pri m itive is i l l ustrated i n F i g u re 8-28.

I CA

15

I PC I

14

13 0

12 o

11

10 o

9 1

8 0

7 o

6 o

5 0

4 o

3 0

2 o

1 o

0 0

Figure 828. Eva luate and Transfer Effective Address Primitive Format Both the CA and PC bits are al lowed and are i nterpreted as descri bed in 8.5.1 Coprocessor Response Primitive Format. 8.6.6.2 OPERATION. When the main processor receives this primit ive during the execu tion of a general category i nstruct ion, the main processor eva luates the effective ad dress specif ied in the i nstruction operat ion word. If the effect ive address req u i res any

8-32

extension words, the sca n PC is assu med to be poi nting to the f i rst of these words when the main processor receives this primit ive. The sca n PC i s incremented by two after each of these extension words is referenced by the mai n processor. After the effective ad d ress is calcu lated, the res u l t i n g 32-bit va l ue i s wri tten to the operand address C I A . Only al terable control addressing modes are calcu l ated b y t h e M C68020 i n response t o t h i s primit ive. If t h e add ress i n g mode i n t h e operation word i s n o t an alterable control mode, the main processor aborts the i nstruction by writ i ng a $0001 to the control C I A and i n i t iates F-l i ne emulat ion exception processing (see 8.8.2.2 FLl N E E M U LATOR EXC EPTIO NS). 8.6.7 Evaluate Effective Address and Transfer Data The main processor transfers an operand between the coprocessor and the effective ad d ress specified in the coprocessor i nstruction operat ion word. This primit ive is a l l owed with general category i nstructions. If t h i s primit ive is used by the coprocessor d u ri n g the execut ion of a cond itional category i n struction, the main processor w i l l i n i t i ate protocol violation exception processing. 8.6.7.1 FORMAT. The format of the eval uate effective address and transfer data pri m i t ive is i l l ust rated i n F i g u re 8-29.

I CA I PC I DR I

15

14

13

12

11

10

9 8 Valid EA

3 Length

Figure 829. Evaluate Effective Address and Transfer Data Primitive Format The CA, PCr and DA bits are a l l owed and are i nterpreted as descri bed in 8.5.1 Coprocessor Response Primitive Format. The val i d effect ive add ress field (bits [1 0-8]) of the primit ive format a l lows the coprocessor to specify the legal effective address categories for this primit ive. I f the ef fect ive add ress specified in the i nstruction operat ion word is not a mem ber of the c l ass specif ied by bits [1 0-8], the main processor aborts the coprocessor i nstruction by writing $0001 to the control C I A , and i n i t i ates F-l i ne emu lation exception process i n g . The val id effective add ress field encod i ngs are l i sted i n Table 8-4. Table 84. Valid Effective Address Codes
000 001 010
al l

100 101 1 10 111

Control Alterable Data Alterable Memory Alterable Alterable Control Data Memory Any Effective Address I N o Restrictionl

N ote that the control a l terable, data a lterable, and memory alterable categories are determ i ned by the i ntersect ion of the a lterable effective address i n g category with the

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cont rol, data, and memory effective add ress i n g categories respect ively (see Table C-2. Effect ive Address i n g M ode Categori es). If the val i d effect ive address fields spec i f ied i n t h e primitive a n d i n t h e i nstruction operat ion word match, the M C68020 w i l l i n i t i ate pro tocol violation except ion processi ng if the primit ive req uests a write to a non-a lterable effective add ress. The length in bytes of the operand to be transferred i s specified by bits [7-0) of the primit ive format. There are several restrictions on the operand length field used with cer tain effective add ress i n g modes. I f the effect ive address is a main processor reg i ster (reg ister d i rect mode), only operand lengths of one, two, or four bytes are legal; other lengths cause the mai n processor to i n itiate protocol violation exception processing. Thus, a length of zero for a reg ister d i rect effective add ress w i l l res ult i n a protocol viola t ion. Operand lengths of zero th rou gh 255 bytes are legal i n conj u n ction with the memory address i n g mode. There is one exception to the length field for the memory effective add ress category. I f t h e effective add ress is i m med iate, t h e operand length m u s t b e o n e o r even a n d t h e d i rec tion of transfer must be to the coprocessor; otherwise, the mai n processor w i l l i n i t i ate protocol violation except ion processing. 8.6.7.2 OP ERATIO N. When the m a i n processor receives t h i s primit ive during the execu tion of a general category i n struction, it f i rst verifies that the effective add ress encoded in the i n struct ion operat ion word is in the effective address category specified by the primit ive. If t h i s cond ition is sat isfied, the effective add ress is calcu lated u s i n g any necessary effective add ress extension words located at the cu rrent sca n PC add ress and the sca n PC is i n cremented by two for each word refere nced. The main processor then t ran sfers the number of bytes specified i n the primitive between the operand C I R and the effective add ress using long word transfers whenever possi ble. Refer to 8.4.8 Operand C I R for i nformat ion concern i n g operand a l ignment for t ran fers i nvolvi ng the operand C I R.

The d i rect ion of the operand transfer is spec i f ied by the D R bit. D R = 0 i n d i cates a transfer f rom the effect ive add ress to the operand C I R and DR = 1 i n d i cates a transfer from the operand CI R to the effective add ress. If the effective add ress is the predecrement mode, the add ress reg ister used is decremented by the size of the operand before the transfer. The bytes w i t h i n the operand are then t ransferred to/from ascending add resses beg i n n i ng with the locat ion spec if ied by the decremented add ress reg i ster. If the effective add ressing mode is predec reme nt, A7 i s used as the add ress reg ister, and the operand is one byte i n length, A7 w i l l be decremented by two to maintain a word a l i g ned stack. For the post i ncrement effective add ress i ng mode, the address reg i ster used IS i n cre mented by the size of the operand after the transfer. The bytes w i t h i n the operand are t ran sferred to/from ascend i n g add resses beg i n n i ng with the locat ion spec ified by the ad dress reg ister. If the effective address i n g mode is post i ncrement, A7 is used as the ad d ress reg i ster, and the operand is one byte in length, A7 w i l l be i ncremented by two after the transfer to m a i n t a i n a word a l i g ned stack. It shou l d be noted that the transfer of odd length operands of lengths g reater than one using the - (A7) or (A7) + addreSSing modes can res u l t in a stack pOinter which i s not word a l i g ned .

8-34

The effect ive add ress calcu lation is repeated each time that this primit ive is i ssued d u ri n g the execution of a g iven i nstruction. The effective add ress is calcu l ated using the cu rrent contents of any add ress and data reg isters used i n the address i n g mode. The main processor locates any necessary effect ive add ress extension words at the cu rrent sca n PC locat ion and i n crements the scanPC by two for each extension word referenced in the i nstruction stream. The M C68020 s i g n extends byte and word size operands to a long word va l ue when t hey are tran sferred to an address reg ister (AOA7) u s i n g t h i s primitive and the reg ister d i rect effect ive add ress i n g mode. Byte and word size operands transferred to a data reg ister (DOD7) w i l l only overw rite the lower byte or word respectively of the data reg i ster referenced. 8.6.8 Write to Previously Evaluated Effective Address The m a i n processor tran sfers an operand from the coprocessor to a previously eva l uated effect ive add ress. This p r i m i t ive is al lowed w i th general category i nst ruct ions. I f t h i s primit ive i s u sed b y the coprocessor d u ri n g t h e execution of a cond i t ional category i n struct ion, the main processor w i l l i n itiate protocol violation exception processing. 8.6.8.1 FOR MAT. The format of the write to previously eva l uated effective add ress primit ive is i l l ust rated in F i g u re 8-30.

I CA

15

I PC I

14

13

12

I0

11

10

4 3 Length

Figure 830. Write to Previously Evaluated Effective Address Primitive Format The CA, and PC bits are allowed and a re i nterpreted as described in 8.5.1 Coprocessor Response Prim itive Format. The length in bytes of the operand t ransferred is spec i f ied in bits [7-0] of the primitive for mat. The M C68020 w i l l t ransfer operands between zero and 255 bytes in length. 8.6.8.2 OPERATION. When the main processor receives this pri mit ive during the execu t ion of a general category i nstruction, it t ran sfers an operand from the operand C I R to an effective add ress s pecif ied by a tem porary reg i ster w i t h i n the M C68020. This tem porary reg i ster w i l l conta i n the eva l uated effective address spec if ied in the coprocessor i nstruc t ion operation word i f t h i s primit ive is used after either the eva l uate and t ran sfer effective address, eva luate effect ive add ress and transfer data, or tran sfer m u l t i p l e coprocessor reg isters coprocessor response primit ive has been executed d u ri n g the coprocessor i n struct ion. I f t h i s primit ive is used d u r i n g an i nstruction i n which the effective add ress specif ied in the i nstruction operat ion word has not been calculated, the effective ad d ress used for the write is u ndefi ned. Also, if the previously eva l uated effective address was reg i ster d i rect, the va lue w ritten to in res ponse to t h i s pri m i t ive is undefi ned. The value on the M C68020 fu nction code signals d u ri n g the write operat ion w i l l i n d i cate either su pervisor or u ser data s pace depen d i n g on whether the S bit in the MC68020 status reg i ster is one or zero respectively when this primit ive is received. W h i l e a

8-35

coprocessor shou ld req uest writes to only alterab le effective add ress i n g modes, the M C68020 does not check the type of effective add ress used i n conj u nction with the exe cution of t h i s primit ive. For example, if the previously eva l uated effective add ress was p rogram counter relat ive and the M C68020 is in the user state (S = 0 in status reg i ster) when t h i s primit ive is received, the MC68020 w i l l write to user data space at the previ ously calcu lated program re lative add ress (the 32-bit va l ue contai ned i n the temporary in ternal reg i ster of the processor). Operands of length greater than four bytes are t ransferred in i nc rements of fou r bytes (operand parts) when possi ble. The m a i n processor w i l l f i rst read a long word operand part from the operand CI R and then transfer t h i s part to the current effective address locat ion. The t ransfers cont inue in t h i s manner u s i n g ascending memory locat ions u n t i l a l l o f t h e l o n g word operand parts are transferred a n d a n y rem a i n i n g operand part is then t ransfe rred using a one, two, or th ree byte transfer. For all effective addresses i n the memory category, the operand parts are stored in memory using ascending addresses beg i n n i ng with the add ress contai ned in the M C68020 tem porary reg ister. The execution of t h i s p ri m i tive wi l l not mod i fy any of the reg i sters that ap pear in the M C68020 program mers model. If the previously eval u ated effective add ress ing mode u t i l ized any of the M C68020 i nternal address or data reg i sters, the effective add ress value used w i l l be the l ast value generated by the eval u ate and transfer effective address, eval uate effect ive add ress and transfer data, or transfer m u l t i p l e coprocessor reg i sters primit ives. Thus, the write to p reviously evaluated effective add ress primitive w i l l not modify any data or add ress reg isters even if the previously eva l uated effective add ress is predecrement or post i ncrement mode. Note that the take add ress and t ransfer data primit ive desc ribed in 8.6.9 Take Address and Transfer Data does not rep lace the effective add ress value which has been calcu lated by the M C68020. Thus, the address that the main processor obta ins i n res ponse t o the take add ress and transfer data primitive can not be referenced by the w rite to previously eva l uated effect ive add ress primitive. It is possible to i m plement read-mod ify-write i nstructions (but not i n d ivisible bus cycles) u s i n g t h i s primit ive and the eva l u ate effective add ress and t ransfer data primit ive. 8.6.9 Take Address and Transfer Data The main processor t ransfers an operand between the coprocessor and an address sup p l ied by the coprocessor. This primit ive can be used with general or cond itional category i nstructions. 8.6.9.1 FORMAT. The format of the take address and t ransfer data primit ive is i l l ust rated in F i g u re 8-31 .
15 14
PC

13

I CA I

DR

12 0

11 0

10 1

9 0

8 1

Length

Figure 831 . Take Address and Transfer Data Primitive Format

8-36

The CA, PC, and DR bits are al lowed and are i nterpreted as described i n 8.5.1 Coprocessor Response Primitive Format. If t h i s primit ive is issued with CA = 0 d u ri n g a cond i t ional category i n struct ion, the main processor w i l l i n i t iate protocol violat ion ex cept ion processing. The operand length, which can be from zero to 255 bytes, is specif ied by bits [70] of the primit ive format. 8.6.9.2 OP ERATION. The main processor f i rst reads a 32-bit address from the operand address C I R. The operand i s then transferred, u s i n g a series of long word t ransfers, be tween t h i s address and the operand C I R. The operand parts are read or written to ascend i n g add resses start i n g with the add ress read from the opera nd address CI R. I f the operand length i s not a m u lt i p l e of fou r bytes, the f i nal operand part is transferred u s i n g a one, two, or t h ree byte transfer. The function code signals u sed w i t h the address read f rom the operand add ress C I R i nd i cate e i t h e r su pervi sor o r u ser data space depend i n g on whether the S bit i n the MC68020 status reg i ster is one or zero respectively when t h i s pri m i t ive is received. 8.6. 1 0 Transfer To/From Top of Stack The main processor transfers an operand between the coprocessor and the top of the c u rrently act ive main p rocessor stack (see 2.10 SYSTEM STACK). This primitive can be used with general or condit ional category i nstructions. 8.6.1 0.1 FOR MAT. The format of the transfer to/from top of stack primit ive i s i l l u strated in F i g u re 8-32.

I CA I PC I

15

14

13 DR

12

11 1

10 1

3 4 Length

Figure 832. Transfer To/From Top of Stack Primitive Format The CA, PC, and DR bits are al lowed and are i nterpreted as described i n 8.5.1 Coproces sor Response Primitive Format. I f t h i s pri m i t ive is i ssued with CA = 0 d u r i n g a cond it ional category i n struction, the main processor w i l l i n i t iate protocol violation except ion proc essing. Bits [7-0] of the primit ive format specify the length i n bytes of the operand to be trans ferred. The operand may be one, two, or four bytes in length; other length field val ues cause the main processor to i n i t iate protocol violat ion exception process i ng.

8.6. 1 0.2 OPE RATION. I f DR = 0, the main processor transfers the operand from the c u r rently act ive system stack to the operand C I R . The i m p l ied effective add ress used for the t ransfer i s therefore the (A7) + address i n g mode. Operands of length one cause the stack pointer to be i ncremented by two after the transfer to maintain word a l i g n ment of the stack.

If DR = 1 , the main processor tran sfers the operand from the operand C I R to the cu rrently active stack. The i m p l ied effect ive address used for the transfer is therefore the (A7)
-

8-37

add ressi n g mode. Operands of length one cause the stack poi n ter to be decremented by two before the t ra nsfer to maintain word a l i g n ment of the stack. 8.6. 1 1 Transfer Single Main Processor Register The main processor t ran sfers an operand between one of its data or add ress reg i sters and the coprocessor. This primit ive can be used with general or conditional category i nstructions. 8.6.1 1 .1 FORMAT. The format of the transfer s i n g l e main processor reg i ster primitive is i l l ust rated i n F i g u re 8-33.

I CA I PC I DR I

15

14

13

12 0

11 1

10 1

9 0

8 0

7 0

6 0

5 0

4 o

101 A I

2 Register

Figure 833. Transfer Single Main Processor Register Primitive Format The CA, PC, and DR bits are a l l owed and are i nterpreted as desc ribed i n 8.5.1 Coprocessor Response Prim itive Format. I f t h i s primitive i s issued w i t h C A = 0 d u ro i n g a cond i t ional category i nstruction, the main processor w i l l i n i t iate protocol violation exception processi ng. B i t [3], denoted by DIA, i n d icates w hether an address or data reg i ster is referenced . DIA = 0 i n d icates a data reg ister and DIA = 1 i n d icates an add ress reg i ster. Bits [2-0] iden t ify the reg ister n u mber referenced.

8.6.1 1 .2 OPERATIO N . I f DR = 0, the main processor writes the long word operand con tai ned in the s pecif ied reg i ster to the operand C I R . If DR = 1 , the main processor reads a long word operand f rom the operand C I R and transfers it to the i n d i cated data or address reg ister. 8.6. 1 2 Transfer Main Processor Control Register The main processor tran sfers a long word operand between one of its control reg i sters and the coprocessor. This primit ive can be used with general or cond itional category i nstruct ions. 8.6.1 2.1 FORMAT. The format of the t ransfer main p rocessor control reg i ster primit ive i s i l l ust rated i n F i g u re 8-34.

I CA I PC I

15

14

13 DR

12 0

11 1

10

9 0

8 1

7 o

6 0

5 0

4 o

3 0

2 0

1 o

0 0

Figure 8-34. Transfer Main Processor Control Register Primtive Format The CA, PC, and DR bits are a l l owed and are i nterpreted as descri bed i n 8.5.1 Coprocessor Response Primitive Format. I f t h i s primitive i s issued w i t h C A = 0 d u ro i n g a cond i t ional category i nstruction, the main processor w i l l i n it i ate protocol violation except ion proceSS i n g .

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8.6.1 2.2 OPERATI ON. When the main processor receives t h i s primit ive it f i rst reads a control reg i ster select code from the reg i ster select C I R . This code determ i nes which main processor contro l reg i ster is referenced d u ri n g the transfer. The control reg i ster select codes recognized by the MC68020 are shown in Table 85. If the control reg i ster selector code is not recog n ized by the M C68020, the MC68020 w i l l i n itate protocol vi ola tion except ion process i n g (see 8.8.2.1 P ROTOCOL VIOLATIO NS). Table 85. Main Processor Control Register Selector Codes

Hex

xOOO Source Function Code I SFCI Register xOOl Destination Function Code IDFCI Register x002 Cache Control Register ICACRI User Stack Pointer IUSP) xBOO x801 Vector Base Register IVBR) x802 Cache Address Register I CAAR) Master Stack Pointer IM SP) x803 x804 Interrupt Stack Pointer l i SP) All other codes cause a protocol violation exception

Control Register

After read i n g a val i d code from the reg i ster select C I R, if DR = 0, the main processor writes the long word operand from the spec ified control reg ister to the operand C I A . I f DR = 1 , the m a i n processor reads a long word operand from t h e operand C I R a n d p laces i t i n t h e spec if ied control reg i ster. 8.6.1 3 Transfer Multiple Main Processor Registers The main processor transfers long word operands between one or more of its data or add ress reg i sters and the coprocessor. This primitive can be used with general or cond i tional category i nstructi ons. 8.6.1 3.1 FORMAT. The format of the transfer m u l t i p l e main processor reg i sters primit ive is i l l ustrated in F i g u re 835.

I CA I PC

15

14

13 DR

12 0

11

10

3 0

0 0

Figure 835. Transfer Multiple Main Processor Registers Primitive Format The CA, PC, and DR bits are a l l owed and are i nterpreted as descri bed in 8.5.1 Coprocessor Response Prim itive Format. If t h i s primit ive is issued with CA = 0 during a conditional category i n struct ion, the main processor w i l l i n itiate protocol violation ex cept ion processing. 8.6.1 3.2 OPERATION. When the main processor receives t h i s primit ive it f i rst reads a 1 6bit reg i ster select mask from the reg i ster select CIR. The format of the reg i ster select mask i s i l l ust rated in F i g u re 836. A reg i ster w i l l be transferred if the bit correspond i ng to that reg i ster in the reg i ster select mask is set to one. The selected reg i sters are trans ferred i n the order 0007 and then AOA7.

839

I A7 I A6 I A5 I A4 I A3 I A2 I A1 I AO I 07 I D6 I 05 I 04 I 03 I 02 I 01 I DO I
Figure 836. Register Select Mask Format If DR = 0, the main processor writes the conten t s of each reg ister ind icated in the reg i ster select mask to the operand CIR u s i n g a sequence of long word transfers. If DR = 1 , the main processor reads a long word operand from the operand C I R i nto each reg i ster i n d i cated i n the reg i ster selector mask. The reg i sters are transferred i n the same order regard less of the d i rection of transfer i n d icated by the DR bit in the primit ive. 8.6. 1 4 Transfer Multiple Coprocessor Registers From zero to s ixteen operands are transferred between the effective address s pecified i n the coprocessor i nstruct ion and the coprocessor. This primitive i s allowed w i t h general category i nstruct ions. If t h i s p r i m i t ive is i ssued by the coprocessor during the execution of a con d i t ional category i nst ruct ion, the main processor w i l l i n i t iate protocol violation exception proceS S i n g . 8.6.1 4.1 FO RMAT. T h e format o f the transfer m u l t i p l e coprocessor reg i sters primit ive is i l l u st rated i n F i g u re 837.

15

14

13

12

11

10

I CA I PC I

15

14

13 DR

12 0

11

10
o

9 0

Length

Figure 837. Transfer Multiple Coprocessor Registers Primitive Format The CA, PC, and DR bits are a l lowed and 8.5.1 Coprocessor Response Primitive Format. are i nterpreted as descri bed in

Bits [7-0) of the primit ive format ind icate the length in bytes of each operand transferred. The operand length must be an even n u mber of bytes, odd length operands w i l l cause the MC68020 to i n it i ate protocol violation exception process ing (see 8.8.2.1 P ROTOCOL VIO LATIONS). 8.6.1 4.2 OPERATION. When the main processor receives t h i s primit ive it w i l l calcu late the effective address s pec if ied in the coprocessor i nstruction operat ion word. The sca n PC should be poi n t i n g to the f i rst of any necessary effective address extension words when t h i s p r i m i t ive i s read from the response CIR and the scanPC w i l l be i n cremented by two for each extension word reference during the effective address calcu lation. For tran sfers from the effective address to the coprocessor (DR = 0), the con trol address i n g modes and the posti ncrement add ress i ng mode are legal. For transfers from the coprocessor to the effective address (DR = 1 ), the a l terable control and predecrement address i n g modes are lega l. I l legal addreSS i n g modes cau ses the MC68020 to abort the i nstruction by writing a $0001 to the control CIR and i n itiate F- l i ne emulator exception process i n g (see 8.8.2.2 FLl N E EMULATOR EXC EPTIO NS). After perform i n g the effective add ress calcu lation, the MC68020 reads a 1 6-bit reg i ster select mask from the reg i ster select CIR. W h i le the coprocessor can use the reg i ster

8-40

select mask to i n d icate which reg ister it w i l l transfer, the M C68020 simply counts the n u m ber of ones in the reg ister select mask to determ i ne the number of operands that w i l l be transferred. Thus, t h e order o f t h e ones i n t h e reg ister select mask is not relevant to the operat ion of the main p rocessor and up to 16 operands can be t ransferred by the main processor i n res ponse to t h i s primit ive. Thus, the total number of bytes transferred is the prod uct of the number of operands transferred and the length of each operand specif ied by bits [7-0] of the pri m i tive format.

If DR = 1 , the main processor wi l l read the n u m ber of operands specified in the reg ister sel ect mask f rom the operand C I R and write these operands to the effective add ress s pec if ied in the instruction operation word u s i n g long word transfers whenever poss i ble. If DR = 0, the main processor w i l l read the number of operands specif ied i n the reg i ster select mask from the effective address and write them to the operand CIA. For the control address i n g modes, the operands are transferred to/from memory u s i n g ascend i n g addresses. F o r the post i ncrement add ress i ng mode, the operands are read from memory with ascen d i n g addresses and the add ress reg i ster used is i ncremented by the s ize of each operand after that operand is t ran sferred. Thus, the final val u e of the add ress reg i ster used with the (An) + address i n g mode w i l l be i ncremented by the total number of bytes transferred d u ri n g the pri m i t ive execution. For the predecrement add ressi n g mode, the operands are w ritten to memory with descen d i n g add resses, w h i l e the bytes within each operand are w ritten to memory with ascend i n g add resses. As a n example, the format i n a long word wide memory for two 1 2 byte operands t ransfe rred from the coprocessor to the effective add ress u s i n g the - (An) add ress i n g mode is i l l u st rated in F i g u re 8-38. The address reg i ster used is decremented by the s ize of each operand before that operand i s tran sferred. The bytes w i t h i n each operand are then written to memory w i t h asce n d i n g addresses. Thus, the add ress reg ister used is decremented by the total number of bytes transferred by the end of the p r i m i t ive execution. The MC68020 w i l l transfer the data u s i n g long word transfers whenever poss i b le.
31 24 Op 1 , Byte 1O)

An - 2 * Length = F i nal A n _

I
I

23

16

I
I I

15

I
I I

7 O p 1 , Byte I L- 1 )

A n - Length _

Op 0, Byte 101

I I I I

I I

I n i tial A n _ NOTE:

I I

I I I

O p O, Byte l L- 1 1

O p 0, B y t e 101 is the first byte written to memory

O p 0, Byte I L- l i IS the last byte of the f i rst operand written to memory O p 1 , Byte 101 is the first byte of the second operand written to memory O p 1 , Byte

I L- 1 1

is the last byte written to memory

Figure 8-38. Operand Format i n Memory for Transfer to - (An) 8_6_ 1 5 Transfer Status Register and Scan PC The main processor t ransfers operands between the coprocessor and either the main processor status reg ister or bot h the status reg i ster and scan PC, This primit ive is

8-41

a l lowed with general category i nstruct ions. I f t h i s primit ive i s used by the coprocessor d u r i n g the exec ution of a cond itional category i nstruction, the main processor w i l l i n i t iate protocol violation exception processing. 8_6_1 5_1 FORMAT. The format of the t ransfer status reg i ster and scanPC primit ive i s i l l ust rated i n F i g u re 8-39.

15
CA

14
PC

13

DR

12

11

10

sp

Figure 839. Transfer Status Register and ScanPC Primitive Format The CA, PC, and DR bits a re a l l owed and are i nterpreted as descri bed in 8.5.1 Coprocessor Response Primitive Format. Bit [8] of the primit ive format, denoted by SP, i n d icates whether the scan PC, in add ition to the status reg ister, w i l l be t ra nsferred during the primit ive execution. I f SP = 1 , both the sca n PC and status reg i ster w i l l be t ransferred. If SP = 0, only the status reg ister w i l l be t ransferred. 8.6.1 5.2 OPERATIO N . If SP = 0 and DR = 0, the main processor w i l l write a 1 6-bit operand from its status reg ister to the operand CIR. If SP = 0 and DR = 1 , the main processor w i l l read a 1 6-bit operand from t h e operand C I R i nto the status reg i ster . If SP = 1 , operands w i l l be t ransferred between the status reg i ster and the operand C I R a n d between the s c a nP C a n d i nstruction add ress CIR. The order a n d d i rect ion of the t ransfer depends on the DR bit in the primit ive format. If SP = 1 and DR = 0, the main proc essor f i rst writes the long-word value in the scanPC to the i nstruction add ress CI R and then writes the status reg i ster to the operand CIR. If SP = 1 and DR = 1 , the main proc essor f i rst reads a 1 6-bit va l ue f rom the operand D I R i nto the status reg ister and then reads a long word va lue from the i nstruction add ress CIR i nto the scan PC. Th is primit ive a l lows the i m p lementation of i n structions in the general i nstruct ion category which change the mai n processor prog ram fl ow. The main processor change of f l ow can occ u r due to t ransfers to the status reg i ster, the scan PC, or both. Access to the status reg ister enab les the coprocessor to determi ne and m a n i pu l ate the main processor cond ition codes, su pervisor status, t race modes, master or i nterrupt stack usage, and i n terru pt mask level . A n y i nstruction words that have been prefetched by t h e main processor beyond t h e cur rent scan PC locat ion are d i scarded by the MC68020 when t h i s primitive is i ssued with DR = 1 (transfer to main processor). The M C68020 w i l l then ref i l l the i nstruction p i pe from the scan PC add ress in the add ress space i n d icated by the status reg i ster S bit. If the sca nPC was not a ltered by the primit ive, the i nstruction pipe w i l l be ref i l led using the value of the scanPC before the p r i m i t ive execution. I f T1ITO = 01 i n the MC68020 status resgister (trace on change of f low, see 6.3.9 Tracing) when the coprocessor i n struct ion beg ins execution and t h i s pri mit ive is i ssued with

8-42

DR = 1 , a trace except ion w i l l be made pend i n g w i t h i n the MC68020. Th is trace exception w i l l be taken when the coprocessor signals that it has completed all processing associated with the i n struction by ret u r n i n g the null pri m i t ive with CA = 0 and PF = 1 (see 8.8.2.5 TRACE EXCEPTIONS). 8.6. 1 6 Exception Processing Request Prim itives There are three p r i m i t ives defi ned for the M68000 coprocessor i n terface that a l low the coprocessor to cause exception processing based on its operat ions. When the main processor receives one of these t h ree primit ives from the coprocessor, the main proces sor w i l l i n i t i ate except ion processing. These primit ives enable a coprocessor to suspend or abort an i nstruction due to a n exception that occu rred during the coprocessor opera t ion. The t h ree "Take Except ion" coprocessor res ponse pri m i t ives d i ffer m a i n ly i n the stack frame saved by the M C68020 in res ponse to the primit ive. Si nce d i fferent stack frames are saved for each of the primit ives, the RTE i nstruct ion executed to exit the exception handler routine w i l l cause the M68020 to operate d ifferently for each of the stack frames. When the RTE i nstruction i s executed i n the exception hand ler, the MC68020 w i l l either restart the i nstruct ion d u ri n g which the primit ive was received, cont inue the instruction, or proceed with the execution of the next i nstruction i n the instruction stream. 8.6.1 6.1 TAKE P REI NSTRUCTION EXCEPTION. The main processor i n i t iates exception processing u s i n g a coprocessor suppl ied exception vector and the pre- i nstruction excep t i on stack frame format. This primit ive can be used with general or cond it ional category i nstructions. 8.6. 1 6. 1 . 1 Format. The format of the take pre-i nstruction exception primit ive is i l l ustrated in F i g u re 8-40.

15 0

14
PC

13 0

12 1

11 1

I 1

10

2 4 3 Vector Number

Figure 840. Take Pre-Instruction Exception Primitive Format The PC bit is a l lowed and is i nterpreted as descri bed in 8.5.1 Coprocessor Response Primitive Format. Bits [70] of the p r i m i t ive format a re u sed to specify the exception vector number used by the main processor to i n it i ate exception processing. 8.6.1 6.1 .2 Operation. When the main processor receives t h i s primit ive, it f i rst acknowledges the coprocessor exce ption req uest by writ i n g a $0002 to the control C I R. The M C68020 then proceeds with exception processing as detai led i n 6.2.4 Exception Processing Sequence. The vector number for the exception is taken from bits [7-0] of the primit ive and the MC68020 uses the fou r word stack frame format i l l u strated in F i g u re 8-4 1 .

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SP r+ 02
r-

15

14

13

12

11

10

__ __ __ __ __ __ __ __ __ __ __ __

6 8 S ta tu s_ g i s te r _ _R _ _ e _

__ __ __ __ __ __ __ __ __ __ __

- - - - - - - - - - - - Program Counter - - - - __ __ __

+ 06 0 0

m _ __ __ __ __ 0 __ __ _ __ __ __ __ _ Bc tor_ u_ e r __ __ __ __ __ __ _

-- - - - -

Figure 8-41 . MC68020 Prelnstruction Stack Frame The value of the program counter saved in t h i s stack frame is the operation word add ress of the coprocessor i nstruct ion d u r i n g which the pri mit ive was received. Thus, if no mod ificiations are made to the stack frame with i n the except ion handler routi ne, an RTE i nstruction w i l l cause the M C68020 to retu rn to re- i n i t iate the i nstruction during which the take pre- i n st ruct ion exception primit ive was received. This primit ive can be u sed in a number of c i rcu mstances in which the coprocessor must req uest except ion processing rel ated to its operat ion. The take pre-i nstruction exception primit ive can be u sed when the coprocessor does not recogn ize a value wri tten to either its command CIR or con d i t ion CIR to i n itiate a general or con d i t ional i nstruct ion respec tively. This primit ive can also be used if an exception occu rred in the coprocessor i n struction before any program visible resources where mod i f ied by the i nstruction opera tion. Th i s primit ive should not be u sed d u r i n g a coprocessor i nstruction if prog ram visible resources have been mod if ied by that i nstruction. Si nce the M C68020 w i l l re- i n i t iate the i nst ruct ion when i t ret urns from exception process i ng, the restarted i nstruction would receive the previously mod if ied resou rces i n an i nconsistent state. One of the most i m portant uses of the take pre-i nst ruct ion exception primit ive is to signal an exception cond ition in a cpG EN i nstruct ion that was executing concu rrently with the main processor's i nstruction execution. If the coprocessor no longer req u i res the services of the m a i n processor to complete a cpGEN i n struction and the concu rrent i nst ruct ion completion is t ransparent to the prog rammer's model, the coprocessor can release the main processor by iss u i n g a pri m i t ive with CA = O. Thus, the main processor w i l l genera l ly proceed to execute the next instruction in the i n struction stream and the coprocessor w i l l complete its operat ions conc urre ntly w i t h the main processor opera t ion. If an except ion occ urs w h i l e the coprocessor is executing an i nstruction conc urrent ly, the coprocessor m u st wait u n t i l the main processor attempts to i n it i ate the next general or condit ional i nstruction before the exception can be processed. After the main processor writes to the command or cond ition CIR to i n i t iate a general or con d i t i onal i n struction respect ively, it w i l l then read the response C I R. At t h i s t i me, the coprocessor can ret u rn the take pre- i nstruction except ion primit ive. This protocol a l lows the main processor to proceed w i t h exception processing related to the previous concurrently ex ecut i n g coprocessor i nstruction and then return to re- i n i t iate the coprocessor i nstruct ion d u ri n g which the except ion was sig nal led. The coprocessor should record the address of a l l general category i nstructions which can be executed concu rrently with the main processor if exception processing and ex cept ion recovery is to be su pported for that i n struction. Si nce the exception w i l l not be reported u nt i l the next coprocessor i nstruction is i n it i ated, the i nstruction add ress i s genera l ly necessary to determ i ne w h i c h i nstruction t h e coprocessor was executing when the exception occu rred. A coprocessor can record the i nstruction add ress by sett i n g

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PC = 1 i n one of the p r i m i t ives u sed before the main processor is released after servicing a primit ive with CA = O. 8.6.1 6.2 TAKE M I DINSTRUCTION EXCEPTION. The main processor i n i t iates except ion processing using a coprocessor suppl ied exception vector and the m id-i nstruction ex cept ion stack frame format. This primit ive can be used with general or condit ional category i nst ruct ions. 8.6. 1 6.2.1 Format. The format of the take m id-instruction exception pri mit ive is i l l u strated i n F i g u re 8-42.
15
a

14
PC

13

12 1

11 1

10 1

8 1

Vector Number
4 3

Figure 8-42. Take M id-I nstruction Exception Primitive Format The PC bit is a l lowed and is i nterpreted as described in 8.5.1 Coprocessor Response Prim itive Format. Bits [7-0] of the pri m i t ive format are used to specify the exception vector number used by the main processor to i n i t iate except ion process i ng. 8.6. 1 6.2.2 Operation. When the main processor receives this primitive, it f i rst acknowledges the coprocessor exception req uest by writing a $0002 to the control C I R . T h e M C68020 then proceeds with exception processing as detai led i n 6.2.4 Exception Processing Sequence. The vector nu mber for the exception is taken from bits [7-0] of the primit ive and the M C68020 uses the ten word stack frame format i l l ust rated in F i g u re 8-43. The value of the program counter saved in t h i s stack frame is the operation word add ress of the coprocessor i nstruct ion d u r i ng which the primit ive was received. The scan PC field contains the value of the M C68020 scan PC when the pri m i t ive was received. I f no p r i m i t ive cau sed the eval uation of the effective address i n the coprocessor i nstruction operat ion word prior to the except ion req uest primit ive, the value of the effective address field in the stack frame is u ndefi ned.

SP06

Status Register + 02 f- - - - - - - - - - - - - - S can PC - - - - - - - - I Vector Number + -- -- -- -- -- -- -- --- -- -- L- -- -- -- -- -- -- -- -- -1 + rProgram Cou nter - - - - - - - R e l n terna I gister -1 + OC OE eratio nord o pW + -1 + 10 I- - - - - - - - - - - - Effective Address - - - - - - - - 15 14
a

13
a

12

11

10

08

_ _ _ _ _

__ __ __ __ __ __ __ __ __ __

__ __ __ __ __ __ __ __ __ __ __

__ __ __ __ __ __ __ __ __ __ __

__ __ __ __ __ __ __ __ __ __ __ -

Figure 8-43. MC68020 M id-I nstruction Stack Frame

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This primit ive al lows the coprocessor to req uest exception processing to handle an ex cept ion that occu rred w h i l e the coprocessor is engaged in the i nstruction d i alog with the main processor. I f no mod ifications are made to the stack frame w i t h i n the exception hand ler, the M C68020 w i l l return from the except ion handler after an RTE i nstruction and read the response CIR. Thus, the main processor w i l l attempt to continue the execution of an i nstruction suspended by the take m id-i nstruction exception primit ive by read i n g t h e response C I R a n d process i n g t h e primit ive it receives. 8_6_1 6.3 TAKE POSTINSTRUCTION EXC EPTION. The main processor i n i t iates exception processing using a coprocessor suppl ied exception vector and the post-i nstruction ex ception stack frame format. This primit ive can be used with general or cond itional category i nstructions. 8.6.1 6.3.1 Format. The format of the take post-i nstruction exception primit ive is i l lustrated i n F i g u re 8-44.
15 0

1 PC 1 0 1

14

13

12 1

11

10

2 3 4 Vector Number

Figure 8-44. Take Post-Instruction Exception Primitive Format The PC bit is a l lowed and is i nterpreted as descri bed in 8.5.1 Coprocessor Response Primitive Format. Bits [7-0] of the p r i m i t ive format are used to s pec ify the except ion vector number u sed by the main processor to i n it i ate exception process i ng. 8.6.1 6.3.2 Operation. When the main processor receives this primit ive, it f i rst acknowledges the coprocessor except ion request by writing a $0002 to the control CIR. The MC68020 then proceeds with exception processing as deta i led i n 6.2.4 Exception Processing Sequence. The vector nu mber for the exception is taken from bits [7-0] of the primit ive and the M C68020 u ses the six word stack frame format i l l ustrated in F i g u re 8-45.
6 5 14 13 12 11 10 9 8 15 Status Register SP_ + 02 _ _ _ _ _ _ _ _ _ _ _ _ _ Scan PC _ _ _ 4 3 2

v_to r _ m b er e c _N _ _ o _ u_ 08 r- - - - - - - - - - - - + Prog ram C ounter - - - - - -

+ oo o

__ __ __ __ __ _

oIL-

______ ____
__ __ __ __ __ __ __ -

__ __ __ __ __ __ __ __

---

- -

Figure 845. MC68020 Post-Instruction Stack Frame The value of the main processor sca n PC at the t i me t h i s primit ive is received is saved i n the sca n PC field o f the post-i nstruction except ion stack frame. The value of the program counter saved i s the operat ion word add ress of the coprocessor i nstruction during which the pri m i t ive was received.

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When the M C68020 receives the take post-instruction exception primit ive it assu mes that the coprocessor either com pleted or aborted the i n struction in progress with an excep tion. If no mod ificat ions are made to the stack f rame w i t h i n the except ion hand ler, the MC68020 w i l l ret u rn f rom the exception handler after an ATE i n struction to beg i n execu tion at the location specif ied by the scanPC field of the stack frame, which should be the address of the next i n st ruct ion to be executed. This primit ive a l l ows the coprocessor to req uest except ion processing when the coprocessor com pletes or aborts an i nst ruct ion with an exception w h i l e the main pro cessor was wa i t i n g for either a release (for general category i nstructions) or an eva l u ated true/false cond ition i nd icator (for cond i t ional category i nst ruct ions). Thus, the operat ion of the MC68020 i n response to this pri m i t ive is analogous to standard M68000 Fam i ly i n struct ion rel ated exception process i ng, for example the d ivide-by-zero except ion.

8.7 COP ROCESSOR C LASS I FICATIONS M68000 coprocessors can be c l assif ied i nto two categories depending on their bus i nter face capab i l ities. The f i rst category, non-DMA coprocessors, a lways operate as bus slaves. The second category, D M A coprocessors, operate as bus sl aves while com m u n icat i n g with the m a i n processor across the coprocessor i nterface, but also have the abil ity to operate as bus masters and d i rectly control the system bus. Si nce non-DMA coprocessors a lways operate as bus s l aves, a l l external bus rel ated fu nc tions that the coprocessor req u i res are hand led by the main processor. The main proc essor w i l l tran sfer operands f rom the coprocessor by f i rst read i n g the operand from the appropri ate CIA and then writing the operand to a specif ied effective address. Li kew i se, the mai n processor tran sfers operands to the coprocessor by f i rst read i n g the operand from a spec ified effective add ress and then writing that operand to the approp riate C I A . I f t h e operat ion o f a coprocessor does n o t req u i re a large portion o f t h e avai lable bus bandwidth, that coprocessor can be effici ently i m p lemented as a non-DMA coprocessor. Si nce non-D M A coprocessors o n ly operate as bus slaves, the bus i n terface c i rc u i t ry of the coprocessor does not need to be as com plex as that of a device which can operate as a bus master. D M A coprocessors have the capabi l ity to operate as bus masters. This i m p l ies that the coprocessor i m plements all control, address, and data signals necessary to req uest and obta i n the bus, and then perform D M A t ran sfers using the bus. I f the operation of a coprocessor req u i res a re latively high amount of bus bandw idth, that coprocessor can be i m p lemented as a D M A coprocessor to i m p rove the eff i c iency of operand transfers bet ween memory and the coprocessor. D M A coprocessors, however, must st i l l act as bus s l aves when they req u i re i nformat ion or services of the main processor u s i n g the M68000 coprocessor i nterface protocol . I n particu lar, if the coprocessor must access data con tai ned in the main processor reg isters, the coprocessor must com m u n i cate t h i s req uest to the main processor u s i n g the response primit ives and operate as a bus s l ave d u ring the execution of those p r i m i t ives.

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8.8 EXCEPTIONS A n u m ber of except ion con d i t ions may occur rel ated to the execut ion of coprocessor i n struct ions. W h i l e these exceptions may be detected by either the main processor or the coprocessor, except ion process i n g is coord inated and handled by the main processor. This protocol a l l ows the service of coprocessor rel ated exceptions to be a simple exten sion of the protocol u sed to service standard M68000 Family except ions. That is, when either the main processor detects an except ion or i s s i g nal led by the coprocessor that an exception cond ition has occu rred, the main processor p roceeds with except ion process i n g as described in 6.2.4 Exception Processing Sequence. 8.8.1 Coprocessor Detected Exceptions Exceptions which are perceptible to the coprocessor, whether or not they are also perceptible to the main processor, a re generally c l assif ied as coprocessor detected ex cept i ons. These exceptions can arise from the M68000 coprocessor i nterface operations, i nternal operat ions, or other system re lated operat ions of the coprocessor. M ost coprocessor detected except ions are s i g nal led to the main processor t h rough the use of one of the t h ree "Take Exception" p r i m i t ives defi ned for the M6800 coprocessor i nterface. When the main p rocessor receives one of these exception s i g nal l i ng p r i m i t ives, it proceeds as desc ribed i n 8.6.1 6 Exception Processing Request Prim itives. There is one type of coprocessor detected exception which is not s i g n a l l ed to the coprocessor by a response pri m i t ive. Coprocessor detected format errors during the cpSAVE or cpRESTOR E i nstruction are s i g n a l led to the main p rocessor u s i n g the i nva l i d format word as described i n 8.3.3.4.3 Invalid Format Words. 8.8.1 .1 COPROCESSOR DETECTED PROTOCOL VIOLATIONS. Protocol vio lat ion excep tions are com m u n i cation fai l u res between the main processor and coprocessor across the M68000 coprocessor i nterface. Coprocessor detected protocol violations occ u r when the main processor accesses entries i n the coprocessor interface reg i ster set i n a se q uence that is determ i ned to be i l legal by the coprocessor. The sequence of operat ions that the main processor w i l l perform for a g iven coprocessor inst ruct ion or coprocessor respon se pri m i t ive have been desc ribed previously in t h i s section. Thus, a g iven C I R ac cess by the main processor can be considered i l l egal by the coprocessor if the coprocessor was not expect i n g that access to occur. Coprocessors can be i m plemented with a range of i n terface protocol violation detection capabi l it ies. Accord i n g to the M68000 coprocessor i n terface protocol, the main proc essor a lways accesses the operation word, operand, reg ister select, i nstruction add ress, or operand add ress C I Rs in a synchronous man ner with respect to the operation of the coprocessor. That is, bot h the main processor and the coprocessor are aware of the se q uence in which these five reg i sters w i l l be accessed d u ri n g the execution of a g iven coprocessor response primit ive. As a m i n i m u m , a l l M68000 coprocessors should detect a protocol violation if the main processor accesses any of these five reg isters when the coprocessor i s expecting an access to either the command or condit ion CIR. Likew ise, if the coprocessor i s expecting an access of the command or cond ition C I R and the main processor accesses one of these five reg i sters, the coprocessor should detect and s i g nal a protocol violation.

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Accord i n g to the M68000 coprocessor interface protocol, the main processor can per form a read of either the save or response CIRs or a write of either the restore or control C I Rs asynchronously to the operat ion of the coprocessor. That is, val i d accesses can be made to these reg i sters w i t hout the coprocessor exp l icitly expecting these accesses at a g iven point i n its operation. W h i l e the coprocessor can ant i c i pate certai n accesses to either the restore, res ponse, and control coprocessor i nterface regi sters, these reg isters can also be accessed when not antici pated by the coprocessor operat ion. Protocol violations can not be s i g n a l led to the main processor during the execution of c pSAV E or cpRESTO R E i nstructions. I f a coprocessor detects a protocol violat i on d u r i ng the cpSAVE or cpRESTO RE i nstruct ion, it should signal the exception to the main proc essor when the next coprocessor i nstruction is i n it iated. The main p h i losophy of the coprocessor detected protocol violat ion is that the coprocessor should always res pond when one of its i nterface reg isters i s accessed. I f t h e access is determ i ned to be not val i d by the coprocessor, it should st i l l assert DSACKx to the main processor and s i g nal a protocol violation w hen the main processor next reads the response CIA. This p rotocol ensures that an access to one of the coprocessor i nterface reg i sters w i l l never halt the main processor by not having DSACKx asserted by the coprocessor. Coprocessor detected protocol violations can be s i g nal led to the main processor with the take m id-i nstruct ion except ion p r i m i t ive encoded with the coprocessor protocol violation except ion vector n u m ber 1 3 to mainta i n consi stency with main processor detected protocol violations. When the main procssor reads t h i s primit ive, it w i l l p ro ceed as descri bed in 8.6.1 6.2 TAKE M I D-INSTRUCTION EXCEPTION. If no mod i f ications are made to the stack frame w i t h i n the exception handler, the M C68020 w i l l ret u rn from the except ion handler after an RTE instruction and read the response C I R. A l l M otorola M68000 coprocessors s i g nal protocol violations u s i n g the take m id i nstruction exception p r i m i t ive with the coprocessor protocol violation exception vector n u m ber. 8.8.1 .2 COPROCESSOR DETECTED I LLEGAL COMMAND OR CON DITION WO RDS. I I legal coprocessor command or cond ition words are val ues written to the command C I R or cond ition C I R res pectively that are n o t recog nized b y t h e coprocessor. If a value w rit ten to either of these reg i sters i s not val id, the coprocessor should pl ace the take pre i nstruction except ion prm i m it ive in the response C I R. When it receives t h i s primit ive, the main processor w i l l proceed as described in 8.6.1 6.1 TAKE PREINSTRUCTI ON EXCEp TION. If no mod if ications are made to the main processor stack frame w i t h i n the excep t ion hand ler, an RTE i nstruction w i l l cause the MC68020 to ret u rn to re- i n i t iate the i n struct ion d u r i n g which the take pre-i nstruct ion exception primit ive was received. The coprocessor des ig ner should ensure that the state of the coprocessor is not u n recoverably altered by an i l legal command or cond ition except ion if emu lat ion of the u n recogn ized command or con d i t ion word i s to be supported . A l l M otorola M68000 coprocessors S i g na l i l legal command and condition words by ret u r n i n g the take p re- i nstruction exception p r i m i tive with the F l i ne emu lator exception vector nu mber 1 1 .

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8.8.1 .3 COP ROCESSO R DATA P ROCESSI NG EXC EPTIONS. Except ions rel ated to the i n ternal operat ion of a coprocessor are c l assified as data process i n g re lated exceptions. These except ions are analogous to the d ividebyzero exception defi ned by M68000 m i croprocessors and should be s i g nal led to the main processor u s i n g one of the t h ree "Take Exception" primit ives conta i n i ng an appropriate exception vector nu mber. Which of t hese t h ree primit ives is u sed to s i g n a l the exception is generally determ i ned by the poi n t in the i nstruct ion operat ion where the main processor should continue the prog ram flow after except ion processi n g . These considerat ions are d i scu ssed in 8.6. 1 6 Except ion Processing Request Primitives. 8.8. 1 .4 COPROCESSOR SYSTEM RELATED EXC EPTIONS. System related exceptions detected by a D M A coprocessor i nc l ude t hose associ ated with bus activity, and any other except ions generated external to the coprocessor. These externa l ly generated ex cept ions could i nclude nonbus cycle associated events (l i ke i nterru pts) detected by the coprocessor. The actions taken by the coprocessor and the main processor depend on the type of exception encou ntered and are thus not genera l . W h e n an address o r bus error is detected b y a D M A coprocessor, a n y i nformat ion necessary for the main processor exception hand l i ng routi nes should be recorded in system access ible reg isters by the coprocessor. The coprocessor should p l ace one of the th ree "Take Except ion" primit ives encoded with an appropriate except ion vector number in the res ponse CIR. Which of the three primit ives is u sed depends upon the po i n t i n the coprocessor i nstruction at which the exception was detected , and the point i n the i nstruction execution where the main processor should continue the program flow after except ion process i n g . 8.8.1 .5 FORMAT E R R O R . Format errors are t h e only coprocessor detected exceptions t hat are not sig nal led to the main processor with one of the three "Take Except ion" cop rocessor response p r i m i t ives. When the main processor writes a format word to the restore C I R d u ri n g the execution of a cp RESTO RE i nstruction, the coprocessor decodes t h i s word to determ ine if it is val i d (see 8.3.3.2 COP ROCESSO R CONTEXT RESTO R E). I f t h e format word i s not va l i d , the coprocessor w i l l p lace the i nva l i d format code i n the restore C I R. When the main processor reads the i nval i d format code, it w i l l f i rst abort the coprocessor i nstruction by writing a $0001 to the control C I R. The main processor then proceeds with exception process i n g using a four word pre i nstruction stack f rame and the format error except ion vector number 1 4. Thus, if the stack f rame is not mod ified by the exception handler, the MC68020 w i l l restart the cp RESTORE i nstruction after an RTE is execu ted to exit the hand ler. I f the coprocessor retu rns the i nva l i d format code when the main processor reads the save CI R to i n i t iate a cpSAVE instruction the main pro cessor w i l l proceed w i t h format error except ion proceSSi ng as outli ned above for the cpRESTO RE i n struction. 8.8.2 Main Processor Detected Exceptions A n u m ber of except ions re lated to coprocessor i n struction execution are not d i rect ly perceptible to the coprocessor, but can be detected and serviced by the main processor. These except ions can be re lated to the execution of coprocessor res ponse primitives, com m u n i cat ion across the M68000 coprocessor i nterface, or the completion of cond i t i onal coprocessor i n struct ions by the main processor.

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8.8.2.1 P ROTOCOL VIOLATIO NS. The main p rocessor detects a p rotocol violation when it reads a primit ive from the response CIR that i s not a va l i d primit ive encod i ng. The pro tocol violations that can be generated by the MC68020 in response to the primit ives defi ned for the M68000 coprocessor i nterface are summarized in Table 86. When the M C68020 detects a p rotocol violation it does not automatica l ly notify the coprocessor of the res u l t i n g exception processing by wri t i n g to the control C I R. The ex cept ion hand l i ng rout i n e may, however, use the MOVES instruction to re-read the response C I R and thus determ ine the pri m i t ive that caused the M C68020 to i n i t iate pro tocol violation except ion process i n g . The main p rocessor i n i t i ates exception processing u s i n g the m i d-i nstruction stack frame (see F i g u re 8-43) and the coprocessor protocol violat ion except i o n vector n u m ber 1 3. If the stack frame is not mod ified w i t h i n the excep tion hand ler, the main processor w i l l ret u rn and read the res ponse C I R fo l low i n g the ex ecution of an RTE i nstruction in the exception hand ler. Th i s protocol al lows extensions to the M68000 coprocessor i nterface to be emu lated i n software by a main processor that does not provide hardware support for these extensions. Thus, the protocol violation is t ransparent to the coprocessor if the p r i m i t ive execution can be emu lated i n software by the main processor. 8.8.2.2 FL l N E EMU LATOR EXC EPTIONS. The F-l i n e emulator except ions detected by the MC68020 are either exp l icitly or i m p l icitly re lated to the encod i ngs of F-l i ne operat ion words encountered in the i nstruct ion stream. I f the main processor determ i nes the F- l i ne operat ion word is not a legal encod i n g , i t w i l l i n itiate F-l i ne emu lator exception process i ng. Any F- l i ne operat ion word with bits [8-6] = 1 1 0 or 1 1 1 cau ses the MC68020 to i n i t iate exception processing without any com m u n i cation be ing i n it iated with the coprocessor for that i nstruct ion. A l so, an operation word with bits [8-6] = 000-101 that does not map to one of the legal coprocessor i nst ruct ion encod i ngs in APPENDIX B I NSTRUCTION SET, cau ses the M C68020 to i n i t iate F- l i ne emulator exception processing. If the F- l i ne emu lator exception is generated as a resu l t of one of these two situations, the main pro cessor w i l l not w rite to the control C I R prior to i n itiating exception process i ng. F-l i ne except ions can also occ ur if the operat ions requested by a coprocessor response primit ive are not com pat ible w i t h the effective address type encoded in bits [5-0] of the coprocessor instruction operat ion word. The F-l i ne emu lator exceptions that can result from the use of the M68000 coprocessor response primit ives are sum marized i n Table 8-6. If the exception i s cau sed by the rece ipt of a primit ive, the coprocessor i nstruction i n progress i s aborted by the main p rocessor writing a $0001 t o the control C I R prior to F-l i ne emu lator exception process ing. When the main p rocessor i n i t iates F-l i ne emu lator exception process i n g , i t uses a four word pre-i nstruction exception stack frame (see F i g u re 8-4 1 ) and the F- l i ne emu lator ex cept ion vector number 1 1 . Thus, if the stack frame is not modif ied w i t h i n the exception hand ler, the main processor w i l l attem pt to restart the i nstruction that caused the excep t ion after an RTE is executed. Ge neral ly, i f the cause of the F- l i ne exception can be emu lated in software, the handler w i l l reflect the results of the emu lation in the programmer's model and in the status reg i ster field of the saved stack frame. The exception handler w i l l adj ust the program

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Table 86. Exceptions Related to Primitive Processing

Busy NULL Supervisory Check* Other: Privilege Violation if "S" Bit = O Transfer Operation Word * Transfer from I nstruction Strea m * Protocol: If Length Field i s O d d IZero Length Legal( Evaluate and Transfer Effective Address Protocol: If Used with Conditional Instruction F-Line: If EA in Op-Word is NOT Control Alterable Evaluate Effective Address and Transfer Data Protocol : 1 . If Used with Conditional Instructions 2. Length is Not 1, 2, or 4 and EA = Register Direct 3. If EA= Immediate and Length Odd and Greater Than 1 4. Attempt to Write to Non-Alterable Address Even if Address Declared Legal in Primitive F-Line: Valid EA Field Does Not Match EA in Op-Word Write to Previously Evaluated Effective Address Protocol: If Used with Conditional I nstruction Take Address and Transfer Data * Transfer To/ From Top-of-Stack* Protocol: Length Field Other Than 1, 2 , or 4 Transfer To/From Main Processor Register* Transfer To/From Main Processor Control Register Protocol: Invalid Control Register Select Code Transfer Multiple Main Processor Registers* Transfer Multiple Coprocessor Registers Protocol: 1 If Used with Conditional I nstructions 2. Odd Length Value F-Line 1 EA Not Control Alterable or IAnl + for CP to Memory Transfer 2. EA Not Control Alterable or - IAnl for Memory to CP Transfer Transfer Status and/ or ScanPC Protocol: If Used with Conditional Instruction Other: 1 Trace - Trace Made Pending If M C68020 in "Trace on Change of Flow" Mode and DR = l 2. Address Error - If Odd Value Written to ScanPC Take Pre-Instruction, Mid- I nstruction, or Post-I nstruction Exception Exception Depends on Vector Supplied in Primitive * Use of thiS primitive with CA 0 Will cause protocol violation on conditional Instructions. Abbreviations: EA = Effective Address CP = Coprocessor
=

Primitive

Protocol

F-Line

Other
X

X X X X

X X

X X X

counter field of the saved stack frame to point to the next i nstruction operat ion word and execute the RTE i nstruction. The M C68020 w i l l then proceed with the execution of the i n struction follow i n g the i nstruct ion that was e m u l ated. 8.8.2.3 PRIVILEGE VIOLATIONS. Privi lege violations can res u l t from the use of the c pSAV E and cpRESTO R E i nstructions as well as from the use of the su pervisor check coprocessor response primit ive. The main processor w i l l i n i t iate privilege violation

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except ion process i n g if it encou nters either the cpSAVE or cpRESTO RE i nstruction when i t is in the user state (S = 0 in status reg i ster). The main processor w i l l i n i t iate t h i s excep t i on process i n g prior to any com m u n i cat ion with the coprocessor associated w i t h the cpSAVE or cpRESTO R E i nstructions. I f the main processor is in the u ser state w h i l e executing a coprocessor i nstruction when i t reads the su pervisor check primit ive, it w i l l f i rst abort the coprocessor i nstruction i n progress by writing a $0001 t o the control C I R. The main processor w i l l then proceed with privi lege violation exception process ing. If a privi lege violation occu rs, the main processor i n it i ates except ion processi n g u s i n g a four word pre-i nstruct ion stack frame (see Figure 8-4 1 ) and the privi lege violation excep tion vector nu mber 8. Thus, if the stack frame is not mod i fied with i n the exception hand ler, the main processor w i l l attempt to restart the i n struction during which the ex cept ion occu rred after an RTE is executed to exit the hand ler. 8.8.2.4 cpTRAPcc I NSTRUCTION TRAPS. The main processor may i n i t i ate trap exception processing d u ri n g the execution of the cpTRAPcc i nstruction. If the coprocessor ret u rns the TRU E cond ition i n d icator to the main processor with a n u l l primit ive, the main pro cessor w i l l i n it i ate trap exception process i ng. The main processor w i l l use a six word post- i nstruction exception stack frame (see Fig ure 8-45) and the trap exception vector number 7. The sca n PC field of t h i s stack frame w i l l conta i n the address of the i nstruction following the c pTRAPcc i nstruction. The process i n g associated with the cpTRAPcc i n struction can then proceed and the exception handler can locate any i m med iate operand words encoded in the c pTRAPcc i nstruction using the i n format ion contai ned i n the s i x word stack frame. If the stack frame i s n o t mod i f ied w i t h i n the exception hand ler, the main processor w i l l proceed with the i nstruction following the cpTRAPcc i nstruction after an RTE i s executed to exit the handler. 8.8.2.5 TRACE EXCEPTIONS. The M C68020 supports two modes of i nstruction trac ing which are d i scussed i n 6.3.9 Tracing. In the t race on i nstruction execution mode, the M C68020 takes a trace exception after the completion of each i nstruction. I n the trace on change of f low mode, the M C68020 takes a trace exception after each i nstruction that a l ters the status reg ister or cau ses the program cou nter to be u pdated in a non sequential man ner. The protocol u sed to execute coprocessor cpSAVE, cpRESTO RE, or cond itional category i nstructions does not change when a trace exception is pend i n g in the main processor. The main processor w i l l proceed with a pen d i ng trace on i nstruction execution exception after com pleting the execution of that i nstruction. If the main processor i s in trace on change of f l ow mode, it w i l l take a trace except ion after the i nstruction execu t i on i f the i nstruction caused the program counter to be u pdated i n a non-seq uent i a l fashion, for example a branch was taken. The cond itions on which the main processor w i l l termi nate com mun ication with the coprocessor d u ri n g the execution of a cpGEN i nstruction and proceed with the next i n struction are altered when the main processor is i n a trace mode. When a trace except ion i s pen d i ng, the main processor w i l l not take the t race exception until the coprocessor i n d icates that a l l processing associ ated with a cpG EN i nstruction has comp leted.

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I f a trace except ion is not pend i n g during a general category i nstruction, the main pro cessor w i l l term i nate commun ication with the coprocessor after read i ng any primit ive with CA = O. This protocol a l lows the coprocessor to com plete a cpGEN i nstruction con c u rrently with the i nstruction execution of the main processor. When a trace exception is pend i n g , however, the main processor must i n s u re that a l l process ing associ ated w i th c pG EN i nstruct ion has been comp leted before the trace except ion i s taken. U nder these c i rcu mstances, the main processor w i l l continue to read the response C I R and service the primitives received u n t i l it receives ei ther a n u l l , CA = 0, PF = 1 primit ive or after ex ception processing cau sed by a take post-i nstruction exception primit ive. The coprocessor should ret u rn the n u l l , CA = 0 primitive with PF = 0 w h i l e it is com plet i ng the execution of the c pG EN i nstruction. The main processor may service pending i nterrupts between reads of the res ponse CIR i f IA = 1 i n these n u l l, CA = 0 primit ives (see Table 8-3). This protocol i n s u res that a t race except ion w i l l not be taken u n t i l a l l processing associ ated with a c pG EN i n struction has been completed.

If T1 1T0 = 01 in the MC68020 status reg i ster (trace on change of f l ow) when a general category i nstruction is i n it i ated, a trace except ion w i l l be taken after the i nstruction only when the transfer status reg ister and scan PC primit ive is issued with DR = 1 duri ng the execution of that i nstruct ion. If an i nstruction follow i n g the cpGEN i nstruction does cause a change of flow, the coprocessor may be executing the previous cpGEN i nstruc t ion concurrently when the main processor beg i n s execution of the trace exception hand ler. A cpSAVE i n struct ion used w i t h i n the trace on change of flow exception handler could thus suspend the execution of a concu rrently operat ing cpGEN i nstruction. 8.8.2.6 I NTERRU PTS. I nterrupt processing by the main processor can occu r at any i n struction boundary and is d i scussed in 6.3. 1 0 Interrupts. I nterrupts may also be serviced during the execution of a general or cond it ional category i nstruction u nder either of two condit ions. If the main processor reads a n u l l primit ive with CA = 1 and IA = 1 the main processor will service any pend i n g i nterrupts prior to reading the response CIR. Likew ise, if a trace exception i s pend i n g d u ri n g c pG E N i nstruction execution and the main pro cessor reads a n u l l p r i m i t ive with CA = 0, I A = 1 , and PF = 0 (see 8.8.2.5 TRACE EXCEp TIONS) the main processor w i l l service pend ing i nterrupts prior to re-read i n g the response C I R . The MC68020 uses t h e t e n word m id-instruction stack frame w hen i t services i nterrupts d u r i n g the execution of a general or cond i t ional category coprocessor i nstruction. The use of t h i s stack frame a l lows the main processor to perform all necessary processing and then ret urn to read the res ponse C I R and thus cont i n ue the coprocessor i nstruction d u r i n g which the i nterrupt except ion was taken. The MC68020 w i l l a l so service i nterrupts if i t reads the not ready format word from the save CIR during a cpSAVE i nstruction. The MC68020 uses the normal fou r word pre i nstruction stack frame when it services i nterrupts after reading the not ready format word. Thus, the processor can service any pen d i n g i nterrupts and execute an RTE to ret urn and re- i n i t i ate the cpSAVE i nstruction by read i n g the save CIR. 8.8.2.7 ADDRESS AND BUS ERRO RS. Coprocessor i nstruction related bus faults can occur during main processor bus cycles to CPU space to com mun icate with a

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coprocessor or d u ri n g memory cycles run as part of the coprocessor i nstruction execu t i on. If a bus error occurs d u r i n g the coprocessor i nterface reg i ster access that is used to initiate a coprocessor i nstruct ion, the main processor assumes that the coprocessor is not present i n the system and takes an F-line emu lator exception as descri bed i n 8_8_2_2 F-Li N E E M U LATOR EXCEPTI ONS_ Thus an F-l i ne emulator except ion w i l l be taken if a bus error occu rs d u ri n g the i n i t i a l access to the command, cond i t ion, restore, or save C I R that w a s made to i n i t iate a genera l , condit ional, context restore, or context save i nstruc tion respect ively. If a bus error occu rs on any other coprocessor access or on a memory access made d u ri n g the execution of a coprocessor i nstruction, the main processor pro ceed s with bus error except ion process i n g as descri bed i n 6.3.3. Bus Error. After the ex ception handler has corrected the cause of the bus error, the main processor can ret urn to the point in the coprocessor i n struction at which the fault occu rred. An address error w i l l occur if the MC68020 attempts to prefetch an i n struction from an odd address. This can occ u r if the calcu lated dest i nation address of a cpBcc or cpDBcc i n struct ion i s odd, or if an odd va l ue is transferred to the scan PC with the transfer status reg i ster and scanPC response primit ive. If an add ress error occurs, the MC68020 pro ceeds with exception process i n g as desc ribed in 6.3.2 Address Error. 8.8.2.8 MAIN PROCESSOR DETECTED FORMAT E R RO RS. The MC68020 can detect a format error d u ri n g the execution of a cpSAVE or cpRESTO RE i nstruction if the length field of a va l i d format word i s not a m u l t i ple of four bytes in length. If the MC68020 reads a format word with an i nval i d length field from the save C I R during the cpSAVE i n struc t i on, it w i l l abort the coprocessor instruction by writing a $0001 to the control C I R and i n it iate format error except ion processing. I f the MC68020 reads a format word with an i n va l i d length field from the effective address specif ied in the cp RESTORE i nstruction, the MC68020 w i l l write that format word to the coprocessor restore CIR and then read the coprocessor res ponse from the restore C I R. The M C68020 w i l l then abort the cpRESTORE i nstruct ion by writing a $0001 to the control CIR and i n it iate format error ex cept ion process i n g . T h e M C68020 uses the f o u r word pre-i nstruction stack frame a n d t h e format error vector number 1 4 when it i n i t i ates format error except ion processi ng. Thus, if the stack frame is not mod ified w i t h i n the exception hand ler, the main processor w i l l attempt to restart the i nstruction d u r i n g which the except ion occu rred after an RTE i s executed to exit the hand ler. 8.8.3 Coprocessor Reset When a system (hardware) reset occurs, the coprocessor should be reset and i n itial ized appropriately. At the d i scretion of the system desig ner, there may be a d i sti nction made between an ent i re system reset and the execut ion of the RESET i n struction by the main processor. In keeping with the function of the RESET i nstruct ion, it is genera l ly desi rable that the i nternal state of a coprocessor is only affected by an external system reset and not by the RESET i nstruction. This convent ion is des i rable s i nce the coprocessor is view ed as an extension to the main processor progra m m i n g model, and thus an extension to the i nternal state of the M C68020.

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8.9 COP ROCESSO R I N STRUCTION FORMAT S U M MARY A sum mary of the coprocessor i nstruction formats is p resented in F i g u re 8-46. 8.1 0 COP ROCESSO R RESPONSE PRIM ITIVE FORMAT S U M MARY The M68000 coprocessor response primit ive formats a re i l l ustrated in APPENDIX C I N STRUCTION FORMAT S U M MARY. A n y res ponse pri m i t ive w i t h b i t s [1 3-8] = $00 or $3F w i l l always cause a protocol violation. Response primit ives with bits [1 3-8] = $O B, $ 1 8-$1 B, $1 F, $28-$2B, and $38-$3E curre ntly cause a protocol, but are u ndefi ned and reserved for future use by M otorola.

15 1

14 1

13 1

cpGEN 4 5 3 2 8 7 6 Effective Address I I 0 I 0 I 0 I Coprocessor Command Optional Effective Address or Coprocessor Defined Extension Words 12 1 11 10 Cp- I D 9 cpBcc.W 3 2 4 5 10 9 8 7 6 Condition Selector 1 Cp-I D 0 0 Optional Coprocessor Defined Extension Words Displacement

15 1

15 1

14 1

13 1

12 1

11

I 1 I

14

13 1

12 1

11

cpBcc. L 2 3 4 5 8 7 6 9 10 Condition Selector Cp-ID I 0 I 1 I 1 I Optional Coprocessor Defined Extension Words Displacement - High Displacement - Low

15
1

14 1

13 1

12
1

10 Cp- I D 1 Reservedl

11

cpScc 8 7 0 I o

6 1

Optional Coprocessor Defined Extension Words Optional E f fective Address Extension Words

I I

3
Effective

A dd ress

Cond,tlon Selector

10-5

Wordsl

15 1

14 1

I 1 I

13

12 1

cpDBcc 3 10 9 8 7 6 5 4 o Cp-ID I 0 I 0 I 1 I 0 I o I 1 I Register I Condition Selector I Reservedl I Optional Coprocessor Defined Extension Words Displacement 11

Figure 8-46. Coprocessor Instruction Formats (Sheet 1 of 2)

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15 1

14 1

13 1

12 1

cpTRAPcc 6 4 o 3 9 5 8 7 10 1 I 1 0 I 1 Cp- ID Opmode 1 I I 0 Condition Selector I Reserved! I Optional Coprocessor Defined Extension Words Optional Word or Long Word Operand
11

15

14

13

12

11

SAVE 3 4 5 9 7 10 8 Effective Address Cp- I D Effective Address Extension Words 10-5 Words! RESTORE 8

15

14

13

12

11

10

Cp- I D Effective Address Effective Address Extension Words 10-5 Words!

Figure 846. Coprocessor I nstruction Formats (Sheet 2 of 2)

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S ECTI ON 9 I NSTRUCTION EXECUTION T I M I N G

This sect ion describes the i nstruction execut ion ti mes o f the MC68020 i n terms o f exter nal clock cyc les. 9.1 TI M I N G ESTI MATION FACTO RS The advanced architectu re of the M C68020 makes exact i nstruct ion t i m i n g calculations d ifficult due to t he effects of: 1) A n On-C h i p I n st ruct ion Cache and I nstruction Prefetch, 2) Operand M i sa l i gn ment, and 3) I nstruction Execut ion Overlap. These factors make M C68020 i nstruct ion set t i m i ng d ifficult to calcu late on a s i n g l e i n struction bas i s s i nce i nstruct ions vary i n execution t i me from one context to another. A detai led explanation of each of these factors fol l ows. 9.1 .1 Instruction Cache and Prefetch The on-c h i p cache of the M C68020 is an i nstruct ion-only cache. Its pu rpose is to i ncrease execution effi ciency by provid i ng a q u i ck-store for i nstruct ions. I nstruct ion prefetches t hat hit in the cache w i l l occur with no delay in i nstruction execu tion. I nstruction prefetches t hat m i ss in the cache w i l l cause an external memory cyc le to be performed, which may overlap with i nternal i nstruction execution. Thus, w h i le the execut ion unit of the m icroprocessor i s busy, the bus control ler prefetches the next i n struction from external memory. Both cases are i l l u strated i n later examples. When prefetching i nstruct ions from external memory, the m icroprocessor w i l l ut i l ize long word read cycl es. When the read is a l i gned on a long word address boundary, the processor reads two words, which may load two i nstructions at once, or two words of a m u l t i-word i nstruction. The su bseq uent i nstruct ion prefetch w i l l find the second word i s a l ready avai lable a n d there i s no need to r u n an external bus cyc le (read). The M C68020 always prefetches long words. When an i nstruction prefetch fal l s on an odd word boundary (e.g . , due to a branch to an odd word l ocat ion), the M C68020 w i l l read the even word associ ated with the long word base address at the same t i me as (32-bit memory) or before (8- or 1 6-bit memory) the odd word i s read. When an i nstruct ion prefetch fal l s on an even word boundary (as would be the normal case), the M C68020 reads both words at the long word address, thus effect ively prefetch i n g the next two words.

9-1

9.1 .2 Operand Misalignment Another significant factor affec t i n g i nstruction t i m i n g is operand m is a l i g nment. Operand misalig nment has i m pact on performance w hen the microprocessor is read i ng or writing external memory. I n this case the add ress of a word operand falls across a long word boundary or a long word operand falls on a byte or word add ress w h i c h is not a long word boundary. W h i l e the M C68020 w i l l automat ically handle a l l occurrences of operand m isal i g n ment, i t must u se m u l t i ple bus cycles to com plete such transfers. 9.1 .3 Concurrency The M C68020 al l ows concu rrency to take p lace when exec u t i n g i nst ruct i ons. The main e lements part i c i pating i n t h i s concu rrency are the bus controller and the seq uencer. The bus contro l ler is responsible for a l l bus activity. The sequencer controls the bus con t ro l ler, i nstruction execution, and i nternal processor operat ion, such as calcu lation of ef fect ive add resses and setting of condition codes. The sequencer is responsible for i n itiating i nstruction prefetc hes, decod i ng and va l idating incoming i nstructions i n the p i pe. The bus contro l ler and seq uencer can operate on a n i nstruction concu rrent ly. The bus controller can perform a read or write w h i l e the seq uencer controls an effective add ress calculation or sets the condition codes. The seq uencer may also request a bus cyc le that the bus control ler can not i m med i ately perform. I n t h i s case the bus cycle is q ueued and the bus control ler runs the cycle when the c u rrent cycle is complete. Concu rrency of operat ion between the seq uencer and bus control ler introd uces ambigu ity into the calculation of i nstruction t i m i ng due to potenti a l overlap of i nstruction execut ion . 9.1 .4 Overlap Overlap is the t i me, measured in c locks, when two i nstructions execute s i m u ltaneously. Overlap i s measu red as the t i me that an instruction i s execu t i n g concu rrent to the previous instruction. In Figure 91 , i nstructions A and B execu te s i m u ltaneously and the overlapped port ion of instruction B i s absorbed in the i nstruction execution t i me of A (the previous i nstruct ion). The overlap t i me is deducted from the execut ion t i me of instruction B. Simi larly, there is a n overlap period between i nstruction B and i nstruction C, w h i c h red u ces the attri buted execution t i me f o r C .

- - - - Instruction A -------I

- - - - lnstruction B ------i

- - - - I nstruction C -------l Overlap

Overlap

Figure 91 . Simultaneous Instruction Execution

9-2

The execution t i me attributed to i nstructions A, B, and C (after consideri ng the overlap) is depi cted i n F i g u re 92. I---
nstruction A ------;

I---- Instruction B -----i

-- Instructlon C --...,

Overlap Period (Absorbed by Instruction AI

Overlap Period (Absorbed by Instruction BI

Figure 92. I nstruction Execution for Instruction Timing Purposes It is poss ible t hat the execution t i me of an i nstruction w i l l be absorbed by the overlap with a previous i nstruction for a net execution t i me of zero c locks. 9.1 .5 Instruction Stream Timing Examples A progra m m i n g exam ple al l ows a more detai l ed exam i nation of these effects. The effect of i nstruction execution overlap on i nstruction t i m i n g is i l l u strated by the fol low i n g ex ample i nstruction stream: Instruction # 1 ) MOVE.L #2) ADD.L #3) MOVE.L #4) ADD.L D4,(A1 ) + D4, D5 (A1), - (A2) D5, D6

For the f i rst example, the assu m pt ions are: 1) The data bus is 32 bits, 2) The fi rst i nstruction i s prefetched from an ODD word address, 3) Memory access with no wait states, and 4) The i nstruction cache i s d i sabled. For this example, the i nstruction stream i s positioned i n 32bit memory as:

Address

n n+4 n+8

. . . A D D #2 ADD #4

M OV E #1 MOVE #3 . . .

93

F i g u re 9-3 shows processor activity on the f i rst exam ple i nstruct ion stream. It shows the act ivity of the external bus, and bus control ler, the sequencer, and the attributed i n struc tion execution t i me.

Clock

10

11

12

13
'----

14

15

17

Bus Activity ( Prefetch Bus Controller Sequencer Instruction Execution Time Clock Count
1-----

X _w___...J ,,- _ rite X

_ _

R_ d_ X ea -, _

Prefetch

---, Write---' ,.,---

(61 ------ir--- 191 -------111- 1 1, -1 LEGEND: #11 MDVE.L 121 ADD.L 131 MOVE.L 141 ADD.L D4,(All+ 04,D5 (A11,- (A21 D5,D6

_ C=:J _ C:=J

Figure 9-3. Processor Activity Example 1

For the f i rst three c l ocks of this example, the bus controller and seq uencer are both per form i ng tasks associated with the MOVE #1 i nstruct ion. The next th ree c locks (clocks four, five, and six) demonstrate i nstruction overlap. The bus controller is performing a write to memory as part of the MOVE #1 i nstruction. The sequencer, on the other hand, i s perform i n g the ADD # 2 i nstruction f o r t w o clocks (clocks f o u r a n d five) a n d beg i n n i n g source effective address (EA) calcu l at ions for t h e M O V E #3 i n struction. The b u s con troller act ivity completely overlaps the execution of the ADD #2 i nstruct ion, cau s i n g the ADD #2 attributed execution t ime to be zero clocks. This overlap a lso shortens the effec tive execution time of the M OV E #3 i nstruct ion by the one clock because the bus con troller completes the MOVE #1 write operation w h i l e the seq uencer beg i ns the MOVE #3 effective address calcu lation. The sequencer cont i n ues the source EA calculation for one more clock period (clock seven) w h i l e the bus controller beg i n s a read for MOVE #3. When counting i nstruction

9-4

execution t i me i n bus c locks, the MOVE #1 com pletes at the end of c lock 6 and the ex ecution of MOVE #3 beg i n s on c lock 7. Both the seq uencer and bus contro l ler continue with MOVE #3 until the end of clock 1 4, w hen the seq uencer beg i n s to perform A D D #4. T i m i n g for MOVE #3 cont i n ues, because the bus controller is st i l l perform i n g the write to the desti nation of MOVE #3. The bus ac t ivity for MOVE #3 com pletes at the end of clock 1 5. The effective execution t i m e for MOVE #3 is 9 clocks. The one c l ock cycle (c l ock 1 5) w hen the seq uencer is perform ing ADD #4 and the bus con t rol ler is writing to the dest i nation of MOVE #3 i s absorbed by the execution t i me of MOVE #3. This shortens the effective execut ion t i me of A D D #4 by one c lock, g iving it an attri buted execution t i m e of one clock. U s i n g the same i nstruct ion stream, the second example demonstrates the d i ffere nt ef fects of i nstruction execution overlap on i nstruction t i m i n g when the same i nstructions a re pos it ioned s l ightly d i fferently, in 32-bit memory:

Add ress

n n+4 n+8

MOVE #1 MOVE #3
. . .

ADD #2 ADD #4
. . .

The ass u m ptions for the second example i n F i g u re 9-4 are: 1) The data bus is 32 bits, 2) The fi rst i n st ruction i s p refetched from a n EVE N word address, 3) Memory access occ u r w i t h no wait states, and 4) The cache is d i sabled. W h i l e the total execution t i me of the i nstruction seg ment does not change in this exam ple, the i nd ividual i nstruction t i mes are s i g n i f i cantly d i fferent. This demonst rates that the effects of overlap are not o n ly i nstruction seq uence dependent, but a re also depen dent upon the a l i g nment of the i nstruction stream in memory. Both F i g u res 9-3 and 9-4 show i n st ruction execution without benefi t of the M C68020 i n struction cache. F i g u re 9-5 shows a t h i rd exam ple for the same i nstruction stream ex ecu t i n g in the cache. The assumptions for Example 3 are: 1 ) The data bus is 32 bits, 2) The cache is enabled and i nstructions are in the cache, and 3) Memory access occur with no wait states.

9-5

Clock

10

11

12

13

14

15

16

17

Bus Activity f------1(

Bus Controller

Write

X Prefetch X

Read

Write

X Prefetch )
Prefetch Bvtes n+ 1 2 Next Instruction
ADD.L D5,06

Sequencer Instruction Execution Time Clock Counter LEGE N D : 1 1 ) MOVE.L

D4, I A1 ) +

--

131 16) D4,D5

141

(3)

----1 D

#2) A D D . L

#3)

MOVE.L

IA1 ), - IA2)

#4) ADD . L

D5,D6

Figure 94. Processor Activity for Example 2

Clock

7
_ _

8
_ _

10

11

12

13

Bus Activity f------l(_ _ite _ >------< R ea d '- w r_ ___ ___ ___ _

_

...I '- _W_e_ -' X_ _ rit_ _)-----i _

Bus Controller Sequencer Instruction Execution Time Clock Counter

f------ (4) -----+-- (7) --------+-1 ( 1 ) --1

LEGEND: '1) MOVE.L D4,IA1 ) +

#2) A DD . L D4,D5

'3)

MOVE.L IA1 ) , - IA2)

#4) ADD . L D5,D6

Figure 95. Processor Activity for Example 3

9-6

N ote that once the i nstructions are i n the cache, the original locat ion in external memory is no longer a factor in t i m i ng. F i g u re 9-5 i l l u strates the benefits of the i nstruction cache. The total n u m ber of c lock cycles i s reduced from 16 to 1 2 c l ocks. S i nce the i nstructions are res ident i n the cache, the i nstruction prefetch activity does not req u i re the bus contro l ler to perform external bus cycles. Prefetch occu rs with no del ay, and su bseq uently, the bus control ler is idle more often. Such idle c lock cycles are u sefu l in M C68020 systems t hat requ i re wait states w hen ac ceSSing external memory. This is i l l ustrated by the fourth exam ple i n Figure 9-6 with the following ass u m pt i ons: 1 ) The data bus i s 32 bits, 2) The cache i s enabled and i nstructions are in t he cache, and 3) Memory access occu r with one wait state.

Clock Bus Activity Bus Controller Sequencer Instruction Execution Time Clock Count

10

11

12

13

14

-- Write -- X -. --

----

Read

X -- Write -- '" ---

1------ (5) -----+---- (8) -------

LEGEND: 11) MOVE.L D4.(All+ .. #21 AOO.L 04,05 CJ #31 MOVE.L (Al l , - (A21 .. #41 AOO.L 05,06

Figure 96. Processor Activity for Example 4

9-7

F i g u re 9-6 shows the same i nstruction stream executing with four c locks for every read and write. The i d le bus cyc les coincide with the wait states of the memory access, so the total execution t i me i s only 13 c l ocks. These exam ples demonstrate the com plexity of i nstruct ion t i m i n g calculat ion for the M C68020. I t i s i m possible to a n t i c i pate i nd ividual i nstruct ion t i m i n g as an absol ute n u m ber of c lock cyc les due to the dependency of overlap on the i n struction sequence and a l i g nment, as wel l as the n u mber of wait states in memory. Th i s can be seen by com pari ng i n d ividual and composite t i me for F i g u re 9-3 through 9-6. These i nstruction t i m i ngs are compared i n Table 9-1 , where t i m i ng varies for each i nstruction as the context varies.

Table 9-1 . Example Instruction Stream Execution Comparison

Instruction
#11 #2 ) #3 ) #41 MOVE. L AOO.L MOV E . L AOO.L

Example 2 Example 1 (Odd Alignment! (Even Alignment)

6
0

04,IAl I + 04,05 IAl I , - IA2 ) 05,06

9 1 16

4 3 6 3

Example 3 (Cache)
4
0

Example 4 (Cache With Wait States)

5
0

7 1 12

8
0

Total Clock Cycles

16

13

9.2 I N STRUCTION T I M I N G TAB L ES The i nstruction t i mes below i nclude the following ass u m ptions about the MC68020 system: 1) A l l operands are long word a l i g ned as i s the stack, 2) 32-bit data bus, and 3) No wait state memory (3 cyc le read/write). There are th ree values g iven for each i n struction and add ress i n g mode: 1) The best case (BC) which reflects the t i me ( i n clocks) when the i nstruction is in the cache and benef its from max i m u m overlap due to other i nstructions. 2) Cache-only-case (CC) when the i nstruction i s in the cache but has no overlap, and 3) Worst case (WC) when the i nstruction i s not in cache or the cache i s d isabled and there is no i nstruction overlap. The only i nstances for which the s ize of the operand has any effect are the i nstruct ions with i m med i ate operands. U n less s pecif ied otherwi se, i m mediate byte and word operands have ident i cal execution t i mes.

9-8

W i t h i n each set or column of i nstruction t i m i ng s are fou r sets of numbers, three of which are enclosed i n parentheses. The outer number is the total nu mber of c locks for the i n struction. The f i rst number i nside the parentheses is the n u mber of operand read cycles performed by the i nstruct ion. The second val ue i nside parent heses is the nu mber of i n struction accesses performed by the i nstruction, i nc l u d i n g a l l prefetches to keep the i n struction p i pe f i l led. The t h i rd value w i t h i n parent heses is the nu mber of write cyc les per formed by the instruction. One example from the i nstruction t i m i ng table is:

Total N u mber Of CIOCkS

N u mber of I nstruct ion Access Cyc les

I N u mber of Read CYCles --.J

N u mber of Write Cyc les

24

@//Q)

The total n u m ber of bus activity c locks for the above example i s derived i n the fol lowi n g way: (2 Reads * 3 Clocks/Read) + (3 I nstruction Accesses * 3 Clocks/Access) + (0 Writes * 3 ClockslWrite) = 1 5 Clocks of Bus Activity 24 Total C locks 1 5 C locks (Bus Activity) = 9 I nternal Clocks
-

The example u sed here was taken from a worst-case "fetch effect ive address" t i me. The add ressi n g mode was ([d 32 , B],I,d 32). The same add ressi n g mode under the best case en t ry is 1 7 (2/0/0). For the best case, there are no i nstruction accesses because the cache is enabled, and the seq uencer does not have to go to externa l memory for the inst ruct ion words. The f i rst tables deal exclus ively with fetc h i n g and calculating effective addresses and i m med i ate operands. The tables are arranged in t h i s manner because some i nstructions do not req u i re effective address calculation or fetch i ng. For example, the i nstruction CLR < ea > (found in the table u nder 9.2.1 1 Single Operand Instruction) only needs to have a calcu lated EA t i me added to its table entry because no fetch of an operand i s re q u i red. This i nstruction only writes to memory or a reg ister. Some i nstructions use s pecific addres s i n g modes which exc lude t i m i ng for calcu l ation or fetc h i n g of an operand. When t hese i nstances arise, they are footnoted to i n d i cate which other tables are needed in the t i m i n g calcu l at i on. The MOVE i nstruct ion t i m i n g tables i nclude all necessary t i m i ng for extension word fetch, address calcu lation, and operand fetch. The i nstruction t i m i ng tables are u sed to calcu l ate a best case and worst case bou nds for some target i nst ruct ion stream. Calcu lating exact t i m i n g from the t i m i ng tables i s im poss ible because the tables can not antici pate how the com bi nation of factors w i l l i n fl uence every particu l a r seq uence of i nst ruct ions. This is i l l ustrated by comparing the observed i nstruct ion t i m i n g from the prior four examples with i nstruction t i m i ng derived from the i nst ruct ion t i m i n g tables.

9-9

Table 9-2 shows the orig i nal instruction stream and the correspond i ng c lock t i m i n g from the a ppropriate t i m i ng tables for the best case (BC), cache o n ly case (CC), and worst case (WC). Table 92. Instruction Timings from Timing Tables
#11 #21 #31 #41 MOVE.L AOO . L MOVE. L AOO . L

Instruction

04,IA1 1 + 04,05 IAl I , - IA21 05,06

Best Case
4 0 6 0

Cache Case
4 2 7 2

Worst Case
6 3 9 3

Total

10

15

21

Table 9-3 s u m marizes t h e observed i nstruction t i m i ngs for t h e same i nstruction stream as executed accord i n g to the ass u m pt ions of the four exam ples. For each example, Table 93 shows which entry (BC/CC/WC) from the t i m i n g tables corresponds to the observed t i m i n g for each of the fou r i nst ruct ions. Some of the observed i nstruction t i m ings cannot be found in the t i m i n g tables and appear i n Table 9-3 w i t h i n parenthes i s in the most a ppropriate col u m n . These occur when i nstruction execution overlap dynamical l y a lters what wou l d otherwi se be a BC, CC, or WC t i ming. Table 93. Observed Instruction Timings

#11 #21 #31 #41

MOVE.L AOO. L MOVE. L AOO. L

Instruction

04, I A l I + 04,05 IA1 1 , - IA21 05,06

Example 1 Example 2 Example 3 Example 4 BC CC WC BC CC WC BC CC WC BC CC WC

0 111 1 1 61 6 4 9 6 1 161 3 3 0 III 4 7 1 1 21 0 0 1 1 31 151 181

Total

Com pari ng Tables 9-2 and 9-3 demonstrates t hat calculation of i nstruction t i m i ng can not be a simple looku p of o n ly BC or o n ly WC t i m i ngs. Even when the assumptions are known and f i xed, as in the fou r exam p les summarized i n Table 9-3, the m icroprocessor can somet i mes achieve best case t i m i n g s u nder worst case ass u m pt ions. Looking across the fou r examples in Table 9-3 for an i ndividual i nstruction, it is d i fficult to pred ict which t i m i ng table entry i s u sed, s i nce the i n f l uence of i nstruction overlap may or may not i m p rove the BC, WC, or CC t i m i ngs. When looking at the observed i nstruction t i m i ngs for one example, it i s also d ifficult to determ ine which com bination of BC/CC/wC t i m i ng is req u i red. J ust how the i nstruction stream w i l l fit and run with cache enabled, how i nstructions are posit ioned in memory, and the degree of i nstruction overlap are fac tors t hat are i m possible to be accounted for i n a l l combinations of the t i m i n g tab les. Although the t i m i n g tables can not accurately pred i ct the i nstruction t i m i ng that wou ld be observed when executing an i nstruction stream on the M C68020, the tables can be u sed to calcu l ate best case and worst case bounds for i nstruction t i m i n g . Absol ute i nstruction t i m i n g must be measu red by u s i n g the mic roprocessor itself, to execute the target i n struction stream.

9-1 0

9.2.1 Fetch Effective Address The fetch effective add ress table i n d i cates the number of c lock periods needed for the processor to calcu late and fetch the s pecif ied effective add ress. The total nu mber of c lock cyc les i s outside the parentheses, the number of read, prefetch, and w rite cyc les are g iven i nside the parentheses as (r/p/w). They are i n c l uded in the total c lock cyc le n u mber.

On An IAnl IAnl + - IAnl I d 1 6 ,Anl of I d 1 6 , PCI Ixxxl . W I xxxl . L # < data > . B # < data > .W # < data> . L Ids,An,Xnl or I dS , PC, Xnl Id 1 6 ,An,Xnl or Id 1 6 , PC,Xnl IBI Id 1 6 , BI Id32 , BI I[B].II I [ B l . I , d 1 61 I [ B l . I , d32 1 ( [ d 1 6 , B] . 1 J l [ d 1 6 , Bl . I , d 1 6 1 ( [ d 1 6 , B] . I , d32 1 ( [ d32 , B l . I I ( [ d32 , B l . I , d 1 6 1 ([d32 , B l . I ,d32 1
=

Address Mode

Best Case
3 4 3 3 3 3
o o o

o 10/0/01 o 10/0/01

Cache Case
4 4 5 5 4 4 2 2 4 7 7 7 9 13 12 14 14 14 16 16 lS 20 20
o 10/0/01 o 10/0/01

Worst Case
4 4 5 6 6 7 3 3 5 S 9 9 12 16 13 16 17 16 19 20 20 22 24
o 10/0/01 o 10/0/01

4 4 4 6 10 9 11 11 11 13 13 15 17 17

1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 10/0/01 10/0/01 10/0/01 1 1 / 0/01 1 1 / 0/01 1 1 10/01 1 1 /0/01 1 1 /0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0101 12/0101

1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 10/0/01 10/0/01 10/0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0101 12/0101 12/0101

1 1 /0/01 1 1 /0/01 1 1 /0101 1 1 / 1 101 1 1 / 1 101 1 1 / 1 101 10/ 1 101 10/ 1 /01 10/ 1 / 01 1 1 / 1 101 1 1 / 1 /01 1 1 / 1 /01 1 1 / 1 /01 11 /2/01 12/ 1 /01 12/ 1 101 12/2/01 12/ 1 101 12/2/01 12/2/01 12/2/01 12/2/01 12/3/01

B Base address; 0, An, PC, Xn, An + Xn, PC + Xn. Form does not affect timing. 1 I ndex; 0, Xn
=

NOTE:

Xn cannot be in B and I at the same time. Scaling and size of Xn does not affect timing.

9.2.2 Fetch Immediate Effective Address The fetch i mmed iate effective add ress table i n d i cates the n u mber of c lock periods need ed for the processor to fetch the i m med i ate sou rce operand, and calcu late and fetch the s pec ified dest i nation operand. The total n u m ber of c lock cyc les is outside the paren theses, the n u mber of read, prefetch, and w rite cyc les are g iven inside the parent heses as (r/p/w). They are i nc l uded in the total clock cyc le number.

9-1 1

# < data > .W,On # < data > . L,On # < data > .W,IAnl # < data > . L, IAnl # < data > .W,IAnl + # < data > . L,IAnl + # < data > .W, - IAnl # < data > .L, - IAnl # < data > .W,lbd,Anl # < data> . L, l bd,Anl # < data > .W,xxx.W # < data > . L,xxx.W # < data> .W,xxx.L # < data> . L,xxx . L # < data > .W,# < data > . B ,W # < data > .W,# < data> . B,W # < data > .W,# < data > . L # < data> .L,# < data > . L # < data > .W,ld8 ,An,Xnl or IdS , PC,Xnl # < data > . L , l d8 , An,Xnl or Id8 , PC,Xnl # < data > .W,ld 1 6 ,An,Xnl or Id 1 6 , PC,Xnl # < data> . L,ld 1 6 ,An,Xnl or Id 16 ,PC,Xnl # < data > .W,IBI # < data > . L, I B I # < data > .W,lbd,PCI # < data > . L, lbd,PCI # < data > .W,ld 1 6 ,BI # < data > . L,ld 1 6 , BI # < data> .W,ld32 , B I # < data> . L, l d 32 , B I # < data> W , ( [ Bl.Il # < data > . L, ( [ B ] . 1I # < data> W,([BJ.l.d 1 6 1 # < data> . L, I [ B J . l . d 1 6 1 # < data> .W,([BJ.l.d32 1 #< data > . L.Ild 16 , B] . I , d32 1 # < data > W , ( ( d 1 6 , B l . I l # < data> .L,([d 1 6 , B l . I l # < data > .W,((d 1 6 ,B]. I,d 16 ) # < data> . L.Ild 16 ,BJ.l.d 1 6) # < data > .W,((d32 , B] . 1 I # < data > . L,l[d 32 , Bl . I ) # < data> . W,I[d32 , B J , I , d 1 6 ) # < data > . L , ll d32 , BJ.l.d 1 6 1 # < data > .W,((d32 , B ] . I ,d 32 ) #< data > . L,((d32 , BL I , d32 1

Address Mode

Best Case
1 3 3 4 5
3

o 10/0/01

Cache Case
2 4 4 4 6 8 10/0/01 10/0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 / 0/01 1 1 / 0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 10/0/01 10/0/01 10/0/01 10/0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/0) 12/0/0)

Worst Case
3 5 4 7 7 9
6

1 4 5 4 5 4 5 10 11 6 7 10 11 9 10 11 12 11 12 11 12 13 14 15 16 17 18 17 18

4 3 4 3 4 3 4 1

10/0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 11 /0/01 1 1 /0/01 ( 1 /0/01 ( 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 10/0/01 10/0/01 10/0/01 10/0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01 12/0/01

7 5 7 5 7 6 8 4 6 6 8 9 11 9 11 9 11 15 17 11 13 15 17 14 16 16 18 16 18 16 18 18 20 20 22 22 24 22 24

8 7 10 7 10 10 12 6 8 8 10 11 13 12 15 12 14 19 21 15 17 19 21 16 18 19 21 20 22 19 21 22 24 23 25 25 27 27 29

10/ 1 / 01 10/ 1 /01 1 1 / 1 /01 1 1 / 1 /01 1 1 / 1 /01 1 1 / 1 /01 1 1 / 1 /01 1 1 / 1 /01 1 1 / 1 /01 1 1 /2/01 1 1 / 1 /01 1 1 /2/01 1 1 /2/01 1 1 /2/01 10/2/01 10/2/01 10/2/01 10/2/01 1 1 /2/01 1 1 /2/01 1 1 /2/01 1 1 /2/01 1 1 /2/01 1 1 /2/01 1 1 /3/01 1 1 /3/01 1 1 /2/01 1 1 /2/01 1 1 / 3/01 1 1 /3/01 12/2/01 12/2/01 12/2/01 12/2/01 12/3/01 12/3/01 12/2/01 12/2/01 12/3/01 12/3/01 12/3/01 12/3/0) 12/3/01 12/3/01 12/4/01 12/4/01

B = Base address; 0, An, PC, Xn, An+ Xn, PC + Xn. Form does not affect timing. I = I ndex 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn does not affect timing.

9-1 2

9.2.3 Calculate Effective Address The calc u l ate effective add ress table i n d icates the n u m ber of c l ock periods needed for the processor to calcu late the s pecif ied effect ive add ress. Fetch t i me is only i nc l uded for the f i rst level of i n d i rection on memory i n d i rect add ress i n g modes. The total n u m ber of c l ock cycles is outside the parentheses, the n u m ber of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are i ncl uded in the total c lock cyc le n u m ber.

On An IAnl IAnl + - IAnl I d 1 6 .Anl or Id 1 6 . PCI < data > .W < data > . L I d8 .An.Xnl or I d8 . PC .Xnl Id 16 .An.Xnl or I d 1 6 . PC.Xnl I BI I d1 6. B I I d32 . BI IIBI.II I [ BI . I . d 16 1 I [ B l . I . d32 1 l [ d 1 6. B l . I I I [ d 1 6 . B I. I . d 16 1 l [ d 1 6 . Bl . I . d32 1 l [ d32 . B I . I I l [ d32 . B I . I . d 1 6 1 l [ d32 . B l . I . d32 1
=

Address Mode

Best Case
o

o (010101

Cache Case
2 2 2 2 2 4 4 6 6 8 12 11 13 13 13 15 15 17 19 19
o 1010/01 o 10/0/01

Worst Case
2 2 2 3 3 5 5 7 7 10 15 12 15 16 15 18 19 19 21 24
o 10/0/01 o 10/0/01

2 2 2 2 2 1 1 3 3 5 9 8 10 10 10 12 12 14 16 16

10/0/01 1010lOJ (0/0/01 1010lOJ 1010lOJ 10/0/01 10/0/01 10/0/01 1010lOJ 10/0/01 10/0/01 1010lOJ 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01

1010lOJ 1010/01 (010101 10/0/01 10/0/01 10/0/01 10/0/01 10/0/01 1010lOJ 10/0/01 10/0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01

1010lOJ 10/0/01 1010/01 10/ 1 101 101 1 10J 10/ 1 101 10/ 1 IOJ 10/ 1 101 10/ 1 101 10/ 1 101 10/2/01 1 1 / 1 /01 1 1 / 1 /01 11 /2101 1 1 / 1 /01 1 1 /2/01 1 1 /2/01 1 1 /2/01 1 1 /2/01 1 1 /3/01

B Base address; O. An. PC. Xn. An + Xn. PC + Xn. Form does not affect timing. I
=

I ndex; O. Xn Xn cannot be in B and I at the same time. Scaling and size of Xn does not affect timing.

NOTE:

9.2.4 Ca lculate Immediate Effective Address The calcu late i m med iate effective add ress table i nd icates the nu mber of c l ock periods needed for the processor to fetch the i m med iate source operand and calcu late the s pec ified dest i nation effect ive address. Fetch time i s o n ly i nc l uded for the f i rst level of i n d i rection on memory i n d i rect add ressing modes. The total n u mber of clock cyc les is outside the parentheses, the nu mber of read, prefetch, and write cyc les a re g iven i nside the parentheses as (r/p/w). They are i ncl uded i n the total clock cyc le nu mber.

91 3

Address Mode
# < data > .W,Dn # < data > . L,Dn # < data > .W,IAnl # < data > . L, I An) # < data > .W,IAnl + # < data > . L, I Anl + # < data > .w,lbd.An) # < data > . L, l bd,Anl # < data > .W, lxxx) . W # < data > . L, lxxxl. W # < data > .W, lxxxl . L # < data > . L, l xxxl . L # < data > .W,ld8 ,An,Xn) or Id8 , PC,Xn) # < data> . L, l d8 ,An,Xnl or Id8 , PC,Xnl # < data > .W,ld 1 6 .An,Xnl or Id 1 6 , PC,Xnl # < data > L.ld 1 6 ,An,Xn) or Id 1 6 . PC,Xnl # < data > W , I B ) # < data > . L, I B ) # < data > .W,lbd,PCI # < data > . L , l bd, PC) # < data > .W, ld 1 6 , B) # < data > .L,ld 1 6 , B)1 # < data > .W, ld32 , B) # < data > . L, Id32 , BI # < data > .W,I[ B l , l I # < data > . L , I [ B l , l l # < data > W , I [ B l . I,d 16 ) # < data > . L, I [ B l , l , d 1 6 1 # < data > . W , ( [ B l . I,d32 ) # < data> L,I [ Bl . I,d 32 1 # < data > .w,([d 1 6 , Bl . I I # < data > .L,([d 1 6 , B l , l I #< data > .w,ld 1 6 , B l , l , d 1 6 1 : # < data > L,([d 1 6 , B l . I . d 1 6) # < data > ([d 1 6 , Bl . I , d 32 1 #< data > ( [ d 16 , Bl . l , d32 ) # < data > .W,I[d32 , Bl . lI # < data > . L, I [ d32 , B l . I I # < data > .W,I[d32 , Bl . I , d 1 6 ) # < data> . L, I [ d32 , Bl . l , d 1 6 1 # < data> .w,I[d32 , B l . l ,d32 1 # < data> 1.I[d 32 , B l . I , d 32 1
I=
=

Best Case

1 1010101 o 1010/01 1 1010101 2 (0/0/0) 3 10/0101 1 1010/01 3 10/0/01 1 1010/01 3 10/0/01 2 10/0/01 3 10/0/01 o 1010/01 2 10/0/01 3 10/0/01 4 (0/0/0) 3 10/0/01 4 10/0/01 9 10/0/01 10 10/0/01 5 1010/01 6 10/0/01 9 10/0/01 10 10/0/01 8 1 1 /0/01 9 1 1 /0/01 10 ( 1 /010) 1 1 1 1 /0101 10 1 1 /0/01 1 1 1 1 /0/01 10 1 1 /0/01 1 1 1 1 /0/01 1 2 1 1 /0/01 13 1 1 /0/01 12 1 1 /0/01 13 ( 1 /0/0) 14 1 1 /0/01 1 5 1 1 /0/01 16 ( 1 /0/0) 17 1 1 /0/01 16 ( 1 /0/0) 17 1 1 /0/0)

o 1010101

Cache Case
2 4 2 4 4 6 4 6 4 6 4 8 6 8 8 10 8 10 14 16 10 12 14 16 13 15 15 17 15 17 15 17 17 19 17 19 19 21 21 23 21 23 1010101 1010101 1010/01 1010/01 10/0/01 1010101 10/0/01 10/0/01 (0/0/0) 10/0/01 10/0/01 10/0/01 10/0/01 1010101 1010101 (0/010) 10/0101 (0/0/0) (0/0/0) 10/0/01 10/0/01 10/0/01 10/0/01 1010/01 1 1 /0101 1 1 /0/01 1 1 /0/01 1 1 /0101 1 1 /0/01 1 1 /0101 1 1 /0101 1 1 /0101 1 1 /0/01 1 1 /0/01 ( 1 /0/0) 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01 1 1 /0/01

Worst Case
3 5 3 5 5 7 5 8 5 8 6 10 8 10 10 12 10 12 18 20 13 15 18 20 15 17 18 20 19 21 18 20 21 23 22 24 22 24 24 26 24 29 10/ 1 101 10/ 1 101 10/ 1 101 10/ 1 /01 10/1 101 10/1 /01 10/1 101 (0/2/0) 10/ 1 /01 10/2/01 10/2/01 10/2/01 10/2/01 10/2/01 10/2/01 10/2/01 10/2/01 (0/2/0) 1013101 (0/3/0) 10/2/01 10/2/01 10/3/01 10/3/01 1 1 /2/01 1 1 /2/01 1 1 /2/01 1 1 /2/01 1 1 / 3/01 1 1 / 3/01 1 1 /2/01 1 1 /2/01 ( 1 /3/0) 1 1 /3/0) 1 1 /3/01 ( 1 /3/0) ( 1 /3/0) 1 1 /3/01 1 1 / 3/0) 1 1 / 3/01 1 1 / 3/01 1 1 / 3/01

B Base address; 0, An, PC, Xn, An + Xn, PC + Xn. Form does not affect timing. Index; 0, Xn

NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn does not affect timing.

9- 1 4

9.2.5 Jump Effective Address The j u m p effective add ress table i nd i cates the n u m ber of c l ock periods needed for the processor to calcu l ate and j u m p to the specif ied effective address. Fetch t i me is o n ly i n c l uded for t he f i rst level of i n d i rect ion on memory i n d i rect address i n g modes. The total n u m ber of c lock cycles i s outside the parentheses, the nu mber of read, prefetch, and w rite cycles are g iven i n s ide the parentheses as (r/p/w). They are i ncl uded in the total c l ock cycle n u m ber.

Address Mode

Best Case

Cache Case

Worst Case

B Base address; O. An. PC. Xn. An + Xn. PC + Xn. Form does not affect timing.
=

IAnl Id 16 .Anl Ixxxl .W Ixxxl . L I ds.An.Xnl or Ids.PC.Xnl I d 1 6 .An.Xnl or Id 1 6 . PC.Xnl IBI I B . d 1 61 I B . d32 1 I [ B ] . II I [ B ] . I . d 1 61 I [ B ] . I . d32 1 l[d 1 6 . B] . 1 1 ( [ d 1 6 . B] . I . d 1 6 1 ( [ d 16 . Bl . I . d32 1 ( [ d32 . B] . I I ( [ d32 . Bl , l . d 1 6 1 ( [ d32 . Bl . I . d32 1 Index ; O. Xn

o 1010101
1 1010/01 o 10/0101 o 1010/01 3 1010/01 3 1010/01 3 10/0/01 5 10/0/01 9 1010/01 S 1 1 /0101 10 1 1 /0/01 10 1 1 /0101 10 1 1 /0101 1 2 1 1 /0101 1 2 1 1 /0101 14 1 1 /0101 16 1 1 /0/01 16 1 1 /0101

2 4 2 2 6 6 6 S 12 11 13 13 13 15 15 17 19 19

1010101 1010101 10/0/01 10/0/01 1010/01 1010/01 10/0/01 10/0/01 1010/01 1 1 /0/01 1 1 /0/01 1 1 /0101 1 1 /0101 1 1 /0101 1 1 /0101 1 1 / 0101 1 1 /0101 1 1 /0101

2 4 2 2 6 6 6 S 12 11 14 14 14 17 17 19 21 23

1010101 1010101 10/0/01 1010101 1010/01 1010/01 10/0/01 101 1 101 101 1 101 1 1 / 1 /01 1 1 1 1 /01 1 1 1 1 /01 1 1 / 1 /01 1 1 1 1 /01 1 1 / 1 /01 1 1 /2/01 1 1 / 2/01 1 1 /3/01

NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn does not affect timing.

9.2.6 MOVE Instruction The MOVE i nstruction t i m i ng table ind icates the n u m ber of c lock periods needed for the processor to fetch, calcu late, and perform the MOVE or MOVEA with the spec if ied source and dest i nation effective addresses, i n c l u d i n g both levels of i n d i rect ion on memory i n d i rect address i n g modes. N o add it ional tables are needed to calcu late the total effective execut ion t i me for the MOVE or MOV EA i nstru ct ion. The total number of c lock cycles i s outside the parentheses, the number of read, prefetch, and wri te cyc les are g iven i n side the parent heses as (r/p/w). They are incl uded in the total c lock cyc le number.

9 1 5

BEST CASE
Source Address Mode Destination

An # < data> . B,W # < data> . L (An) (Anl + - (An) I d 16 .An) or (d 16 , PC) (xxx) . W Ixxx) . L I d8 ,An,Xn) o r I d8 , PC,Xnl ( d 1 6 .An,Xnl o r I d 16 , PC,Xnl IBI ( d 1 6, B I Id32 , B I I[B],II ( [ B l , I , d 1 61 I [ B l , I , d32 1 l [ d 1 6 , B] ' 1 I ( [ d 16 , B] , I , d 1 6 1 ( [ d 1 6 , Bl , I , d 32 1 ( [ d32 , B] , I 1 l [ d32 , B l , I , d 16 1 l [ d32 , B ] , I , d32 1

o (0/0/01
3 4 3 3 3 3 4 4 4 6 10 9 11 11 11 13 13 15 17 17 1 1 /0/01 ( 1 /0/0) ( 1 /0/0) ( 1 /0/0) ( 1 /0/0) ( 1 /0/01 ( 1 /0/0) ( 1 /0/01 ( 1 /0/01 1 1 /0/01 1 1 /0/01 12/0/01 12/0/01 (2/0/01 12/0/01 (2/0/01 12/0/01 12/0/01 (2/0/01 (2/0/01

o (0/0/0) o (0/0/0)
An

3 4 3 3 3 3 4 4 4 6 10 9 11 11 11 13 13 15 17 17

o (0/0/0) o (0/0/0) o (0/0/0)

On

(An)

(An) +

- (An)

(d 16 .An)

(xxx).W

(xxxl . L

( 1 /0/0) ( 1 /0/0) ( 1 /0/01 ( 1 /0/0) ( 1 /0/0) ( 1 /0/01 ( 1 /0/0) ( 1 /0/01 ( 1 /0/01 ( 1 /0/01 1 1 /0/01 (2/0/01 (2/0/01 12/0/01 12/0/01 (2/0/01 (2/0/01 12/0/01 (2/0/01 (2/0/01

3 3 3 6 7 6 6 6 6 7 7 7 9 13 12 14 14 14 16 16 18 20 20

(0/01 1 ) (0/01 1 ) (0/0/ 1 ) ( 1 /0/ 1 ) ( 1 /01 1 ) ( 1 /01 1 ) ( 1 /0/ 1 ) ( 1 /0/ 1 ) ( 1 10/ 1 ) ( 1 /01 1 ) ( 1 /01 1 1 1 1 /01 1 1 ( 1 /0/ 1 1 1 1 /0/ 1 1 (2/01 1 1 12/0/ 1 1 12/011 I (2/01 1 1 (2/01 1 1 (2/0/ 1 ) 12/01 1 1 12/01 1 1 (2/0/ 1 )

4 4 4 6 7 6 6 6 6 7 7 7 9 13 12 14 14 14 16 16 18 20 20

(0/0/ 1 ) (0/01 1 ) (0/01 1 ) ( 1 /01 1 ) ( 1 /0/ 1 ) ( 1 /01 1 ) 1 1 /01 1 ) 1 1 /0/ 1 ) ( 1 /0/ 1 ) 1 1 /01 1 ) ( 1 /0/ 1 1 1 1 /01 1 1 1 1 /011 I 1 1 /011 I 12/0/ 1 1 12/0/ 1 1 (2/01 1 1 (2/0/ 1 1 12/0/ 1 ) (2/01 1 1 (2/0/ 1 1 (2/01 1 1 (2/0/ 1 )

3 3 3 6 7 6 6 6 6 7 7 7 9 13 12 14 14 14 16 16 18 20 20

(0/0/ 1 ) (0/0/ 1 ) (0/01 1 1 ( 1 /0/ 1 ) 1 1 /0/ 1 1 ( 1 /0/ 1 ) ( 1 /0/ 1 ) ( 1 /01 1 ) 1 1 /01 1 ) ( 1 /0/ 1 ) 1 1 /0/ 1 ) 1 1 /01 1 1 1 1 /01 1 1 1 1 /01 1 1 12/01 1 1 (2/0/ 1 1 (2/0/ 1 1 (2/0/ 1 ) 12/01 1 1 12/0/ 1 1 12/0/ 1 1 (2/0/ 1 ) (2/0/ 1 1

3 3 3 6 7 6 6 6 6 7 7 7 9 13 12 14 14 14 16 16 18 20 20

10/01 1 ) (0/01 1 ) (0/01 1 ) ( 1 /0/ 1 ) ( 1 /01 1 ) ( 1 /01 1 1 ( 1 /01 1 1 ( 1 /0/ 1 ) 1 1 /01 1 1 ( 1 /01 1 ) 1 1 /01 1 1 ( 1 /0/ 1 ) ( 1 /01 1 1 ( 1 /01 1 1 (2/01 1 1 (2/0/ 1 1 12/0/ 1 1 12/01 1 1 12/01 1 1 (2/01 1 1 12/01 1 1 12/01 1 1 12/0/ 1 1

3 3 3 6 7 6 6 6 6 7 7 7 9 13 12 14 14 14 16 16 18 20 20

10/011 I 10/011 I (0/0/ 1 1 1 1 /0/ 1 ) 1 1 /0/ 1 ) 1 1 /0/ 1 ) ( 1 /01 1 ) ( 1 /0/ 1 ) ( 1 /0/ 1 ) 1 1 /01 1 1 1 1 /01 1 1 1 1 /01 1 1 ( 1 /01 1 1 1 1 /01 1 1 12/0/ 1 ) (2/0/ 1 1 (2/01 1 1 (2/01 1 1 12/01 1 1 12/0/ 1 1 12/01 1 1 (2/01 1 1 (2/0/ 1 1

5 5 5 8 9 8 8 8 8 9 9 9 11 15 14 16 16 16 18 18 20 22 22

10/0/ 1 ) 10/01 1 1 10/01 1 1 ( 1 /01 1 1 1 1 /0/ 1 1 ( 1 /01 1 1 ( 1 /01 1 ) ( 1 /01 1 ) ( 1 /0/ 1 ) 1 1 /01 1 1 ( 1 / 01 1 1 1 1 /01 1 1 1 1 /0/ 1 ) 1 1 /0/ 1 ) 12/01 1 1 12/01 1 1 12/01 1 1 12/0/ 1 1 12/01 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1

BEST CASE (Continued)

Source Address Mode Destination (ds,An,Xnl I d 1 6.An,Xnl

An # < data > . B, W # < data > . L IAnl IAnl + - IAnl I d 16 ,Anl o r I d 16 , PCI Ixxxl. W Ixxxi. L I d8 ,An,Xnl o r I d8 , PC,Xnl I d 1 6 ,An,Xnl or I d 16 , PC,Xnl IBI I d 16 , B I I d32 , B I ( [ B ] ' II ( [ B ] , I , d 1 61 ( [ B ] , I ,d 32 1 l [ d 1 6 , B I . II l [ d 1 6 , B] , I , d 16 1 l [ d 16 , B ] , I , d32 1 l [ d 32 , B ] , 1 1 l [ d 32 , B ] , I , d 1 6 1 ( [ d32 , B l , I , d32 1

4 4 4 8 9 8 8 8 8 9 9 9 11 15 14 16 16 16 18 18 20 22 22

10/01 1 1 10/01 1 1 10/0/ 1 ) ( 1 /01 1 1 ( 1 /0/ 1 1 1 1 /0/ 1 1 ( 1 /01 1 1 ( 1 /0/ 1 1 ( 1 /01 1 1 1 1 /0/ 1 1 ( 1 /0/ 1 ) 1 1 /01 1 1 1 1 /01 1 1 1 1 /0/ 1 1 12/01 1 1 12/01 1 1 (2/01 1 1 12/01 1 1 (2/01 1 I 12/0/ 1 1 12/01 1 1 12/0/ 1 1 12/0/ 1 1

6 6 6 10 11 10 10 10 10 10 11 11 13 17 16 18 18 18 20 20 22 24 24

(0/01 1 1 (0/01 1 1 (0/01 1 1 1 1 /01 1 1 ( 1 /0/ 1 1 ( 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /01 1 1 1 1 /01 1 1 1 1 /0/ 1 1 ( 1 /01 1 1 1 1 /0/ 1 1 1 1 /01 1 1 1 1 /0/ 1 1 12/01 1 1 (2/0/ 1 ) 12/01 1 1 12/01 1 1 12/011 I 12/0/ 1 1 12/01 1 1 12/0/ 1 1 12/01 1 1

5 5 5 9 10 9 9 9 9 10 10 10 12 18 17 19 19 19 21 21 23 25 25

(B) (0/0/ 1 ) (0/01 1 1 (0/01 1 1 1 1 /0/ 1 1 1 1 /01 1 1 1 1 /0/ 1 1 ( 1 /01 1 1 ( 1 /01 1 1 ( 1 /01 1 1 1 1 /01 1 1 ( 1 /01 1 1 1 1 /0/ 1 1 1 1 /01 1 1 1 1 /0/ 1 1 (2/01 1 1 (2/0/ 1 ) 12/0/ 1 1 (2/0/ 1 1 12/01 1 I 12/011 I 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1

( d 1 6,BI 7 (0/0/ 1 ) 7 10/0/ 1 1 7 10/01 1 I 1 1 1 1 /0/ 1 ) 1 2 1 1 /01 1 1 1 1 1 1 /011 I 1 1 ( 1 /01 1 1 1 1 1 1 /01 1 1 1 1 ( 1 /01 1 1 1 2 1 1 /01 1 1 1 2 ( 1 /01 1 1 1 2 1 1 /0/ 1 1 1 4 1 1 /01 1 1 1 8 1 1 /0/ 1 1 1 7 12/01 1 1 1 9 12/01 1 1 1 9 12/01 1 1 1 9 12/0/ 1 1 21 12/0/ 1 ) 21 12/01 1 1 23 12/0/ 1 1 25 12/0/ 1 1 25 12/0/ 1 1

(d32,BI 1 1 10/01 1 1 1 1 10/01 1 1 1 1 10/01 1 1 1 5 ( 1 /01 1 1 1 6 1 1 /01 1 1 15 ( 1 /01 1 1 1 5 1 1 /01 1 1 1 5 ( 1 /01 1 1 1 5 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 1 6 1 1 /01 1 1 1 6 1 1 /0/ 1 1 1 8 1 1 /0/ 1 1 22 1 1 /01 1 1 2 1 12/0/ 1 1 23 12/01 1 I 23 12/01 1 1 23 (2/0/ 1 ) 25 12/01 1 1 25 12/01 1 1 27 12/0/ 1 1 29 12/01 1 1 29 12/0/ 1 1

( [ B] , II 9 1 1 /01 1 1 9 ( 1 /01 1 1 9 1 1 /0/ 1 1 1 3 (2/0/ 1 1 1 4 12/01 1 1 1 3 12/0/ 1 1 1 3 12/01 1 1 1 3 12/01 1 1 13 12/01 1 1 14 (2/0/ 1 1 14 (2/0/ 1 1 1 4 12/01 1 1 1 6 12/01 1 1 20 12/01 1 1 19 (3/01 1 1 21 13/01 1 1 2 1 13/0/ 1 1 2 1 13/01 1 1 23 13/01 1 1 23 13/01 1 1 25 13/0/ 1 1 27 13/0/ 1 1 27 13/0/ 1 1

( [ B ] , I , d 16 1

11 11 11 15 16 15 15 15 15 16 16 16 18 22 21 23 23 23 25 25 27 29 29

1 1 /01 1 1 1 1 /01 1 1 1 1 /01 1 1 (2/01 1 1 12/01 1 1 12/01 1 1 12/0/ 1 1 12/01 1 1 12/01 1 1 12/01 1 I 12/01 1 I 12/01 1 1 12/01 1 I 12/01 1 1 13/01 1 1 13/0/ 1 1 (3/01 1 1 13/0/ 1 1 13/0/ 1 1 13/01 1 1 13/01 1 1 (3/01 1 1 13/01 1 1

([B]'I,d321 1 2 1 1 /01 1 1 1 2 1 1 /01 1 1 1 2 1 1 /01 1 1 1 6 (2/01 1 1 1 7 12/0/ 1 1 1 6 12/0/ 1 1 1 6 12/0/ 1 1 1 6 12/01 1 1 1 6 12/01 1 1 1 7 12/01 1 I 1 7 12/0/ 1 1 1 7 12/0/ 1 1 19 12/01 1 I 23 12/01 1 1 22 13/0/ 1 1 24 (3/01 1 1 24 13/0/ 1 1 24 13/01 1 1 26 13/0/ 1 1 26 13/0/ 1 1 28 13/01 1 1 30 13/01 1 1 30 13/01 1 1

9-1 6

B EST CASE (Concluded)

Source Address Mode Destination

Rn # < data > . B,W # < data > . L IAnl IAnl + IAnl Id 1 6 ,Anl or Id 16 , PCI Ixxxl. W Ixxxl . L I d8 ,An,Xnl o r Id8 , PC,Xnl Id 1 6 ,An,Xnl or I d 16 , PC,Xnl IBI I d1 6, B I Id32 , B I I [ B] ' II I [ B] , I , d 1 6 1 I [ Bl,I,d32 1 l[d 1 6 , BL l I l[d 1 6 , Bl , I,d 1 6 1 I [ d 1 6 ,8l,1,d32 1 I[d32 , B] . I I l[d32 , B l , I , d 1 6 1 l[d32 , Bl,I,d32 1

11 11 11 15 16 15 15 15 15 16 16 16 18 22 21 23 23 23 25 25 27 29 29

([d16,Bl,lI

1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 12/0/ 1 I 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 13/0/ 1 1 13/0/ 1 1 13/0/ 1 I 13/0/ 1 1 13/0/ 1 1 13/0/ 1 1 13/0/ 1 1 13/0/ 1 1 13/0/ 1 I

([d 16, Bl, l , d161 ([d16,Bl,I,d321 14 1 1 /0/ 1 1 1 3 1 1 /0/ 1 1

13 13 17 18 17 17 17 17 18 18 18 20 24 23 25 25 25 27 27 29 31 31 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 13/0/ 1 I 13/0/ 1 1 13/0/ 1 1 13/0/1 I 13/0/ 1 1 13/0/ 1 1 13/0/ 1 I 13/0/ 1 1 13/0/ 1 I 14 14 18 19 18 18 18 18 19 19 19 21 25 24 26 26 26 28 28 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 13/0/ 1 I 13/0/ 1 1 13/0/ 1 I 13/0/ 1 I 13/0/ 1 1 13/0/ 1 1 30 13/0/ 1 1 32 13/0/ 1 I 32 13/0/ 1 I

15 15 15 19 20 19 19 19 19 20 20 20 22 26 25 27 27 27 29 29 31 33 33

([d32,Bl,II

1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 13/0/ 1 1 13/0/ 1 1 13/0/ 1 1 13/0/ 1 I 13/0/ 1 1 13/0/ 1 1 13/0/ 1 1 13/0/1 I 13/0/ 1 I

([d32, Bl,l,d 1 61 ([d32, Bl,l,d321

17 17 17 21 22 21 21 21 21 22 22 22 24 28 27 29 29 29 31 31 33 35 35 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 13/0/ 1 I 13/0/ 1 1 13/0/ 1 1 13/0/ 1 I 13/0/ 1 1 13/0/ 1 1 13/0/ 1 1 13/0/ 1 I 13/0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 I 12/0/ 1 1 12/0/ 1 I 12/0/ 1 I 12/0/ 1 I 12/0/ 1 1 12/0/ 1 I 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 13/0/ 1 I 13/0/ 1 1 13/0/1 I 13/0/ 1 I 13/0/ 1 I 13/0/ 1 I 34 13/0/ 1 1 36 13/0/ 1 I 36 13/0/ 1 I 18 18 18 22 23 22 22 22 22 23 23 23 25 29 28 30 30 30 32 32

CAC H E CASE
Source Address Mode An On Destination IAnl IAnl + - IAn) IAn)

Rn # < data > . B,W # < data > . L IAnl IAnl + - IAnl Id 1 6 ,Anl o r Id 1 6 , PCI Ixxxl.W Ixxxl . L Id8 ,An, Xnl or I d8 , PC,Xnl Id 1 6 ,An,Xnl or Id 1 6 ,PC,Xnl IBI Id 16 , BI Id32 , B I I [ B] ' II I [ B l , I , d 1 61 I [ B l , I , d32 1 l[d 1 6 , B ] . 1 I l[d 1 6 , Bl , I ,d 1 61 l[d 1 6 , BLI, d32 1 l[d32 , BLiI l[d32 , Bl , I,d 1 6 1 l[d32 , Bl,I,d32 1

2 4 6 6 6 7 7 6 6 9 9 9 11 15 14 16 16 16 18 18 20 22 22

(01010) 1010101 1010101 1 1 /0/01 1 1 / 0/01 1 1 /0101 1 1 /0101 1 1 /0/01 1 1 /0101 1 1 /0101 1 1 /0101 1 1 /0101 1 1 /0101 1 1 / 0/01 12/0101 12/0/01 12/0101 12/0/01 12/0101 12/0101 12/0101 12/0/01 12/0/01

2 1010101 (01010) 6 1010/01 6 1 1 /0101 6 1 1 /0/01 7 1 1 /0101 7 1 1 /0/01 6 1 1 /0/01 6 1 1 10/01 9 1 1 /0101 9 1 1 /0101 9 1 1 /0101 1 1 1 1 /0101 15 1 1 /0101 14 12/0101 16 12/0/01 1 6 12/0/01 1 6 12/0/01 1 8 12/0/01 1 8 12/0/01 20 12/0101 22 12/0/01 22 12/0101

6 8 7 7 8 8 7 7 10 10 10 12 16 15 17 17 17 19 19 21 23 23

4 1010/ 1 I

(010/ 1 ) 1010/ 1 1 1 1 10/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 10/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 I 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 12/0/ 1 1

4 6 8 7 7 8 8 7 7 10 10 10 12 16 15 17 17 17 19 19 21 23 23

1010/ 1 ) 1010/ 1 1 1010/ 1 1 1 1 10/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 10/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 12/0/ 1 1

5 7 9 7 7 8 8 7 7 10 10 10 12 16 15 17 17 17 19 19 21 23 23

1010/ 1 1 1010/ 1 I 1010/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 10/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 12/0/ 1 I

5 7 9 7 7 8 8 7 7 10 10 10 12 16 15 17 17 17 19 19 21 23 23

1010/ 1 I 1010/ 1 ) 1010/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 12/0/ 1 I 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 12/0/ 1 I

6 8 7 7 8 8 7 7 10 10 10 12 16 15 17 17 17 19 19 21 23 23

4 1010/ 1 I

( xxxl .W

(xxx) . L

1010/ 1 1 1010/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 10/ 1 I 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 I 12/0/ 1 I 12/0/ 1 1 12/0/ 1 I 12/0/ 1 I 12/0/ 1 I 12/0/ 1 I 12/0/ 1 1 12/0/ 1 I

6 8 10 9 9 10 10 9 9 12 12 12 14 18 17 19 19 19 21 21 23 25 25

1010/ 1 1 1010/ 1 1 1010/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/1 I 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 12/0/ 1 I 12/0/ 1 1

9-1 7

CAC H E CASE (Continued)

Source Address Mode Ide,An,Xnl I d 1 6,An,Xnl Destination

Rn l < data > . B,W # < data > . L IAnl IAnl + - IAn) Id 1 6 ,Anl or Id 16 , PCI I xxx).W I xxxl . L I d8 ,An,Xnl o r Id8 , PC,Xnl I d 16 ,An,Xnl or I d 16 , PC,Xnl IBI Id 16 ,BI I d32 , BI ([Bl,Il ([Bl,I,d 16 1 ( [ B ] ' I ,d32 ) IId 16 ,B] ' 1I IId 16 ,B],I,d 16 1 IId 1 6 , B ] ' I,d32 ) IId32 , B ] , II IId32 , B] ' I,d 16) I I d32 ,B],I,d32 )

7 7 9 9 9 10 10 9 9 12 12 12 14 18 17 19 19 19 21 21 23 25 25

1010/ 1 I 1010/ 1 1 1010/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 ) 1 1 /0/ 1 1 1 1 /0/ 1 I 1 1 /0/ 1 ) 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 (2/0/ 1 ) (2/0/ 1 ) 12/0/ 1 ) (2/0/ 1 ) 12/0/ 1 1 12/0/ 1 I 12/0/ 1 )

9 9 11 11 11 12 12 11 11 14 14 14 16 20 19 21 21 21 23 23 25 27 27

1010/ 1 1 (010/ 1 ) (010/ 1 ) 1 1 /0/ 1 ) 1 1 /0/ 1 1 ( 1 /0/ 1 ) 12/0/ 1 1 1 1 /0/ 1 ) 1 1 /0/ 1 ) 1 1 /0/ 1 1 ( 1 / 0/ 1 ) 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 I 12/0/ 1 1 (2/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 )

8 8 10 10 10 11 11 10 10 13 13 13 15 19 18 20 20 20 22 22 24 26 26

I B) 1010/ 1 1 10/0/ 1 1 1010/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 ) 1 1 /0/ 1 ) 1 1 /0/ 1 ) 1 1 /0/ 1 ) 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 1 12/0/ 1 ) 12/0/1 I 12/0/ 1 1 12/0/ 1 )

Id16,BI

Id32,BI

( [ BI. l l

( [ B I . I , d161

( [ B l , I , d321

10 10 12 12 12 13 13 12 12 15 15 15 17 21 20 22 22 22 24 24 26 28 28

1010/ 1 I 1010/ 1 I 10101 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 ) 1 1 /0/ 1 1 1 1 /0/ 1 ) 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/1 I 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 1

14 14 16 16 16 17 17 16 16 19 19 19 21 25 24 26 26 26 28 28

1010/ 1 1 1010/ 1 I 1010/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 ) ( 1 /0/ 1 ) 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 ) 12/0/ 1 1 12/0/ 1 I 12/0/ 1 I 12/0/ 1 I 12/0/ 1 1 12/0/ 1 I 30 12/0/ 1 I 32 12/0/ 1 ) 32 12/0/ 1 1

1 1 /0/ 1 1 1 1 /0/ 1 1 ( 1 /0/ 1 ) 12/0/ 1 I 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 1 (2/0/ 1 ) 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 I 13/0/ 1 1 13/0/ 1 1 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 I 13/0/ 1 I 30 13/0/ 1 1 30 13/01 1 1

12 12 14 14 14 15 15 14 14 17 17 17 19 23 22 24 24 24 26 26 28

14 14 16 16 16 17 17 16 16 19 19 19 21 25 24 26 26 26 28 28

1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 I 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 ) 13/0/ 1 ) 13/0/ 1 1 13/0/ 1 ) 13/0/ 1 I 13/0/ 1 1 13/0/ 1 ) 30 13/0/ 1 1 32 13/01 1 1 32 13/0/ 1 )

1 1 /0/ 1 ) 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 I 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 I 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 ) 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 1 (3/0/ 1 ) 29 13/0/ 1 1 3 1 13/0/ 1 ) 33 13/0/ 1 ) 33 13/0/01

15 15 17 17 17 18 18 17 17 20 20 20 22 26 25 27 27 27 29

CACH E CASE (Concluded)

Source Address Mode ( [ d16, B I . I I ( [ d1 6 , B I . I , d1 61 l [ d 1 6 , B I . I,d321 ( [ d32 , B I . I I Destination I I d32, Bl.I.d 161 ( [ d32, B I . I,d321

Rn # < data > . B , W # < data > . L IAn) IAn) + - IAn) Id 16 ,Anl or Id 16 , PCI I xxx) .W Ixxx ) . L Id8 ,An,Xnl o r Id8 , PC,Xn) I d 16 ,An,Xnl o r I d 16 , PC,Xnl I B) Id 16 , B) Id32 , B) I I B ] ' II I [ B] ' I,d 16 ) II B I , I , d32 ) I I d 16 , B ] ' 1 I IId 16 , B ] ' I ,d 16) IId 16 , B L I , d32 ) IId32 , B],II IId32 , BL I,d 16 ) IId32 , B L I , d32 1

14 14 16 16 16 17 17 16 16 19 19 19 21 25 24 26 26 26 28 28 30 32 32

1 1 /0/ 1 1 1 1 /0/ 1 ) 1 1 /0/ 1 ) 12/0/ 1 ) (2/0/ 1 ) 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 1 (3/0/ 1 ) 13/0/ 1 ) 13/01 1 1 13/0/ 1 1 (3/0/ 1 ) 13/0/ 1 1

16 16 18 18 18 19 19 18 18 21 21 21 23 27 26 28 28 28

1 1 /0/ 1 1 1 1 10/ 1 1 1 1 /0/ 1 ) (2/0/ 1 ) 12/0/ 1 1 (2/0/ 1 ) (2/0/ 1 ) (2/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 1 13/0/ 1 ) (3/0/ 1 ) 13/0/ 1 1 13/0/ 1 ) 30 13/0/ 1 ) 30 13/0/ 1 ) 32 13/0/ 1 1 34 13/0/ 1 ) 34 13/0/ 1 I

17 17 19 19 19 20 20 19 19 22 22 22 24 28 27 29 29 29 31 31 33 35 35

1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 ) 12/0/ 1 ) (2/0/ 1 ) 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 ) 13/0/ 1 1 13/0/ 1 I 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 ) (3/0/ 1 )

18 18 20 20 20 21 21 20 20 23 23 23 25 29 28 30
30 30 34

32 32

36 36

1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 ) 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 ) 13/0/ 1 1 13/0/ 1 1 13/0/ 1 ) 13/0/ 1 1 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 1 13/01 1 1 13/0/ 1 1

20 20 22 22 22 23 23 22 22 25 25 25 27 31 30 32 32 32

1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 1 12/0/ 1 ) 12/0/ 1 I 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 I 12/0/ 1 ) (3/0/ 1 ) 13/0/ 1 ) 13/0/ 1 1 13/0/ 1 ) 34 13/0/ 1 ) 34 13/0/ 1 ) 36 13/0/ 1 ) 38 13/0/ 1 ) 38 13/0/ 1 )

21 21 23 23 23 24 24 23 23 26 26 26 28 32 31 33 33
33

35 35 37

39

39

1 1 /0/ 1 1 1 1 /0/ 1 1 1 1 /0/ 1 ) 12/0/ 1 1 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 ) 12/0/ 1 1 12/0/ 1 1 12/0/ 1 ) (2/0/ 1 ) (2/0/ 1 ) 12/0/ 1 1 (3/0/ 1 ) 13/0/ 1 1 13/0/ 1 ) 13/0/ 1 1 13/0/ 1 ) 13/0/ 1 ) 13/0/ 1 1 13/0/ 1 1 13/0/ 1 )

9-1 8

WO RST CASE
Source Address Mode An l < data > . B .W l < data > . L IAn) An 3 101 1 /01 3 (01 1 10) 5 101 1 /01 7 ( 1 1 1 10) 7 1 1 / 1 / 0) 8 1 1 / 1 101 9 1 1 / 2/01 8 1 1 / 2/01 1 0 1 1 /2/01 1 1 1 1 /2/01 12 1 1 / 2/01 12 1 1 / 2/01 1 5 1 1 / 2/01 19 ( 1 /3/0) 1 6 12/2101 19 12/2/01 20 12/3/01 19 12/2/01 22 12/3/01 23 12/3/01 23 12/3/01 25 12/3/01 27 12/4/0) Dn 3 101 1 /01 3 101 1 /01 5 (01 1 1 0) 7 ( 1 1 1 10) 7 1 1 1 1 / 01 8 1 1 / 1 /01 9 1 1 / 2/01 8 1 1 /2/01 10 1 1 / 2/0) 1 1 1 1 /2/01 1 2 1 1 /2/0) 1 2 1 1 12101 15 1 1 12101 1 9 1 1 /3/01 1 6 (2/2/0) 1 9 12/2/01 20 12/3/01 1 9 12/2/01 22 12/3/01 23 12/3/01 23 12/3/01 25 12/3/01 27 12/4/01 (An) 5 101 1 /01 5 (01 1 10) 7 (010/ 1 ) 9 (11111) 9 11/1/11 10 ( 1 1 1 1 1 ) 1 1 ( 1 / 21 1 ) 1 0 ( 1 /2/ 1 ) 1 2 1 1 / 21 1 ) 13 ( 1 /2/ 1 ) 1 4 1 1 / 21 1 1 1 4 1 1 /21 1 1 1 7 1 1 /21 1 1 21 1 1 /31 1 ) 1 8 (2/2/ 1 ) 1 2 1 12/21 1 ) 22 12/31 1 1 21 12/21 1 1 24 12/3/ 1 1 25 12/3/ 1 1
29 (2/41 1 )

Destination (An) + 5 (01 1 1 1 ) 8 (01 1 1 1 ) 7 (01 1 1 1 ) 9 (11111) 9 (1/1/1) 10 (111/1) 1 1 1 1 /21 1 1 1 0 ( 1 12 1 1 ) 1 2 1 1 /21 1 1 1 3 ( 1 / 2/ 1 ) 1 4 1 1 / 2/ 1 1 1 4 1 1 / 21 1 1 1 7 ( 1 / 21 1 ) 2 1 1 1 / 3/ 1 ) 1 8 12/2/ 1 1 21 12/21 1 1 22 12/3/ 1 1 2 1 12/21 1 1 24 12/31 1 1 25 12/31 1 1 25 12/31 1 1 27 12/31 1 1 29 12/4/ 1 1 - IAn) 6 (01 1 1 1 ) 6 (01 1 1 1 ) 8 (01 1 1 1 ) 9 (11111) 9 1111111 10 (1/111) 1 1 ( 1 / 2/ 1 ) 1 0 ( 1 12/ 1 ) 1 2 1 1 / 21 1 ) 1 3 ( 1 /21 1 ) 1 4 1 1 /2/ 1 ) 1 4 ( 1 /21 1 ) 1 7 ( 1 / 31 1 ) 2 1 ( 1 / 3/ 1 ) 1 8 12/21 1 ) 2 1 12/2/ 1 ) 22 12/3/ 1 ) 2 1 12/21 1 1 24 12/31 1 1 25 12/31 1 1
29 12/4/ 1 )

I d l s.An) 7 (01 1 1 1 ) 7 (01 1 1 1 ) 9 (01 1 1 1 ) 11 (1/111) 1 1 (1/1/1) 12 ( 1 / 1 1 1 ) 1 3 ( 1 /211) 1 2 ( 1 /2/ 1 ) 1 4 1 1 /21 1 1 1 5 ( 1 / 2/ 1 ) 1 6 1 1 /2/ 1 ) 1 6 ( 1 12 1 1 ) 1 9 1 1 /2/ 1 ) 23 ( 1 / 31 1 ) 20 (2/21 1 ) 23 12/2/ 1 1 24 12/3/ 1 ) 23 12/2/ 1 ) 26 12/31 1 1
29 12/3/ 1 )

(xxx).W 7 (01 1 1 1 ) 7 (0/ 1 1 1 ) 9 (01 1 1 1 ) 11 (11111) 11 (1/1/1) 12 ( 1 1 1 / 1 ) 1 3 ( 1 /2/ 1 ) 1 2 ( 1 /2/ 1 ) 1 4 1 1 /2/ 1 1 1 5 ( 1 /21 1 ) 1 6 1 1 /2/ 1 ) 16 1 1 /2/ 1 ) 1 9 1 1 /2/ 1 ) 23 ( 1 / 31 1 ) 20 (2/21 1 ) 23 (2/21 1 ) 24 (2/31 1 ) 23 12/21 1 1 26 12/31 1 1
29 12/31 1 1

I xxxl. L 9 (0/2/ 1 ) 9 (012/ 1 ) 1 1 (0/21 1 ) 1 3 ( 1 121 1 ) 1 3 ( 1 /2/ 1 ) 1 4 ( 1 12/ 1 ) 1 5 ( 1 / 3/ 1 ) 1 4 1 1 / 31 1 1 1 6 1 1 / 3/ 1 ) 1 7 1 1 /31 1 1 18 1 1 /31 1 1 1 8 ( 1 / 3/ 1 ) 2 1 ( 1 /31 1 ) 25dl l / 4/ 1 ) 22d(2/3/ 1 ) 25 12/3/ 1 1 26 (2/41 1 )
29 (2/41 1 )

IAn) +

- IAn)

Id 1 6 .Anl o r I d 1 6 . PCI Ixxxl . W I x xx) . L Id8 . A n . X n) o r Id8 . PC . X n l I d 1 6 . A n . X nl o r I d 1 6 . PC . X nl I B) I d 1 6 . B) I d32 . B) I I B]'II I [ B LI . d 1 6 1 I I B L I . d32 1 I I d 1 6 . B ] ' 1I I I d 1 6. B ] , I . d 1 61 I I d 16 . B l , l .d32 1 I I d32 . B ] , II I I d32 . Bl . I . d 1 61 l [ d32 . B LI . d32 )

25 12/31 1 1

27 12/31 1 1

27 12/31 1 1

25 12/3/ 1 1

25 12/31 1 1

27 12/31 1 1

27 12/31 1 1

27 12/31 1 1

27 12/31 1 1

3 1 (2/41 1 )

3 1 (2/41 1 )

3 1 12/4/ 1 )

33 12/51 1 1

29 12/41 1 1

28 12/4/ 1 1

WO RST CASE (Continued)

Source Address Mode An # < data> . B. W # < data > . L IAn) IAn) + I d I 6 .An) o r Id 1 6 . PC) - I Anl I xxx) . W Ixxx) . L I d8 . A n . X n) or I d8 . PC . X n) I d I 6 . A n . X n) or I d I 6 . PC . X n) IB) I d I 6. B ) I d32 . B I IIBLI) II B L I . d I 6 ) I I B L I . d32 ) ( [ d I 6 . B ] , 1I l [ dI 6 . B LI . d I 6 ) I I d I 6 . B ] ' I .d32 ) ( [ d32 . B ] , I ) I I d32 . 8 1 , 1 . d I 6 ) I I d32 . B I . I . d32 ) (da.An.Xn) 9 (01 1 1 1 ) 9 101 1 / 1 ) 1 1 101 1 1 1 1 11 ( 1 1 1 1 1 ) 11 (11111) 12 ( 1 1 1 1 1 ) 1 3 ( 1 / 21 1 ) 1 2 1 1 / 21 1 ) 1 4 1 1 /21 1 ) 15 1 1 /21 1 ) 16 ( 1 /21 1 ) 16 ( 1 /21 1 ) 19 ( 1 /2/ 1 ) 2 3 ( 1 /31 1 ) 2 0 (2/21 1 ) 23 (2/21 1 ) 24 (2/3/ 1 ) 23 12/2/ 1 ) 26 (2/31 1 ) 27 (2/31 1 ) 2 7 (2/3/ 1 ) 29 12/31 1 ) 31 (2/41 1 ) [ d l s.AnXn) 1 2 1012/ 1 ) 1 2 10/21 1 ) 1 4 10/21 1 ) 1 4 ( 1 /21 1 ) 1 4 ( 1 12/ 1 ) 1 5 1 1 /21 1 1 1 6 (2/31 1 ) 1 5 ( 1 / 31 1 ) 1 7 1 1 /3/ 1 ) 1 8 1 1 /31 1 1 1 9 ( 1 / 31 1 ) 1 9 ( 1 /31 1 ) 22 ( 1 /31 1 ) 26 1 1 /4/ 1 ) 23 (2/3/ 1 ) 26 (2/3/ 1 ) 27 (2/41 1 ) 26 (2/3/ 1 ) ( B) 1 0 (01 1 1 1 ) 1 0 101 1 1 1 1 1 2 10/ 1 / 1 1 12 1 1 1 1 / 1 ) 12 1111/1) 13 (11111) 1 4 ( 1 /21 1 ) 1 3 ( 1 / 21 1 ) 1 5 1 1 / 2/ 1 ) 1 6 1 1 /21 1 ) 1 7 ( 1 /21 1 ) 1 7 1 1 /21 1 1 20 ( 1 /21 1 ) 24 ( 1 /31 1 ) 2 1 (2/2/ 1 ) 24 12/2/ 1 ) 25 12/31 1 ) 24 (2/21 1 ) 27 (2/31 1 ) 28 12/3/ 1 1 Destination IdlS.B ) 1 4 1012/ 1 ) 1 4 1012/ 1 ) 1 6 10/2/ 1 ) 1 6 1 1 /21 1 ) 1 6 1 1 /2/ 1 ) 1 7 1 1 /2/ 1 ) 1 8 1 1 /31 1 )
20 1 1 / 31 1 )

(d32 . B ) 1 9 10/21 1 1 19 10/21 1 ) 2 1 10/21 1 ) 21 ( 1 /21 1 ) 2 1 1 1 /21 1 1 2 2 1 1 / 21 1 1 23 1 1 /3/ 1 1 22 1 1 /31 1 1 24 1 1 /31 1 1 25 ( 1 /3/ 1 ) 26 ( 1 /3/ 1 ) 26 ( 1 /31 1 ) 29 ( 1 /31 1 )
33 12/31 1 ) 33 ( 1 /4/ 1 )

([ B]'II 14 (11111) 14 (1/111) 16 1 1 / 1 1 1 ) 1 2 (2/ 1 / 1 ) 1 2 (21 1 1 1 ) 1 3 (21 1 1 1 ) 1 4 12/21 1 1 1 3 (2/21 1 ) 1 5 (2121 1 ) 1 6 (2/21 1 ) 1 7 12/21 1 ) 1 7 (2/21 1 ) 20 (2121 1 ) 24 (2/31 1 ) 2 1 (3/21 1 ) 24 (3/21 1 ) 25 (3/3/ 1 ) 24 (3/21 1 ) 27 (3/3/ 1 ) 28 13/31 1 1

( [ B ] , I . d 1 6) 1 7 1 1 /21 1 ) 1 7 ( 1 1 21 1 ) 1 9 1 1 /21 1 ) 1 9 (2/2/ 1 ) 1 9 12/2/ 1 ) 20 12121 1 1 2 1 12/31 1 1 20 12/3/ 1 ) 22 12/31 1 ) 23 (2/3/ 1 ) 24 (2/3/ 1 ) 24 (2/31 1 ) 27 (2131 1 ) 3 1 (2/41 1 ) 28 (3/31 1 ) 3 1 (3/31 1 ) 3 1 (3/3/ 1 )
34 (3/4/ 1 )

( [ B I , I . d32) 20 ( 1 /21 1 ) 20 ( 1 1 21 1 ) 22 1 1 /21 1 ) 22 (2/21 1 ) 22 (2/21 1 ) 23 12/21 1 ) 24 (2/31 1 ) 23 (2/3/ 1 ) 25 (2/31 1 ) 26 (2/31 1 ) 27 (2/31 1 ) 27 (2/31 1 )

1 7 1 1 /3/ 1 )

1 9 1 1 / 3/ 1 )

2 1 1 1 / 31 1 ) 2 1 ( 1 /31 1 ) 24 ( 1 /31 1 ) 28 ( 1 /41 1 ) 25 (2/3/ 1 ) 28 (2/31 1 ) 29 (2/41 1 ) 28 12/31 1 ) 31 (2/41 1 ) 32 (2/41 1 )

36 (2/51 1 )

30 30 34

29 (2/4/ 1 ) (2/4/ 1 ) 12/41 1 1 (2/5/ 1 )

36 (2/4/ 1 )

33 (2/31 1 )

34

30

30

(2/3/ 1 )

3 1 (3/3/ 1 )

34 (3/31 1 )

34 (2/41 1 )

(2/31 1 )

12/4/ 1 )

32 (3/41 1 )

37 (3/41 1 )

34

35 (3/4/ 1 )
38 (3/41 1 )

(3/31 1 )

3 7 (2/41 1 )

35 (3/41 1 ) 35 (3/41 1 )

32 12/41 1 1

32 (2/41 1 )

30

28 (2/31 1 ) 12/31 1 )

34

32 12/41 1 1 (2/41 1 )

4 1 (2/5/ 1 )

39

37 (2/4 1 1 ) 12/4/ 1 )

32 (3/41 1 )

30

28 (3/31 1 ) (3/31 1 )

39

37 (3/41 1 ) (3/51 1 )

40 (3/41 1 )

38 (3/41 1 )

42 (3/51 1 )

9-1 9

WORST CASE (Concluded)

Source Address Mode Destination

Rn # < data > . B,W # < data > . L IAnl IAnl + - IAnl I d l6 .Anl o r I d 1 6 , PCI Ixxxl. W Ixxxl . L I d8 ,An,Xnl or I d8 , PC,Xnl I d 1 6 .An,Xnl or Id 1 6 , PC,Xnl IBI I d I 6 , BI I d32 , BI I[BI,II I [ B l , I , d I 61 I [ B I , I , d32 1 l [ d 16 , Bl ,Il l[dI 6 , Bl , I, d I 6 1 l [ d 16 , Bl , I , d 32 1 l [ d32 , BI , I I I I d32 , Bl , I , dI 6 1 ( [ d32 , BI , I , d32 1

IId 1 6,BI,I) 1 7 1 1 / 21 1 1 1 7 1 1 / 2/ 1 1 19 1 1 / 2/ 1 1 1 9 12/21 1 1 19 12/2/ 1 1 20 12/2/ 1 1 21 12/31 1 1 20 12/31 1 1 22 12/31 1 1 23 12/3/ 1 1 24 12/31 1 1 24 12/31 1 1 27 12/31 1 1 31 12/41 1 1 2 8 13/31 1 1 31 13/3/ 1 1 32 13/41 1 1 31 13/3/ 1 1 34 13/4/ 1 1 35 13/4/ 1 1 35 13/4/ 1 1 37 13/4/ 1 1 39 13/5/ 1 1

IId 1 6,BI,I, d 1 61 20 1 1 / 2/ 1 1 20 1 1 / 2/ 1 1 22 1 1 / 2/ 1 1 22 12/21 1 1 22 12/2/ 1 1 23 12/2/ 1 1 24 12/31 1 1 23 12/3/ 1 1 25 12/31 1 1 26 12/3/ 1 1 27 12/31 1 1 27 12/31 1 1 30 12/31 1 1 34 12/41 1 1 3 1 13/3/ 1 1 34 13/31 1 1 35 13/41 1 1 34 13/3/ 1 1 37 13/41 1 1 38 13/41 1 1 38 13/41 1 1 40 13/4/ 1 1 42 13/51 1 1

IId 1 6, BI,I,d32 1 23 1 1 / 31 1 1 23 1 1 /3 / 1 1 25 1 1 /31 1 1 25 12/31 1 1 25 12/3/ 1 1 26 12/31 1 1 2 7 12/41 1 1 26 12/4/ 1 1 28 12/41 1 1 29 12/41 1 1 30 12/41 1 1 30 12/4 / 1 1 33 12/4/ 1 1 37 12/51 1 1 34 13/4/ 1 1 37 13/4/ 1 1 38 13/51 1 1 37 13/41 1 1 40 13/51 1 1 4 1 13/51 1 1 41 13/51 1 1 43 13/51 1 1 45 13/6/ 1 1

l [ d32,BI,I) 22 1 1 /21 1 1 2 2 1 1 /21 1 1 24 1 1 /21 1 1 24 12/21 1 1 24 12/21 1 1 25 12/21 1 1 26 12/3/ 1 1 27 12/3/ 1 1 29 12/31 1 1 30 12/31 1 1 3 1 12/3/ 1 1 3 1 12/31 1 1 34 12/31 1 1 38 12/41 1 1 35 13/31 1 1 38 13/3/ 1 1 39 13/41 1 1 38 13/31 1 1 41 13/4/ 1 1 42 13/41 1 1 42 13/41 1 1 44 13/4/ 1 1 46 13/51 1 1

IId32,BI,I,d 1 61 25 1 1 /31 1 1 25 1 1 /31 1 1 27 1 1 /3/ 1 1 27 12/31 1 1 27 12/3/ 1 1 28 12/31 1 1 29 12/41 1 1 28 12/4/ 1 1 30 12/41 1 1 3 1 12/4/ 1 1 32 12/4/ 1 1 32 12/4/ 1 1 35 12/4/ 1 1 39 12/5/ 1 1 36 13/41 1 1 39 13/41 1 1 40 13/5/ 1 1 39 13/41 1 1 42 13/51 1 1 43 13/5/ 1 1 43 13/51 1 1 45 13/51 1 1 47 13/6/ 1 1

I Id32,BI,I,d321 27 1 1 /31 1 1 27 1 1 /3/ 1 1 29 1 1 /3/ 1 1 29 12/31 1 1 29 12/3/ 1 1 30 12/31 1 1 3 1 12/41 1 1 30 12/41 1 1 32 12/4/ 1 1 33 12/4/ 1 1 34 12/4/ 1 1 34 12/4/ 1 1 37 12/4 / 1 1 4 1 12/5/ 1 1 38 13/4/ 1 1 4 1 13/4/ 1 1 42 13/51 1 1 4 1 13/41 1 1 44 13/5/ 1 1 45 13/51 1 1 45 13/51 1 1 47 13/5/ 1 1 49 13/61 1 1

9-20

9.2.7 Special Purpose MOVE Instruction The special pu rpose MOVE t i m i ng table i nd i cates the n u m ber of c lock periods needed for the processor to fetch, calcu late, and perform the s pecial pu rpose MOVE operation on the control reg i sters or s pecified effective address. The total n u mber of c lock cyc les i s outside t h e parentheses, the n u m ber o f read, prefetch, a n d w rite cyc les are g ive n i ns ide the parentheses as (r/p/w). They are i n c l uded in the total c lock cyc le number.
Instruction Best Case Cache Case Worst Case

EXG MOVEC MOVEC MOVE # MOVE . MOVE . MOVE # . MOVEM # . MOVEM MOVEPW MOVE P . L MOVEP.W MOVEP . L # + MOVES # . MOVES MOVE SWAP n RL
=

RY, Rx Cr,Rn Rn,Cr PSW, Rn PSW, Mem EA, CCR EA. S R EA, R L R L,EA Dn,ld 1 6 ,Anl Dn,ld 1 6 .Anl Id 1 6 . Anl,Dn Id 16 . Anl,Dn EA, Rn Rn,EA USP RX,Ry

o 1010/01
3 9 1 5 4 8 8 + 4n 4 + 3n 8 14 10 16 7 5 1010/01 10/0/01 10/0/01 10/0/ 1 1 10/0/01 10/0/01 In/O/Oi 10/01 nl 10/0/21 10/0/41 12/0/01 14/0/01 1 1 /0/01 10/0/ 1 I a 10/0/01 1 10/0/01

2 6 12 4 5 4 8 8 + 4n 4 + 3n 11 17 12 18 7 5 2 4

1010/01 1010101 10/0/01 10/0/01 10/0/1 I 10/0/01 10/0/01 In/O/OI 10/0/ni 10/0/21 10/0/41 12/0/01 14/0/01 1 1 /0/01 10/0/ 1 1 10/0/01 10/0/01

3 7 13 5 7 5 11 9 + 4n 5+ 3n 11 17 12 18 8 7 3 4

10/ 1 /01 10/1 101 10/ 1 101 10/ 1 101 10/ 1 / 1 1 10/ 1 10 1012101 In/ 1 /OI 1O/ 1 / nl 10/ 1 121 10/ 1 141 12/ 1 101 14/ 1 101 1 1 / 1 101 10/ 1 / 1 1 10/ 1 101 10/ 1 101

number of registers to transfer Register List Add Fetch Effective Address time Add Calculate Effective Address time #+ Add Calculate Immediate Address time
=

9-21

9.2.8 Arithmetic/Logical Operations The arithmetic/log ical operations t i m i n g table ind icates the n u m ber of c lock periods needed for the processor to perform the specified arithmet ic/logical operat ion u s i n g the specified addressi n g mode. It a l so i ncl udes, i n worst case, the amount of time needed to prefetch the i nstruct ion. Footnotes specify w hen to add either fetch address or fetch i m med iate effective address t i me. This sum g ives the total effective execution t i me for the operat ion u s i n g the spec ified addressing mode. The total n u m ber of c lock cycles i s out side the parentheses, the n u m ber of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are i ncl uded in the total clock cyc le n u m ber.
Instruction
* * * * * * * * * * * * * * * * * * * * * * * * *

Best Case

Cache Case

Worst Case

ADD ADD ADD AND AND EOR EOR OR OR SUB SUB SUB CMP CMP C M P2 MUL.W MUL.L DIVU.W DIVU . L DIVS.W DIVS . L

EA,Dn EA,An Dn, EA EA, Dn Dn,EA Dn,Dn Dn, Mem EA,Dn Dn,EA EA,Dn EA,An Dn,EA EA,Dn EA,An EA, Rn EA, Dn EA,Dn EA, Dn EA,Dn EA,Dn EA, Dn

o (0/0/01 o (0/0/01
3 (0/0/ 1 1

o (0/0/01
3 (0/0/ 1 1 o (0/0/01 3 (0/0/ 1 1 o (0/0/01 3 (0/0/ 1 1 o (0/0/01 o (0/0/01 3 (0/0/ 1 1 o (0/0/01 1 (0/0/01 16 ( 1 / 0/01 25 (0/0/01 41 (0/0/01 42 (0/0/01 76 (0/0/01 54 (0/0/01 88 (0/0/01

2 2 4 2 4 2 4 2 4 2 2 4 2 4 18 27 43

(0/0/01 10/0/01 (0/0/ 1 1 (0/0/01 (0/0/ 1 1 (0/0/01 (0/0/ 1 1 (0/0/01 (0/0/ 1 1 (0/0/01 (0/0/01 (0/0/ 1 1 (0/0/01 (0/0/01 ( 1 /0/01 (0/0/01 (0/0/01 44 (0/0/01 78 (0/0/01 56 (0/0/01 90 (0/0/01

(0/ 1 /01 (0/ 1 /01 (0/ 1 / 1 1 (0/ 1 /01 (0/ 1 / 1 1 (0/ 1 /01 (0/ 1 / 1 1 (0/ 1 /01 (0/ 1 / 1 1 (0/ 1 /01 (0/ 1 /01 (0/ 1 / 1 1 (0/ 1 /01 (0/ 1 /01 ( 1 / 1 /01 (0/ 1 /01 44 (0/ 1 /01 44 (0/ 1 /01 78 (0/ 1 /01 56 (0/ 1 /01 90 (0/ 1 /01

3 3 6 3 6 3 6 3 6 3 3 6 3 4 18 28

* *

Add Fetch Effective Address time Add Fetch Immediate Address time

9.2.9 Immediate Arithmetic/Logical Operations The i mmediate arithmetic/log ical operat ions t i m i n g table i nd icates the n u mber of clock periods needed for the processor to fetch the source i mmed i ate data val ue, and perform the specifi ed arith met i cllogical operat ion u s i n g the specif ied dest i nation addressing mode. Footnotes i ndicate w hen to add appropriate fetc h effective or fetch i m med i ate ef fective address t i mes. This computation w i l l g ive the total execution t i me needed to per form the appropriate i mmed i ate arithmet i cllogical operat ion. The total n u m ber of clock cycles i s outside the parentheses, the n u m ber of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are i nc l uded in the total clock cyc le n u mber.

9-22

Instruction

Best Case o o

Cache Case

Worst Case

. . . . . . . . - - . . _ . . .

MOVEO ADDO ADDO S U BO SUBO ADDI ADDI ANDI ANDI EORI EORI ORI ORI SUBI SUBI CMPI

# < data > , On # < data > , R n # < data > , Mem # < data> , R n # < data > , Mem # < data > ,Dn # < data > , Mem # < data > ,On # < data > ,Mem # < data > ,On # < data > , Mem # < data > ,Dn # < data > , Mem # < data > , On # < data > , Mem # < data > , EA

3 3 3
o

o o

3
o

3
o

1010/01 1010101 1010/ 1 1 1010/01 10101 1 1 1010101 1010/ 1 1 1010101 10101 1 1 1010101 10101 1 1 1010101 10101 1 1 10/0101 10/01 1 1 10/0101

2 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2

1010101 1010/01 1010/ 1 1 1010101 1010/ 1 1 1010/01 10101 1 1 1010101 1010/ 1 1 1010101 10101 1 1 1010101 10101 1 1 1010/01 1010/ 1 1 1010/01

3 3 6 3 6 3 6 3 6 3 6 3 6 3 6 3

10/ 1 /01 10/ 1 /01 10/ 1 1 1 1 101 1 /01 101 1 1 1 1 101 1 101 101 1 1 1 1 101 1 /01 101 1 / 1 1 101 1 /01 101 1 1 1 1 101 1 /01 101 1 / 1 1 10/ 1 /01 10/ 1 / 1 1 101 1 /01

Add Fetch Effective Address time Add Fetch Immediate Address time

9.2.1 0 Binary Coded Decimal Operations The bi nary coded decimal operat ions table ind icates the n u m ber of c lock periods needed for the processor to perform the spec ified operation u s i n g the g iven addressing modes, with complete execution t i mes g iven. No add itional tables are needed to calcu late total effective execution time for these i nstructions. The total nu mber of c lock cyc les i s out side the parentheses, the n u mber of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are i n c l uded in the total c l ock cyc le n u m ber.
Instruction Best Case Cache Case Worst Case

ABCD ABeD SBCD SBCD ADDX ADDX SUBX SUBX CMPM PACK PACK UNPK UNPK

Dn,Dn - IAnl, - IAnl Dn,Dn - IAnl, - IAnl Dn,Dn - IAnl, - IAnl Dn,Dn - IAnl, - IAnl IAnl + ,IAnl + Dn,Dn,# < data > - IAnl, - IAnl , # < data> Dn,Dn,# < data > - IAnl, - IAnl ,# < data >

4 14 4 14 2 10 2 10 8 3 11

10/0101 12/01 1 1 1010/01 12/0/ 1 1 10/0101 12/0/ 1 1 10/0101 12/01 1 1 12/0101 10/0101 1 1 /01 1 1 5 1010/01 1 1 1 1 /011 I

4 16 4 16 2 12 2 12 9 6 13 8 13

1010/01 12/0/ 1 1 1010/01 12/01 1 1 1010/01 12/0/ 1 1 10/0101 12/0/ 1 1 12/0/01 1010/01 1 1 /01 1 1 10/0101 1 1 /01 1 1

5 10/ 1 /01 1 7 12/ 1 1 1 1 5 10/ 1 /01 1 7 121 1 1 1 1 3 10/ 1 /01 1 3 121 1 1 1 1 3 101 1 101 1 3 121 1 1 1 1 10 1211 101 7 101 1 101 1 3 1 1 / 1 1 1I 9 101 1 /01 13 1111111

9-23

9.2.1 1 Single Operand Instructions The s i ng l e operand i nstructions table i n d i cates the n u mber of clock periods needed for the processor to perform the specif ied operat ion on the g iven addressi n g mode. Foot notes i n d icate w hen i t is necessary to add another table entry to calcu late the total effec t ive execution t i m e for the i nstruction. The total n u m ber of clock cycles is outside the parentheses, the n u mber of read, prefetch, and write cycles are g iven i nside the paren theses as (r/p/w). They are i ncl uded in the total clock cycle n u mber.
Instruction Best Case
a a

Cache Case

Worst Case

# #

CLR CLR NEG NEG NEGX NEGX NOT NOT EXT NBCO Sec Scc TAS TAS TST

On Mem On Mem On Mem On Mem On On On Mem On Mem EA

3 3

3 1 6 1 6 1 12
a

10/0/01 10/01 1 1 10/0/01 10/0/ 1 1 10/0/01 10/01 1 1 10/0/01 10/01 1 1 10/0/01 10/0/01 10/0/01 10/01 1 1 10/0/01 1 1 /01 1 1 10/0/01

2 4 2 4 2 4 2 4 4 6 4 6 4 12 2

10/0/01 10/0/ 1 1 10/0/01 10/01 1 1 10/0/01 10/01 1 1 10/0/01 10/01 1 1 10/0/01 10/0/01 10/0/01 10/0/ 1 1 10/0/01 1 1 /01 1 1 10/0/01

3 6 3 6 3 6 3 6 4 6 4 6 4 13 3

10/ 1 /01 101 1 1 1 1 101 1 /01 101 1 1 1 1 10/ 1 /01 10/ 1 1 1 1 101 1 /01 101 1 1 1 1 10/ 1 /01 1011 /01 101 1 /01 101 1 1 1 1 1011 /01 11/1/11 101 1 /01

Add Fetch Effective Address time Add Calculate Effective Address time

9_2.1 2 Shift/Rotate Instructions The s h ift/rotate i nstruct ions table i n d i cates the n u mber of clock periods needed for the processor to perform the specifi ed operat ion o n the g iven addressi n g mode. Footnotes i nd icate when it is necessary to add another table entry to calculate the total effective execution t i me for the i nstruction. The nu mber of bits sh ifted does not affect execu tion t i me. The total n u m ber of clock cyc les i s outside the parentheses, the n u m ber of read, prefetch, and write cycles are g iven i nside the parentheses as (r/p/w). They are i ncl uded i n the total clock cyc le n u m ber.

9-24

I nstruction

Best Case

Cache Case

Worst Case

* *

* *

* *

lS l lSR lSl lSR lSl lSR ASl ASR ASl ASR ROl ROR ROl ROR ROXl ROXR ROXd

On I Staticl On I S tatiel On ! Dynamiel On I Dynamic) Mem by 1 Mem b y 1 On On Mem by 1 Mem by 1 On On Mem by 1 Mem by 1 On On Mem by 1

1 1 3 3 5 5 5 3 6 5 5 5 7 7

(01010) (01010) (01010) (01010) (010/ 1 ) 10/0/ 1 ) (01010) (01010) (010/ 1 ) 1010/ 1 ) 1010/01 (01010) 10/0/ 1 ) 1010/ 1 1 9 10/0/01 9 1010/01 5 1010/ 1 )

4 4 6 6 5 5
8

6 6 5 8 8 7 7 12 12 5

(01010) (01010) (01010) (01010) 1010/ 1 ) 1010/ 1 ) (01010) 1010/01 1010/ 1 ) 1010/ 1 1 1010/01 1010/01 10/0/ 1 ) 1010/ 1 ) (01010) 1010/01 1010/ 1 )

10/ 1 101 10/ 1 101 10/1 10) 10/1 101 10/ 1 / 1 ) 10/ 1 / 1 1 8 10/1 10 6 10/ 1 101 7 10/ 1 / 1 ) 6 10/ 1 1 1 1 8 (0/ 1 /0) 8 10/ 1 10) 7 10/ 1 / 1 ) 7 10/ 1 / 1 ) 1 2 10/ 1 101 12 10/ 1 101 6 10/ 1 / 1 )

4 4 6 6 6 6

Add Fetch Effective Address time Is direction of shiftl rotate; l or R

9.2.1 3 Bit Manipulation I nstructions The b i t manipu lation i nstructions table i n d i cates the n u mber o f c lock periods needed for t he processor to perform the s pecif ied bit operation on the g iven addressing mode. Foot notes ind icate when it is necessary to add another table entry to calcu late the total effec tive execut ion time for the i n st ruction. The total n u mber of c lock cyc les is outside the parentheses, the n u m ber of read, prefetch, and w rite cyc les are g iven i nside the paren theses as (r/p/w). They are i nc l uded in the total c lock cycle n u mber.
Instruction Best Case Cache Case Worst Case

* * *

* * *

* * *

* * *

BTST BTST BTST BTST BCHG BCHG BCHG BCHG BClR BClR BClR BClR BSET B SET B S ET BSET

# < data > ,On On,On # < data > , Mem On, Mem # < data> ,On On,On # < data > , Mem On, Mem # < data > ,On On,On # < data > , Mem On, Mem # < data > ,On On,On # < data > , Mem On, Mem

1 1 4 4 1 1 4 4 1 1 4

1010/01 (01010) (01010) 1010/01 (01010) (01010) 1010/ 1 1 1010/ 1 ) (01010) (01010) 1010/ 1 ) 4 1010/ 1 1 1 1010/01 1 1010/01 4 1010/ 1 ) 4 1010/ 1 )

4 (01010) 4 (01010) 4 1010/01 4 101010) 4 (01010) 4 101010) 4 1010/ 1 ) 4 1010/ 1 ) 4 1010/01 4 1010/01 4 1010/ 1 ) 4 (010/ 1 ) 4 (01010) 4 1010/01 4 1010/ 1 1 4 1010/ 1 )

5 5 5 5 5 5 5 5 5 5 5

10/ 1 10) 10/ 1 101 10/ 1 10) (01 1 /0) 10/ 1 10) 10/ 1 10) 10/ 1 / 1 ) 10/ 1 / 1 ) 10/ 1 10) 10/ 1 10) 10/ 1 / 1 ) 10/ 1 / 1 1 5 10/ 1 101 5 (0/ 1 /0) 5 10/ 1 / 1 1 5 10/ 1 / 1 )
5

Add Fetch Effective Address time Add Fetch Immediate Address time

9-25

9.2. 1 4 Bit Field M anipulation Instructions The bit field manipu lation i nstructions table i nd icates the n u mber of c lock periods need ed for t he processor to perform the s pecified bit field operat ion using the g iven add ress i n g mode. Footnotes i nd i cate when it is necessary to add another table entry to calcu late the total effective execution time for the i nstruction. The total nu mber of c lock cyc les is outside the parentheses, the n u m ber of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are i ncl uded in the total c lock cycle number.
I nstruction Best Case Cache Case Worst Case 7

#. #.
h

#.

#. #. #. #.

h Add Calculate Immediate Address time NOTE: A bit field of 32 bits may span 5 bytes that requires two operand cycles to access, or may span 4 bytes that requires only one operand cycle to access.

BFTST B FTST BFTST B FCHG B FCHG BFCHG BFCLR BFCLR BFCLR BFSET BFSET BFSET BFEXTS BFEXTS BFEXTS B FEXTU B FEXTU B FEXTU BFINS BFINS BFINS B FFFO BFFFO BFFFO

Dn Mem 1 < 5 bytesl Mem 15 bytesl Dn Mem 1 < 5 bytesl Mem 1 5 bytesl Dn Mem 1 < 5 bytesl Mem 15 bytesl Dn Mem 1 < 5 bytesl Mem 15 bytesl Dn Mem 1 < 5 Bytesl M E M 15 Bytesl Dn Mem 1 < 5 Bytesl Mem 15 Bytesl Dn M e m 1 < 5 Bytesl M e m 15 Bytesl Dn Mem 1 < 5 Bytesl Mem 1 5 Bytesl

3 11 15 9 16 24 9 16 24 9 16 24 5 13 18 5 13 18 7 14 20 15 24 32

1010101 1 1 /0101 12/0/01 1010101 1 1 /0/ 1 1 12/0/21 1010101 1 1 /0/ 1 1 12/0/21 1010101 1 1 /0/ 1 1 12/0/21 1010/01 1 1 /0101 12/0101 1010101 1 1 /0101 12/0/01 1010101 1 1 /0/ 1 1 12/0/21 1010/01 1 1 10101 12/0101

6 11 15 12 16 24 12 16 24 12 16 24 8 13 18 8 13 18 10 14 20 18 24 32

1010101 1 1 /0101 12/0101 1010101 1 1 /0/ 1 1 12/0/21 10/0/01 1 1 /0/ 1 1 12/0/21 1010101 1 1 /0/ 1 1 12/0/21 1010101 1 1 /0/01 12/0101 1010/01 1 1 /0101 12/0101 1010101 1 1 /0/ 1 1 12/0/21 1010101 1 1 /0/01 (2/0/01

12 16 12 16 24 12 16 24 12 16 24 8 13 18 8 13 18 10 15 21 18 24 32

10/ 1 /01 1 1 / 1 /01 12/1 /01 10/ 1 /01 11I1111 12/0/21 10/ 1 101 11/1/11 12/0/21 10/ 1 101 11/1/11 12/0/21 10/ 1 /01 11 I 1 101 12/1 /01 10/ 1 /01 1 1 / 1 /01 12/1 /01 10/ 1 /01 11/1/11 12/1 121 10/ 1 /01 1 1 / 1 /01 12/1 /01

9.2. 1 5 Conditional Branch Instructions The cond itional branch i nstructions table i nd i cates the n u mber of c lock periods needed for the processor to perform the s pecified branch on t he g iven branch s ize, with com plete execution ti mes g iven. No add itional tables are needed to calcu late total effective execu tion t i me for these i nstruct ions. The total n u m ber of c lock cyc les is outside the paren theses, the n u m ber of read, prefetch, and w rite cyc les are g iven i nside the parentheses as (r/p/w). They are i n c l uded in the total c lock cycle number.
I nstruction Best Case Cache Case Worst Case

Bcc (takenl Bcc. B Inot takenl Bcc.W (not takenl Bcc.L I not takenl DBcc Icc= false, count not expiredl D8cc (cc = false, count expiredl DBcc ( cc = truel

10/0/01 (0/0/01 10/0/01 10/0/01 10/0/01 7 (0/0/01 3 (0/0/01

3 1 3 3 3

6 4 6 6 6 10 6

10/0/01 10/0/01 (010/01 10/0/01 10/0/01 (0/0/01 10/0/01

9 (0/2/01 5 (0/ 1 101 7 10/1 101 9 10/2/01 9 1012101 10 10/3/01 7 (0/ 1 101

926

9.2.1 6 Control Instructions The control i nstructions table i nd icates the n u m ber of c lock periods needed for the pro cessor to perform the s pecified operation. Footnotes specify when it is necessary to add an entry from another table to calcu late the total effective execution t i me for the g iven in struction. The total n u m ber of c l ock cycl es is outside the parentheses, the n u mber of read, prefetch, and w rite cycles are g iven ins ide t he parentheses as (r/p/w). They are i n c l uded i n the total c lock cyc le n u mber.

Instruction

Best Case

Cache Case

Worst Case

ANDI to S A EOAI t o S A O A I t o SA ANDI to CCA EOAI to CCA O A I to CCA BSA CALLM Itype 01 CALLM Itype 1 1 - no stack copy CALLM I type 1 1 - no stack copy CALLM Itype 1 1 - stack copy , . CAS Isuccessful comparel CAS lunsuccessful comparel CAS2 Isuccessful comparel CAS2 l unsuccessful comparel CHK CHK2 EA, A n % JMP % JSA LEA # LlNK.w LlNK . L NO P # PEA RTD Itype 01 ATM Itype 1 1 ATM ATA ATS UNLK
* * * * * * * * * * *

10/0/01 10/0/01 10/0/01 10/0/01 10/0/01 10/0101 10/01 1 I 12/0/61 48 15/0/81 55 16/0/81 63 + 6n 1 7 + n/0/ 8 + nl 15 1 1 /01 1 1 1 2 1 1 /0101 23 12/0/21 1 9 12/0/01 8 10/0/01 16 12/0/01 1 10/0/01 3 10/0/ 1 1 2 10/0/01 3 10/0/ 1 1 4 10/01 1 1 2 10/0/01 3 1010/ 1 1 9 1 1 10/01 18 14/0/01 31 16/0/ 1 I 13 12/0/01 9 1 1 /0/01 5 1 1 /0/01

9 9 9 9 9 9 5 28

12 10/0/01 12 10/0/01 12 10/0/01 12 10/0/01 12 10/0/01 12 1010/01 7 10/01 1 I 30 12/0/61 50 15/0/81 57 16/0/81 65 + 6n 17 + n/0/ 8 + nl 1 5 1 1 /01 1 1 12 1 1 10/01 25 12/0/21 22 12/0/01 8 10/0/01 1 8 12/0/01 4 10/0/01 5 10/0/ 1 1 2 10/0/01 5 10/011 I 6 10/0/ 1 1 2 10/0/01 5 10/01 1 I 10 1 1 /0/01 19 14/0/01 32 16/01 1 I 14 12/0/01 10 1 1 /0/01 6 1 1 /0/01

10/2/01 10/2/01 10/2/01 10/2/01 10/2/01 10/2/01 10/21 1 I 36 12/2/61 56 15/2/81 64 16/2/81 7 1 6n 17 + n/2/8+ nl 16 1111111 13 1 1 1 1 101 28 12/2/21 25 12/2/01 8 101 1 /01 18 12/1 /01 7 10/2/01 1 1 10/2/ 1 1 3 101 1 101 7 101 1 / 1 1 10 10/211 I 3 101 1 101 6 101 1 / 1 1 12 1 1 /2/01 22 14/2/01 35 16/21 1 I 15 12/2/01 12 1 1 / 2/01 7 1 1 1 1 101

15 15 15 15 15 15 13

number of operand transfers required Add Fetch Effective Address time Add Calculate Effective Address time % Add J ump Effective Address time Add Fetch Immediate Address time ,. Add Calculate Immediate Address time

9-27

9.2.1 7 Exception Related Instructions

The except ion related i nstruct ions table i nd i cates the nu mber of clock periods needed for the processor to perform the specified exception related act ion. Footnotes s pec ify when it is necessary to add the entry from another table to calcu late the total effective execution time for the g iven i nstruction. The total n u mber of c lock cyc les is outside the parentheses, the n u m ber of read, prefetch, and write cyc les are g iven ins ide the paren theses as (r/p/w). They are i n c l uded in the total clock cyc le n u m ber.
I nstruction Best Case Cache Case Worst Case

B K PT Interrupt II-stack) Interrupt 1 M-stack) R ES ET Instruction STOP Trace TRAP #n Illegal Instruction A-Line Trap F-Line Trap Privilege Violation TRAPcc Itrap) TRAPcc Ino trap) TRAPcc.W Itrap) TRAPcc.W Ino trap) T RAPcc.L Itrap) T RAPcc.L I no trap) TRAPV Itrap) TRAPV Ino trap)

9 26 41 518 8 25 20 20 20 20 20 23 1 23 3 23 5 23 1

1 1 /010) 12/0/4) 12/0/8) 101010) 101010) 1 1 /0/5) 1 1 10/4) 1 1 10/4) 1 1 / 0/4) 1 1 /0/4) 1 1 /0/4) 1 1 /0/5) 101010) 1 1 /0/5) 101010) 1 1 /0/5) 101010) 1 1 /0/5) 101010)

10 26 41 518 8 25 20 20 20 20 20 25 4 25 6 25 8 25 4

1 1 /010) 12/0/4) 12/0/8) 101010) 1010/01 1 1 /0/5) 1 1 /0/4) 1 1 /0/4) 1 1 /0/4) 1 1 /0/4) 1 1 /0/4) 1 1 /0/5) 101010) 1 1 /0/5) 1010/01 1 1 /0/5) 101010) 1 1 /0/5) 1010/01

10 1 1 /0/01 33 12/2/4) 48 12/2/8) 519 10/ 1 /01 8 1010/01 32 1 1 12/5) 27 1 1 12/4) 27 1 1 /2/4) 27 1 1 /2/4) 27 1 1 /2/4) 27 1 1 /2/4) 32 1 1 / 2/5) 5 101 1 /01 33 1 1 /3/5) 7 101 1 /0) 33 1 1 /3/5) 10 10/2/0) 32 1 1 /2/5) 5 10/ 1 /0)

9.2. 1 8 Save and Restore Operations

The save and restore operat ions table i nd icates the n u m ber of c lock periods needed for the processor to perform the s pec i f ied state save, or return from except ion, with com p lete execution t i mes and stack length g iven. No add itional tables are needed to calcu l ate total effective execution time for these operat i ons. The total n u mber of clock cyc les is outside the parent heses, the n u mber of read, prefetch, and w rite cycles are g iven i nside the parent heses as (r/p/w). They are i nc l uded in the tota l c lock cyc le number.

Operation

Best Case

Cache Case

Worst Case

Bus Cycle Fault I S hort) Bus Cycle Fault I Long) RTE I Normal! RTE ISix-Word) RTE !Throwaway) * R T E l Coprocessor) RTE I Short Fault! RTE I Long Fault) * Add the time for RTE on second stack frame.

42 79 20 20 15 31 42 91

1 1 /0/ 10) 1 1 /0/24) 14/010) 14/010) 141010) 17/0/01 ( 1 0/010) 124/010)

43 79 21 21 16 32 43 92

1 1 /01 10) 1 1 /0/24) 14/010) 14/0/01 14/010) (7/010) 1 1 0/0/01 124/010)

50 86 24 24 39 33 45
94

1 1 /21 101 1 1 /2/24) 14/2/01 1412/0) 14/0/01 (71 1 10) 1 1 012/01 124/2/0)

9-28

S ECTI O N 1 0 ELECT RICAL SPECI FICATIONS

T h i s section conta i n s electrical specifications a n d associated t i m i ng i nformat ion for the MC68020. 1 0.1 MAXI M U M RATI NGS
Rating Symbol Value Unit

Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range

V CC V in TA T stg

- 0.3 to + 7.0 - 0.3 to + 7.0 o to 70 - 55 to 1 50

V V c c

This device contains protective circuitry against damage due to high static voltages or electrical fields; however. it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g . . either GND or V CC I .

1 0.2 TH ERMAL CHARACTERISTICS - P G A PACKAG E

Characteristic Symbol Value Rating

Thermal Resistance - Ceramic Junction to Ambient Junction to Case * Estimated

8JA 8J C

30* 15*

C/W

1 0.3 POWER CONSIDERATIONS The average c h i p-j u nction tem perat ure, TJ , i n C c a n b e obta i ned from: TJ = TA + (P O -OJ A) Where: TA = Ambient Temperatu re, C OJ A = Package Thermal ReSistance, J unction-to-Ambient, C/W Po = P I N T + P lIO P I NT = I CC x V CC , Watts - Chip I nternal Power P lIO = Power Dissipat ion on I n put and Output Pins - User Determi ned For most appl ications P I/O < P I N T and can be neg lected. (1)

An approxi mate re lations h i p between Po and TJ (if P lIO is neglected) is: P O = K + J + 2n o q Solvi ng equations 1 and 2 for K gives: (3) K = P O -(TA + 273 q + OJ A - P 02 Where K is a constant pertai n i ng to the particular part. K can be determ i ned from eq ua tion 3 by meas u r i n g Po (at eq u i l i brium) for a known TA . U s i n g this value of K the values of Po and TJ can be obtai ned by solving equations ( 1 ) and (2) iterat ively for any value of TA 1 0-1

The total thermal res i stance of a package (OJ A) can be separated i nto two components, OJ C and OCA , representing the barrier to heat f low from the sem iconductor j u nction to the package (case) su rface (OJ C) and from the case to the outside am bient (O CA). These terms are related by the equation: (4) OJ A = OJ C + O CA OJ C is device rel ated and can not be i n f l uenced by the u ser. H owever, O CA is u ser depen dent and can be m i n i m ized by such thermal management tec h n i q ues as heat sinks, am bient a i r coo l i n g and thermal convention. Thus, good t hermal management on the part of the user can s i g n ificantly reduce O CA so that OJ A approx i mately equals OJ C . Substitut ion of OJ C for OJ A in equat ion (1) w i l l resu l t in a l ower sem i conductor j u nct ion tem perat ure. Values for thermal res i stance presented in t h i s data sheet, u n less est i mated, were de rived using the proced u re descri bed in M otorola Reliabil ity Report 7843, "Thermal Resi stance Measurement M ethod for MC68XX M icrocomponent Devices," and are pro vided for desi g n pu rposes on ly. Thermal measurements are complex and dependent on procedu re and setup. User derived values for thermal res i stance may differ. 1 0.4 DC ELECTRICAL CHARACTERISTICS (V CC = 5.0 Vdc 5 % ; V SS = O Vdc, TA = O to 70 C; see Figures 1 0-1 , 1 0-2, and 1 0-3)
Characteristic Symbol

Input High Voltage I nput low Voltage Input leakage Current V S S :s V i n :S V CC

II

Hi-l 1 0 ff-Statel leakage Current @ 2.4 V /0.5 V Output High Voltage 10 H = - 400 p.A Output low Voltage 10 l = 3. 2 mA AO-A31 , FCO-FC2, SilO-S i l l , B G , 00-031 10 l = 5.3 mA AS, O S R/ W, RMC, OBEN, IPEND I Ol = 2.0 mA ECS, OCS 10 l = 10.7 mA HALf, R ESET Power Dissipation IT A = OCI Capacitance Isee Note 1 1 V in = O V, T A = 25C, f = l MHz NOTE: Capacitance is periodically sampled rather than 100% tested.
,

B E RR . BGACK. ClK. IPLO-ru. AVEC. COIS. OSACKO. OSACKl HALT, R ES ET AO-A31 , AS, OBEN, OS, 00-031 , i FCO-FC2, R / ii , RMC, SilO-Sill AO-A31 , AS, im, 00-031 , OBEN, [)S, ECS, R/iN, I PENO, OCS, RMC, SilO-Sill , FCO-FC2

V IH Vi l l in I TS I VO H V OL Po C in

2.0 - 0.5 - 2.5 - 20 - 20 2.4

-

Min

V CC 0.8 2.5 20 20
-

Max

Unit

V V p.A p.A p.A V V V V V W pF

0.5 0.5 0.5 0.5 1 .75 20.0

1.

+5V

+5V

420

420

l 30 PF

I
1 0-2

l 30 PF

Figure 1 01 . RESET Test Load

Figure 1 0-2. HALT Test Load

+5V

A*

MMD7000 or Equivalent

C l = 50 pF for ECS and OCS C l = 1 30 pF for All Other ( Includes all Parasiticsl A l = 6.0 kO * A = 1 .22 kO for AO-A31 , DO-D31 , B G , FCO-FC2, SilO-Sill A 2 kO for ECS, OCS A = 740 0 for AS , 55, A/W, AMC, DBEN, IPEND
=

Figure 1 03. Test Loads

1 0.5 AC ELECTRICAL SPECI FICATIONS - CLOCK I N PUT (See Figure 1 0-4)

MC68020AC12 Num Characteristic Symbol Min Max MC68020AC16 Min Max Unit

1 2, 3 4, 5

Frequency of Operation Cycle Time Clock Pulse Width Aise and Fall Times

f tcvc t Cl , t CH t Cr , t Cf

8 80 32
-

12.5 1 25 1 25 5

60

24
-

1 6.7 1 25 95 5

MHz ns ns ns

II

NOTE Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted. The voltage swing through this range should start outside, and pass through, the range such that the rise or fall will be linear between 0.8 volt and 2.0 volts.

Figure 1 04. Clock Input Timing Diagram

1 0-3

1 0.6 AC ELECTRICAL SPECI FICATIONS - READ AND WRITE CYCLES (VCC = 5.0 Vdc 5 % ; G N D = 0 Vdc; TA = 0 to 70 C; see Figures 1 0-5, 1 0-6, and 1 0-7)
MC68020RC12 MC68020RC16 Min Max Unit

Num 6 6A 7 8 9 9Al 10 lOA 1 16 12 12A 13 14 14A 15 16 1 76 18 20 21 6 226 23 256 266 27 27A 28 29 29A 31 2 3 1 A3 32 33
34

Characteristic

35 37 39 39A 40

Clock High to Address/ FC/ Size/ R MC Valid Clock High to ECS, OCS Asserted Clock High to Address, Data, FC, RMC, S ize H igh Im pedance Clock High to Address/ FC/ Size/ R MC Invalid Clock low to AS, DS Asserted AS to DS Assertion l Read) I S kew) ECS Width Asserted OCS Width Asserted Address/ FC/ Size/ R M C Valid to AS (and DS Asserted Read) Clock low t o A S , D S Negated Clock low 1 0 ECS/ OCS Negated AS, DS Negated t o Address, FC, Size Invalid AS land D S Read) Width Asserted OS Width Asserted Write AS, DS Width Negated Clock High to AS, OS, R/W, DBEN High Impedance AS, DS Negated 10 R/W High Clock High t o R/W High Clock High to R/W low R/W High to AS Asserted R/W low 10 DS Asserted IWrite) Clock High to Data Out Valid DS Negated to Data Out Invalid Data Out Valid to DS Asserted (Write) Data-In Valid to Clock low ( Data Setup) late BERR/HAl T Asserted to Clock low Setup Time AS, DS Negated to DSACKx, B E R R , HALT, AVEC Negated DS Negated to Data-In Invalid l Data-ln Hold Time) DS Negated to Data-In ( High Impedance) DSACKx Asserted to Data-In Valid DSACKx Asserted to DSACKx Valid I DSACK Asserted Skew) R ES ET Input Transition Time Clock low to BG Asserted Clock low to BG Negated BR Asserted to BG Asserted ( R M C Not Asserted) BGACK Asserted to BG Negated BG Width Negated BG Width Asserted Clock High to DBEN Asserted ( Read)

Symbol t C HAV tC HEV t CHAZx tC HAZn tC lSA t STSA t ECSA tOCSA tAVSA tcu N !Cli N t SNAI t SWA t SWAW tS N tcsz tS N R N tC H R H tCH Rl t RAAA t RASA t SNDI t DVSA t DICl t BElCl t SNDN tS N D I tS N D I t DADI t DADV t H Rrf tClBA tClBN t BRAGA tGAGN tG_ N t GA t C H DAR

Min

Max

0 0 0 0 3 - 20 25 25 20 0 0 20 1 20 50 50
-

40 30 80
-

0 0 0 0 3 - 15 20 20 15 0 0 15 100 40 40
-

30 20 60
-

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clk Per ns ns Clk Per Clk Per ns ns ns

40 20
-

30 15
-

40 40
-

30
-

30
-

80
-

60
-

l.GJ:!QQ

90
-

20 0 0 20

40 40
-

15 0 0 15 70
-

30
-

30
-

40
-

20 20 10 25 0 0
-

15 15 5 20 0 0
-

30
-

1 10
-

80 60 20 2.5 40 40 3.5 3.5

-

80 60 50 15
30

0 0 1 .5 1 .5 1 20 1 20 0

40

0 0 1 .5 1 .5 90 90 0

2.5

30 3.5 3.5
-

30

1 0-4

1 0.6 AC ELECTRICAL SPECI FICATIONS - READ AND WRITE CYCLES (Continued) (V CC = 5.0 Vdc 5 % ; G N D = 0 Vdc; TA = 0 to 70 C; see Figures 1 0-5, 1 0-6, and 1 0-7)
MC68020RC12 Num Characteristic Symbol Min Max M C68020RC16 Min Max

41 42 43 440 455 46 47a 47b 53 55 56 57

Clock Low to DB EN Negated I R eadl Clock Low to DB EN Asserted (Writel Clock High to DB EN Negated (Writel R / W Low to D B E N Asserted (Writel DBEN Width Asserted R/W Width Asserted (Write or Readl Asynchronous Input Setup Time Asynchronous Input Hold Time DSACKx Asserted to BERR . HALT Asserted Data Out Hold from Clock High R/W Asserted to Data Bus Impedance Change R ES ET Pulse Width ( R eset Instructionl B E R R Negated to HALT Negated I R erunl

t CLDNR t CLDAW t CHDNW Read Write

tRADA

t DA

48'l

t RWA tAIST tA I H T tDABA t DOCH t RADC t H R PW tB N H N

1 60 180 10 20
-

20 80

0 0 0

40 40 40
-

1 20 150 5 15
-

15 60

0 0 0

30 30 30
-

Un it

35
-

0 40 512 0

0 40 512 0

30
-

ns ns ns ns ns ns ns ns ns ns ns ns Clks ns

NOTES: 1 . This number can be reduced to 5 nanoseconds if strobes have equal loads. 2. If the asynchronous setup time (#471 requirements are satisfied, the DSACKx low to data setup time 1#3 1 1 and DSACKx low to BERA low setup time (#481 can be ignored. The data must only satisfy the data-in to clock low setup time (#271 for the following clock cycle, B E R R must only satisfy the late BERR low to clock low setup time (#27AI for the following cloc k 3. This parameter specifies the maximum allowable skew between DSACKO to DSACK 1 asserted or DSACK 1 to DSACKO asserted, specification #47 must be met by DSACKO or DSACK 1 4. In the absence of DSACi(X, B E R R is an asynchronous input using the asynchronous input setup time (#471. 5. i5'i3'EN may stay asserted on consecutive write cycles. 6. Actual value depends on the clock input waveform.

T i m i n g D i agrams ( F i g u res 1 0-5, 1 0-6, and 1 0-7) are located on foldout pages at the end of t h i s document.

1 0-5

1 0.7 AC ELECTRICAL CHARACTERISTICS - TYPICAL CAPACITANCE DERATING CU RVES F i g u res 1 08 t h rough 1 0 1 3 provide the capacitance derating cu rves for the M C68020. These graphs may not be l i near outside of range shown. Capac itance i nc ludes st ray capacitance.

20

40

60

60

100

1 20

140

160

180

200

220

240

260

C in IpFI

Figure 1 08. Address Capacitance Derating Curve

45 40 35 30
v;
c -

25 20 15 10 5
o

t CLSL 30 ns t CLSH 30 ns

20

40

60

60

100

1 20 140 C in IpFI

1 60

180

200

220

240

260

Figure 1 09. DS, AS, I P EN D, and BG Capacitance Derating Curve

1 0-6

45 40 35 30
v;
c:

25 20
15 10

t CLDNR . tC HDNW 30 ns t CHDAR . tCLDAW 30 ns

5
o

20

40

60

80

100

1 20 140 C in (pFI

160

180

200

220

240 260

Figure 1 0 1 0. DBEN Capacitance Derating Curve

45
40

30

35

... .... .... ....

_ .... ....

25 20
15

.... .... .... ....

..
-- - - t CHEV 20 ns -- t CLEN 30 ns

10 5
o

20

40

60

80

100

1 20 1 40 C in (pFI

1 60

180

200

220

240

Figure 1 01 1 . ECS and OCS Capacitance Derating Curve

1 07

45 40 35

Vi
-

30
25 20 15 10 5

.::

t C H R L 30 ns t C H R H 30 ns

20

40

60

80

100

120

140

160

180

200

220

240

260

C in IpFI

Figure 1 0 1 2. RIW, FC, SIZOSIZ1 , and RMC Capacitance Derating Curve

45 40 35

Vi
c

30
25 20 15 10 5

t CHDH 30 ns t CHDL 30 ns
200

20

40

60

80

100

1 20

140

160

180

220

240

260

C in IpFI

Figure 1 01 3. Data Capacitance Derating Curve

1 08

S ECTION 1 1 O R D E R I N G I N FO RMATION A N D M ECHANICAL DATA

This section contai n s the p i n assignments and package d i mensions of the MC68020. I n add ition, detai led i nformat ion i s p rovided t o be used a s a g u ide when ordering.
1 1 .1 STANDARD MC68020 O RDERING I N FORMATION

Package Type P i n G rid A rray RC Suffix

Frequency (MHz) 1 2.5 1 6.7

Temperature O C to 70 C O C t o 70 C

Order Number MC68020RC 1 2 MC68020RC16

1 1 -1

1 1 .2 PACKAGE DIM ENSIONS AND PIN ASSI G N M ENT

M C68020 R C S uffix Package

DIM A C DO

MILLIMETERS

INCHES MIN 1 . 345 1 . 345 . 1 00 .0 1 7 . 1 70 .065 MAX 1 .3 7 5 1 .375 . 1 50 .019 . 1 90 .095

Preli m i na ry Mechanical Detail

B G K V

MIN 34. 1 8 34. 1 8 2.67 .46 4.32 1 .74

MAX 34.90 34.90 3. 1 7 .51 4.82 2.2B

2 . 5 4 BSe

. 1 00 BSe

Top View

1
A

II-.

------+I

1 1 -2

Pin Number

Function

Pin Number

Function

Pin Number

Function

A1 A2 A3 A4 A5 A6 A7 A8 A9 AlO Al l A12 A13

BGACK A1 A31 A28 A26 A23 A22 A19 VCC GNO A14 All A8

01 02 03 04-01 1 012 013 E1 E2 E3 E12 E13

VCC VCC VCC

-

A4 A3 FCO RMC VCC A2 OCS

K1 K2 K3 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L1 1 L1 2 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13

A30 A27 A24 A20 A18 GNO A15 A13 A10 A6

BG SA

GNO

F1 F2 F3 F12 F13

SIZO FC2 FC1 GNO IPENO

R/IN 030 027 023 019 GNO 015 011 07 GNO 03 02 OS 029 026 024 021 018 016 VCC 013 010 06 05 04 031 028 025 022 020 017 GNO VCC 014 012 09 08 VCC

AS

GNO HALT GNO 01 DO

G1 G2 G3 G11 G12 G13

ECS SIZ1 OBEN VCC GNO VCC

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13

RESET CLOCK GNO AO A29 A25 A21 A17 A16 A12 A9 A7 A5

H1 H2 H3 H12 H13

COIS A V EC OSACKO I P L2 GNO

J1 J2 J3 J12 J13

iPLT

OSAC K 1 BERR GNO I P LO

The Vee and G N D p i n s are separated i nto t h ree groups to provide i ndividual power su pply connections for the address bus buffers, data bus buffers, and a l l other output buffers and i nternal l og i c.
Group
VCC

GNO

Address 8us Data B u s Logic Clock

A9, 03 M 8 , N8, N 1 3 0 1 , 02, E3, G 1 1 , G 1 3

A 10, B9, C3, F 1 2 L 7 , L 1 1 , N 7 , K3 G 1 2 , H13, J 3 , K 1 B1

1 1 -3/1 1 -4

APPEN DIX A CON DITION CODES COMPUTATION

A.1 I NTRODUCTION This appendix provides a d iscussion o f how t h e con d ition codes were developed, the mea n i n g s of each bit, how t hey are computed, and how they are represented in the i n struction set detai ls. Two criteria were used i n developing the condition codes: Consistency - across i nstruction, u ses, and i nstances M ean i ng f u l Res u lts - no change u n less it provides usef u l i nformation The cons istency across i nstructions means that i nstructions which are spec ial cases of more general i nstructions affect the con d it i on codes in the same way. Consistency across i nstances means that if an i nstruction ever affects a condition code, it w i l l always affect that condition code. Consistency across uses means that whether the condition codes were set by a com pare, test, or move i nstruction, the cond itional i nstructions test the same situation. The tests u sed for the conditional i nstructions and the code com putations are g iven in paragraph A.5. A.2 CON DITION CODE REG ISTER The N Z V C X con d it i on code reg i ster portion of the status reg i ster contains five bits: - Negative - Zero - Overflow - Carry - Extend

The f i rst fou r bits are true condition code bits in that they reflect the condition of the res u l t of a processor operat ion. The X bit is an operand for m u l t i preci s ion computations. The carry bit (C) and the m u l t i prec ision operand extend bit (X) are separate i n the M68000 Fam i ly to s i m p l ify the programming model. A.3 CON DITION CODE REGISTER NOTATION In the i nstruction set detai l s g iven i n APPENDIX B, the desc ription of the effect on the condition codes i s g iven i n the follow i n g form: Cond ition Codes: X N Z V C

A-1

where: N (negat ive) Z (zero) V (overflow) C (carry)

X (extend)

Set if the most s i g n i fi cant bit of the resu l t is set. Cleared otherwise. ' Set if the resu l t eq uals ze ro. Cleared otherw ise. Set if there was an arithmet i c overflow. This i m p l ies that the resu l t is not representable in the operand s ize. Cleared otherwise. Set if a carry is generated out of the most s i g n ificant bit of the operands for an add ition. Also, set if a borrow i s generated in a su btract ion. Cleared otherwise. Tran sparent to data movement. When affected, by arithmetic opera tions, it is set the same as t he C bit.

The convention for the notation that i s used in the con d ition code reg i ster representation is: * set accord i n g to the res u l t of the operation not affected by the operation o cleared 1 set u ndefi ned after t he operat ion U A.4 CON DITION CODE COM PUTATION M ost operations take a source operand and a dest i nation operand, compute, and store the resu l t in the dest i nation location. U nary operat ions take a desti nation operand, com pute, and store the resu l t in the dest i nation location. Table A-1 detai l s how each i nstruc tion sets the condition codes. A.5 CON DITION TESTS Table A-2 l ists the cond ition names, encod i ngs, and tests for the condition branch and set i nstructions. The test associated with each cond ition i s a logical form u l a based on the cu rrent state of the condition codes. If this formula evaluates to one, the condition su cceeds, or i s true. I f the form u l a eval u ates to zero, the condition i s u nsuccessful, or false. For example, the T condition always succeeds, w h i le the EQ condition succeeds o n ly if the Z bit is cu rrently set in the condition codes .

A-2

Table A1 . Condition Code Computations

Operations X

ABCD ADD, ADDI, ADDO ADDX AND, ANDI, EaR, EaRl, MOVEO, MOVE, OR, O R I , CLR, EXT, N O T , T A S , TST CHK CHK2, CMP2 S U B , S U B I , SUBO SUBX CAS, CAS2, CMP, CMPI, CMPM DIVS, DIVU MULS, M U LU SBCD, NBCD N EG N EGX BTST, BCHG, B S ET, BCLR BFTST, BFCHG, BFSET, BFCLR BFEXTS , BFEXTU, BFFFO BFINS ASL A S L I r = OI LSL, ROXL LSR I r = OI ROXL I r = OI ROL ROL I r = OI A S R , LSR, ROXR A S R , LSR I r = OI ROXR I r = OI ROR ROR I r = OI U

C
, 7

U
, 7

0 U U
, 7 7 7 7

0 U
7 ,

C = S m fl DmVR m fl DmVS m fl R m fl RO Z = Z fl R m fl

C = Decimal Carry fI RO Z = Z fl Rm fl V = S m fl Dm fl RmVS m fl Dm fl Rm C = Sm fl DmVRm fl DmVSm fi R m V = Sm fl Dm fl R mVS m fl Dm fl Rm

Special Definition

?
7

0 0
? 7 -

U
7 7

7 ?

?
7 7

0 0 0
,

0 0 0
7

?
7

Z = I R = LBI V I R = U B I c = I L B < = U B I fl I I R < L B I V I R > U B I IV I U B < LBI fl I R > U B I fl I R < LBI V= Sm fl Om fl R mVSm fl Dm fl R m C = S m fl DmVRm fl DmVSm fl R m V = Sm fl Dm fl RmVSm fl Dm fl Rm C = Sm fI DmVRm fI DmVSm fI R m fI RO Z = Z fl R m fl V = Sm fl Dm fl R mVSm fl Dm fl Rm C = S m fl DmVRm fl DmVSm fl Rm V = Division Overflow V = Multiplication Overflow C = Decimal Borrow fl RO Z = Z fl Rm fl V = Dm fl Rm, C = DmVRm V = Dm fl R m, C = DmVRm Z = Z fl Rm fl . fI RO Z= On N = Dm Z = Dm fl Dm- 1 f1 . fl DO N = Sm Z = Sm fl S m - 1 f1 fI SO N = Dm Z = Dm fl Dm - 1 f1 . fl DO V = Dm fl l Dm - l V . . VDm - rlVOm fl l D m - l V . C = Dm - r + 1 C = Dm - r + 1 C=X C = Dm - r + 1 C = Dr - 1 C=X C = Dr - 1
R

+ Dm - ri

0 0 0 0 0 0 0 0 0 0 0

0 ? 0
7 7 7 7

0 0 ? 0

Sm Om

Not Affected Undefined, result meaningless Other - See Special Definition General Case X= C N = Rm Z = Rm fl . fl RO Source Operand - most significant bit Destination Operand - most significant bit

Rm n LB UB V Rm

Result Operand - most significant bit Register Tested Bit Number Shift Count Lower Bound Upper Bound Boolean AND Boolean OR NOT R m

A3

Table A2. Conditional Tests

Mnemonic Condition Encoding Test

T* F* HI LS CCIHSI C S I LOI NE EO VC VS PL MI GE LT GT LE
=

True False High Low or Same Carry Clear Carry Set Not Equal Equal Overflow Clear Overflow Set Plus Minus G reater or Equal Less Than Greater Than Less or Equal

0000 000 1 0010 001 1 0100 0101 0110 01 1 1 1000 1001 1010 101 1 1 100 1 101 1 1 10 1111

1 0 CZ C+Z
Z C

Z V V N N NV + N . V N V + N.V N . V . Z + N VZ Z + N.V+ NV

Boolean ANO Boolean OR N Boolean NOT N

= =

Not available for the Bee instruction

A4

APP EN DIX B I NST RUCTION SET D ETAI LS

B.1 I NTRODUCTION This appen d i x conta i n s detai led i nformat ion about each i nstruction in the M C68020 i n struction set. They are arranged i n a l phabetical order with the mnemonic head i n g set i n l arge bold type for easy reference. B.2 ADDRESSING CATEG O R I ES Effective add ress modes may be categorized by the ways i n which they may be u sed. The follow i n g classifications w i l l be used in the i nstruction def i n itions. Data Memory I f an effective address mode may be u sed to refer to data operands, it i s considered a data add ress i n g effective address mode. If an effective add ress mode may be u sed to refer to memory operands, it is considered a memory address i n g effective add ress mode. If an effective add ress mode may be used to refer to a lterable (writeable) operands, i t i s considered a n alterable addressing effec tive add ress mode. If an effective address mode may be used to refer to memory operands without an associated s ize, it is considered a control ad d ressi n g effective address mode.

Alterable

Control

Table 8-1 shows the various categories to which each of the effective add ress modes belong.

8-1

Table B1 . Effective Addressing Mode Categories

Assembler Syntax

Address Modes

Mode

Register

Data

Memory
-

Control
-

Alterable

Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Address Register Indirect with Index IS-Bit Displacement! Address Register Indirect with Index I Base Displacementl Memory Indirect Post-Indexed Memory Indirect Pre-Indexed Absolute S hort Absolute Long Program Counter Indirect with Displacement Program Counter Indirect with Index IS-Bit Displacement! Program Counter Indirect with Index I Base Displacement! PC Memory Indirect Post-Indexed PC Memory Indirect Pre-Indexed Immediate

000 001 010 01 1 1 00 101 1 10 1 10 1 10 1 10 111 111 111 111 111 111 111 111

reg. no. reg. no. reg. no. reg. no. reg. no. reg. no reg. no. reg. no. reg. no. reg. no. 000 001 010 01 1 01 1 01 1 01 1 100

X
-

X X X X X X X X X X X X X X X X

X X X X X X X X X X X X X X X X

X
-

X X X X X X X X X X X X
-

On An IAnl IAnl + - IAnl Id 16 .Anl Ids,An,Xnl I bd,An,Xnl I [ bd,Anl.Xn,odl I [ bd,An,Xnl.odl Ixxxl. W Ixxxl . L Id 1 6 ,PCI Ids,PC,Xnl Ibd,PC,Xnl I[bd,PCl.Xn,odl I[bd, PC,Xnl.odl # < data >

X X X X X X X X X X X X
-

These categories may be combi ned so that add itional, more rest rict ive, c l assifications may be defi ned. For example, the instruction desc riptions use such c lassifications as a lterable memory or data alterable. The former refers to those address i n g modes which are bot h alterable and memory addresses, and the l atter refers to addressing modes which are bot h data and alterable .

82

B.3 I NSTRU CTIO N DESC R I PTION The formats of each i nstruction are g iven i n the follow i n g pages. F i g u re B1 i l l ustrates w hat i nformation is g iven.
------.+-

I nstruction Name

O peration Description --- Opera tion: (see para grap h B.4) -Assem bler Syntax for t h i s I nstruction
_

ABeD

Add

- .... Assembler _ -

Source 1 Q + DestinatiOl ABCD DY,Dx ABCD - (Ay), - (Ax) Size = (Byte)

Syntax:

Attributes:

Text Desc ription of I nstruct ion Operation

Description: Add the source operar

2.
Cond ition Code Effects (see Appendix A)

--------i_ Condition x

bit, and store the result i n the d binary coded decimal arithmeti ways: 1. Data register to data registe, specified in the i nstruction. M e mory to memory: The oper ing mode using the address I This operation is a byte operati
Codes:
N z V c

* ! u ! *! u ! *!
I nstruction Format - Spec ifies the bit pattern and fields of the operat ion word and any other words which are part of the i nstruction. The ef fect ive add ress extensions are not expl icitly i l l u strated. T h e extensions (if there are a ny) would fol l ow the i l l u st rated port ions of the i nstructions. For the MOVE i n struction, the sou rce effective add ress extension is the f i rst, fol lowed by the dest i nation effect ive address extension.
N Z V
X

Undefined. Cleared if the result is n Undefined. Set if a carry (decimal) '" Set the same as the can

Normally the Z conditior an operation. This allows multiple-precision opera

Instruction Format:
15 14 13 12 11 Register Ax 10

Instruction Fields:

Meanings and a l l owed values of the various . . fIe Id s req u i red by t h e i n S t rue t Ion f ormat ;

Register Rx field - Specifies t If RIM = 0, specifies a data r! I f RIM = 1 , speCifies an addre RIM field _ Specifies the oper - The operation is data re 1 - The operation is memor

Figure B1 . I nstruction Description Format

B-3

B.4 OPERATION DESC RIPTION DEFINITIONS The fol lowi n g def i n itions are used for t he operation description i n the deta i l s of the i n struction set. OPERA N DS: An On An PC SA CCA SSP USP SP X Z V I m med i ate Data d Sou rce Dest i nation Vector ea address reg i ster data reg ister any data or address reg ister program counter statu s reg i ster cond ition codes (lower order byte of status reg ister) s u pervisor stack poi nter u ser stack poi nter active stack pOi nter (eq u ivalent to A7) extend operand (from condition codes) zero cond ition code overflow cond ition code i m med i ate data from the i nstruction address d i s pl acement sou rce contents desti nation contents l ocation of except ion vector any va l i d effective address

SUBFI ELDS AND a UALI FI ERS: selects a s i n g l e b i t o f t h e operand < bit > OF < operand > selects a bit field < ea > ( offsetw idth) ( < operand > ) the contents of the referenced l ocat ion the operand i s binary coded dec imal; operat ions are to be per < operand > 1 0 formed in decimal. the reg i ster i nd i rect operator which ind i cates that the address reg i ste r operand reg i ster pOints to the memory locat ion of the i nstruc - address reg i ster tion operand. The optional mode q u a l i f iers are - , + , (d) and address reg ister + (d, ix); these are explai ned in SECTION 2 DATA O RGAN IZA TION AND ADDRESSI NG CAPABI LITI ES. i m med i ate data located with the i nstruct ion is the operand. #xxx or # < dat a >

8-4

OP ERATIO NS: Operat ions are grou ped i nto binary, u nary, and other. Binary- These operati ons are w ritten < operand > < op > < operand > w here < op > i s o n e o f t h e following: the left operand is moved to the right operand the two operands are exchanged the operands are added t he right operand is su btracted from t he left operand the operands are m u l t i p l ied the f i rst operand i s divided by the second operand the operands are logically A N Oed the operands are logica l l y O Red t he operands are logical l y exclus ively ORed relational test, true if left operand is less than right operand relational test, true if left operand is g reater t han right operand the left operand is shifted or rotated by the n u mber of pos ition s specified b y t h e r i g h t operand

I 1\ V

< > shifted by rotated by

Unary: the operand is logica l ly complemented - < operand > < operand > s i g n-extended the operand is s i g n extended, a l l bits of t he u pper portion are made eq ual to high order bit of t he lower portion t he operand is com pared to 0, the resu lts are used to set < operand > tested t he cond ition codes Other: TRAP STOP eq u ivalent to Format/Offset Word - (SSP); SSP - 2 - SSP; SSP - 4 - SS P; SR - (SSP); SSP - 2 - SS P; (vector) - PC enter the stopped state, waiting for i nterru pts PC - (SSP);

If < cond ition > then < operations > else < operations > . The cond ition is tested. If true, t he operat ions after the "then" are performed. I f the cond ition i s false and the optional "else" clause i s present, the operat ions after the "else" are performed. I f the condi tion i s false and the optional "else" c lause is absent, the i nstruction performs no operat ion.

8-5

ABCD
Operation: Assembler Syntax: Attributes:

Add Decimal with Extend Sou rce 1 Q + Dest ination 1 0 + X Size = (Byte) ABCD DY,Dx ABCD - (Ay), - (Ax) Dest ination

ABCD

--

Description: Add the sou rce operand to the dest i nation operand along with the extend bit, and store the resu l t in the dest i nation locat ion. The add it ion i s performed using bi nary coded dec i mal arithmetic. The operands may be add ressed i n two d i fferent ways: 1 . Data reg i ster to data reg i ster: The operands are contai ned in the data reg i sters specified in the i nstruct ion. 2. M emory to memory: The operands are add ressed with the predec rement address i n g mode u s i n g the add ress reg i sters specif ied in the i nst ruct ion. This operation i s a byte operation only. Condition Codes:
x

l u l * l u l * 1
U ndefi ned. Cleared if the resu l t is non-zero. U nchanged otherwise. U ndefined. Set if a carry (dec i mal) was generated. Cleared otherw ise. Set the same as the carry bit. N OTE Normally the Z cond ition code bit i s set via program m i ng before the start of an operat ion. This al lows successf u l tests for zero resu lts upon completion of m u l t i ple-prec ision operat ions.

N Z V C X

I nstruction Format:
14 13 12 11 10 Register Rx
9 8 7 6

15

2 Register Ry

Instruction Fields: Reg ister Rx field - Spec ifies the dest ination reg i ster: If RIM = 0, specifies a data reg ister If RIM = 1 , specifies an address reg i ster for the predecrement addressing mode RIM field - Spec ifies the operand addressing mode: o The operat ion is data reg ister to data reg ister 1 - The operat ion is memory to memory Register Ry field - Spec ifies the sou rce reg ister: I f RIM = 0, spec ifies a data reg i ster If RIM = 1 , spec ifies an address reg ister for the predecrement address i ng mode
-

B-6

ADD
Operation: Assembler Syntax: Attributes: Sou rce + Dest i nat ion ADD < ea > ,Dn ADD Dn, < ea >
-+

Add Dest i nation

ADD

Size = (Byte, Word, Long)

Description: Add the source operand to the destination operand using bi nary add ition, and store the res u l t in the dest i nation locat ion. The s ize of the operation may be specified to be byte, word, or long. The mode of the i nstruction i nd icates which operand is the sou rce and which i s the dest i nation as wel l as the operand size. Condition Codes:
x *

N *

z *

V *

c *

N Z V C X

Set Set Set Set Set

if the res u l t is negative. Cleared otherw i se. if the resu l t is zero. Cleared otherwise. if an overflow is generated. Cleared otherwi se. if a carry is generated. Cleared otherw ise. the same as the carry bit.

Instruction Format:
11 10 Register Dn 9
8 7 6

OpMode

Effective Address Register Mode

Instruction Fields: Reg i ster field - Spec if ies any of the eight data reg isters. Op-M ode field Operation Byte Word Long 000 001 010 < ea > + < On > < On > 1 00 < O n > + < ea > < ea > 101 1 10
-+ -+

Effective Address Field - Determi nes addres s i ng mode: a. If the l ocation specified in a sou rce operand, the a l l addreSSing modes are a l l owed as shown:

B-7

ADD
Addr. Mode Mode Register

Add

ADD
Addr. Mode Mode Register

On An* (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od) * Word and Long only.

000 001 010 011 1 00 101 110 110 1 10 1 10

reg. number:On reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(xxx).w (xxx).L # < data>

111 111 111

000 001 1 00

(d 1 6 , PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,XnJ,od) ([bd,PCJ,Xn,od)

111 111 111 111 111

010 011 011 011 01 1

b. If the locat ion specif ied is a dest i nation operand, then only alterable memory address i n g modes are al lowed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od)

(xxx).w (xxx).L # < dat a >

111 111
-

000 001
-

010 011 1 00 1 01 1 10 110 1 10 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,XnJ,od) ([bd,PCJ,Xn,od)

Notes: 1 . If the dest i nation is a data reg i ster, then it can not be spec ified by u s i n g the dest ination < ea > mode, but must u se the dest ination On mode i nstead . 2. A DDA is used when the dest i nation is an address reg ister. ADDI and ADDQ are used when the sou rce is i m mediate data. M ost assemblers automat ica l ly make t h i s d istinction .

8-8

A D DA
Operation: Assembler Syntax: Attributes: Sou rce + Dest i nat ion ADDA < ea > ,An Size = (Word, Long)
-+

Add Address Dest i nation

A D DA

Description: Add the source operand to the dest i nation address reg i ster, and store the res u l t in the address reg i ster. The size of the operation may be spec i f ied to be word or long. The entire dest i nation address reg ister is u sed regard less of the operat ion size. Condition Codes: I nstruction Format:
15 14 13 12 11 10 Register An 9 s
7

Not affected.
o

4 Mode

2 Register

OpMode

Effective Address

I nstruction Fields: Reg ister field - Specifies any of the eight address reg i sters. This is always the dest i nat ion. Op-M ode field - Spec if ies the s ize of the operat ion: 01 1 - word operat ion. The sou rce operand i s s i g n-extended to a long operand and the operat ion i s performed on the address reg ister using a l l 32 bits. 1 1 1 - long operat ion. Effect ive Address field - Specifies the sou rce operand. A l l addressing modes are al lowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xn],od) ([bd,Anj,Xn,od)

000 001 010 011 100 101 110 110 110 110

reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. nu mber:An

(xxx).W (xxx).L # < data >

111 111 111

000 001 100

(d 1 6 ,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC),Xn,od)

111 111 111 111 111

010 011 011 011 011

8-9

ADDI
Operation: Assembler Syntax: Attributes:

Add I mmediate I m med iate Data + Dest i nation -- Dest i nation ADDI # < data > , < ea >

ADDI

Size = (Byte, Word, Long)

Description: Add the i m med iate data to the destination operand, and store the resu l t i n the dest ination location. The s ize o f the operation may b e specified to b e byte, word, or long. The s ize of the i m med iate data matches the operation s ize. Condition Codes:
x N z V c

* 1 * 1 * 1 * 1 * 1
Z V C X

Set Set Set Set Set

if the res u l t is negative. Cleared otherw i se. if the res l,l l t is zero. Cleared otherwise. if an overflow is generated. Cleared otherwise. if a carry is generated. Cleared otherw ise. the same as the carry bit.

I nstruction Format:

15 14 13 12 11 1 0 0 1010J 0 I 0 1 1 1 1 1 0 1 I
9 8

6 Size

Word Data

Long Data (Includes Previous Word)

5 4 3 2
Byte Data

Effective Address Mode Register

I nstruction Fields: Size field - Specifies the s ize of the operat ion: OO- byte operat ion. 01 -word operat ion. 1 0 - long operation. Effective Address field - Specif ies the dest i nation operand. Only data alterable address i n g modes are a l l owed as shown:

B1 0

ADDI
Addr. Mode Mode

Add I mmediate
Register Addr. Mode Mode

ADDI
Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (de,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od)

000
-

reg. number:Dn
-

(xxx).w (xxx).L # < data>

111 111
-

000 001
-

010 01 1 1 00 101 1 10 110 110 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (de,PC,Xn) (bd,PC,Xn) ([bd,PC,XnJ,od) ([bd,PCJ,Xn,od)

I m mediate field [f size = 00, then If size = 01 , then If size = 1 0, then

(Data i m mediately following the i nstruction): the data is the low order byte of the immediate word. the data i s the entire i m med iate word. the data i s the next two i m mediate words.

81 1

A D DQ
Operation: Assembler Syntax: Attributes:

Add Quick

A D DQ

I m med iate Data + Dest i nat ion ADDQ # < data > , < ea >

-+

Dest ination

Size = (Byte, Word, Long)

Description: Add the i m mediate data to the operand at the dest ination locat ion. The data range is from 1 to 8. The size of the operation may be spec ified to be byte, word, or long. Word and long operat ions are also al lowed on the address reg i sters, in which case the condition codes are not affected. When add i n g to address reg isters, the entire dest i nation address reg ister is used, regard less of the operation s ize. Condition Codes:
x N Z V c * 1 * 1 * 1 * 1 *

N Z V C X

Set Set Set Set Set

if the resu l t is negat ive. Cl eared otherwise. if the resu l t is zero. Cleared otherwi se. if an overflow is generated. Cl eared otherwise. if a carry is generated . Cl eared otherwise. the same as the carry bit.

The cond ition codes are not affected if the dest i nation i s an address reg i ster. Instruction Format:
11 10
Data

4 3 2 o Effective Address Register Mode

Instruction Fields: Data field - Three bits of i m med iate data, 0, 1 -7 representing a range of 8, 1 to 7 respect ively. Size field - Specifies the size of the operat ion: OO- byte operat ion. 01 - word operat ion . 1 0 - long operat ion. Effective Address field - Specifies the dest i nation locat ion. O n ly alterable add ress i n g modes are a l lowed as shown:

B-1 2

A D DQ
Addr. Mode Mode Register

Add Quick

A D DQ
Addr. Mode Mode Register

Dn An (An) (An) + - (An) (d 1 6,An) (de,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od) * Word and Long Only.

000

reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(xxx).W (xxx).L # < data>

111 111
-

000

001 010 011 100 101 110 110 1 10 1 10

001
-

(d 1 6 ,PC) (de,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC],Xn,od)

B 1 3

A D DX
Operation: Assembler Syntax: Attributes: A DDX DY, Dx ADDX - (Ay), - (Ax)

Add Extended Sou rce + Dest i nat ion + X Dest i nation

A D DX

-+

Size = (Byte, Word, Long)

Description: Add the sou rce operand to the desti nation operand along with the extend bit and store the result in the destination location. The operands may be addressed in two dif ferent ways: 1 . Data reg ister to data reg ister: the operands are contai ned in data reg i sters specif ied in the i nstruction. 2. Memory to memory: the operands are addressed with the predecrement add ress i n g mode u s i n g the address reg i sters specified in the i nstruction. The s ize of the operat ion may be spec ifi ed to be byte, word, or long. Condition Codes:
x

* 1 * 1 * 1 * 1 * 1
N Z V C X Set if the resu l t is negative. Cleared otherwise. C leared i f the res u l t is non-zero. U nchanged otherw i se. Set if an overfl ow is generated. Cleared otherwise. Set i f a carry is generated. Cleared otherw i se. Set the same as the carry bit. N OTE Normaliy the Z condition code bit is set via programming before the start of an opera tion. This aliows successful tests for zero results upon completion of multiple-precision operat ions.

Instruction Format:
15 14

13

12

11

10 Register Rx

2 Register Ry

B-1 4

A D DX

Add Extended

A D DX

I nstruction Fields: Reg i ster Rx field - Specifies the dest ination reg ister: If RIM = 0, specifies a data reg i ster. If RIM = 1 , specifies an address reg i ster for the predecrement addressing mode. Size field - Specifies the size of the operat ion: OO- byte operation. 01 - word operation. 1 0 - long operat ion. RIM field - Spec ifies the operand address mode: 0-The operation is data reg ister to data reg ister. 1 -The operat ion i s memory to memory. Register Ry field - Specifies the sou rce reg i ster: If RIM = 0, spec ifies a data reg i ster. If RIM = 1 , specifies an address reg i ster for the predecrement addres s i n g mode .

8-1 5

AN D
Operation: Assembler Syntax: Attributes:

AND Logical

AN D

Sou rce" Dest i nat ion - Dest i nation AND < ea > , D n AN D D n, < ea >

Size = (Byte, Word, Long)

Description: AN D the source operand to the dest ination operand and store the result i n the dest i nation location. The s ize o f the operation may be speci fied t o be byte, word, or long. The contents of an address reg ister may not be u sed as an operand. Condition Codes:
x N z

1-1 1 10 0 \
V c

N Z V C X

Set if the most s i g n i f i cant bit of the resu l t is set. Cleared otherwi se. Set if the res u l t is zero. Cleared otherwise. A l ways cleared. A lways cleared. Not affected.

I nstruction Format:
15 14 13 12 11

Register On

10

4 Mode

2 Register

OpMode

Effective Address

I nstruction Fields: Register field - Spec ifies any of the eight data reg i sters. Op-Mode field Byte Word Long Operation 000 001 010 ea A Dn - Dn Dn " ea - ea 1 00 1 01 1 10 Effective Address field - Determi nes address i n g mode: If the l ocation specifi ed is a sou rce operand then o n ly data addressing modes are a l lowed as shown:

B-1 6

AN D
Addr. Mode Mode Register

AND Logical
Addr. Mode Mode

AN D
Register

On An (An) (An) + - (An) (d 1 6,An) (de,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,An],Xn,od)

000
-

reg. number:On
-

(xxx).w (xxx).L

111 111 111

000

001 1 00

010 011 1 00 1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

# < data>

(d 1 6,PC) (de,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC),Xn,od)

111 111 111 111 111

010 011 011 011 011

I f the locat ion specif ied i s a dest i nation operand then only alterable memory addressing modes are al lowed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6 ,An) (de,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj.Xn,od)

(xxx).W (xxx).L

111 111
-

000

001
-

010 01 1 1 00 101 110 110 110 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

# < data>

(d 1 6 ,PC) (de,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC),Xn,od)

Notes: 1 . I f the dest i nation is a data reg i ster, then it can not be spec ified by u s i n g the dest i nat ion < ea > mode, but m u st u se the dest i nation Dn mode i n stead . 2. A N D I is u sed w hen the sou rce is i m mediate data. M ost assemblers automati cally make t h i s d istinction.

II

8-1 7

AN DI
Operation: Assembler Syntax: Attributes:

AND Immediate I m med iate Data A Dest i nation - Dest i nation AN DI # < data > , < ea >

AN DI

Size = (Byte, Word, Long)

Description: A N D the i m med iate data to the dest i nation operand and store the resu l t i n the dest i nation location. The s ize o f the operation may b e specified to b e byte, word, or long. The size of the i mmediate data matches the operation s ize. Condition Codes:

1- 1 * 1 * 1 0 1 0
N Z V C X

Set if the most s i g n i f icant bit of the res u l t is set. Cleared otherw i se. Set if the resu l t is zero. Cleared otherwise. A lways c leared. A lways c leared. Not affected.

I nstruction Format:

15 0

1 1 1 1 1 1 1 0 1I
9 8

14 0

13 0

12 0

11 0

10 0

7 Size

Word Data

Long Data (I ncludes Previous Word)

3
I

Effective Address Register Mode Byte Data

Instruction Fields: S ize field - Specifies the size of the operation: OO- byte operat ion. 01 -word operation. 1 0 - long operat ion. Effective Address field - Spec ifies the dest i nation operand. Only data alterable addressi n g modes are al lowed as shown:

B-1 8

AN DI
Addr. Mode Mode

AN 0 Immediate
Register Addr. Mode Mode

AN DI
Register

On An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000
-

reg. number:On
-

(xxx).W (xxx).L

111 111
-

000

001
-

010 011 100 1 01 1 10 110 110 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

# > data >

(d 1 6 , PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd, PC].Xn,od)

I m mediate field If size = 00, then If size = 01 , then If s ize = 1 0, then

(Data i m mediately fol lowi n g the i nstruction): the data is the l ow order byte of the i mmediate word. the data i s the entire i m med iate word. the data is the next two i mmediate words.

8-1 9

AN DI to CC R
Operation: Assembler Syntax: Attributes: Sou rce
A

AN 0 Immediate to Condition Codes CCR - CCR

AN DI to CC R

A N DI # < data > ,CCR Size = (Byte)

Description: A N D the i m med iate operand with the cond ition codes and store the resu l t i n t h e low-order byte o f the status reg i ster. Condition Codes:
x *

N *

z *

V *

c *

N Z V C X

Cleared Cleared Cl eared Cleared Cleared

if if if if if

bit bit bit bit bit

3 2 1 0 4

of of of of of

i m mediate i m mediate i mmed i ate i m med iate i m med iate

operand operand operand operand operand

is is is is is

zero. zero. zero. zero. zero.

U nchanged U nchanged U nchanged U nchanged Unchanged

otherwi se. otherwi se. otherw i se. otherw ise. otherw ise.

Instruction Format:

B-20

AN DI to S R
Operation:

A N D Immediate to the Status Register (Privileged Instruction) If su pervisor state then Sou rce A SR - SR else TRAP A N D I # < data > ,SR Size = (Word)

AN DI to S R

Assembler Syntax: Attributes:

Description: A N D the i m med iate operand with the contents of the status reg ister and store the resu l t in the status reg ister. A l l bits of the status reg i ster are affected. Condition Codes:
x

* if if if if if bit bit bit bit bit

* 3 2 1 0 4

1
of of of of of i m med iate i m med iate i m med iate i m mediate i m med iate operand operand operand operand operand is is is is is zero. zero. zero. zero. zero. U nchanged U nchanged U nchanged Unchanged U nchanged otherw i se. otherw ise. otherwise. otherwise. otherw i se.

N Z V C X

Cleared Cleared Cleared Cleared C leared

Instruction Format:
15 0 14 0

13 0

12 0

11 0

10

Word Data (1 6 Bits)

0 0

8-21

AS L, AS R
Operation: Assembler Syntax:

Arithmetic Shift

AS L, AS R

Dest i nation Shifted by < count > -- Dest i nation ASd DX, Dy ASd # < data > , Dy ASd < ea > where d i s d i rection, L o r R Size = (Byte, Word, Long)

Attributes:

Description: Arith metically sh ift the bits of the operand i n the d i rect ion (L or R) specif ied. The carry bit receives the last bit sh ifted out of the operand. The sh ift cou nt for the shifting of a reg i ster may be specif ied in two d i fferent ways: 1 . I m med iate: the sh ift cou n t i s spec ified in the i nstruction (shift range, 1 -8). 2. Reg i ster: the sh ift cou n t is contai ned in a data reg ister specified in the i nstruction (shift cou nt i s modulo 64). The s ize of the operation may be spec ified to be byte, word, or long. The content of memory may be sh ifted one bit o n ly, and the operand s ize is restricted to a word. For ASL, the operand is sh ifted left; the nu mber of pos itions sh ifted is the sh ift count. Bits sh i fted out of the high order bit go to both the carry and the extend bits; zeroes are sh ifted i nto the low order bit. The overflow bit i nd i cates if any s i g n changes occ u r d u r i n g t h e sh ift.

ASL:

+.----.I

__

__ __

o pe ra n d _ _ _ _

__

14

For ASR, the operand is sh ifted right; the n u mber of pos itions shifted is the sh ift count. Bits sh ifted out of the low order bit go to bot h the carry and the extend bits; the sign bit (MSB) i s rep l i cated i nto the high order bit. ASR: MS B Operand

B-22

AS L, AS R
Condition Codes: x N z

Arithmetic Shift

AS L, AS R

* 1 * 1 * 1 *
Z V C X

* 1

Set if the most s i g n ificant bit of the resu l t is set. Cleared otherw i se. Set if the res u l t is zero. Cleared otherw ise. Set if the most s i g n if icant bit is changed at any t i me during the sh ift opera tion. Cleared otherw i se. Set accord i ng to the last bit sh ifted out of the operand. Cleared for a sh ift count of zero. Set accord i ng to the last bit sh ifted out of the operand. U naffected for a sh ift cou nt of zero.
0
Register

Instruction Format (Register Shi fts):

15 14 13 12 11 10 Count Register 9 8 7 6 5 4 3 2

Instruction Fields (Reg i ster S h i fts): Cou nt/Reg i ster field - Spec ifies sh ift cou nt or reg ister where count is located: If i/r = O, the sh ift cou nt i s specif ied in t h i s field. The va lues 0, 1 -7 represent a range of 8, 1 to 7 respect ive ly. If i/r = 1 , the sh ift cou nt (mod u l o 64) i s contai ned in the data reg ister specified i n t h i s field. dr field - Spec if ies the d i rection of the sh ift: O-sh ift right. 1 - sh i ft left. Size field - Spec if ies the s ize of the operat ion: OO- byte operat ion. 01 -word operat ion. 1 0- long operat ion. i/r field If i/r = 0, specifies i m med iate sh ift count. I f i/r = 1 , specifies reg i ster sh ift count. Register field - Spec ifies a data reg i ster whose content is to be sh ifted .

8-23

AS L, AS R
Instruction Format (Memory Shi fts):
15 14 13 12 11 10 9

Arithmetic Shift

AS L, AS R
4 3 2 Effective Address Register Mode

Instruction Fields (Memory Shifts): dr field - Spec ifies the d i rect ion of the sh ift: O-shift right 1 - sh i ft left Effective Address field - Spec ifies the operand to be shifted. Only memory alterable add res s i n g modes are al lowed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xn],od) ([bd,An],Xn,od)

(xxx).W (xxx).L

111 111
-

000 001
-

010 01 1 100 101 110 110 110 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

# < dat a >

(d 1 6 ,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn],od) ([bd,PC],Xn,od)

8-24

Bee
Operation: Assembler Syntax: Attributes:

Branch Conditiona lly If (cond ition true) then PC + d - PC

Bee < labe l >

Bee

Size = (Byte, Word, Long)

Description: I f t h e specif ied cond ition i s met, program execution cont i n ues a t locat ion (PC) + disp lacement. The disp lacement i s a twos complement i nteger which counts the relat ive d i stance i n bytes. The value in the PC i s the S i g n-extended i nstruct ion l ocat ion p l u s two. I f the 8-bit d isplacement in the i nstruction word is zero, then the 1 6-bit d i s placement (word i m mediately follow i n g the i nstruction) i s u sed. If the 8-bit displacement in the i nstruction word is all ones ($FF), then t he 32-bit d i splacement (long word i m med iately follow i n g the i nstruction) i s used. "cc" may specify the follow i n g cond itions:
cc CS EQ GE GT HI LE
carry clear carry set equal greater or equal greater than high less or equal 0 1 00 0101 01 1 1 1 1 00 1110 0010 1111 C C Z N .V + N.V N . V.Z + N.V.Z C.Z Z + N .V+ N.V LS LT MI NE PL VC VS low or same less than minus not equal plus overflow clear overflow set 001 1 1 1 01 1011 01 1 0 1010 1 000 1001

C+Z N .V + N . V N Z N V V

Condition Codes: Instruction Format:

15

Not affected.

14

13

12

11

10

Condition

1 6Bit Displacement if 8Bit Displacement = $00 32Bit Displacement if 8Bit Displacement = $FF

8Bit Displacement

Instruction Fields: Cond ition field - One of fou rteen cond itions d iscussed in description. 8-Bit Displacement field - Twos complement i nteger spec ifyi ng the relative d i stance ( i n bytes) between the branch i nstruction and the next i nstruction to be executed if the cond ition is met. 1 6- B it Displacement field - A l l ows a larger disp lacement than 8 bits. Used only if the 8-bit d isplacement is eq ual to $00. 32- B it D isplacement field - A l lows a larger disp lacement than 1 6 bits. Used only if the 8-bit d isplacement i s equal to $FF. Note: A short branch to the i m mediately follow i n g i nstruct ion can not be generated, be cause it wou ld res u l t in a zero offset, which forces a word branch i nstruct ion def i n ition.

II

B-25

BCHG
Operation: - -

Test a Bit and Change

BC H G

bit nu m ber > of Desti nation) - Z; bit nu m ber> of Dest i nation) - < bit number> of Dest i nation

Assembler Syntax: Attributes:

Size = (Byte, Long)

BCHG Dn, < ea > BCHG # < data > , < ea >

Description: A bit in the dest i nat ion operand is tested and the state of the spec ified bit i s reflected i n the Z cond ition code. After the test, the state of the specified bit i s changed i n the dest i nat ion. If a data reg ister is t h e dest i nation, t h e n t h e bit nu mber i n g is mod u l o 32 allowing bit m a n i pu lation on a l l bits i n a data reg ister. If a memory l ocat ion is the dest i nation, a byte is read from that location, the bit operation is per formed using the bit n u mber, modulo 8, and the byte is written back to the locat ion. In a l l cases, bit zero refers to the least s i g n i f i cant bit. The bit n u m ber for this opera t i on may be specif ied i n two d i fferent ways: 1 . I m mediate - the bit n u m ber is specified in a second word of the i nstruction. 2. Reg i ster - the bit n u m ber i s contai ned i n a data reg i ster specified i n the i nstruc tion. Condition Codes: c

x
-

I-I
Not Set N ot Not Not

N Z V C X

affected. if the bit tested is zero. Cleared otherw i se. affected. affected. affected.

Instruction Format (Bit N u m ber Dynamic specified by a reg i ster):

15 14 13 12 11 10 Register Dn 9 8 7 6 5 4 Mode 3 2 Register 0 Effective Address

II

I nstruction Fields (Bit N u m ber Dynamic): Reg i ster field - Specifies the data reg i ster w hose content i s the bit number. Effective Address field - Specif ies the desti nation locat ion. Only data alterable addres s i n g modes are al lowed as shown:

B-26

BCHG
Addr. Mode Mode

Test a Bit and Change

BC H G
Mode Register

Register

Addr. Mode

Dn * An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,Anl,Xn,od)

000
-

reg. number:Dn
-

(xxx).W (xxx).L # < data>

111 111
-

000 001
-

010 011 1 00 101 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (dsPC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

* Long only; all others are byte only.

Instruction Format (Bit N u mber Static, specif ied as i m mediate data):

15 0 0 14 0 0 13 0 0 12 0 0 11 1 0 10 0 0 9 0 0 s 0 0 7 o

I I
1

4 Mode

o Register

Effective Address Bit Number

I nstruction Fields (Bit N u m ber Stat ic): Effective Address field - Specifies the dest i nation l ocation. O n ly data alterable ad dressing modes are allowed as shown:

Addr. Mode

Mode

Register

Addr. Mode

Mode

Register

Dn * An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000
-

reg. number:Dn
-

(xxx).W (xxx).L # < data>

111 111
-

000 001
-

010 011 1 00 101 110 1 10 1 10 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

* Long only, all others are byte only.

B i t N u mber field - Specifies the bit n u mber.

B-27

BC L R
Operation:

Test a Bit and Clear - bit n u m be r > of Desti nation) - Z; 0 - < bit n u mber > of Dest i nation BClR On, < ea > BClR # < data > , < ea >

BCLR

Assembler Syntax: Attributes:

Size = (Byte, long)

Description: A bit i n the dest i nat ion operand i s tested and the state of the spec i fied bit i s reflected i n the Z condition code. After the test, the spec i fied bit is cleared i n the dest ination. I f a data reg ister i s the dest ination, then the bit n u m bering is modulo 32 al low i n g bit manipu lation on a l l bits i n a data reg i ster. If a memory locat ion is the dest i nation, a byte i s read from that locat ion, the bit operation performed using the bit n u mber, mod u l o 8, and the byte w ritten back to the locat ion. In all cases, bit zero refers to the least S i g n i ficant bit. The bit n u m ber for t h i s operation may be specif ied in two d i fferent ways: 1 . I m med iate - the bit n u m ber is specif ied in a second word of the i nstruction. 2. Regi ster - the bit n u m ber i s contai ned in a data reg i ster specified in the inst ruc tion. Condition Codes: x N z V c

N Z V C X

Not Set Not Not Not

affected . if the bit tested is zero. Cl eared otherw ise. affected. affected. affected.

I nstruction Format (Bit N u m ber Dynamic, specif ied in a reg i ster):

15 14 13 12 11 10 Register Dn 9 8 7 6 5 4 Mode 3 2 Register 0 Effective Address

I nstruction Fields (Bit N u mber Dynamic): Register field - Specif ies the data reg ister w hose content is the bit nu mber. Effect ive Address field - Spec i fies the dest i nation locat ion. Only data alterable ad dressi n g modes are al lowed as shown:

B-28

BC L R
Addr. Mode Mode

Test a Bit and Clear

BC L R
Mode Register

Register

Addr. Mode

On* An (An) (An) + - (An) (d 1 6,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xn],od) ([bd,Anj,Xn,od)

000
-

reg. number:On
-

(xxx)W (xxx).L # < data>

111 111
-

000 001
-

010 01 1 100 1 01 1 10 1 10 1 10 1 10

reg. nu mber:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (ds,PC,Xn) (bd, PC,Xn) ([bd , PC,Xn],od) ([bd,PGj,Xn,od)

* Long only; all others are byte only

I nstruction Format (Bit N u m ber Stat ic, spec ified as i m med iate data):
15 0 0 14 0 0 13 0 0 12 0 0 11 1 0 10 0 0 9 0 0 s 0 0 7 1

I I
0

4 Mode

Effective Address Bit Number

Register

Instruction Fields (Bit N u m ber Stat ic): Effective Address field - Specifies the dest i nation locat ion. Only data alterable ad dressi n g modes are al lowed as shown:

Addr. Mode

Mode

Register

Addr. Mode

Mode

Register

On * An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000
-

reg. number:On
-

(xxx).w (xxx).L # < data >

111 000
-

000 001
-

010 01 1 100 101 110 110 110 110

reg. nu mber:An reg. nu mber:An reg. nu mber:An reg. nu mber:An reg. number:An reg. nu mber:An reg. number:An reg. number:An

(d 1 6 , PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PGj,Xn,od)

* Long only; all others are byte only.

--

Bit N u m ber field - Spec i f ies the bit n u mber.

B-29

B FC H G
Operation: Assembler Syntax: Attributes:
-

Test Bit Field and Change bit field > of Dest i nat ion)

B FC H G

< bit field > of Desti nat ion

BFCHG < ea > [offset:widthl Uns ized

Description: Complement a bit field at the specif ied effective address locat ion. The con d i t ion codes are set accord i n g to the va lue in the field before it is changed. The field selection is specified by a field offset and field width. The field offset denotes the start i ng bit of the field. The field width determ i nes the n u m ber of bits to be i ncl uded in the field. Condition Codes: x N z

* I * I

0 0
I

N Z V C X

Set if the most significant bit of the field is set. Cleared otherwise. Set if a l l bits of the field are zero. Cleared otherw ise. A lways cleared. A lways c leared. Not affected.

Instruction Format:

15 14 13 12 11 1 0 5 4 3 2 1 1 1 0 1 o11 10 11 11 I I 0 0 0 0
9 8 7 6 Mode Do Offset Dw

Effective Address Register Width

Instruction Fields: Effective Address field - Specif ies the base locat ion for the bit field. O n ly data reg ister d i rect or a l terable control addressing modes are allowed, as shown below: Do field - Determi nes how the field offset i s spec ified. O-the field offset is i n the Offset field. 1 - bits [8:6] of the extension word specify a data reg i ster which contains the off set; bits [1 0:9] are O. Offset field - Spec ifies the field offset, depend i n g on Do. If Do = O-the Offset field i s an i mmed iate operand; the operand value is in the range 0-31 , specifying a field offset of 0-31 . I f Do = 1 - the Offset field specif ies a data reg ister which contai n s the offset. The value is in the range - 231 to 231 - 1 .

8-30

B FC H G

Test Bit Field and Change

B FC H G

Dw field - Determ i nes how the field width is spec ified . O-the f i e l d w i d t h i s i n t h e W i d t h field. 1 - bits [2:0] of the extension word specify a data reg i ster which contains the width; bits [3:4] are O. Width field - Spec ifies the field width, depend i n g on Dw. If Dw = O-the Width field i s an i mmediate operand; the operand va lue i s in the range 0, 1 -31 specifying a field width of 32, 1 -31 respectively. If Dw = 1 - the Width field specifies a data reg i ster which contai n s the width. The operand val u e is taken mod u l o 32, w i t h val ues 0, 1 -31 spec ifying a field width of 32, 1 -31 .

Addr. Mode

Mode

Register

Addr. Mode

Mode

Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000
-

reg. number:Dn
-

(xxx).W (xxx).L # < data>

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 , PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

8-31

B FC L R
Operation: Assembler Syntax: Attributes: 0
-+

Test Bit Field and Clear < bit field > of Dest i nat ion

B FC L R

B FCLR < ea > [ offsetw idth] U n sized

Description: C lear a bit field at the spec ific effective address locat ion. The cond ition codes are set accord i n g to the value i n the field before it i s cleared. The field selection is specified by a field offset and field width. The field offset denotes the start i ng bit of the field. The field width determines the nu mber of bits to be i nc l uded in the field. Condition Codes:

1- 1 * 1 * 1 0 1 0
N Z V C X

Set if the most s i g n i f icant bit of the field is set. Cleared otherwise. Set if a l l bits of the field are zero. Cleared otherwise. Always cleared. Always cleared. N ot affected.

I nstruction Format:
15 1 14 1 13 1 12 11 1 Do 1

0 0

I0I0I I
1 Offset

6 1

4 Mode

0
Register

Effective Address Dw

Width

I nstruction Fields: Effective Address field - Spec ifies the base l ocat ion for the bit field. Only data reg ister d i rect or alterable control addressing modes are allowed, as shown below: Do field - Determi nes how the field offset i s spec ified. O-the field offset i s i n the Offset field. 1 - bits [8:6] of the extension word specify a data reg i ster which conta ins the off set; bits [10:9] are O. Offset field - Specifies the field offset, depend i n g on Do. If Do = O-the Offset field is an i m med iate operand; the operand value is in the range 0-31 , specifying a field offset of 0-31 . If Do = 1 -the Offset field specifies a data reg i ster which conta ins the offset. The value is in the range - 231 to 231 - 1 .

8-32

B FC L R

Test Bit Field and Clear

B FC L R

Ow field - Determi nes how the field width i s specified. O-the field width i s i n the Width field. 1 - bits [2:0] of the extension word specify a data reg i ster which contains the width; bits [4:3] are O. Width field - Spec if ies the field width, depend i n g on Ow. If Ow = O-the Width field i s an i m med iate operand; the operand value is i n the range 0, 1 -31 specifying a field width of 32, 1 -31 . I f Ow = 1 - the Width field specifies a data reg i ster which conta i ns the width. The operand va lue is taken mod u l o 32, with val ues 0, 1 -31 spec ifying a field width of 32, 1 -31 .
Addr. Mode Mode Register Addr. Mode Mode Register

On An (An) (An) + - (An) (d 1 6,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000
-

reg. number:On
-

(xxx).W (xxx).L # < data>

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. nu mber:An

(d 1 6,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PCI,Xn,od)

8-33

B F EXTS
Operation: Assembler Syntax: Attributes:

Extract Bit Field Signed

B F EXTS

<bit field > of Sou rce - O n

B F EXTS < ea > [ offsetwidth) , D n

U nsized

Description: Extract a bit field from the specified effective address locat ion, s i g n extend to 32 b its, and load the resu l t i nto the dest i nation data reg ister. The field selection is spec ified by a field offset and field width. The field offset denotes the start i n g bit of the field. The field width determi nes the n u mber of bits to be incl uded in the field. Condition Codes: x N z c

1- 1 * 1 *1 0 1 0
N Z V C X

Set if the most s i g n ificant bit of the f ield is set. Cleared otherw i se. Set if a l l bits of the field are zero. Cleared otherw i se. A lways cleared. A l ways cleared. N ot affected.

Instruction Format:
15

14 1

Register

11 10

13

12

11

1
Do

111 111
1 Offset

6 1

4 Mode

0
Register

Effective Address Dw

Width

Instruction Fields: Effective Address field - Specif ies the base l ocation for the bit field. Only data reg i ster d i rect or control addressing modes are al lowed as shown below: Reg i ster field - Specifies the dest i nation reg i ster. Do field - Determi nes how the field offset is spec ified. O-the field offset i s i n the Offset field. 1 - bits [8:6] of the extension word spec ify a data reg i ster which conta i ns the off set; bits [1 0:9] are o. Offset field - Spec ifies the field offset, depending on Do. If Do = O-the Offset field is an i m med iate operand; the operand value is in the range 0-31, speCifying a field offset of 0-31 . I f Do = 1 - the Offset field spec ifies a data-reg i ster which contains the offset. The val ue is in the range - 231 to 231 - 1 .

8-34

B F EXTS

Extract Bit Field Signed

B F EXTS

Dw field - Determ i nes how the field width is specified. O-the field width i s in the Width field. 1 - bits [2:0] of the extension word specify a data reg ister which contains the width; bits [4:3] are O. Width field - Spec ifies the field width, depen d i n g on Dw. I f Dw = O-the Width field i s an i mmediate operand; the operand va lue i s i n the range 0, 1 -31 , specifying a field width of 32, 1 -31 . I f Dw = 1 - the Width field specifies a data reg i ster which contai n s the width. The operand value is taken mod u l o 32, w i t h val ues 0, 1 -31 specify i ng a field width of 32, 1 -31 .

Addr. Mode

Mode

Register

Addr. Mode

Mode

Register

Dn (An) + (An) - (An) (d 1 6,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od) An

000
-

reg. number:Dn
-

(xxx).W (xxx).L # < data >

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 , PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC],Xn,od)

111 111 111 111 111

010 01 1 011 011 011

II

8-35

B F EXT U
Operation: Assembler Syntax: Attributes:

Extract Bit Field Unsigned

B F EXT U

< bi t field > of Sou rce - On

BFEXTU < ea > { offsetwidt h},Dn

Unsized

Description: Extract a bit field from the specified effective address locat ion, zero extend to 32 bits, and l oad the results i nto the dest i nation data reg i ster. The field selection is spec ified by a field offset and field width. The field offset denotes the start i n g bit of the field. The field width determi nes the n u mber of bits to be i n c l uded in the field. Condition Codes: x N z c

1- 1 * 1 * 1 0 1 0
N Z V C X

Set if the most s i g n i fi cant bit of the source field is set. Cleared otherw i se. Set if a l l bits of the field are zero. Cleared otherw i se. A l ways cleared. A lways cleared. N ot affected.

Instruction Format:
15
1

14 1

Register

I I0

13
1

12

11 1 Do

I0I I I
1 1 Offset

6
1

4 Mode

0
Register

Effective Address Dw

Width

II

Instruction Fields: Effective Address field - Spec ifies the base locat ion for the bit field. O n ly data reg i ster d i rect or control addressi n g modes are a l l owed as shown below: Register field - Spec i fies the dest ination data reg ister. Do field - Determi nes how the field offset i s specified. O-the field offset is in the Offset field. 1 - bits [8:6] of the extension word specify a data reg i ster which conta i ns the off set; bits [1 0:9] are O. Offset field - Specif ies the field offset, depend i n g on Do. If Do = O-the Offset field is an i m mediate operand; the operand value is in the range 0-31, specifying a field offset of 0-31 . If Do = 1 - the Offset field spec ifies a data reg i ster w h i c h contains the offset. The val u e is in the range - 231 to 231 - 1 .

8-36

B F EXT U

Extract Bit Field U nsigned

B F EXT U

Ow field - Determi nes how the field width is spec ified. O-the field width i s in the Width field. 1 - bits [2:0] of the extension word specify a data reg i ster which contains the width; bits [4:3] are O. Width field - Spec ifies the field width, depend i n g on Ow. If Ow = O-the Width field i s an i m med iate operand; the operand value i s i n the range 0, 1 31 , spec ifying a field width of 32, 1 31 . If Ow = 1 -the Width field specifies a data reg i ster which contai n s the width. The operand val ue is taken mod u l o 32, w i t h val ues 0, 1 31 spec ifying a field width of 32, 1 31 .

Addr. Mode

Mode

Register

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000
-

reg. number:On
-

(xxx).w
(xxx).L # < data >

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd, PC),Xn,od)

111 111 111 111 111

010 011 01 1 01 1 011

B37

B F F FO
Operation: Assembler Syntax: Attributes:

Find First One in Bit Field

B F F FO

< bit field > of Sou rce B i t Scan -- O n BFFFO < ea > { offsetw idth),Dn Uns ized

Description: The source operand is searched for the most Signi ficant bit pos i t ion that contains a set bit. The bit offset (the orig i nal bit offset p l u s the offset of the f i rst set bit) of that bit is then placed in On. If no bit of the bit field is set, the value placed i n On i s t h e field offset plus field width. The cond ition codes are set accord i n g t o the bit field operand. The field selection is specified by a field offset and field width. The field offset denotes the start i ng bit of the field. The field width determi nes the n u m ber of bits to be i n c l uded in the field. Condition Codes:

1 -1 * 1 * 1 0 1 0
N Z V C X

Set if the most s i g n ificant bit of the field is set. Cleared otherwi se. Set if a l l bits of the field are zero. Cleared otherw ise. A l ways cleared. A l ways cleared. N ot affected.

Instruction Format:

15 1 0

14 1

Register

1 1

13 1

12 0

11
Do

10 1

J01 1 11 11
Offset

5
Ow

4
I
Mode

3
I

2
Register Width

Effective Address

Instruction Fields: Effective Address field - Specifies the base locat ion for the bit field. Only data reg i ster d i rect or control addressing modes are a l l owed as shown below: Regi ster field - Specifies the dest ination data reg ister operand. Do field - Determi nes how the field offset i s spec ified. O-the field offset i s i n the Offset field. 1 - bits [8:61 of the extension word specify a data reg i ster which conta i ns the off set; bits [1 0:91 are O. Offset field - Spec ifies the field offset, depend i n g on Do. It Do = O-the Offset field is an i m med iate operand; the operand value is in the range 0-31 , specify i n g a field offset of 0-31 . I f Do = 1 - the Offset field spec ifies a data reg ister which contains the offset. The val ue is in the range - 231 to 231 - 1 . B-38

B F F FO

Find First One in Bit Field

B F F FO

Dw field - Determ i nes how the field width is specified. O-the field width i s in the Width field. 1 - bits [2:0] of the extension word specify a data reg ister which conta i n s the width; bits [4:3] are O. Width field - Spec if ies the field width, depending on Dw. If Dw = O-the Width field i s an i mmed i ate operand; the operand value i s in the range 0, 1 31 , spec ify i ng a field width of 32, 1 31 . I f Dw = 1 -the Width field specifies a data reg ister which contai n s the width. The operand val u e is taken modulo 32, w i t h va lues 0, 1 31 spec ifying a field width of 32, 1 31 .

Addr. Mode

Mode

Register

Addr. Mode

Mode

Register

Dn An (An) (An) + - (An) (d 1 6,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od)

000
-

reg. number:Dn
-

(xxx).W (xxx).L # < data >

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,XnJ,od) ([bd,PCJ,Xn,od)

111 111 111 111 111

010 011 011 011 011

839

B FI NS
Operation: Assembler Syntax: Attributes: On
-+

I nsert Bit Field < bit field > of Dest i nation

B FI NS

B F I N S Dn, < ea > (offsetwidth)

Uns ized

Description: M ove a bit field from the l ow-order bits of the specified data reg ister to a bit field at the specified effective address locat ion. The condit ion codes are set accor d i ng to the i nserted val ue. The field select ion is specif ied by a field offset and field width. The field offset denotes the starti ng bit of the field. The field width determ i nes the n u m ber of bits to be i nc l uded in the field. Condition Codes: x N Z V c

1- 1 * 1 * 1 0 1 0
N Z V C X

Set if the most s i g n ificant bit of the field is set. Cleared otherw ise. Set if a l l bits of the field are zero. Cleared otherw i se. A lways c leared. A lways c leared. Not affected.

Instruction Format:
15 1 14 1

Register

1 1
1

13

12 0

11 1 Do

10 1

1 1 1 1
1 1 1 Offset

6 1

4 Mode

0 Register

Effective Address Dw

Width

Instruction Fields: Effective Add ress field - Specif ies the base locat ion for the bit field. Only data reg i ster d i rect or alterable control addressi n g modes are a l l owed as shown below: Regi ster field - Spec ifies the source data reg ister operand. Do field - Determi nes how the field offset i s spec ified. O-the field offset i s i n the Offset field. 1 - bits [8:61 of the extension word specify a data reg i ster which contains the off set; bits [1 0:91 are O. Offset field - Specifies the field offset, depending on Do. It Do = O-the Offset field is an i mmediate operand; the operand value is in the range 0-31 , specify i n g a field offset of 0-31 . If Do = 1 -the Offset field specifies a data reg i ster which contains the offset. The value is i n the range - 231 to 231 - 1 .

B-40

B FI NS

Insert Bit Field

BFINS

Dw field - Determi nes how the field width i s specified. O-the field width is i n the Width field. 1 - bits [2:0] of the extens ion word spec ify a data reg i ster which contains the width; bits [4:3] are 0. Width field - Specifies the field width, depend i n g on Dw. If Dw = O-the Width field i s an i m med iate operand; the operand va lue i s in the range 0, 1 -31 , specifying a field width of 32, 1 -31 . I f Dw = 1 - the Width field specifies a data reg ister which contai ns the width. The operand va lue is taken modulo 32, with va lues 0, 1 -31 spec ifyi n g a field width of 32, 1 -31 .

Addr. Mode

Mode

Register

Addr. Mode

Mode

Register

Dn An (An) (An) + - (An) (d 1 6,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000
-

reg. nu mber:Dn
-

(xxx).W (xxx).L # < data >

111 111
-

000 001
-

010
-

reg. nu mber:An
-

1 01 110 1 10 1 10 1 10

reg. nu mber:An reg. number:An reg. number:An reg. number:An reg. nu mber:An

(d 1 6 ,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC],Xn,od)

8-4 1

B FS ET
Operation: Assembler Syntax: Attributes: 1s
-

Set Bit Field

B FS ET

< bit field > of Dest i nation

8FSET < ea > (offsetwidth) Uns ized

Description: Set a l l bits of a bit field at the specif ied effective address locat ion. The con d it i on codes are set accord i n g to the value in the field before i t i s set. The field selection is specified by a field offset and f ield width. The field offset denotes the start i n g bit of the field. The field width determi nes the n u mber of bits to be i n c l uded in the field. Condition Codes:

1-1 * 1 * 1 0 1 0
N Z V C X

Set if the most s i g n ificant bit of the f ield is set. Cleared otherw i se. Set if a l l bits of the field are zero. Cleared otherwise. A l ways cleared. A lways cleared. Not affected.

I nstruction Format:

5 4 3 2 15 14 13 12 11 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 I I 0 0 0 0
9 8 7 6 Mode Do Offset Ow

0
Register

Effective Address Width

Instruction Fields: Effective Address field - Specifies the base locat ion for the bit field. O n ly data reg i ster d i rect or alterable control addressi n g modes are al lowed as shown below: Do field - Determ i nes how the field offset i s spec ified . O-the field offset is i n the Offset field. 1 - bits [8:6] of the extension word specify a data reg ister which contains the off set; bits [1 0:9] are O. Offset field - Spec ifies the field offset, depend i n g on Do. If Do = O-the Offset field is an i mmediate operand; the operand va lue is in the range 0-31 , spec ifyi n g a field offset of 0-31 . I f Do = 1 -the Offset field specifies a data reg i ster which contains the offset. The val ue is i n the range - 231 to 231 - 1 .

8-42

B FS ET

Set Bit Field

B FS ET

Dw field - Determ i nes how the field width is spec ified. O-the field width i s i n the Width field. 1 - bits [2:0] of the extension word specify a data reg i ster which contai n s the width; bits [4:3] are O. Width field - Spec ifies the field width, depend i n g on Dw. If Dw = O-the Width field is an i m med iate operand; the operand value is in the range 0, 1 31 , specifying a field width of 32, 1 31 . I f Dw = 1 - the Width field specifies a data reg i ster which contains the width. The operand va lue is taken modulo 32, with val ues 0, 1 31 specifying a field width of 32, 1 31 .

Addr. Mode

Mode

Register

Addr. Mode

Mode

Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) (lbd,An,XnJ,od) ([bd,AnJ,Xn,od)

000
-

reg. number:Dn
-

(xxx)W (xxx).L # < data>

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6, PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn],od) ([bd,PCJ,Xn,od)

..

843

B FTST
Operation: Assembler Syntax: Attributes:

Test Bit Field

B FTST

< bit field > of Dest i nation 6FTST < ea > [ offsetwidth} Uns ized

Description: Extract a bit field from the specified effective address l ocat ion, and set the condit ion codes accord i n g to the value in the field. The field selection i s specif ied by a field offset and field width. The field offset denotes the start i n g bit of the field. The field width determi nes the n u m ber of bits to be i n c l uded in the field. Condition Codes:

1- 1 * 1 * 1 0 1 0
N Z V C X

Set if the most S i g n i f icant bit of the field is set. Cleared otherwi se. Set if a l l bits of the field are zero. Cleared otherwise. A lways cleared. A lways c leared. Not affected.

Instruction Format:

15 14 13 12 11 1 1 1 0 1
0 0 0 0

10

Do

10I011 1
9 8 7 Offset

6
1

5 4 3 2
Ow

Effective Address

Mode

IWidthRegister

Instruction Fields: Effective Address field - Spec ifies the base locat ion for the bit fie ld. Only data reg i ster d i rect or control address i n g modes are a l l owed as shown below: Do field - Determ i nes how the field offset is specif ied . O-the field offset is i n the Offset field. 1 - bits [8:6] of the extension word specify a data reg ister which contains the off set; bits [1 0:9] are O. Offset field - Spec ifies the field offset, depen d i n g on Do. If Do = O-the Offset field is an i m med iate operand; the operand va lue is in the range 0-31 , spec ify i n g a field offset of 0-31 . I f Do = 1 - the Offset field specif ies a data reg ister which conta ins the offset. The value is in the range - 231 to 231 - 1 .

6-44

B FTST

Test Bit Field

B FTST

Dw field - Determi nes how the field width i s specified. O-the field width i s in the Width field. 1 - bits [2:0] of the extension word specify a data reg ister which conta i n s the width; bits [4:3] are O. Width field - Specifies the field width, depend i n g on Dw. If Dw = O-the Width field is an i m med iate operand; the operand value is in the range 0, 1 -31 , spec ifyi n g a field width of 32, 1 -31 . If Dw = 1 - the Width field specifies a data reg ister which conta i n s the width. The operand value i s taken mod u l o 32, with values 0, 1 -31 spec i fying a field w idth of 32, 1 -31 .

Addr. Mode

Mode

Dn An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000 010
-

Register

Addr. Mode

reg. number:Dn
-

(xxx).w (xxx).l

Mode

111 111
-

Register

000 001
-

reg. number:An
-

# < data>

1 01
-

1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PC1,Xn,od)

111

111 111 111

010 011 01 1 01 1 01 1

111

8-45

B K PT
Operation:

Breakpoint If breakpoi n t vector acknowledged then execute returned operat ion word else Trap as I l legal i nstruction BKPT # < data > Unsized

B K PT

Assembler Syntax: Attributes:

Description: This i nstruct ion is used to support the prog ram breakpoint function for debug monitors and real-time hardware emulators, and the operation w i l l be depen dent on the i m p lementat ion. Execution of t h i s instruction w i l l cause the M C68020 to run a breakpoi n t acknowledge bus cycle, with the i mmed iate data (val ue 0-7) presented on address l i nes A2, A3, and A4, and zeros on address l i nes AO and A 1 . Two responses are perm itted: normal and except ion. The normal response to the M C68020 i s an operation word (typically an i nstruct ion, origi nal ly replaced by the breakpoi n t i nstruction) on the data l i nes with the DSACKx signal asserted. This operat ion word w i l l then be executed in place of the breakpoint i nstruction. For the except ion res ponse, a bus error signal w i l l cause the M C68020 to take an i l legal i nstruct ion exception. Condition Codes: Instruction Format: Not affected.

15

14
1

13

12 0

11 1

10 0

9 0

8 0

7 0

6 1

5 0

4 0

3 1

Vector

Instruction Fields: Vector field - Specifies the breakpOint for which the processor is to request the correspond i n g operation word .

B-46

B RA
Operation: Assembler Syntax: Attributes: PC + d - PC B RA < label >

Branch Always

B RA

Size = (Byte, Word, Long)

Description: Program execution cont i n ues at l ocation (PC) + displacement. The dis placement is a twos complement i nteger, which cou nts the relative d i stance i n bytes. The val u e i n the P C i s the i nstruction locat ion plus two. I f the 8-bit displace ment in the i nstruct ion word is zero, t hen the 1 6-bit displacement (word i m mediately follow i n g t he instruction) i s u sed. If the 8-bit displacement in the instruction word is all ones ($FF), t hen the 32-bit displacement (long word im mediately fol low i n g the in struction) is used. Condition Codes: I nstruction Format:
15

Not affected.

14 1

13 1

12 0

11

1 6-Bit Displacement if 8-BIt Displacement = $00 32-Bit Displacement if 8-Bit Displacement = $FF

10

o
9

o
8

8Bit Displacement

Instruction Fields: 8-Bit Displacement field - Two com plement i nteger specifying the relative d istance (in bytes) between the branch i nstruction and the next i nstruct ion to be executed. 1 6-Bit Displacement field - A l l ows a larger displacement than 8 bits. Used o n ly if the 8-bit displacement is equal to $00_ 32-Bit Displacement field - A l l ows a larger displacement than 8 bits_ Used o n ly if the 8-bit displacement is eq ual to $FF. Note: A short branch to the i mmed iately fol lowing i nstruction can not be generated because it wou ld result in a zero offset, which forces a word branch i nstruction def i n i t ion.

II

B-47

B S El
Operation:
-

Test a Bit and Set - bit n u m be r > of Dest i nation) - Z; 1 < bit numbe r > of Dest i nation BSET Dn , < ea > BSET # < data > , < ea >

B S El

Assembler Syntax: Attributes:

Size = (Byte, Long)

Description: A bit i n the dest i nation operand i s tested, and the state of the spec ified bit i s reflected i n the Z condition code. After the test, the specified bit i s set i n the desti nat ion. I f a data reg i ster i s the desti nation, then the bit n u mbering i s mod u l o 32, al low i n g bit manipulation on a l l bits in a data reg i ster. If a memory l ocat ion is the dest i nat ion, a byte i s read from that locat ion, the bit operat ion performed u s i n g the bit n u m ber, modulo 8, and the byte w ri tten back to the location. B i t zero refers to the least s i g n i f i cant bit. The bit n u m ber for this operat ion may be spec ified in two d if ferent ways: 1 . I mmediate - the bit n u m ber is spec ified in a second word of the i nstruction. 2. Regi ster - the bit n u m ber i s contai ned in a data reg i ster specified in the i nst ruc tion. Condition Codes:

1-I-I
N Z V C X Not Set Not Not N ot

affected. if the bit tested is zero. Cleared otherwise. affected. affected. affected.

Instruction Format (Bit N u m ber Dynam ic, specified in a reg ister):

15

14

13

12

11

10

2
Register

Register

Effective Address Mode

Instruction Fields (Bit N u m ber Dynamic): Register field - Specifies the data reg ister w hose content is the bit number. Effective Address field - Spec ifies the dest i nation locat ion. Only data alterable address i n g modes are al lowed as shown:

B-48

B S ET
Addr. Mode Mode

Test a Bit and Set

B S ET
Mode Register

Register

Addr. Mode

Dn An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xn].od) ([bd,Anl,Xn,od)

000
-

reg. number:Dn
-

(xxx)W (xxx).L

111 111
-

000 001
-

010 011 100 101 1 10 110 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

# < data >

(d 1 6 , PC) (dsPC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

Long only; all others are byte only.

I nstruction Format (Bit N u m ber Stat ic, specified as i m med iate data):
15 0 0 14 0 0 13 0 0 12 0 0 11 1 0 10 0 0 9 0 0 s 0 0 7 1

1 1
1

4 Mode

o Register

Effective Address Bit Nu mber

Instruction Fields (Bit N u mber Static): Effective Address field - Spec ifies the dest i nation locat ion. Only data alterable add ress i n g modes are al lowed as shown:

Addr. Mode

Mode

Register

Addr. Mode

Mode

Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000
-

reg. number:Dn
-

(xxx).w (xxx).L

111 111
-

000 001
-

010 011 100 101 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

# < data >

(d 1 6 ,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

Long only; all others are byte only.

Bit N u mber field - Spec i f ies the bit number.

B-49

BSR
Operation: Assembler Syntax: Attributes: SP
-

Branch to Subroutine 4 S P; PC (SP); PC + d PC

BSR

-+

-+

-+

Size = (Byte, Word, Long)

BSR < label >

Description: The long word address of the i nstruction i mmediately follow i n g the BSR i n struction is pushed onto the system stack. Program execution then con t i n ues at location (PC) + displacement. The d i splacement i n a twos complement i nteger which counts the relative d istances i n the bytes. The val ue i n the PC is the i nstruction loca t ion p l u s two. If the 8-bit d i splacement in the i nstruction word is zero, then the 1 6-bit d isplacement (word i m mediately follow i n g the i nstruction) i s u sed. If the 8-bit d isplacement i n the i nstruction word i s all ones ($FF), then the 32-bit d i splacement (long word i m mediately following the i nstruction) i s u sed. Condition Codes: N ot affected. Instruction Format:
15

14 1

13 1

12

I 1 6oBit Displacement if 8Bit Displacement I I o I I

1

11

10

4
=

8Bit Displacement $00

32Bit Displacement if 8Bit Displacement = $FF

Instruction Fields: 8-Bit Displacement field - Twos com plement i nteger specifying the relat ive d istance ( i n bytes) between the branch i nstruction and the next i nstruction to be executed. 1 6-Bit Displacement field - A l l ows a larger d i splacement than 8 bits. Used only if the 8-bit displacement i s equal to $00. 32-Bit D i splacement field - A l l ows a larger d i splacement than 8 bits. Used only if the 8-bit d i splacement i s eq ual to $FF. Note: A short subrou t i ne branch to the i m mediately fol lowi n g i nstruct ion can not be generated becau se it would res u lt in a zero offset, which forces a word branch i nstruction def i n ition .

B-50

8TST
Operation: Assembler Syntax: Attributes: - BTST Dn, < ea > BTST # < data > , < ea >

Test a Bit

8TST

bit n u m be r > of Dest i nation) - Z;

S ize = (Byte, Long)

Description: A bit in the destination operand is tested, and the state of t he specified bit is reflected in the Z cond ition code. If a data reg i ster is the destination, then the bit n u m beri n g is mod u l o 32, allowing bit manipu lation on a l l bits i n a data reg i ster. If a memory l ocation is the dest ination, a byte is read from t hat locat ion, and the bit operat ion performed using the bit number, mod u l o 8, with zero referring to the least s i g n ificant bit. The bit n u m ber for this operat ion may be specified i n two d i fferent ways: 1 . I m mediate - the bit n u m ber is spec ified in a second word of t he i nstruction. 2. Regi ster - the bit n u mber i s contained in a data reg ister spec ified i n the i nstruct ion. Condition Codes:
x

N
-

V
-

I * I

N Z V C X

Not Set Not Not Not

affected. if the bit tested is zero. Cleared otherw i se. affected. affected. affected.

I nstruction Format (Bit N u m ber Dynam ic, spec ified in a reg ister):
15 14 13 12 11 10 Register Dn 9 8 7 6 5 4 Mode 3 2 Register 0 Effective Address

Instruction Fields (Bit N u m ber Dynamic): Register field - Specifies the data reg i ster w hose content is the bit number. Effective Address field - Spec ifies t he desti nation locat ion. O n ly data addressing modes are al l owed as shown:

II

B-51

8TST
Addr. Mode Mode Register

Test a Bit

8TST
Addr. Mode Mode Register

On * An (An) (An) + - (An) (d 1 6,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000
-

reg. number:On
-

(xxx).W (xxx).L # < data >

111 111 111

000 001 1 00

010 011 1 00 101 110 110 110 1 10

reg. nu mber:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (dSPC,Xn) (bd,PC,Xn) ([bd,PC,Xn],od) ([bd,PC],Xn,od)

111 111 111 111 111

010 011 011 011 011

* Long only; all others are byte only.

Instruction Format (Bit N u m ber Stat ic, spec if ied as i mmediate data):
15 0 0 14 0 0 13 0 0 12 0 0 11 1 0 10 0 0 9 0 0 s 0 0 7 0

I I
0

4 Mode

o Register

Effective Address Bit Number

Instruction Fields (Bit N u mber Stat i c): Effective Address field - Speci f ies the dest ination locat ion. O n ly data addressing modes are al lowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

On * An (An) (An) + - (An) (d 1 6,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000
-

reg. number:On
-

(xxx).w (xxx).L # < data >

111 111
-

000 001
-

010 01 1 100 101 110 1 10 1 10 1 10

reg. nu mber:An reg. number:An reg. number:An reg. number:An reg. number:An reg. nu mber:An reg. number:An reg. number:An

(d 1 6,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

111 111 111 111 111

010 011 01 1 011 01 1

* Long only; all others are byte only .

B i t N u m ber field - Specifies the bit number.

B-52

CA L L M
Operation:

CALL Module

CA L L M

Save cu rrent module state on stack; Load new module state from dest ination CALLM # < data > , < ea > U ns ized

Assembler Syntax: Attributes:

Description: The effective add ress of the i nstruction i s the locat ion of an external module desc riptor. A mod u l e frame i s created on the top of the stack, and the cur rent module state is saved i n the frame. The i mmediate operand specifies the number of bytes of arg u ments to be passed to. the cal led mod u le. A new module state is l oaded from the descri ptor addressed by the effective address. Add itional i n format ion is presented i n Appendix D. Condition Codes: Instruction Format:
15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 1 0 9 1 0 s 0 0 7 1

N ot affected.

1 1
1

4 Mode

Effective Address Argument Count

Register

I nstruction Fields: Effective Address field - Spec ifies the address of the module descriptor. Only con trol add ressing modes are al lowed as show n :
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

(xxx),W (xxx).L # < data >

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

111 111 111 111 111

010 011 011 011 011

Agrument Count field - Spec ifies the nu mber of bytes of arguments to be passed to the cal led mod u le. The 8-bi t field can specify from 0 to 255 bytes of arg u ments. The same n u m ber of bytes is removed from the stack by the RTM i nstruction.

8-53

CAS CAS2
Operation:

Compare and Swap with Operand CAS Dest i nat ion - Com pare Operand -- cc; if Z, Update_Operand -- Dest i nation else Dest ination -- Compare_Operand CAS2 Dest i nat ion 1 - Com pare 1 -- cc; if Z, Dest i nat ion 2 - Compare 2 -- cc if Z, Update 1 -- Dest i nation 1 Update 2 -- Dest i nation 2 else Dest i nat ion 1 -- Com pare 1 Dest i nation 2 -- Compare 2

CAS CAS2

Assembler Syntax: Attributes:

CAS Dc, Du, < ea > CAS2 Dc1 : Dc2, Du1 : Du2,( R n 1 ):(Rn2) Size = (Byte, Word, Long)

Description: The Effective Address operand(s) i s fetched and com pared to the com pare operand data reg i ster(s). If the operands match, the update operand data reg i ster(s) is (are) w ritten to the dest ination locat ion(s); otherw i se, the memory operand l oca t ion is left unchanged and the com pare operand is l oaded with the memory operand. The operat ion i s i ndivisible (using a read-modify-write memory cycle) to al l ow synchron izat ion of several processors. Additional i nformat ion is presented i n Appendix D_ Condition Codes: x N z N Z V C X Set Set Set Set N ot

1 -1 1 1 * 1 * 1
if the resu l t is negat ive. Cleared otherw i se. if the res u l t is zero. Cleared otherw i se. if an overflow is generated. Cleared otherwise. if a carry is generated. Cleared otherwise. affected.

Instruction Format: (Si n g le Operand):

15 14 13 12 11 1 1

0 0

0 0

0 0

0 0

Size

0 1 0

I I
1 Du

2 Register Dc

Effective Address

Mode I I 0 I 0 I

Instruction Fields: Size field - Spec ifies the s ize of the operation. 01 - byte operat ion. 1 0 - word operat ion. 1 1 - long operation. Effective Address field - Specifies the locat ion of the tested operand. Only alter able memory addressing modes are al lowed as shown below: Du field - Spec ifies the data reg ister which holds the update va lue to be w ri tten to the memory operand l ocat ion if the comparison i s successfu l . S i ng l e Operand Form Only
---

B-54

CAS CAS2

Compare and Swap with Operand

CAS CAS2

Dc field - Spec i f ies the data reg i ster which conta i n s the test value to be compared against the memory operand.
Addr. Mode On An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xn],od) ([bd,An],Xn,od) Mode
-

Register
-

Addr. Mode (xxx).w (xxx).l # < data >

Mode 111 111

-

Register 000 001

-

010 01 1 1 00 101 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 , PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn],od) ([bd,PC],Xn,od)

I nstruction Format (Dual Operand):

15 0 O/A1 O/A2 14

o I

13 0 Rn1 Rn2

12 0

11 1 0 0

10 Size 0

o I

0 0

o I

7 1 Ou1 Ou2

5 1 0 0

4 1 0 0

3 1 0 0

2 1 0 Oc1 Oc2

o
0

Instruction Fields: Size field - Specifies the s ize of the operation. 1 0 - word operat ion. 1 1 - long operat ion. D/A 1 , D/A2 fields - Specify w hether Rn1 and Rn2 reference data or address reg i sters, respect ively. 0-The correspond i n g reg ister i s a data reg ister. 1 -The correspond i n g reg i ster is an address reg ister. Rn1 , R n2 fields - Spec ify the n u m bers of the reg isters which conta i n the address of the f i rst and second tested operands, respectively. If the operands overlap i n memory, the res u lts o f any memory u pdate are u ndefi ned. Du1 , Du2 fields - Specify the data reg i sters which hold the update va lues to be written to the f i rst and second memory operand l ocations if the comparison i s successf u l . D c 1 , Dc2 f i e l d s - Spec ify t h e data reg isters which contai n t h e test va l ues to b e com pared against the f i rst and second memory operands, respectively. If Dc1 and Dc2 specify the same data reg ister and the comparison fai l s, the data reg ister is l oaded from the f i rst memory operand. Programming Note: The CAS and CAS2 i nstructions may be used to perform sec u re update operat ions on system control data structu res i n a m u lti processing environment. 8-55

a .

CH K
Operation: Assembler Syntax: Attributes:

Check Register Against Bounds If On < 0 or On > Sou rce then TRAP C H K < ea > , O n

CH K

Size = (Word, Long)

Description: The content of the data register specified in the instruction is exami ned and com pared to the u pper bound. The u pper bound is a twos comp lement integer. If the register value is less than zero or greater than the u pper bound, then the pro cessor initiates exception processing. The vector n u m ber is generated to reference the C H K instruction except ion vector. Condition Codes:
x N z V c

I * I u I u I u
N Z V C X Set if On < 0; cleared if O n > Source. U ndefi ned otherwise. U ndefi ned. U ndefi ned. U ndefi ned. N ot affected.

Instruction Format:
15 14

13

12

11

10 Register Dn

7 Size

4 Mode

2 Register

Effective Address

Instruction Fields: Register field - Specif ies the data register w hose content is checked. Size field - Specifies the size of the operation. 1 1 0- word operation. 1 00- long operation. Effective Address field - Specifies the u pper bou nd operand word. O n ly data add ressing modes are al lowed as shown:

8-56

CH K
Addr. Mode Mode

Check Register Against Bounds

CH K
Mode Register

Register

Addr. Mode

Dn * An (An) (An) + - (An) (d 1 6,An ) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,Anj,Xn,od)

000
-

reg. number:Dn
-

(xxx).W (xxx).L I# < data>

111 111 111

000 001 100

010 011 100 101 110 110 110 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (dSPC,Xn) (bd,PC,Xn) ([bd, PC,Xnj,od) ([bd,PC],Xn,od)

111 111 111 111 111

010 01 1 011 011 011

8-57

C H K2
Operation:

Check Register Against Bounds If Rn < Sou rce - l ower-bound or Rn > Source- upper-bo u nd Then TRAP C H K2 < ea > , R n

C H K2

Assembler Syntax: Attributes:

Size = (Byte, Word, Long)

Description: Check the value i n Rn against the bou nds pai r at the effective address loca t i on. The lower bound is at the address spec ified by the effective address, with the u pper bound at that address plus the operand length. For s i g ned comparisons, the arithmet ically smaller val u e should be the lower bound, w h i l e for u nsig ned com parison, the logically smaller val ue should be the lower bound. The s ize of the data to be checked, and the bounds to be u sed, may be spec ified as byte, word, or long. If the checked reg i ster is a data reg i ster and the operation size is byte or word, only the appropriate low-order part of Rn is checked. I f the checked reg i ster is an address reg ister and the operat ion s ize is byte or word, the bou nds operands are sign-extended to 32 bits and the resu ltant operands com pared against the f u l l 32 bits of An. If the u pper bound equals the lower bou nd, then the valid range i s a single value. If the reg ister operand is out of bou nds, the processor i n i t iates except ion processing. The vector n u m ber is generated to reference t he CH K i nstruction except ion vector. Otherwise, the next i n struction is executed. Condition Codes:

1 N Z V C X

* 1

U ndefi ned. Set if Rn is equal to either bou nd. Cleared otherw i se. U ndefi ned. Set if Rn is out of bounds. Cleared otherw i se. Not affected .

Instruction Format:
15 14

0
D/A

Register

I0I0

13

12

11

10
Size

0
1

0 1 0

8 0 0

7
1

6 1

4 Mode

0
Register

Effective Address

0 1 0 1 0 1 0 1 0 1 0

B-58

C H K2

Check Register Against Bounds

C H K2

Instruction Fields: Size field - Spec ifies the s ize of the operation. O- byte operation. 0 1 - word operation. 1 0- long operat ion. Effective Address field - Spec if ies the location of the bounds operands. O n ly con t rol address i n g modes are al lowed as shown below: D/A field - Specifies w hether an address reg ister or data reg ister is to be checked. O- Data reg ister. 1 -Address reg ister. Reg i ster field - Specifies the add ress or data reg ister w hose content is to be checked.
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od)

(xxx).W (xxx).L # < data >

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 1 10 110 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,XnJ,od) ([bd,PC].Xn,od)

111 111 111 111 111

010 011 011 011 011

II

8-59

CLR
Operation: Assembler Syntax: Attributes: 0 - Dest i nation

Clear a n Operand

CLR

Size = (Byte, Word, Long)

CLR < ea >

Description: The dest i nat ion is cleared to a l l zero. The s ize of the operat ion may be specif ied to be byte, word, or long. Condition Codes:

1-I
N Z V C X

N 0

x 1

V 0

c 0

A l ways cleared. A l ways set. A l ways c leared. A l ways cleared . Not affected.

Instruction Format:
15 14 13 12 11 10 9 a 7 6 5 4 Mode 3 2 Register o Effective Address

Instruction Fields: Size field - Specif ies the s ize of the operation. OO- byte operat ion. 01 - word operat ion. 1 0 - long operat ion. Effective Address field - Spec ifies the dest i nation locat ion. Only data alterable address i n g modes are a l l owed as shown:
Addr. Mode Mode Register Addr. Mode (xxx).W (xxx).L Mode Register

Dn * An (An) (An) + - (An) (d 1 6,An) (da,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od)

000
-

reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

010 01 1 1 00 1 01 110 1 10 1 10 110

111 111
-

000 001
-

# < data >

(d 1 6,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,XnJ,od) ([bd, PCJ,Xn,od)

B-60

CM P
Operation: Assembler Syntax: Attributes: Dest i nat ion - Sou rce C M P < ea > , Dn

Compare

CMP

Size = (Byte, Word, Long)

Description: Su btract the sou rce operand from the spec if ied data reg ister and set the cond ition codes accord i ng to the res u l t; the data reg ister is not changed. The s ize of the operation may be byte, word, or long. Condition Codes: x N z V c

1 - 1 1 1 1 1
N Z V C X Set Set Set Set N ot if the resu l t is negat ive. Cleared otherw i se. if the resu l t is zero. Cleared otherwise. if an overflow is generated. Cleared otherw i se. if a borrow is generated. Cleared otherw i se. affected.

Instruction Format:
15 14 13 12 11 10 Register On 9 8 7 OpMode 6 5 4 Mode 3 2 Register 0 Effective Address

Instruction Fields: Regi ster field - Spec ifies the dest i nat ion data reg ister. Op-M ode field Byte Word Long Operation Dn - ( < e a > ) 000 001 010 Effective Address field - Spec ifies the sou rce operand. A l i addressing modes are al lowed as shown:

B-61

CMP
Addr. Mode Mode Register

Compare

CMP
Addr. Mode Mode Register

Dn An * (An) (An) + - (An) (d 1 6,An ) (de,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,AnJ,Xn,od) * Word and Long only.

000 001 010 011 1 00 101 1 10 1 10 1 10 1 10

reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(xxx).w (xxx).L # < data >

111 111 111

000 001 100

(d 1 6,PC) (de,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

111 111 111 111 111

010 011 011 01 1 01 1

Note:

C M PA is used w hen the dest i nation is an address register. C M P I is used when the sou rce i s i mmediate data. C M P M i s used for memory to memory compares. M ost assem blers automat ically make t h i s disti nction.

862

C M PA
Operation: Assembler Syntax: Attributes: Dest i nat ion - Sou rce C M PA < ea > ,An

Compare Address

C M PA

Size = (Word, Long)

Description: Subtract the source operand from the desti nat ion address reg i ster and set the cond ition codes accord i n g to the res u lt; the address reg ister is not changed. The s ize of the operation may be specified to be word or long. Word length sou rce operands are s i g n extended to 32-bit quantities before the operation is done. Condition Codes:
x N z V c

1 - 1 * 1 * 1 * 1 *
N Z V C X Set if the resu l t is negat ive. Cleared otherw i se. Set i f the resu l t is zero. C leared otherwise. Set if an overflow is generated. Cleared otherwise. Set if a borrow is generated. Cleared otherw ise. Not affected.
7
OpMode

Instruction Format:
15 14 13 12 11 10 Register An 9 8

4 Mode

2 Register

Effective Address

Instruction Fields: Reg i ster field - Specifies the dest i nation data reg ister. Op-M ode field - Specifies the size of the operat ion: 0 1 1 -word operat ion. The source operand is s i gn-extended to a long operand and the operat ion is performed on the address reg ister using a l l 32 bits. 1 1 1 - long operat ion. Effective Address field - Spec ifies the source operand. All addressing modes are al lowed as shown:

8-63

C M PA
Addr. Mode Mode

Compare Address

C M PA
Mode Register

Register

Addr. Mode

Dn An (An) (An) + - (An) (d 1 6 ,An) (dB,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od)

000 001 010 011 100 101 1 10 110 1 10 110

reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(xxx).w (xxx).L # < data >

111 111 111

000 001 1 00

(d 1 6 ,PC) (dB,PC,Xn) (bd,PC,Xn) ([bd, PC,XnJ,od) ([bd,PCJ,Xn,od)

111 111 111 111 111

010 011 011 011 011

8-64

CM PI
Operation: Assembler Syntax: Attributes:

Compare Immediate

C M PI

Dest i nation - I m med iate Data C M P I # < data > , < ea >

Size = (Byte, Word, Long)

Description: Su btract the i m med iate data from the dest i nation operand and set the con d i t ion codes accord i ng to the resu lt; the dest i nation locat ion i s not changed. The s ize of the operation may be specif ied to be byte, word, or long. The s ize of the im mediate data matches the operation s ize. Condition Codes:

1-1 * 1 * 1 *
N Z V C X Set Set Set Set Not

*1

if the resu l t is negat ive. Cleared otherwise. if the resu l t is zero. Cleared otherw i se. if an overflow is generated . Cleared otherw ise. if a borrow is generated . Cleared otherw ise. affected.

Instruction Format:
o

15 14 13 12 11 1 0 1010I0I1I I0I0
1

7 Size

Word Data

Long Data

5 4 3 2
Mode Byte Data

Effective Address

Register

Instruction Fields: Size field - Spec i f ies the s ize of the operat ion: OO- byte operat ion. 01 -word operation. 1 0- long operat ion. Effective Address field - Spec ifies the dest i nati o n operand. Only data address i n g modes are al lowed a s shown:

B-65

C M PI
Addr. Mode On An (An) (An) + - (An) (d 1 6,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od) Mode 000
-

Compare Immediate

CMPI
Mode 111 111
-

Register reg. number:On

-

Addr. Mode (xxx).W (xxx).L # < data>

Register 000 001

-

010 011 1 00 1 01 1 10 110 1 10 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC],Xn,od)

111 111 111 111 111

010 011 011 011 011

I m mediate field If s ize = 00, then If size = 01 , then If size = 1 0, then

(Data i m mediately follow i n g the inst ruct ion): the data is the low order byte of the i m med iate word. the data i s the entire i m med iate word. the data i s the next two i mmed iate words.

866

CMPM
Operation: Assembler Syntax: Attributes: Destination - SOu rce C M P M (Ay) + ,(Ax) +

Compare Memory

CMPM

Size = (Byte, Word, Long)

Description: Su btract the source operand from the dest i nation operand, and set the con d ition codes accord i n g to the resu l ts; the dest i nation location i s not changed. The operands are always addressed with the posti ncrement addressing mode, u s i n g the address reg isters specified in the i nstruct ion. The size of the operat ion may be spec ified to be byte, word, or long. Condition Codes: x N z c

1 - 1 * 1 * 1 * 1 *
N Z V C X Set Set Set Set Not

if the result is negat ive. Cleared otherw ise. if the resu l t is zero. Cleared otherw ise. if an overflow is generated. Cleared otherwise. if a borrow is generated. Cleared otherwise. affected.

Instruction Format:
15 14 13 12 11 10 Register Ax 9 8 7 Size 6 5 4 3 2 Register Ay 0

I nstruction Fields: Register Ax field - (always the dest i nat ion) Spec ifies an address reg ister for the post i ncrement add ressing mode. S ize field - Specifies the s ize of the operation: O- byte operat ion. 01 - word operat ion. 1 0 - long operation. Regi ster Ay field - (always the sou rce) Spec ifies an address reg i ster for the post i ncrement addres s i n g mode.

--

B-67

C M P2
Operation:

Compare Register Against Bounds Com pare An < Sou rce- lower-bou nd or A n > Source- u pper-bou nd and Set Cond ition Codes C M P2 < ea > , A n

C M P2

Assembler Syntax: Attributes:

Size = (Byte, Word, Long)

Description: Compare the va lue i n An against the bou nds pai r at the effective address l ocation and set the cond ition codes accord i n g ly. The lower bou nd is at the address specified by the effective address, with the u pper bound at that address plus the operand length. For s i g ned comparisons, the arithmet ically smal ler value should be the lower bound, w h i le for u ns i g ned comparison, the logica l l y smal ler value should be the lower bound. The s i ze of the data to be com pared, and the bou nds to be u sed, may be spec ified as byte, word, or long. If the com pared reg i ster i s a data reg ister and the operation size is byte or word, o n ly the appropriate low-order part of Dn is checked. I f the checked reg i ster is an address reg i ster and the operation s ize is byte or word, the bounds operands are S i g n-extended to 32 bits and the resu ltant operands compared against the f u l l 32 bits of An. If the u pper bou nd eq uals the lower bound, then the va l i d range is a s i n g l e value. NOTE: This i nstruction i s analougous to C H K2, but avoids causing except ion pro cess i n g to hand le the out-of-bou nds case. Condition Codes: x N z

1 - l u l * l u
N Z V C X
15

* 1

U ndefi ned. Set if An is eq ual to either bou nd. Cleared otherw i se. U ndefi ned. Set if An is out of bounds. Cleared otherw i se . Not affected.
14 13 12 11 1

Instruction Format:

0
D/A

Register

I0I0

0
Size

7 1

6 1

4 Mode

0
Register

0 0

0 1 0

0 0

Effective Address

0 1 0 1 0 [ 0 1 010

B-68

C M P2

Compare Register Against Bounds

C M P2

I nstruction Fields: Size field - Spec ifies the s ize of the operat ion. OO- byte operat ion. 01 - word operation. 1 0- long operat ion. Effective Address field - Spec ifies the location of the bou nds pair. Only control addressing modes are al l owed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

Dn An (An) (An) + - (An) (d 1 6,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

(xxx).w (xxx).L lI < data >

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 , PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

111 111 111 111 111

010 011 011 011 011

D/A field - Specifies w hether an address reg ister or data reg ister is to be compared. O- Data reg ister. 1 -Address reg ister. Register field - Specifies the address or data reg ister whose content is to be checked.

8-69

cp Bcc
Operation: Assembler Syntax: Attributes:

Branch on Coprocessor Condition

cp Bcc

If cpcc true then PC + d - PC cpBcc < label >

Size = (Word, Long)

Description: If the specified coprocessor cond ition is met, program execution cont i n ues at location (PC) + d i s placement. The d i splacement is a twos complement i nteger which counts the relat ive d istance in bytes. The value in the PC is the address of the d isplacement word(s). The disp lacement may be either 16 bits or 32 bits. The copro cessor determ i nes the s pec ific cond ition from the cond ition field i n the operat ion word. Condition Codes: Not affected. Instruction Format:
15 1

14 1

13 1

I 1 I

12

11

10 Cpld

Optional Coprocessor Defined Extension Words Word or Long Word Displacement

I 0J

7 1

6 W/L

Coprocessor Condition

Instruction Fields: Cpld field - I dentifies the coprocessor that is to process t h i s operat ion. W/L field - Specifies the size of the displacement. O-the d i s placement is 16 bits. 1 -the displacement is 32 bits. Coprocessor Cond ition field - Specifies the coprocessor cond ition to be tested. This field is passed to the coprocessor, which provides d i rectives to the main processor for processing t h i s i nstruction. 1 6Bit Displacement field - The shortest d i splacement form for coprocessor branches is 16 bits. 32Bit Displacement field - A l lows a disp lacement larger than 1 6 bits .

B70

c p D Bcc Test Coprocessor Condition Decrement and Branch cp D Bcc

Operation: Assembler Syntax: Attributes: If cpcc false then l(Dn - 1 - Dn; If Dn * - 1 then PC + d - PC)

cpDBcc Dn, < label > S ize = (Word)

Description: If the specified coprocessor cond ition is met, execut ion continues with the next i nstruction. Ot herwise, the low order word in the specified data reg ister is decremented by one. I f the res u lt i s eq ual to - 1 , execution cont i n ues with the next i nstruction. I f the res u lt is not equal to - 1 , execution contin ues at the locat ion i n dicated by the c u rrent value of PC p l u s the s i g n extended 1 6-bit displacement. The value in the pC is the address of the displacement word. The coprocessor deter m i nes the specific cond ition from the condition word which follows the operation word. Condition Codes: Instruction Format: N ot affected.

15 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2 0 1 1 1 1 1 1 1 1 Cpld 1 0 1 0 1 1 1 0 1 0 1 1 1 Register Coprocessor Condition 0 1 0 10 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Optional Coprocessor Defined Extension Words Displacement

Instruction Fields: Cp-Id field - Identifies the coprocessor t hat is to process this operat ion. Register field - Specifies the data reg ister which i s the cou nter. Coprocessor Condition field - Specifies the coprocessor cond ition to be tested . Th is field is passed to the coprocessor, which provides d i rectives to the main processor for processi n g this i nstruction. Disp lacement field - Spec i f ies the d i stance of the branch ( i n bytes) .

8-71

cpG E N
Operation: Assembler Syntax: Attributes:

Coprocessor General Function

cpG E N

Pass Command Word to Coprocessor

cpG EN < parameters as defi ned by coprocessor >

U n s ized

Description: This i nstruction is the form u sed by coprocessors to spec ify the general data proces s i n g and movement operations. The coprocessor determ i nes the specific operation f rom the command word which fol l ows the operation word. Usually a coprocessor def i nes s pecific i nstances of this i nstruction to provide its i n struction set. Condition Codes: I nstruction Format:
15 1

M ay be mod i fied by coprocessor. U nchanged otherwise.

I I I I
1 1 1

14

13

12

11

10 Cpld

Coprocessor Command

I I I I
0 0 0

4 Mode

0 Register

Effective Address

Optional Effective Address or Coprocessor Defined Extension Words

I nstruction Fields: Cp-Id field - Identifies the coprocessor that i s to process t h i s operat ion. Effective Address field - Spec ifies the l ocat ion of any operand outside the coprocessor. The al lowable addressi n g modes are determ i ned by the operation to be performed. Coprocessor Command field - Spec ifies the coprocessor operat ion to be per formed. This word is passed to the coprocessor, which provides d i rectives to the main processor for proceSS i n g t h i s i nstruction .

8-72

c p R ESTO R E Coprocessor Restore Functions c p R ESTO R E

(Privileged Instruction) Operation: Assembler Syntax: Attributes: Restore I nternal State of Coprocessor cp R ESTO R E < ea > U n sized

Description: This i nstruct ion is u sed to restore the i nternal state of a coprocessor. Condition Codes: Instruction Format:
15 14 13 12 11 10 Cpld 9 s 7 6 5 4 Mode 3 2 Register Effective Address

Not affected.
o

Instruction Field: Cp-Id field - Identif ies the coprocessor that i s to be restored. Effective Address field - Specif ies the locat ion where the i nternal state of the co processor is l ocated. Only post i ncrement or control addressing modes are al lowed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od)

(xxx).w (xxx).L # < data >

111 111
-

000 00.1
-

010 011
-

reg. number:An reg. number:An

-

1 01 1 10 1 10 1 10 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,XnJ,od) ([bd,PCJ,Xn,od)

111 111 111 111 111

010 011 01 1 01 1 01 1

Programmer's Note: I f the format word ret urned by the coprocessor indicates "come agai n " , pen d i n g i nterrupts are not serviced.

8-73

cpSAV E
Operation: Assembler Syntax: Attributes:

Coprocessor Save Function (Privileged Instruction)

cpSAV E

Save I nternal State of Coprocessor cpSA VE < ea > Uns ized

Description: This i nstruction is u sed to save the i nternal state of a coprocessor. Condition Codes: I nstruction Format:
11 10 Cpld 9 s 7 6 5 4 Mode 3 2 Register o Effective Address

N ot affected.

I nstruction Fields: Cp-Id field - Identifies the coprocessor that is to save its state. Effective Address field - Spec ifies the locat ion where the i nternal state of the coprocessor i s to be saved. O n ly predecrement or alterable control address i n g modes are a l l owed a s shown:
Addr. Mode Mode
-

Register
-

Addr. Mode (xxx)W (xxx).l

Mode

Register

Dn An (An) (An) + - (An) (d 1 6,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

111 111
-

000 001
-

010
-

reg. number:An
-

# < dat a >

1 00 1 01 110 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An (d 1 6 ,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)
-

8-74

c p Scc
Operation:

Set o n Coprocessor Condition If cpcc t rue then 1 s - Destination else Os - Destination cpScc < ea >

c pScc

Assembler Syntax: Attributes:

Size = (Byte)

Description: T h e specified coprocessor cond i t i on code is tested; if t h e cond ition is t rue, the byte specif ied by the effective address i s set to TRUE (al l ones), otherw i se that byte is set to FALSE (al l zeros). The coprocessor determines the specific cond i t ion from the cond ition word which fol lows the operat ion word. Condition Codes: I nstruction Format:
15 1 0 14 1 0 13 1 0 12 1 0 11 10 Cpld 9 a 0 0 0 7 0 0 6 1 0 5 4 Mode 3 2 Effective Address Coprocessor Condition

Not affected.

o
Register

Optional Effective Address or Coprocessor Defined Extension Words

o I o I

Instruction Fields: Cp-Id field - Identifies the coprocessor that is to process this operat ion. Effective Address field - Spec ifies the dest i nation locat ion. Only data alterable addressing modes are a l l owed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn],od) ([bd,An],Xn,od)

000
-

reg. number:Dn
-

(xxx).w (xxx).L # < data >

111 111
-

000 001
-

010 01 1 1 00 1 01 110 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6, PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn],od) ([bd,PC),Xn,od)

Coprocessor Cond it ion field - Spec ifies the coprocessor cond ition to be tested . This field is passed to the coprocessor, which provides d i rect ives to the main processor for processing this i nstruction.

B-75

c p T RA Pcc
Operation: Assembler Syntax: Attributes:

Trap o n Coprocessor Condition

c pT RA Pcc

If cpcc t rue then TRAP cpTRAPcc cpTRAPcc # < data >

Uns ized or Size = (Word, Lon g)

Description: I f t h e selected coprocessor cond ition i s true, t h e processor i n it iates excep t ion process i ng. The vector n u m ber is generated to reference the cpTRAPcc excep t i on vector, the stacked program counter is the address of the next i n struct ion. If the sel ected cond ition i s not true, no operation is performed, and execution cont i n ues with the next i nstruct ion. The coprocessor determ i nes the specific cond ition from the cond ition word which fol lows the operat ion word . Fol low ing the cond ition word is a user-def i ned data operand spec ified as i m mediate data data, to be used by the t rap hand ler. Condition Codes: Instruction Format: Not affected.

15 14 13 12 11 1 0 9 8 7 6 5 4 3 2 0 Cp-Id 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 '1 I OpMode Coprocessor Condition o 1 0 1 o 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Optional Coprocessor Defined Extension Words Optional Word or Long Word Operand

I nstruction Fields: Cp-Id field - Identif ies the coprocessor that is to process t h i s operat ion. Op-Mode field - Selects the i nstruction form. 0 1 O - i nstruct ion i s followed by one operand word . 01 1 - l nstruction is followed by two operand words. 1 00 - l nstruction has no fol low i nQ operand words. Coprocessor Condition field - Spec ifies the coprocessor cond ition to be tested. This field is passed to the coprocessor, which provides d i rect ives to the main processor for processi n g this i nstruction .

8-76

O Bee
Operation: Assembler Syntax: Attributes:

Test Condition, Decrement, and Branch

O Bee

If cond ition false then (Dn - 1 - Dn; If Dn :;:. - 1 then PC + d - PC) OSce On, < label >

Size = (Word)

Description: This i nstruction is a l ooping pri m it ive of three parameters: a cond ition, a cou nter (data reg ister), and a displacement. The instruction first tests the cond ition to determine i f the termination condition for the loop has been met, and if so, no operat ion i s performed. I f the term i nation cond ition is not t rue, the l ow order 16 bits of the counter data reg i ster are decremented by one. If the res u l t is - 1 , the counter is exhausted and execution cont i n ues with the next i nstruction. I f the resu l t i s not eq ual to - 1 , execution cont i n ues at the locat ion i nd icated by the c u rrent value of the PC plus the s i g n-extended 1 6-bit d isplacement. The value in the PC i s the cu rrent i nstruction location plus two. "cc" may specify the fol low i n g cond itions:
CS EQ F GE

cc

GT
HI LE

carry clear carry set equal never true greater or equal greater than high less or equal

0100 0 1 01 01 1 1 0001 1 1 00 1 1 10 0010 1111

Cz Z + N .V+ N.V

C C Z 0 N . V + N.Y N . V .Z+ N.V.Z

LS LT MI NE PL T VC VS

low or same less than minus not equal plus always true overflow clear overflow set

001 1 1 1 01 1011 01 1 0 1010 0000 1 000 1001

C+Z N .V + N.V N Z N 1 V V

Condition Codes: Instruction Format:

N ot affected.

11

10

8
Displacement

2
Register

Condition

Instruction Fields: Condition field - One of the sixteen conditions d i scussed in description . Regi ster field - Specifies the data reg ister which is the cou nter. Displacement field - Specifies the d istance of the branch ( i n bytes). Notes: 1 . The term i n at i ng cond ition is l i ke that defi ned by the U NTI L loop constructs of h i gh-level languages. For example: D B M I can be stated as "decrement and branch u n t i l m i nus".

B-77

D Bee

Test Condition, Decrement, a n d Branch

D Bee

2. M ost assem blers accept O B RA f o r O B F for use w h e n no condition is req u i red for term i nation of a l oop. 3. There are two basic ways of enteri n g a loop: at the beg i n n i n g or by branching to the tra i l i n g O Bcc i nstruction. If a loop structure termi nated with OBcc is entered at the beg i n n i n g, the control i ndex count m u st be one less than t he n u m ber of loop executions desired. This count is u seful for i ndexed add ress i n g modes and dynamically specified bit operations. H owever, w hen enteri ng a loop by branching d i rect ly to t he trai l i n g O Bcc i nstruction, the control i ndex should eq ual the loop execution count. I n this case, if a zero count occurs, the OBcc i nstruction w i l l not branch, cau s i n g a complete bypass of the main l oop.

B-78

D I VS D I VS L
Operation: Assembler Syntax: D I VS.W < ea > , D n DIVS. L < ea > , Dq DIVS. L < ea > , D r: Dq D IVSL. L < ea > , Dr: Dq

Signed Divide Dest i nat ion/Source - Dest i nation 32/ 1 6 - 1 6r: 1 6q 32/32 - 32q 64/32 - 32r:32q 32/32 - 32r:32q

D I VS D I VS L

Attrib4tes:

Size = (Word, Long)

Description: D ivide the desti nation operand by the sou rce and store the result i n the destination. The operation is performed u s i n g s i g ned arithmetic. The i nstruction has a word form and three long forms. For the word form, the dest i nation operand i s a long word and the source operand i s a word. The resu l t is 32bits, such that the quotient is in the l ower word (least s i g n i ficant 16 bits) of the dest i nation and the remai nder is in t he u pper word (most s i g n ificant 16 bits) of the dest i nation. N ote t hat the s i g n of the remainder i s the same as the s i g n of the d ividend. For the f i rst long form, the desti nation operand is a long word and the sou rce operand is a long word. The resu l t is a long q uotient, and the remai nder is d iscarded. For the second long form, the dest i nation operand is a q uad word, contai ned in any two data reg i sters, and the sou rce operand is a long word. The resu l t i s a long word quotient and a long word remai nder. For the t h i rd long form, the dest i nation operand is a long word and the sou rce operand is a long word. The res u lt is a long word q uotient and a long word remai nder. Two special cond itions may arise d u ri n g the operat ion: 1 . D ivision by zero causes a trap. 2. Overlow may be detected and set before completion of the i nstruction. If overfl ow is detected, the condition is flagged but the operands are u naffected. Condition Codes:

1-1 * 1 * 1 * 1 0
N Z V C X

II

Set if the quotient i s negat ive. Cleared otherw i se. U ndefi ned if overf low or d ivide by zero. Set if the quotient is zero. Cleared otherw i se. U ndefi ned if overflow or divide by zero. Set if d ivision overflow is detected. Cleared otherwise. A l ways cleared. N ot affected. 879

D I VS D I VS L
Instruction Format (word form):
15 14 13 12 11 10 Register Dn

Signed Divide

D I VS D I VS L
5 4 Mode 3 2 Register o

Effective Address

I nstruction Fields: Register field - Spec ifies any of the eight data reg i sters. This field always specifi es the destination operand. Effective Add ress field - Specifies the sou rce operand. Only data address i n g modes are a l l owed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

Dn An (An) (An) + - (An) (d 1 6,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000
-

reg. number:Dn
-

(xxx).W (xxx).L # < data >

111 111 111

000 001 100

010 01 1 1 00 101 1 10 1 10 110 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6, PC) (dS,PC,Xn) (bd,PC,Xn) ([bd, PC,Xn),od) ([bd,PC),Xn,od)

111 111 111 111 111

010 011 011 01 1 011

Note:

Overflow occurs if the q uotient is larger than a 1 6-bit s i g ned i n teger.

Instruction Format (long form):

15 0 0 14 1

Register Dq

I I
0

13

12 0

11 1 1

10 1 Sz

9
0 0

s 0 0

7 0 0

6 1 0

4 Mode 0

2 Register

Effective Address

I I

Register Dr

I nstruction Fields: Effective Address field - Spec ifies the sou rce operand. Only data address i n g modes are al lowed a s shown:

8-80

D IVS D I VS L
Addr. Mode Mode Register

Signed Divide

D I VS D I VS L
Addr. Mode Mode Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od)

000
-

reg. llumber:Dn
-

(xxx).w
(xxx).L # < data >

111 111 111

000 001 1 00

010 01 1 100 1 01 110 110 1 10 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,XnJ,od) ([bd,PCJ,Xn,od)

111 111 111 111 111

010 011 011 011 01 1

Reg ister Dq field - Specifies a data reg ister for the dest i nation operand. The low order 32 bits of the d ividend comes from t h i s reg i ster, and the 32-bit quotient i s loaded i nto this reg i ster. Sz field - Selects a 32 or 64 bit d ivision operat ion. 0-32-bit d ividend i s i n Regi ster Dq. 1 -64-bit d ividend i s i n Dr:Dq. Reg i ster Dr field - After the d ivision, the 32-bit remai nder is loaded i nto t h i s reg i ster. If Dr = D q , o n ly t h e quotient i s retu rned. I f S z is 1 , t h i s f i e l d a l so spec ifies the data reg i ster i n which the h i g h order 32 bits of the d ividend i s l ocated. Note: Overflow occu rs if the quotient is larger than a 32-bit s i g ned integer.

8-81

DIVU DIVU L
Operation: Assembler Syntax: DIVU.w < ea > , D n DIVU . L < ea > , Dq DIVU . L < ea > , Dr:Dq DIVUL. L < ea > , Dr: Dq

Unsigned Divide

DIVU DIVU L

Dest i nation/Source ...... Dest i nat ion 32/1 6 ...... 1 6r: 1 6q 32/32 ...... 32q 64/32 ...... 32r:32q 32/32 ...... 32r:32q

Attributes:

Size = (Word, Long)

Description: D ivide the dest i nation operand by the sou rce and store the res u l t i n the dest i nat ion. The operation i s performed u s i ng u n s ig ned arithmetic. The i nstruction has a word from and three long forms. For the word form, the dest i nation operand i s a long word and the sou rce operand is a word. The resu l t is 32bits, such that the q u otient i s in the l ower word (least s i g n ificant 16 b its) of the dest i nation and the remai nder is in the u pper word (most s i g n i f icant 16 bits) of the desti nation. N ote t hat the s i g n of the remai nder i s the same as the s i g n of the d ividend. For the f i rst long form, the dest i nation operand i s a long word and the sou rce operand is a long word. The resu l t is a long word quotient, and the remai nder i s d i scarded. For the second long form, the desti nation operand i s a q uad word, contained in any two data reg isters, and the sou rce operand i s a long word. The resu l t i s a long word quotient and a long word remainder. For the t h i rd long form, the dest i nat ion operand is a long word and the sou rce operand is a long word. The res u l t is a long word quotient and a long word remai nder. Two special cond i t ions may arise: 1 . Division by zero causes a t rap. 2. Overlow may be detected and set before completion of the i nstruction. If overflow i s detected, the condition i s flagged but the operands are u naffected.

Condition Codes:

1 - 1 * 1 * 1 * 1 0 1
N Z V C X Set if the quotient is negat ive. Cleared otherw i se. U ndefi ned if overflow or d ivide by zero. Set if the quotient is zero. Cleared otherw ise. U ndef i ned if overflow or d ivide by zero. Set if d ivision overflow is detected. Cleared otherw i se. A l ways cleared. N ot affected. 882

DIVU DIVU L
Instruction Format (word form):
15 14 13 12 11 10 Register Dn

U nsigned Divide

D IV U DIVU L
4 Mode 3 2 Register

Effective Address

I nstruction Fields: Reg ister field - Spec ifies any of the eight data reg isters. This field always spec if ies the destination operand. Effective Address field - Specifies the sou rce operand. O n ly data addressing modes are a l lowed as shown:
Addr. Mode Mode Register Addr. Mode (xxx)W (xxx).l Mode Register 000

Dn An (An) (An) + - (An) (d 1 6 ,An) (de,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000
-

reg. number:Dn
-

111 111 111

001 1 00

010 011 1 00 1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

# < data >

(d 1 6 ,PC) (de,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

111 111 111 111 111

010 01 1 01 1 01 1 011

Note: Overf low occurs if the quotient is larger than a 1 6-bit u n s ig ned i n teger. Instruction Format (long form):
15 0 0 14 1

Register Dq

I I
0

13

12 0

11 1 0

10 1 Sz

9
0 0

e 0 0

7 0 0

6 1 0

4 Mode 0

o
Register Register Dr

Effective Address

I I I
0

Instruction Fields: Effective Address field - Specifies the sou rce operand. O n ly data address i n g modes are allowed a s shown:

8-83

DIVU DIVU L
Addr. Mode Mode

Unsigned Divide

DIVU DIVU L
Mode Register

Register

Addr. Mode

On An (An) (An) + - (An) (d 1 6 ,An) (dB,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000
-

reg. number:On
-

(xxx).W (xxx).L # < data>

111 111 111

000 001 100

010 011 1 00 101 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (dB,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

111 111 111 111 111

010 01 1 011 011 011

Regi ster Dq field - Spec ifies a data reg ister for the dest i nation operand. The low order 32 bits of the d ividend come from t h i s reg i ster, and the 32-bit q uotient is loaded into t h i s reg ister. Sz field - Selects a 32 or 64 bit d ivision operation. 0-32-bi t d ividend i s in Regi ster Dq. 1 -64-bit d ividend i s in Dr:Dq. Reg i ster Dr field - After the d ivision, the 32-bit remai nder i s loaded i n tp t h i s reg ister. I f Dr = D q , o n ly t h e quotient i s ret u rned. I f S z i s 1 , t h i s f i e l d also specifies the data reg i ster in which the high order 32 bits of the d ividend are l ocated . Note: Overflow occurs if the quotient is larger than a 32-bit u n s i g ned i n teger.

II

8-84

EO R
Operation: Assembler Syntax: Attributes:

Exclusive OR Logical Source e Dest i nation - Dest i nation EOR On, < ea >

EO R

Size = (Byte, Word, Long)

Description: Exc l u s ive OR the sou rce operand to the desti nation operand and store the resu l t i n the dest i nation locat ion. The s ize of the operat ion may be specified to be byte, word, or long. This operat ion is restricted to data registers as the sou rce operand. The dest ination operand is spec ified in the effective address field. Condition Codes:
x N z V

1 - 1 * 1 * 1 0 1 0
N Z V C X

Set if the most s i g n i f icant bit of the resu l t is set. Cleared otherwise. Set if the resu l t is zero. C leared otherw i se. A l ways c leared. A l ways cleared. N ot affected.

Instruction Format (word form):

15

14

13

12

11

10

7 OpMode

4
Mode

2
Register

Register On

Effective Address

I nstruction Fields: Reg i ster field - Spec ifies any of the eight data reg isters. OpM ode field Byte Word Long Operation 1 00 1 01 110 < ea > e < Dx > - < ea > Effective Address field - Specifies the dest i nation operand. O n ly data alterable addressing modes are allowed as shown:

B85

EO R
Addr. Mode Mode

Exclusive OR Logical

EO R
Mode Register

Register

Addr. Mode

Dn An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,Anl,Xn,od)

000
-

reg. number:Dn
-

(xxx).W (xxx).l # < data >

111 111
-

000 001
-

010 01 1 1 00 101 110 110 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PC1,Xn,od)

Note: Memory to data reg ister operat ions are not al lowed. EORI is used when the sou rce is i m mediate data. M ost assemblers automat ically make t h i s distinction .

8-86

EO R I
Operation: Assembler Syntax: Attributes:

Exclusive O R I mmediate I m mediate Data Ell Dest i nation - Dest i nation

EORI # < data > , < ea >

EO R I

Size = (Byte, Word, Long)

Description: Exc l u s ive O R the i mmediate data to the dest i nation operand and store the resu l t in the dest i nation l ocation. The s ize of the operation may be specified to be byte, word, or long. The i mmed iate data matches the operation s ize. Condition Codes:

1- 1 * 1 * 1 0
N Z V C X

0 1

Set if the most s i g n i f i cant bit of the resu l t is set. Cleared otherwise. Set if the resu l t is zero. Cleared otherwise. A l ways c leared. A l ways c leared. N ot affected.

Instruction Format:
15

1 1 1 1 1 1 1
0 0 0
Word Data

14

13

12

11

10

7
Size

(16

Bits)

Long Data

(32

Bits, i n c l u d i ng Previous Word)

4
Mode

0
Register

Effective Address

Byte Data

(8

Bits)

Instruction Fields: Size field - Spec ifies the s ize of the operat ion: OO- byte operat ion. 01 -word operation. 1 0- long operat ion. Effective Address field - Specifies the dest i nation operand. Only data alterable address i n g modes are a l l owed as shown:

B-87

EO R I
Addr. Mode Mode

Exclusive O R I mmediate

EO R I
Mode Register

Register

Addr. Mode

On An (An) (An) + - (An) (d 1 6,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000
-

reg. number:On
-

(xxx).W (xxx).L # < dat a >

111 111
-

000 001
-

010 011 100 101 110 110 110 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

I m mediate field If size = 00, then If size = 01 , then If s ize = 1 0, then

(Data i mmediately fol low i n g the i nstruction): the data is the low order byte of the i m med iate word. the data i s the ent i re i m med iate word. the data is next two i m med iate words.

iii

B88

EO R I to C C R
Operation: Assembler Syntax: Attributes:

Exclusive O R Immediate to Condition Code

EO R I to CC R

Sou rce E9 CCR - CCR EORI # < data > ,CCR

Size = (8yte)

Description: Exclus ive OR the i m med iate operand with the condition codes and store the resu l t in the l ow-order byte of the status register. Condition Codes:
x

* 1 * 1 * 1 * 1 *1 N Changed if bit 3 of i m med iate operand

Z V C X Changed Changed Changed Changed if if if if bit bit bit bit 2 of 1 of 0 of 4 of i m med iate i m med iate i m med iate i m med iate operand operand operand operand

is is is is is

one. one. one. one. one.

U nchanged U nchanged U nchanged U nchanged U nchanged

otherw i se. otherw i se. otherw i se. otherw i se. otherw i se.

Instruction Format:
14 13 10

8-89

EO R I to S R
Operation:

Exclusive O R Immediate to the Status Register (Privileged Instruction) If su pervisor state then Sou rce E9 SR - S R e l s e TRAP EORI # < data > ,SR

EO R I to S R

Assembler Syntax: Attributes:

Size = (Word)

Description: Exc l u sive OR t he i mmediate operand with the contents of the stat us reg i ster and store the resu l t i n the status reg ister. All bits of the status reg i ster are affected. Condition Codes:
x *

N *

z *

V *

I
if if if if if

C *

N Z V C X

Changed Changed Changed Changed Changed

bit bit bit bit bit

3 of i mmed iate 2 of i m med iate 1 of i m med iate 0 of i m med iate 4 of i m med iate

operand operand operand operand operand

is is is is is

one. one. one. one. one.

U nchanged U nchanged U nchanged U nchanged Unchanged

otherw i se. otherwi se. otherwise. otherwise. otherwise.

I nstruction Format:
15

14 0

13 0

12

o I

11 1

10

o o

Word Data (1 6 Bits)

8-90

EXG
Operation: Assembler Syntax: Rx - Ry EXG DX, Dy EXG AX,Ay EXG DX,Ay

Exchange Registers

EXG

Attributes:

Size = (Long)

Description: Exchange the contents o f t w o reg i sters. This exchange i s always a l o n g (32 bit) operat ion. Exchange works i n t h ree modes: 1 . Exchange data reg isters. 2. Exchange add ress reg i sters. 3. Exchange a data reg i ster and an address reg i ster. Condition Codes: Instruction Format:
15 14 13 12 11 10 9 8 7 6 5 OpMode 4 3 2 Register Ry 0

N ot affected.

I nstruction Fields: Reg i ster Rx field - Spec ifies either a data reg ister or an add ress reg i ster depend i n g on the mode. If the exchange i s between data and address reg isters, this field always specifies the data reg ister. Op-Mode field - Spec ifies w hether exchang i n g: 01 000-data reg isters. 0 1 001 - add ress reg i sters. 1 0001 -data reg i ster and add ress reg i ster. Reg ister Ry field - Specifies either a data reg ister or an add ress reg i ster depend i n g on the mode. If the exchange is between data and address reg i sters, t h i s f i e l d always spec i f ies the address reg i ster.

II

8-91

EXT EXT B
Operation: Assembler Syntax:

Sign Extend

EXT EXT B

Dest i nat ion S i g n-extended - Dest i nation EXT.w Dn EXT. L Dn EXTB.L Dn extend byte to word extend word to long word extend byte to long word

Attributes:

Size = (Word, Long)

Description: Extend the s i g n bit of a data reg i ster from a byte to a word, from a word to a long word, or from a byte to a long word operand, depend i n g on the size selected. If the operation i s word, bit [7] of the desig nated data reg i ster is copied to bits [1 5:8] of that data reg i ster. If the operat ion is long, bit [1 5] of the des i g nated data reg i ster is copied to bits [31 : 1 6] of the data reg ister. The EXTB form copies bit [7] of the desig nated reg i ster to bits [31 :8] of the data reg i ster.

Condition Codes: x N z N Z V C X

1 -1 * 1 * 1 0

0 1

Set if the res u l t is negative. Cleared otherw i se. Set if the resu l t is zero. Cleared otherw i se. A lways cleared. Always cleared . N ot affected.

I nstruction Format:

I 0 I

15

14 1

I 0 I

13

12 0

11 1

9 I 0

7
OpMode

o I 0 I 0

Register On

Instruction Fields: Op-M ode field - Spec ifies the s ize of the s i g n-extension operat ion: 01 0-Sign-extend l ow order byte of data reg ister to word . 01 1 - S i g n-extend l ow order word of data reg ister to long. 1 1 1 -Sig n-extend l ow order byte of data reg ister to long. Regi ster field - Spec ifies the data reg ister w hose content i s to be Sig n-extended.

B-92

I L L EG A L
Operation:

Take I llega l Instruction Trap

I L L EG A L

SSP - 2 - SSP; Vector Offset - (SSP); SSP - 4 - SSP; PC - (SSP); SSP - 2 - SSP; SR - (SSP); I l legal I nstruction Vector Address - PC I LLEGAL U ns ized

Assembler Syntax: Attributes:

Description: This bit pattern causes a n i l legal i nstruction exception. A l l other i l legal i n struction bit patterns are reserved for future extension of the i nstruction set. Condition Codes: Instruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 3 2

N ot affected.

0 0

8-93

JMP
Operation: Assembler Syntax: Attributes: Desti nation Address - PC J M P < ea > U n s ized

J ump

JMP

Description: Program execution cont i n ues at the effective address spec ified by the i nstruction. The address is specified by the control addressing modes. Condition Codes: I nstruction Format:
15 14 13 12 11 10 9 a 7 6 5 4 Mode 3 2 Register Effective Address

N ot affected.

Instruction Fields: Effective Address field - Specifies t he add ress of the next i nstruction. O n ly control addressi n g modes are a l l owed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

(xxx).W (xxx).L # < data>

111 111
-

000 001
-

010
-

reg. number:An
-

101 110 110 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

111 111 111 111 111

010 011 011 011 011

894

JSR
Operation:

Jump to Subroutine SP - 4 -- S; PC -- (S P) Dest ination Address -- PC J SR < ea > U nsized

JSR

Assembler Syntax: Attributes:

Description: The long word address of the i nstruction i mmed iately fol low i n g the J SR i n struct ion is pushed onto the system stack. Program execut ion then cont i nues at the address s pecified i n the i nstruction. Condition Codes: Instruction Format:
14 12 11 10 9 5 4 Mode 3 2 Register Effective Address

N ot affected.

I nstruction Fields: Effective Address field - Specifies the address of the next i nstruction. Only contro l addressing modes are allowed a s show n :
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (dI 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn],od) ([bd,An],Xn,od)

,

(xxx).w (xxx).L # < data >

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 110 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(dI 6 ,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn],od) ([bd,PC],Xn,od)

111 111 111 111 111

010 01 1 011 01 1 01 1

8-95

L EA
Operation: Assembler Syntax: Attributes: < ea > - A n LEA < ea > ,An

Load Effective Address

L EA

Si ze = (Long)

Description: The effective address is loaded i nto the spec ified address reg i ster. A l l 32 bits of the address reg ister are affecfed by this i nstruction. Condition Codes: Instruction Format:
15 14 13 12 11 10 Register An 9 s 7 6 5 4 Mode 3 2 Register Effective Address

N ot affected.

Instruction Fields: Reg i ster field - Specifies the address reg i ster which is to be l oaded with the effec tive address. Effective Address field - Spec ifies the address to be loaded into the address reg i ster. O n ly control addressi n g modes are al lowed as shown:
, Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

(xxx)W (xxx).L # < data >

111 111
-

000 001
-

010
-

reg. number:An
-

101 1 10 110 110 110

reg. nu mber:An reg. nu mber:An reg, number:An reg, number:An reg, number:An

(d 1 6 ,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

111 111 111 111 111

010 011 011 011 011

8-96

LI N K
-

Link and Allocate

LI N K

Operation: SP 4 - SP; An - (SP); SP - An ; SP + d - S P Assembler Syntax: L I N K An, # < disj:)lacement > Attributes: Size = (Word, Long)

Description: The cu rrent content of the specifi ed address reg i ster i s pu shed onto the stack. After the push, the add ress reg i ster is loaded from the updated stack poi nter. Final ly, the d isp lacement operand is added to the stack poi nter. For word size opera tion, the d i s placement is the s i g n-extended word follow i ng the operat ion word. For long s ize operat ion, the d isp lacement is the long word fol l ow i n g the operat ion word. The content of the add ress reg i ster occupies one long word on the stack. A negat ive d i splacement is specified to a l l ocate stack area. Condition Codes: Instruction Format: N ot affected.

15

14

13

11

10

2 Register

15

o I

14 1

I 0 I 0 I 1 I 0 I 0 I 0 I 0 I 0 I 0 I0 1 1 1
Long Displacement (High) Long Displacement (Low)

13

12

11

10

2 Register

Instruction Fields: Regi ster field - Spec ifies the add ress reg ister th rou g h which the l i nk is to be constructed. Displacement field - Spec if ies t he twos complement i nteger which is to be added to the stack poi nter. Note: LI N K and U N LK can be used to maintain a l i n ked l i st of l ocal data and parameter areas on the stack for nested su brout i n e calls.

B-97

LS L, LS R
Operation: Assembler Syntax:

Logical Shift

LS L, LS R

Desti nation Sh ifted by < cou nt > - Desti nation LSd DX,Dy LSd # < data > , Dy LSd < ea > where d i s d i rection, L o r R

Attributes:

Size = (Byte, Word, Long)

Description: Shift the bits of the operand in the d i rection (L or R) specified. The carry bit receives the last bit shifted out of t he operand. The shift count for the shift i ng of a reg i ster may be specified i n two d ifferent ways: 1 . I m mediate - the sh ift count is specified in the i nstruct ion (shift range 1 -8). 2. Register - the sh ift count is contai ned in a data reg ister spec ified in the i nstruc tion (sh ift count mod u l o 64). The size of the operat ion may be spec ified to be byte, word, or long. The content of memory may be sh ifted one bit on ly, and the operand size is restricted to a word. For LSL, the operand is shifted left; the n u mber of positions sh ifted is the sh ift count. Bits shifted out of the high order bit go to both the carry and the extend bits; zeroes are sh ifted i nto the low order bit.
__

-4 - -L

__ __ __

O p e ra n d _ _ _ __ _ _ __

---I

LSL:

For LSR, the operand is sh ifted right; the n u mber of positions sh ifted is the shift count. Bits shifted out of the l ow order bit go to both the carry and the extend bits; zeroes are sh ifted i nto the high order bit. LS R:

I - Operan d ,---O --.l,-___

----'1-----11.....--:

- Cont i n ued B-98

LS L, LS R
Condition Codes:
x N Z

Logical Shift

LS L, LS R

* I

N Z V C X

Set if the resu l t is negative. Cleared otherw i se. Set if the resu l t is zero. Cleared otherwise. A lways cleared. Set accord i ng to the last bit sh ifted out of the operand. Cleared for a shift count of zero. Set accord i n g to the last bit sh ifted out of the operand. U naffected for a sh ift count of zero.

I nstruction Format (Register Shifts):

15 14 13 12 11 10 Countl Register

2 Register

I nstruction Field (Reg i ster Shifts): Cou nt/Register field If i/r = O, the sh ift count is spec ified i n this field. The val ues 0, 1 -7 represent a range of 8, 1 to 7 respectively. If i/r = 1 , the sh ift count (mod u l o 64) i s contained in the data reg ister spec ified in this field. d r field - Spec ifies the d i rection of the sh ift: O-sh ift rig ht. 1 - sh ift left. Size field - Specifies the s ize of the operat ion: OO- byte operat ion. 01 -word operat ion. 1 0- long operation. i/r field I f i/r = 0, Specifies i m med iate sh ift count. I f i/r = 1 , Specifies reg i ster sh ift count. Reg ister field - Spec ifies a data reg ister w hose content i s to be shifted. Instruction Format (Memory Shifts):
5 4 Mode 3 2 Register 0 Effective Address

I nstruction Fields (Memory Shi fts): dr field - Spec ifies the d i rection of the shift: O-shift right. 1 - sh ift left. Effective Address field - Spec ifies t he operand to be sh ifted. O n ly memory alterable add res s i n g modes are al l owed as shown: 8-99

LS L, LS R
Addr. Mode Mode
-

Logical Shift

LS L, LS R
Addr. Mode Mode Register

Register
-

Dn An (An) (An) + - (An) (d 1 6 ,An) (de,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

(xxx).W (xxx).L # < dat a >

111 111
-

000 001
-

010 011 1 00 101 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (de,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

8-1 00

M OV E
Operation: Assembler Syntax: Attributes:

Move Data from Source to Destination

M OV E

Sou rce - Dest i nation

Size = (Byte, Word, Long)

MOVE < ea > , < ea >

Description: M ove the content of the sou rce to the desti nation location. The data is exam i ned as it i s moved, and t he condition codes set accord i n g ly. The s ize of the operation may be specifi ed to be byte, word, or long. Condition Codes: x N z V
0

I * I * I

c
0

N Z V C X

Set if the res u lt is negat ive. Cleared otherwise. Set if the res u lt is zero. Cleared otherw i se. A l ways cleared. A l ways cleared. N ot affected.
o
Register

Instruction Format:
15 14 13 12 11 10 Register 9 a 7 Mode 6 5 4 Mode 3 2 Destination Source

Instruction Fields: Size field - Specifies the s ize of the operand to be moved: 01 - byte operation. 1 1 -word operat ion. 1 0- long operat ion. Desti nation Effective Add ress f ield - Spec ifies the desti nation l ocation. Only data alterable add ressing modes are al lowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000
-

reg. number:An
-

(xxx).w (xxx).L # < dat a >

111 111
-

000 001
-

010 01 1 100 1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC),Xn,od)

B1 0 1

M OV E

Move Data from Source to Destination

M OV E

Source Effective Add ress field - Spec ifies the sou rce operand. A l l address i n g modes are allowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

On (An) + (An) - (An) (d 1 6 ,An) (de,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od) An*

000 001 010 01 1 1 00 1 01 1 10 1 10 1 10 1 10

reg. number:On reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(xxx).w (xxx).L # < data>

111 111 111

000 001 100

(d 1 6 ,PC) (de,PC,Xn) (bd, PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

111 111 111 111 111

010 01 1 01 1 01 1 01 1

* For byte size operation, address register direct is not allowed.

Notes: 1 . M OVEA is used when the desti nation is an add ress reg i ster. M ost assem blers automatically make this disti nction. 2. M OVEQ can also be u sed for certain operat ions on data reg isters .

8-1 02

M OV EA
Operation: Assembler Syntax: Attributes: Sou rce -- Dest i nation M OVEA < ea > ,An

Move Address

M OV EA

Size = (Word, Long)

Description: M ove the content of the sou rce to the dest i nation address reg i ster. The s ize of the operat ion may be specified to be word or long. Word size sou rce operands are s i g n extended to 32 bit q u antities before the operation is done. Condition Codes: I nstruction Format:
15 14 13 12 11 10 Register 9 B Destination

N ot affected.
7 o
Register

4 Mode

Source

Instruction Fields: Size field - Spec ifies the s ize of the operand to be moved: 1 1 -Word operation. The sou rce operand i s s i g n-extended to a long operand and all 32 bits are loaded i nto the address reg i ster. 1 0 - Long operat ion. Dest i nation Register field - Specifies the desti nation address reg ister. Sou rce Effective Address field - Specif ies the locat ion of sou rce operand. A l l address i n g modes are al lowed a s shown:
Addr. Mode Mode Register Addr. Mode Mode Register

Dn An (An) (An) + - (An) (d 1 6,An) (dB,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000 001 010 011 100 1 01 110 1 10 1 10 110

reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. nu mber:An

(xxx).w (xxx).L # < data>

111 111 111

000 001 1 00

(d 1 6 ,PC) (dB,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd, PCJ,Xn,od)

111 111 111 111 111

010 011 011 011 01 1

8-1 03

M OV E f rom CC R
Operation: Assembler Syntax: Attributes:

Move from the Condition Code Register

M OV E f rom C C R

GGR - Dest ination MOVE GGR, < ea >

Size = (Word)

Description: The content of the stat u s reg i ster is moved to the dest i nation location. The sou rce operand is a word, but only the low order byte conta i n s t he cond ition codes. The u pper byte is all zeroes. Condition Codes: Instruction Format:
15 14 13 12 11 10 9 a

Not affected.
7 o

4 Mode

2 Register

Effective Address

I nstruction Fields: Effective Address field - Spec ifies the dest ination l ocation. O n ly data alterable addres s i n g modes are a l l owed as show n :
Addr. Mode Mode Register Addr. Mode Mode Register

On An (An) (An) + - (An) (d 1 6,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000
-

reg. number:On
-

(xxx).W (xxx).L # < data >

111 111
-

000 001
-

010 011 100 101 110 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

II

Note: MOVE from GGR is a word operation. A N D I , O R I , and EORI to GGR are byte operat ions.

8-1 04

M OV E to C C R
Operation: Assembler Syntax: Attributes: Source - CCR

Move to Condition Codes

M OV E to CC R

Size = (Word)

MOVE < ea > ,CCR

Description: The content of the source operand is moved to t he condition codes. The sou rce operand is a word, but only the low order byte is used to u pdate the cond ition codes. The upper byte i s i g nored. Condition Codes:
x

I
as as as as as bit bit bit bit bit 3 2 1 0 4 of of of of of the the the t he the sou rce sou rce sou rce sou rce sou rce operand. operand. operand. operand. operand.

N Z V C X

Set Set Set Set Set

the the the the the

same same same same same

Instruction Format:
15 14 13 12 11 10 9 a 7 6 5 4 Mode 3 2 Register o Effective Address

Instruction Fields: Effective Address field - Spec ifies t he locat ion of the sou rce operand. O n ly data addres s i n g modes are al lowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000
-

reg. number:Dn
-

(xxx).w (xxx).L # < data>

111 111 111

000 001 1 00

010 011 1 00 1 01 110 1 10 110 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC],Xn,od)

111 111 111 111 111

010 011 011 011 01 1

Note: MOVE to CCR is a word operat ion. A N D I , O R I , and EORI to CCR are byte operations.

8-1 05

M OV E f rom S R
Operation:
--+

Move from the Status Register (Privileged Instruction)

M OV E f rom S R

I f su pervisor state t hen SR Desti nation else TRAP MOVE SR, < ea >

Assembler Syntax: Attributes:

Size = (Word)

Description: The content of the statu s reg ister is moved to the destination location. The operand size is a word. Condition Codes: Instruction Format:
15 14 13 12 11 10 9 B

N ot affected.
7

4 Mode

2 Register

Effective Address

Instruction Fields: Effective Address field - Specifies the dest i nation l ocation. Only data alterable addressing modes are a l l owed as shown:
Addr. Mode Mode Register

Addr. Mode (xxx)W (xxx).L # < data>

Mode

Register

On An (An) (An) + - (An) (d 1 6 ,An) (dB,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000
-

reg. number:On
-

111 111
-

000 001
-

010 01 1 1 00 1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (dB,PC,Xn) (bd,PC,Xn) ([bd, PC,Xnj,od) ([bd,PC],Xn,od)

Note: Use the MOVE from GGR i nstruct ion to access o n ly the condition codes.

8-1 06

M OV E to SR
Operation:

Move to the Status Register (Privileged I nstruction)

M OV E to S R

If su pervisor state t hen Source - S R else TRAP MOVE < ea > ,SR

Assembler Syntax: Attributes:

Size = (Word)

Description: The content of the source operand i s moved to the status register. The source operand is a word and all bits of the status reg i ster are affected. Condition Codes: I nstruction Format:
15 14 13 12 11 10 9 s

Set accord i n g to the source operand.

7 o

4 Mode

2 Register

Effective Address

Instruction Fields: Effect ive Address field - Spec ifies the locat ion of the sou rce operand. Only data address i n g modes are al lowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

On An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000
-

reg. number:On
-

(xxx).w (xxx).L # < data>

111 111 111

000 001 1 00

010 011 1 00 101 110 110 110 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PC),Xn,od)

111 111 111 111 111

010 01 1 01 1 011 01 1

8-1 07

M OV E USP
Operation:

Move User Stack Pointer (Privileged Instruction)

M OV E USP

If su pervisor state then USP - An or An - USP else TRAP MOVE USP,An M ove An,USP

Assembler Syntax: Attributes:

Size = (Long)

Description: The contents of the u ser stack poi nter are transferred to or from the specified address reg i ster. Condition Codes: I nstruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 o 3 dr

N ot affected.

2 Register

I nstruction Fields: dr field - Spec ifies the d i rect ion of transfer: O-transfer the address reg i ster to the USP. 1 -transfer the USP to t he address reg ister. Reg ister field - Specifies the address reg ister to or from which the user stack poi nter is to be transferred .

8-108

M OV E C
Operation:

Move Control Register (Privileged Instruction)

,M OVEC

If su pervisor state then Rc - Rn or Rn - Rc else TRAP MOVEC RC, Rn M OVEC Rn,Rc

Assembler Syntax: Attributes:

Size = (Long)

Description: Copy the contents of the specified control reg i ster (Rc) t o the specified general reg ister or copy the contents of the spec ified general reg i ster to the spec ified control reg ister. This is always a 32-bit transfer even though the control reg i ster may be i m plemented with fewer bits. U n i mplemented bits are read as zeros. Condition Codes: Instruction Format: Not affected.

I nstruction Fields: d r field - Spec if ies the d i rect ion of the transfer: O-control reg ister to general register. 1 -general reg ister to control reg i ster. AID field - Spec ifies the type of general reg ister: O-data reg i ster. 1 -address reg i ster. Regi ster field - Spec ifies the reg i ster n u m ber. Control Regi ster field - Specifies the control reg i ster. Hex Control Register 000 Source Fu nction Code (SFC) register. 001 002 800 801 802 803 804 Dest i nation Fu nction Code (DFC) reg i ster. Cache Control Reg i ster (CACR). U ser Stack Poi nter (USP). Vector Base Reg i ster (VBR). Cache Address Reg i ster (CAAR). Master Stack Poi nter (MSP). I nterrupt Stack Poi nter (ISP).

A l l other codes cause an i l legal i nstruction except ion.

B-1 09

M OV E M
Operation:

Move Multiple Registers

M OV E M

Regi sters -- Dest i nation Sou rce -- Regi sters MOVEM reg i ster l ist, < ea > MOVEM < ea > , register l i st

Assembler Syntax: Attributes:

Size = (Word, Long)

Description: Selected reg i sters are t ransferred to or from consecutive memory locat ions start i n g at the l ocat ion s pec ified by the effective address. A reg i ster i s t ransferred if the bit correspon d i n g to that reg ister i s set i n the mask field. The i nstruct ion selects how much of each reg i ster is transferred; either the ent i re long word can be moved or j u st the low order word. I n the case of a word transfer to the reg i sters, each word is sig n-extended to 32 bits ( i n c l u d i n g data reg isters) and the res u l t i n g long word loaded i nto the associated reg i ster. MOVEM al lows three forms of add ress modes: the control modes, the predecrement mode, or the posti ncrement mode. If the effective address i s in one of the control modes, the reg i sters are transferred starti n g at the specifi ed address and u p through h i g her addresses. The order o f transfer i s from data reg i ster 0 to data reg i ster 7, then from add ress reg ister 0 to address reg i ster 7. I f the effective address i s the predecrement mode, only a reg ister to memory opera tion is al lowed. The reg i sters are stored start i n g at the spec ified address m i n u s the operand length (2 or 4) and down t h rough lower addresses. The order of storing i s from address reg i ster 7 to address reg i ster 0, t h e n from data reg ister 7 t o data reg ister O. The decremented address reg ister is u pdated to contai n the address of the last word stored. If t he effective address is the post i ncrement mode, only a memory to reg i ster opera t i on is al lowed. The reg isters are loaded start i n g at the specified address and up t h rough h igher addresses. The order of load i n g i s the same as for the control mode add ressi n g . The i ncremented address reg i ster is updated to conta i n the add ress of the last word loaded p l u s the operand length (2 or 4). Condition Codes: I nstruction Format:
15 o 14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 0 Effective Address

N ot affected .

- Conti nued -

8-1 1 0

M OV E M

Move Multiple Registers

M OV E M

I nstruction Fields: dr field - Spec if ies the d i rect ion of t he transfer: O - reg i ster to memory. 1 - memory to reg i ster. Sz field - Specifies the s ize of the reg i sters bei n g transferred: O- word transfer. 1 - long transfer. Effective Address field - Specif ies the memory address to or from which the reg i sters are to be moved. For reg i ster to memory transfers, o n ly control alterable addreSSing modes or the predecrement address i n g mode are a l l owed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

(xxx).W (xxx).l # < data >

111 111
-

000 001
-

010 011 1 00 101 110 110 110 110

reg. number:An
-

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An (d 1 6, PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)
-

For memory to reg i ster transfers, o n ly contro l addressing modes or t he post i ncrement addreSS i n g mode are a l l owed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

(xxx).W (xxx).l # < data>

111 111
-

000 001
-

010 011
-

reg. number:An reg. number:An

-

101 110 1 10 110 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6, PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

111 111 111 111 111

010 011 011 011 011

Reg i ster List Mask field - Specif ies which reg i sters are to be transferred. The low order bit corresponds to the f i rst reg i ster to be transferred; the h i g h bit corresponds to the last reg i ster to be transferred. Thus, both for control modes and for t he post i ncrement mode addresses, the mask correspondence is

I A7 I A6 I A5 I

15

14

13

12 A4

11 A3

10 A2

9 A1

a AO

7 07

D6

5 05

4 04

I 03 I 02 I 01 I DO I

8-1 1 1

M OV E M

Move M u ltiple Registers

M OV E M

w h i l e for the predec rement mode add resses, the mask correspondence i s

I 00 I

15

14 01

13 02

12 03

11 04

10 05

I os I

8 07

I AO I A1 I A2 I A3 I A4 I A5 I A6 I A7 I

Note: An extra read bus cyc le occu rs for memory operands. This accesses an operand at one address hi gher than the last reg i ster i mage req u i red .

81 1 2

M OV E P
Operation: Assembler Syntax: Attributes:

Move Peripheral Data

M OV E P

Sou rce - Dest i nation MOVEP DX,(d,Ay) MOVEP (d,Ay)Dx

Size = (Word, Long)

Description: Data is t ransferred between a data reg i ster and alternate bytes of memory, start i n g at the locat ion specif ied and i ncrementi n g by two. The h i g h order byte of the data reg i ster is transferred f i rst and the low order byte i s t ransferred last. The memory address i s specif ied u s i n g the address reg i ster i nd i rect plus 1 6-bit disp lace ment address i n g mode. This i nstruction is desig ned to work with 8-bit peripherals on a 1 6-bit data bus. If the address i s even, all the transfers are made on the high order half of the data bus; if the address is odd, all the t ransfers are made on the l ow order half of the data bus. On an 8- or 32-bit bus, the i nstruction st i l l accesses every other byte. Examp le: Long transfer to/from an even address. Byte organ izat ion in reg i ster
31 HiOrder 24 23 M idUpper 16 1 5 M idLower 8 7 LowOrder o

Byte organ izat ion i n memory (low add ress at top)

15 H iOrder MidUpper Mid-Lower Low-Order 8 7 o

Examp le: Word transfer to/from an odd address. Byte organ izat ion in reg i ster
31 24 23 16 1 5 H i-Order 8 7 Low-Order o

Byte organ izat ion i n memory (low address at top)

15 8 7 Hi-Order Low-Order o

- Cont i nued -

B-1 1 3

M OV E P
Condition Codes: Instruction Format:
15

Move Peripheral Data

M OV E P

Not affected.
10 2 o

14

13

12

11

7 OpMode

Data Register

Address Register

Displacement

Instruction Fields: Data Reg i ster field - Specifies the data reg ister to or from which the data is to be t ransferred. Op-Mode field - Specifies the d i rection and s ize of the operat ion: 1 00-transfer word from memory to reg i ster. 1 0 1 - transfer long from memory to reg ister. 1 1 0-transfer word from reg i ster to memory. 1 1 1 - transfer long from reg i ster to memory. Address Register field - Specifies the address reg ister which i s u sed in the address reg i ster i n d i rect plus displacement addressing mode. Displacement field - Specifies the displacement which is used in calculat i n g t h e operand address.

II

8-1 1 4

M OV EQ
Operation: Assembler Syntax: Attributes:

Move Quick

M OV EQ

I m med iate Data - Dest ination

Size = (Long)

M OV EO # < data > ,Dn

Description: M ove i m mediate data to a data reg i ster. The data is contai ned i n an B-bit field w i t h i n the operat ion word. The data i s Sign-extended to a long operand and a l l 3 2 bits are transferred t o t h e data register. Condition Codes: x N z N Z V C X V c

/ -1 * 1 * 1 0

0 1

Set if the resu l t is negat ive. Cleared otherw i se. Set if the resu l t is zero. Cleared otherwise. A lways c leared. Always cleared. N ot affected.

Instruction Format:

I 0 I 1 I 1 I 1 I

15

14

13

12

11

10
Registe r

0 I

4
Data

I nstruction Fields: Register field - Specifies t he data reg ister to be loaded. Data field - B bits of data which are sign extended to a long operand.

II

8-1 1 5

M OV ES
Operation:

Move Address Space (Privileged Instruction)

M OV ES

If su pervisor state then Rn - Dest i nation [DFC) or Sou rce [SFC) - Rn else TRAP MOVES Rn, < ea > MOV ES < ea > , R n

Assembler Syntax: Attributes:

Size = (Byte, Word, Long)

Description: M ove the byte, word, or long operand from the specified general reg ister to a locat ion w i t h i n the address space specified by the desti nation fu nction code (D FC) reg i ster. Or, move the byte, word, or long operand from a locat ion w i t h i n the address space spec ified by the sou rce function code (SFC) reg ister to the specified general reg ister. If the dest i nation is a data reg ister, the sou rce operand replaces the correspon d i n g low-order b i t s o f that data reg ister. If the dest i nation i s an address reg ister, the sou rce operand i s s i g n-extended to 32 bits and then loaded i nto that add ress reg i ster. Condition Codes: Instruction Format:
15

Not affected.
10

14

AID

Register

I I
0

13

12

11 1 dr

6 Size

4 Mode

Effective Address

I
1

Register

Instruction Fields: Size field - Specifies the s ize of t he operat ion: OO- byte operat ion. 01 - word operat ion. 1 0- long operation. Effective Address field - Spec ifies the sou rce or dest i nation locat ion w i t h i n the alternate address space. O n ly alterable memory addressing modes are allowed as shown:

- Cont i n ued B-1 1 6

M OV E S
Addr. Mode Mode
-

Move Address Space (Privileged I nstruction)

M OV ES
Mode Register

Register
-

Addr. Mode

On An (An) (An) + - (An) (d 1 6,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

(xxx)W (xxx).L # < data >

111 111
-

000 001
-

010 01 1 100 101 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6, PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

AID field - Spec ifies the type of general reg ister: O-data reg i ster. 1 -add ress reg i ster. Reg i ster field - Spec ifies the reg ister n u m ber. dr field - Specifies the d i rect ion of the transfer: O-from < ea > to general reg i ster. 1 - from general reg i ster to < ea > . M OV ES.x A n(An) + or M OV ES.x An, - (An) where An is the same add ress reg i ster for both sou rce and dest i nation and is an u ndefi ned operat ion. The value stored in memory is u ndefined. N OTE On the M C6801 0 and M C68020 i m p lementat ions, the value stored is the increment or the decrement val u e of An. This i m plementation may not appear on future devices.

II

8-1 1 7

M U LS
Operation: Assembler Syntax: M U LS.w < ea > , D n M U LS. L < ea > , D I M U LS. L < ea > , D h : D I

Signed M u ltiply Sou rce - Desti nation - Dest i nation 1 6 x 1 6 - 32 32 x 32 - 32 32 x 32 - 64

M U LS

Attributes:

Size = (Word, Long)

Description: M u ltiply two s i g ned operands yielding a sig ned resu lt. The operat ion is per formed u s i n g s i g ned arithmetic. The i nstruct ion has a word form and a long form. For the word form, the mu l t i p l ier and m u l t i plicand are both word operands and the resu l t is long word operand. A reg ister operand i s taken f rom the low order word, the u pper word is u n used. A l l 32 bits of the prod uct are saved i n the dest i nation data reg i ster. For the long form, the multipl ier and m u lt i pl i cand are both long word operands and t he res u lt is either a long word or a q uad word. The long word resu l t is the low order 32 bits of the q uad word resu lt. Condition Codes:
x N z V

1- 1 - 1 * 1 * 1 0
N Z V C X

N ote: Overflow (V = 1 ) can occur o n ly in the case of m u lti plying 32-bit operands to yield a 32-bit result. Overfl ow occu rs if t he h i g h-order 32 bits of the quad word pro d uct are not the sig n-extension of the low order 32 bits. Instruction Format (word form):
15 14 13 12 11 1

Set if the resu l t is negat ive. Cleared otherw i se. Set if the resu l t is zero. Cleared otherwise. Set if overflow. Cleared otherw i se. Always cleared. N ot affected.

II

4 Mode

2 Register

Register On

Effective Address

I nstruction Fields: Regi ster field - Spec ifies one of the data reg i sters. This field always specifies the dest i nation. Effective Address field - Specifies the sou rce operand. Only data addressing modes are al lowed as shown:

B-1 1 8

M U LS
Addr. Mode Mode

Signed Multiply

M U LS
Mode Register

Register

Addr. Mode

On An (An) (An) + - (An) (d 1 6,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000

reg. number:On

(xxx).W (xxx).L # < data >

111 111 111

000 001 100

010 011 1 00 101 110 110 110 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. nu mber:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PGj,Xn,od)

111 111 111 111 111

010 011 011 01 1 011

Instruction Format (long form):

15 0 0 14 1

Register

I I
0

13

12 0

11 1 1

10 1
Sz

9 0 0

a 0 0

7 0 0

6 0 0

2 Register

Effective Address

01

I I
0

Mode

Register Oh

I nstruction Fields: Effect ive Address field - Specifies the sou rce operand. Only data addressing modes are allowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

On An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000

reg. number:On

(xxx).w (xxx).L # < data >

111 111 111

000 001 1 00

010 011 1 00 1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 , PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PGj,Xn,od)

111 111 111 111 111

010 011 01 1 01 1 01 1

Reg i ster 01 field - Specifies a data reg i ster for the dest i nation operand. The 32-bit m u l t i pl icand comes from this reg ister, and the low order 32 bits of the prod uct i s loaded into this register. Sz field - Selects a 32- or 64-bit product resu lt. 0-32-bit prod uct to be retu rned to Reg i ster 01. 1 -64-bit prod uct to b e retu rned to Oh:OI. Register Oh field - I f Sz is 1 , spec ifies the data reg i ster i nto which t he h i g h order 32 bits of the prod uct is l oaded. If Oh = 01 and Sz is 1 , the resu lts of the operat ion are u ndefi ned. Otherwi se, this field is u n u sed.

8-1 1 9

M U LU
Operation: Assembler Syntax:

Unsigned M ultiply Source * Dest i nation -- Dest i nation M U LU.w < ea > ,Dn M U LU.L < ea > ,01 M U LU. L < ea > , Dh:DI 1 6 x 1 6 -- 32 32 x 32 -- 32 32 x 32 -- 64

M U LU

Attributes:

Size = (Word, Long)

Description: M u lt i ply two u n s i g ned operands yielding a u nsig ned resu lt. The operat ion i s performed u s i n g u n s ig ned arithmetic. The i nstruct ion has a word form and a long form. For the word form, the m u l t i pl i er and m u lt i pl icand are both word operands and the result is a long word operand. A reg i ster operand is taken from the low order word, the up per word is u n used. A l l 32 bits of the prod uct are saved i n the dest i nation data reg i ster. For the long form, the m u l t i p l ier and m u l t i p l i cand are both long word operands and the res u lt is either a long word or a quad word. The long word result is the low order 32 bits of the quad word result. Condition Codes:
x N z V

1- 1 * 1 * 1 * 1 0
N Z V C X

N ote: Overflow (V = 1) can occur only i n the case of m u l t iplying 32-bit operands to yield a 32-bit resu lt. Overfl ow occurs if the h i g h-order 32 bits of the q uad word pro duct are non-zero. I nstruction Format (word form):

Set i f the resu l t is negat ive. Cleared otherw i se. Set if the resu l t is zero. Cleared otherw ise. Set if overflow. Cleared otherw i se. A l ways cleared. N ot affected.

15

14

13

12

11

10

4
Mode

2
Register

Register Dn

Effective Address

I nstruction Fields: Reg i ster field - Specifi es one of the data reg i sters. This field always specifi es the desti nat ion. Effective Address field - Specif ies the sou rce operand. O n ly data addres s i n g modes are al lowed a s shown:

B-1 20

M U LU
Addr. Mode Mode

U nsigned Multiply

M U LU
Mode Register

Register

Addr. Mode

On An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000
-

reg. number:On
-

(xxx).W (xxx).L # < data >

111 111 111

000 001 100

010 011 1 00 101 110 110 110 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd, PCJ,Xn,od)

111 111 111 111 111

010 011 011 011 011

I nstruction Format (long form):

15 0 0 14 1

Register

I I
0

13

12 0

11 1 0

10 1 Sz

9 0 0

s 0 0

7 0 0

6 0 0

2 Register

Effective Address

01

1 I
Mode 0

Register Oh

I nstruction Fields: Effective Address field - Specifies the sou rce operand. O n ly data addressing modes are al lowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

On An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000
-

reg. number:On
-

(xxx).W (xxx).L # < data >

111 111 111

000 001 100

010 011 1 00 101 110 1 10 110 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

111 111 111 111 111

010 01 1 01 1 011 01 1

Reg i ster 01 field - Spec ifies a data reg i ster for the dest i nation opera nd. The 32-bit m u l t i p l icand comes from this reg i ster, and the low order 32 bits of the product are loaded i nto this reg i ster. Sz field - Selects a 32- or 64-bit prod uct resu lt. 0-32-bit prod uct to be retu rned to Reg i ster 01. 1 -64-bit product to be ret u rned to Oh:OI. Reg i ster Oh field - I f Sz i s 1, spec ifies the data reg i ster i nto which the h i g h order 32 bits of the prod uct are loaded. If Oh = 01 and Sz is 1 , the resu lts of the operat ion are u ndefi ned. Otherw ise, this field i s u n u sed.

8-1 21

N BC D
Operation: Assembler Syntax: Attributes: 0
-

Negate Decimal with Extend Dest i nation 1 Q X Desti nation

N BC D

Size = (Byte)

N BCD < ea >

Description: The operand add ressed as the dest i nation and t he extend bit are sub t racted from zero. The operat ion is performed u s i n g decimal arithmetic. The res u l t i s saved i n the dest i nation locat ion. Th is i nstruction prod uces t h e tens comp lement of the desti nation if the extend bit is clear, the n i nes complement if t he extend bit is set. Th is i s a byte operat ion only. Condition Codes: c *

* N Z V C X

U ndefi ned. Cleared if the res u lt is non-zero. U nchanged otherw i se. U ndefi ned. Set if a borrow (decimal) was generated. Cleared otherw i se. Set the same as the carry bit. N OTE Normally the Z cond ition code bit i s set via prog ramming before the start of an operation. This al lows successfu l tests for zero results u pon completion of m u l t i ple precision operat i ons.

I nstruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 Effective Address Mode Register

Instruction Fields: Effective Address field - Specifies t he destination operand. O n ly data alterable ad dress i n g modes are allowed as shown:

8-1 22

N BC D
Addr. Mode Mode

Negate Decimal with Extend

N BC D
Mode Register

Register

Addr. Mode

Dn An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000
-

reg. number:Dn
-

(xxx)W (xxx).L # < data>

111 111
-

000 001
-

010 011 1 00 1 01 110 110 110 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

B1 23

N EG
Operation: Assembler Syntax: Attributes:

Negate 0 - Dest i nation - Dest i nation

N EG

Size = (Byte, Word , Long)

N EG < ea >

Description: The operand addressed as the dest i nation is su btracted from zero. The resu l t is stored in the dest i nation l ocation. The size of the operat ion may be spec ified to be byte, word, or long. Condition Codes:
x *

N *

Z *

V *

c *

N Z V C X

Set if the resu l t is negative. Cleared otherw i se. Set if the res u l t is zero. Cleared otherwise. Set if an overflow is generated. Cleared otherw i se. Cleared if the resu l t is zero. Set otherw i se. Set the same as the carry bit.
o

Instruction Format:
15 14 13 12 11 10 9 s 7 6 5 4 Mode 3 2 Register Effective Address

Instruction Fields: Size field - Spec ifies the size of the operat ion. OO- byte operat ion. 01 -word operat ion. 1 0 - long operat ion. Effective Address field - Spec ifies t he dest i nation operand. O n ly data alterable ad d ressi n g modes are al lowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od)

000
-

reg. number:Dn
-

(xxx).W (xxx).L # < data >

111 111
-

000 001
-

010 01 1 1 00 101 110 110 1 10 110

reg. number:An reg. nu mber:An reg. number:An reg. number:An reg. number:An reg. nu mber:An reg. number:An reg. number:An

(d 1 6,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,XnJ,od) ([bd, PCJ,Xn,od)

B-1 24

N EG X
Operation: Assembler Syntax: Attributes:

Negate with Extend 0 - (Desti nation) - X Dest i nation

N EG X

Size = (Byte, Word, Long)

N EGX < ea >

Description: The operand addressed as the dest i nation and the extend bit are sub tracted from zero. The resu lt is stored i n the dest i nation locat ion. The size of the operation may be spec ified to be byte, word, or long. Condition Codes:
x

* N Z V C X

I * I * I * I

c *

Set if the resu l t is negat ive. Cleared otherwise. Cleared if the resu l t is non-zero. U nchanged otherw i se. Set if an overflow is generated. Cleared otherwise. Set if a borrow is generated. Cleared otherwise. Set the same as the carry bit. N OTE Normal ly the Z cond ition code bit is set via program m i n g before the start of an operation. This al lows successfu l tests for zero resu lts upon com pletion of m u l t i p le-prec ision operat ions.

I nstruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 0 Effective Address

Instruction Fields: Size field - Spec ifies the size of the operation. OO- byte operat ion. 01 -word operation. 1 0- long operat ion. Effective Address field - Spec if ies the desti nation operand. Only data alterable address i n g modes are a l l owed as shown:

B-1 25

N EG X
Addr. Mode Mode

Negate with Extend

N EG X _
Mode Register

Register

Addr. Mode

On An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000
-

reg. number:On
-

(xxx).W (xxx).L # < data>

111 111
-

000 001
-

010 011 1 00 1 01 110 1 10 110 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC),Xn,od)

8-1 26

NOP
Operation: Assembler Syntax: Attributes: None NOP Uns ized

No Operation

NOP

Description: N o operation occu rs. The processor state, other than the program cou nter, i s u naffected. Execution cont i n ues with the i nstruction fol lowing the NOP i nstruc tion. The N O P i nstruction does not comp lete execution u nt i l a l l pen d i n g bus cyc les are comp leted. This a l l ows synchron izat ion of the p i pe l i ne to be accompl i shed, and prevents i nstruction overlap. Condition Codes: Instruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

N ot affected.

9-1 27

N OT
Operation: Assembler Syntax: Attributes:
-

Logical Complement Dest i nation - Dest i nation

N OT

Size = (Byte, Word, Long)

NOT < ea >

Description: The ones comp lements of t he dest ination operand is taken and t he resu l t i s stored i n the dest i nation locat ion. The s ize o f t h e operat ion may b e specified t o be byte, word, or long. Condition Codes:

1- 1 * 1 * 1 0
N Z V C X

0 /

Set if the resu l t is negat ive. Cleared otherw i se. Set if the resu lt is zero. Cleared otherwise. A l ways cleared. A l ways c leared. Not affected.
o

I nstruction Format:
15 14 13 12 11 10 9 s 7 6 5 4 Mode 3 2 Register Effective Address

I nstruction Fields: Size field - Specifies the s ize of the operation. OO- byte operat ion. 01 - word operat ion. 1 0 - long operat ion. Effective Add ress field - Spec ifies the dest i nation operand. Only data alterable ad dress i n g modes are al l owed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

On An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000
-

reg. number:On

(xxx).w (xxx).l # < data>

111 111

000 001

010 011 1 00 1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd,PCJ,Xn,od)

B-1 28

OR
Operation: Assembler Syntax: Attributes: O R < ea > , D n OR D n , < ea >

Inclusive OR Logical Sou rce v Dest i nation - Dest i nation

OR

Size = (Byte, Word, Long)

Description: I nc l usive O R the sou rce operand to the dest i nation operand and store the resu l t in the dest ination locat ion. The s ize of the operat ion may be specif ied to be byte, word, or long. The contents of an address reg ister may not be used as an operand. Condition Codes:

1 -1 * 1 * 1 0
N Z V C X

Set if the most s i g n i f icant bit of the resu l t is set. Cleared otherw i se. Set if the resu l t is zero. Cleared otherw i se. A l ways cleared. A l ways cleared. Not affected.

I nstruction Format:
15 14 13 12 11 10 Register 9 8 7 OpMode 6 5 4 Mode 3 2 Register Effective Address

Instruction Fields: Reg i ster field - Spec ifies any of the eight data reg i sters. Op-M ode field Byte Word Long Operation 000 001 010 ea > )v( < On - < On > 1 00 1 01 110 Dn v ea - < ea > Effective Address field I f the locat ion spec i f ied is a sou rce operand then only data addressing modes are allowed as shown:

B-1 29

OR
Addr. Mode Mode

Inclusive O R Logical

OR
Mode Register

Register

Addr. Mode

On An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000
-

reg. number:On
-

(xxx).W (xxx).L # < data>

111 111 111

000 001 1 00

010 01 1 100 101 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

111 111 111 111 111

010 01 1 01 1 01 1 01 1

I f the l ocation specified is a dest i nation operand then o n ly memory alterable ad dress i n g modes are al lowed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

(xxx).w (xxx).L # < data>

111 111
-

000 001
-

010 011 100 101 110 110 110 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd, PC),Xn,od)

Notes: 1 . I f the desti nation is a data reg ister, then it cannot be specified by u s i n g the dest i nation < ea > mode, but must u se the dest i nation Dn mode i n stead. 2. ORI is used when the source is i m med i ate data. M ost assem blers auto mat i ca l ly make this d istinction .

8-1 30

ORI
Operation: Assembler Syntax: Attributes:

I nclusive O R Immediate I m med iate Data v Dest i nation - Dest i nation ORI # < data > , < ea >

ORI

S ize = (Byte, Word, Long)

Description: I n c l u s ive O R the i m med i ate data to the dest i nation operand and store the resu l t in the dest i nation locat ion. The s ize of the operat ion may be specified to be byte, word, or long. The size of the i m med iate data matches the operation s ize. Condition Codes:

N Z V C X

Set if the most s i g n if icant bit of the resu l t is set. Cleared otherw i se. Set if the resu l t is zero. Cleared otherw i se. A lways c leared. A l ways cleared. N ot affected.

I nstruction Format:
15 14 13 12 11 1

10 1 0 1 0 1 0 1 0 1 0 1
Word Data

7 Size

Long Data

4 Mode

Effective Address Byte Data

Register

Instruction Fields: Size field - Spec ifies the s ize of the operat ion. O- byte operat ion. 01 -word operat ion. 1 0 - long operat ion. Effective Address field - Spec ifies the dest i nation operand. Only data alterable ad dressi n g modes are al lowed as shown:

B-1 31

O RI
Addr. Mode Mode

Inclusive O R Immediate

ORI
Mode Register

Register

Addr. Mode

Dn An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

000
-

reg. number:Dn
-

(xxx).W (xxx).L # < data >

111 111
-

000 001
-

010 011 100 1 01 1 10 1 10 1 10 110

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd, PC),Xn,od)

I m mediate field If s ize = 00, t hen If s ize = 01 , then If s ize = 1 0, t hen

(Data i m med i ately following the i nstruction): the data is the low order byte of the i m med iate word. the data is the entire i m med i ate word. the data i s the next two i m mediate words.

81 32

O RI to C C R
Operation: Assembler Syntax: Attributes: Sou rce v CCR
-+

Inclusive O R I mmediate to Condition Codes CCR

O RI to CC R

Size = (Byte)

ORI # < data > ,CCR

Description: I nc l us ive OR the i mmediate operand with the condition codes and store t he resu l t in the low-order byte of the stat u s register. Condition Codes: x N z V c * 1 * 1 * 1 * 1 * 1 N Z V C X Set Set Set Set Set if if if if if bit bit bit bit bit 3 2 1 0 4 of of of of of i m med iate i m med iate i m mediate i m med iate i m med iate operand operand operand operand operand is is is is is one. one. one. one. one. U nchan ged U nchanged U nchanged U nchanged U nchanged otherwise. otherwise. otherwise. otherwise. otherwise.

I nstruction Format:
6 5 4 3 2

..

B-1 33

O RI to S R
Operation:

Inclusive O R I mmediate to the Status Register (Privileged Instruction) If su pervisor state then Source v SR - S R e l s e TRAP ORI # < data > ,SR

O RI to S R

Assembler Syntax: Attributes:

Size = (Word)

Description: I nc l u s ive OR the i m med iate operand with the contents of the status reg i ster and store the resu l t in the statu s register. A l l bits of the status reg i ster are affected. Condition Codes: x N z c

* 1 * 1 * 1 * 1 * 1
Z V C X

Set Set Set Set Set

if if if if if

bit bit bit bit bit

3 2 1 0 4

of of of of of

i m mediate i m mediate i m mediate i m mediate i m med iate

operand operand operand operand operand

is is is is is

one. one. one. one. one.

U nchanged U nchanged Unchanged Unchanged Unchanged

otherwise. otherwise. otherwise. otherw i se. otherw i se.

Instruction Format:

15 0

14 0

13 0

12 0

11 0

10 0

9 0

Word Data (1 6 Bits)

8 0

7 0

6 1

5 1

4 1

3 1

2 1

1 0

0 o

81 34

PAC K
Operation: Assembler Syntax: Attributes:

Pack

PAC K

Sou rce (Un packed BCD) + adj ustment - Dest i nation (Packed BCD) PACK - (Ax), - (Ay),# < adj u stment > PACK DX, Dy,# < adj u stment > U ns ized

Description: The l ow fou r bits of each of two bytes are adj usted and packed i nto a s i ngle byte. When both operands are data registers, the adj u stment is added to the value con tained in t he sou rce reg ister. Bits [1 1 :8] and [3:0] of the i ntermedi ate resu l t are con catenated and placed i n bits [7:0] of the dest i nation register. The remai nder of the dest i nation reg i ster is u n affected.

15 14 Ox I x I x 15 14

Source:

13 13

12 12

11 11

10 10 10
b'

9 8 c I d 9 9 I c'

6 5 4 3 2 x I x I x I x I e I f I
7

Add Adj u stment Word:

8 7 6 5 16Bit Extension

2 1

0 0

Resu l t i n g i n :

I x' I

15

14
x'

I x' I x' I

13

12

11

a'

8 7 6 5 4 3 2 d' I x' I x' I x' I x' I e' I f' 8 u I

7 a'

g'

h'

I I

15 14 13 12 OY I U I U I U l u

Dest i nation:

11 1 0 9 u l u l u

b'

5 4 3 2 c' I d ' I e' I f' I

g'

h'

When the add ressing mode specified is predecrement, two bytes from the source are fetched, adjusted, and concatenated. The extension word i s added to the con catenated bytes. Bits [3:0] of each byte are extracted. These eight bits are con catenated to form a new byte which is then w ritten to the destination . Sou rce:
7

4 3 2 0

Concatenated Word:

15

14

13

12

11

10

B-1 35

PAC K
Add Adj u stment Word:
15 14 13 12 11 10 9 8

Pack

PAC K
6 5 4 3 2 0

1 6-Bit Extension

Destination:

(Ay)

Condition Codes: I nstruction Format:

15 14 13

N ot affected.

7 a'

6 b'

5 c'

4 d'

3 e'

I'

1 g'

0 h'

12

11

10 Register Dy/Ay

2 Register Dx/Ax

Adjustment

Instruction Fields: Reg i ster Dy/Ay field - Spec ifies the desti nation reg i ster. If RIM = 0, specifies a data reg ister. If RIM = 1 , specifies an add ress reg i ster for the predecrement addressi n g mode. RIM field - Spec ifies the operand addressing mode. 0-The operat ion i s data reg ister to data reg i ster. 1 -The operat ion is memory to memory. Register DxlAx field - Specifies the sou rce register. If RIM = 0, specifies a data register. If RIM = 1 , specifies an address reg i ster for the predecrement addressi n g mode. Adj u stment field - I m mediate data word which is added to the sou rce operand. Appropriate constants can be used to trans late from ASC I I or E BCDIC to BCD .

B1 36

P EA
Operation: Assembler Syntax: Attributes:

Push Effective Address SP - 4 - SP; EA - (S P) PEA < ea >

P EA

Size = (Long)

Description: The effective address is com puted and pushed onto the stack. A long word address is pushed onto the stack. Condition Codes: I nstruction Format:
5 4 Mode 3 2 Register o Effective Address

N ot affected.

Instruction Fields: Effective Address field - Specif ies the address to be pushed onto the stack. O n ly control add ressing modes are a l l owed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

(xxx).w (xxx).L # < data >

111 111
-

000 001
-

010
-

reg. number:An
-

1 01 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC),Xn,od)

111 111 111 111 111

010 011 011 011 011

8-1 37

R ES ET
Operation:

Reset External Devices (Privileged Instruction)

R ES ET

I f su pervisor state then Assert RESET Line else TRAP R ESET Uns ized

Assembler Syntax: Attributes:

Description: The reset l i n e is asserted, causi n g a l l external devices to be reset. The pro cessor state, other than the program cou nter, is u naffected and execut ion conti nues with the next i nstruct ion. Condition Codes: Instruction Format:
15 o

Not affected.

14 1

13 0

12

11

10

3 o

2 0

1 o

0 0

81 38

RO L RO R
Operation: Assembler Syntax:

Rotate (Without Extend) Desti nation Rotated by < cou nt > - Desti nation ROd DX, Dy ROd # < data > , Dy ROd < ea > w here d i s d i rection, L or R Size = (Byte, Word, Long)

RO L RO R

Attributes:

Description: Rotate the bits of the operand in the d i rection (L or R) specified. The extend bit is not i nc l uded i n the rotat ion. The rotate count for the rotat ion of a reg ister may be specified in two different ways: 1 . I m mediate - the rotate count is specified in the i nst ruct ion (rotate range, 1 -8). 2. Reg i ster - the rotate count is contai ned in a data reg ister specified in the i nstruc tion. The size of the operation may be specified to be byte, word, or long. The content of memory may be rotated by one bit only and the operand size is restricted to a word. For ROL, the operand is rotated left; the n u m ber of positions rotated is the rotate count. Bits rotated out of the high order bit go to both the carry bit and back into the low order bit. The extend bit is not modified or used.

ROL:

---+--r--------r-------' o pe a nd

For ROR, the operand is rotated right; the n u m ber of positions rotated is the rotate count. Bits s h ifted out of the low order bit go to both the carry bit and back i nto high order bit. The extend bit is not mod ified or used.

ROR:

-- - - - -r- -- - - -- -o pe r a nd -+ -- -- .

- Continued -

B-1 39

RO L RO R
Condition Codes:

Rotate (Without Extend)

ROL RO R

1 - 1 * 1 * 1 0
N Z V C X

* 1

Set if the most s i g n i ficant bit of the res u l t is set. Cleared otherw i se. Set if the resu l t is zero. Cleared otherw i se. A lways cleared. Set accord i n g to the last bit rotated out of the operand. Cleared for a rotate count of zero. Not affected.

Instruction Format (Register Rotate):

15 14 13 12 11 10 Rotatel Register 9 8 7 6 5 4 3 2 Register 0

I nstruction Fields (Register Rotate): Rotate/Reg i ster field If i/r = O, the rotate count is specified in t h i s field. The val ues 0, 1 -7 represent a range of 8, 1 to 7 respectively. If i/r = 1 , the rotate count (mod u l o 64) i s contai ned in the data reg ister specified in t h i s field. dr field - Spec ifies the d i rection of the rotate: O- rotate rig ht. 1 - rotate left. Size field - Spec ifies the size of the operat ion: OO- byte operat ion. 01 -word operation. 1 0- long operat ion. i/r field If i/r = 0, specifies i m med iate rotate count. If i/r = 1 , specif ies reg i ster rotate count. Reg i ster field - Specifies a data reg ister whose content i s to be rotated . Instruction Format (M emory Rotate):
5 4 Mode 3 2 Register o Effective Address

- Conti n ued -

8-1 40

ROL RO R

Rotate (without Extend)

RO L RO R

Instruction Fields ( Memory Rotate): dr field - Specifies the d i rect ion of the rotate: O- rotate right. 1 - rotate left. Effective Address field - Specifies the operand to be rotated. Only memory alterable addressing modes are a l l owed as shown:
Addr. Mode Mode

On (An) + (An) - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) bd,An,Xn),od) bd,An),Xn,od) An

Register

Addr. Mode

Mode

Register

(xxx).w (xxx).L #I < data>

111 111

000 001

010 01 1 1 00 1 01 110 1 10 110 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6, PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

81 41

ROX L ROX R
Operation: Assembler Syntax: ROXd DX,Dy ROXd # < data > , Dy ROXd < ea >

Rotate with Extend Dest i nation Rotated with X by < count > - Dest i nation

ROX L ROX R

Attributes:

Size = (Byte, Word, Long)

Description: Rotate t he bits of the dest i nation operand i n t he d i rection spec ified. The ex tend bit (X) is i nc l uded in the rotation. The rotate count for the rotat ion of a reg ister may be specified i n two d i fferent ways: 1 . I m mediate - the rotate count is specified i n the i nstruction (rotate range, 1 -8). 2. Reg i ster - the rotate count (mod u l o 64) is contai ned in a data reg ister specified i n t he i nstruction. The s ize of the operation may be specified to be byte, word, or long. The content of memory may be rotated one bit o n ly and the operand s ize i s restricted to a word. For ROXL, the operand is rotated left; the n u mber of positions rotated i s t he rotate count. Bits rotated out of the h i g h order bit go to both the carry and extend bits; the previous value of the extend bit is rotated into the low order bit.

ROXL:

For ROXR, the operand is rotated right; the n u mber of pos itions shifted is the rotate count. Bits rotated out of the low order bit go to both the carry and extend bits; the previous val ue of the extend bit is rotated into the h i g h order bit.

1.-+l--=====o=p=er=a=n=d==I.-4

ROXR:

Condition Codes: x N z N Z V C X

--I-_-_-_-_-_o=p=er=a=nd====r-l-.
V c

1 1 1 1 0

Set if the most S i g n i f icant bit of the resu l t is set. Cleared otherw i se. Set if the res u l t is zero. C leared otherw i se. A lways cleared. Set accord i n g to the last bit rotated out of the operand. Set to the value of the extend bit for a rotate count of zero. Set accord i n g to the last bit rotated out of the operand. Unaffected for a rotate count of zero. B-1 42

ROXL ROX R
15 14 13 12 11 10 Rotatel Register 9

Rotate with Extend

ROX L ROX R
4 3 2 Register 0

Instruction Format (Register Rotate):

8

Instruction Fields (Register Rotate): Cou nt/Register field I f i/r = 0, the rotate count is s pecified in t h i s field. The values 0, 1 7 represent a range of 8, 1 to 7 respectively. If i/r = 1 , the rotate count (mod u l o 64) is contai ned i n t he data reg i ster spec ified i n t h i s field. d r field - Specifies the d i rect ion of the rotate: O- rotate right. 1 - rotate left. Size field - Specifies the size of the operat ion: OO- byte operat ion. 01 - word operation. 1 0 - long operat ion. i/r field I f i/r = 0, specifies i mmediate rotate count. If i/r = 1 , specifies reg i ster rotate count. Register field - Specifies a data reg ister w hose content i s to be rotated. I nstruction Format (Memory Rotate):
5 4 Mode 3 2 Register 0 Effective Address

I nstruction Fields (M emory Rotate): dr field - Spec ifies the d i rection of the rotate: O- rotate right. 1 - rotate left. Effective Address field - Spec ifies the operand to be rotated. O n ly memory alterable add ressing modes are a l l owed as shown:

81 43

ROX L ROX R
Addr. Mode Mode
-

Rotate with Extend

ROX L ROX R
Mode Register

Register
-

Addr. Mode (xxx).w (xxx).L

Dn An (An) (An) + - (An) (d 1 6 ,An) (dB,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

111 111
-

000 001
-

010 01 1 1 00 1 01 110 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

" < data>

(d 1 6 ,PC) (dB,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PCj,Xn,od)

81 44

RT D
Operation: Assembler Syntax: Attributes:

Return and Deallocate Parameters (SP) - PC; SP + 4 + d - SP

RT D

RTD # < displacemen t >

U ns ized

Description: The program cou nter is p u l led from the stack. The previous program counter value i s l ost. After the program counter i s read from t he stack, the d isplace ment va lue ( 1 6 bits) is S i g n-extended to 32 bits and added to the stack poi nter. Condition Codes: Instruction Format: N ot affected.

Instruction Field: Disp lacement field - Specifies the twos complement i nteger which is to be s i g n extended and added to t he stack pai nter.

15 0

14 1

13 0

12 0

11 1

10 1

9 1

8 0

Displacement

7 0

6 1

5 1

4 1

II

8-1 45

RT E
Operation:
-+

Return from Exception (Privileged I nstruction)

RT E
-+

I f s u pervisor state then (SP) SR; SP + 2 SP; (SP) restore state and dea l l ocate stack according to (SP) else TRAP
-+

-+

PC; SP + 4

SP;

Assembler Syntax: Attributes:

RTE U ns ized

Description: The processor state i nformation in the except ion stack frame on top of t he stack is loaded i nto the processor. The stack format field in the format/offset word is exam i ned to determine how much i nformation m u st be restored. Condition Codes: I nstruction Format: Set accord i n g to the content of the word on the stack.

15 0

14 1

13 0

12 0

11 1

10 1

9 1

8 0

7 0

6 1

5 1

4 1

3 0

2 0

0 1

Format/Offset Word ( i n stack frame):

15 14 13 12 11 0 10 0 9 8 7 6 5 4 3 2 0 Format Vector Offset

Instruction Fields: Format field - Th is 4-bit field def i nes the amount of i nformat ion to be restored. OOOO-Short Format, o n ly fou r words are to be removed f rom the top of the stack. The status reg ister and program cou nter are loaded from the stack f rame. 0001 -Throwaway Format, fou r word s are removed from the top of stack. O n ly the status reg ister is loaded, after w h ich, the processor beg i n s executing t he RTE from t he top of the active system stack. This format is used to mark the bottom of the i nterrupt stack. 001 0 - l nstruction Error Format, six words are removed from the top of the stack. The f i rst fou r words are u sed as in the Short Format and the re maining two words are t h rown away. 1 000- M C680 1 0 Long Format, the M C68020 takes a format error exception. 1 001 -Coprocessor M id-I nstruction Format, 1 0 words are removed from t he top of stack. Resumes coprocessor i nstruction execution. 1 01 0- M C68020 Short Format, 16 words are removed from the top of t he stack. Resumes i nstruction execution. 1 0 1 1 - M C68020 Long Format, 46 words are removed from the top of the stack. Resumes i n struction exec ution. Any others - the processor takes a format error exception.

8-1 46

RT M
Operation: Assembler Syntax: Attributes:

Return from Module Reload Saved Module State from Stack RTM R n Uns ized

RTM

Description: A previously saved mod u l e state i s reloaded from the top of stack. After the module state i s retrieved from the top of the stack, the cal ler's stack pOi n ter is i n cremented by the arg u ment count value i n the module state. Condition Codes: Instruction Format: Set accord i n g to the content of the word on t he stack.

15 0

14 0

13 0

12 0

11 0

10 1

9 1

l OlA I

2 Register

I nstruction Fields: D/A field - Specifies w hether the module data pointer is i n a data or an address reg i ster. O-the reg i ster is a data reg i ster. 1 -the reg ister is an add ress reg ister. Reg ister field - Specifies the reg i ster n u m ber for the mod u le data area poi nter w h i c h i s to be restored from the saved mod u l e state. If the reg ister specified is A7 (SP), the u pdated va lue of the reg ister reflects the stack poi nter operat ions, and the saved mod u l e data area pointer is lost.

8-1 47

RT R
Operation:

Return and Restore Condition Codes (SP) - CCR; SP + 2 - S P; (SP) - PC; SP + 4 - S P RTR Uns ized

RT R

Assembler Syntax: Attributes:

Description: The cond ition codes and program counter are p u l led from the stack. The previous cond ition codes and program cou nter are lost. The su pervisor portion of the status reg i ster is u naffected. Condition Codes: Instruction Format:
15

Set accord i n g to the content of the word on t he stack.

o
1

14 1

13 0

12 0

11

10

8-1 48

RTS
Operation: Assembler Syntax: Attributes: (SP) RTS Uns ized
-+

Return from Subroutine PC; SP + 4 SP

RTS

-+

Description: The program cou nter i s p u l led from t h e stack. The previous program counter is lost. Condition Codes: Instruction Format:
15 0

N ot affected.

14 1

13 0

12 0

11 1

10 1

9 1

8 0

7 0

6 1

5 1

4 1

3 0

2 1

0 1

81 49

SBCD
Operation: Assembler Syntax: Attributes:

Subtract Decimal with Extend Dest i nation 1 0 - Sou rce 1 0 - X S8CD DX,Dy S8CD - (Ax), - (Ay) Dest i nation

SBC D

Size = (8yte)

Description: Subtract the sou rce operand from t he dest i nation operand with the extend bit and store the res u l t in the dest i nation l ocation. The s u btract ion is performed us ing deci mal arith metic. The operands may be addressed in two d i fferent ways: 1 . Data reg i ster to data reg i ster: The operands are contai ned in the data reg i sters specified in the i nstruct ion. 2. Memory to memory: The operands are add ressed with the predecrement address i n g mode u s i n g the address reg i sters specified in the i nstruction. This operation i s a byte operation on ly. Condition Codes:

1 * l u l * l u
N Z V C X

*1

U ndef i ned. Cleared if the resu l t is non-zero. Unchanged otherw ise. U ndef i ned. Set i f a borrow (dec i mal) is generated. Cleared otherwise. Set the same as the carry bit. N OTE Normally the Z cond ition code bit i s set via program m i n g before the start of an operat ion. Th i s al lows s uccessfu l tests for zero resu lts u pon complet ion of m u l t i ple-precision operat ions.

I nstruction Format:
11 10 Register Oy/Ay 9 4 3 2 Register Ox/Ax o

II

Instruction Fields: Reg i ster DylAy field - Specifies t he desti nation reg i ster. If RIM = 0, specifies a data reg ister. If RIM = 1 , specifies an address reg ister for the predecrement addressing mode. RIM field - Spec ifies the operand addressi n g mode: 0-The operation is data reg ister to data reg ister. 1 -The operation is memory to memory. Reg i ster Ox/Ax field - Specif ies the sou rce reg i ster: If RIM = 0, specif ies a data reg i ster. If RIM = 1 , spec i f ies an address reg i ster for t he predecrement addressing mode.

8-1 50

See
Operation:

Set According t o Condition If Cond ition True then 1 s - Dest i nation else Os - Desti nation Scc < ea >

See

Assembler Syntax: Attributes:

Size = (Byte)

Description: T h e specified cond ition code i s tested; if t h e cond ition i s t rue, the byte specif ied by the effective address is set to TRUE (al l ones), otherwise that byte is set to FALSE (al l zeroes). "cc" may specify the fol lowi n g cond itions:
CC CS EQ F GE GT HI LE carry clear carry set equal never true greater or equal greater than high less or equal 0100 0 1 01 01 1 1 0001 1 1 00 1 1 10 0010 1111 C C Z 0 N . V + N .ij" N . V .Z + LS LT MI NE PL T VC VS low or same less than minus not equal plus always true overflow clear overflow set 001 1 1 1 01 1011 01 1 0 1010 1 000 1001 C+Z N .V + N .V N Z 1 V V

C'-Z

N.V.Z

0000

Z + N .V + N.V

Condition Codes: Instruction Format:

Not affected.
a

11

10

4 Mode

2 Register

Condition

Effective Address

Instruction Fields: Cond ition field - One of s i xteen cond ition s d i scussed i n description. Effective Address field - Specifies the locat ion i n which the true/false byte is to be stored. Only data alterable addressi n g modes are al lowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

On An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xnl,od) ([bd,Anl,Xn,od)

000
-

reg. number:On
-

(xxx)W (xxx).L # < data >

111 111
-

000 001
-

010 011 1 00 101 1 10 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6, PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnl,od) ([bd, PCJ,Xn,od)

Note: 1 . An arithmet i c one and zero resu l t may be generated by following the Scc i n struct ion with a N EG i nstruct ion.

B-1 51

STO P
Operation:

Load Status Register and Stop (Privileged Instruction) If s u pervisor state then I m mediate Data - SR; STOP else TRAP STOP # < data > Unsized

STO P

Assembler Syntax: Attributes:

Description: The i mmediate operand is moved i nto t he entire status register; the pro g ram counter is advanced to point to the next i nstruction and t he processor stops fetch i n g and executing i nstructions. Execution of i nstructions resumes w hen a t race, i nterrupt, or reset except ion occu rs. A t race except ion w i l l occur if the t race state is on w hen the STOP i nstruction beg i ns execution. If an i nterru pt request is asserted with a priority h i g her than the priority level set by the im mediate data, an i n terru pt except ion occurs, otherw ise, the i nterrupt request has no effect. If the bit of the im med iate data correspond i n g to t he S-bit is off, execution of the i nstruction w i l l cause a privilege violation. External reset w i l l always i n itiate reset except ion processing. Condition Codes: Instruction Format: Set accord i n g to t he i m med iate operand.

I nstruction Fields: I m mediate field - Specifies the data to be loaded into the status reg ister.

15 0

14 1

13 0

12 0

11 1

10

9 1

8 0

Immediate Data

7 0

6 1

5 1

4 1

3 0

2 0

0 1 0

8-1 52

SU B
Operation: Assembler Syntax: Attributes: SUB < ea > , D n S U B Dn, < ea >

Subtract Binary Dest i nation - Source -- Dest i nation

SU B

Size = (Byte, Word, Long)

Description: Su btract the sou rce operand from the dest i nation operand and store the res u lt in the dest i nation. The s ize of the operation may be spec ified to be byte, word, or long. The mode of the i nstruct ion i n d icates which operand i s the sou rce and which i s the desti nat ion as w e l l as the operand s ize. Condition Codes: c

1 * 1 * 1 * 1 *
N Z V C X Set Set Set Set Set

* 1

if the resu l t is negat ive. Cleared otherw i se. if the resu l t is zero. Cleared otherwise. if an overflow is generated. Cleared otherw i se. if a borrow is generated. Cleared otherwise. the same as the carry bit.

Instruction Format:
11 10 Register 9 8 7 OpMode 6 5 4 Mode 3 2 Register 0 Effective Address

Instruction Fields: Reg i ster field - Spec ifies any of the eight data reg i sters. Op- M od e field Byte Word Long Operation 000 001 010 < Dn > - < ea > -- < Dn > 1 00 1 01 1 10 < ea > - < Dn > -- < ea > Effective Address field - Determ i nes addressing mode: If the location specified is a source operand, then a l l addressing modes are a l l owed as shown:

B-1 53

SU B
Addr. Mode Mode

Subtract Binary
Register Addr. Mode Mode

SU B
Register

On An * (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000 001 010 011 1 00 101 1 10 1 10 1 10 1 10

reg. number:On reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(xxx).W (xxx).L # < data>

111 111 111

000 001 1 00

(d 1 6, PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd, PC),Xn,od)

111 111 111 111 111

010 011 01 1 011 01 1

* For byte size operation, address register d i rect is not a llowed.

If the location specified is a destination operand, then only alterable memory addressing modes are allowed as shown:
Addr. Mode Mode
-

Register
-

Addr. Mode

Mode

Register

On An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od)

(xxx).W (xxx).L # < data >

111 111
-

000 001
-

010 01 1 1 00 101 110 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 ,PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC),Xn,od)

Notes:

1 . If the dest i nation is a data reg ister, t hen it cannot be specif ied by using the destination < ea > mode, but must use the destination On mode i nstead. 2. SUBA is used w he n the dest i nation is an address register. SUBI and SUBQ are used w hen the sou rce is i mmed iate data. M ost assemblers automatical ly make this disti nction .

B1 54

S U BA
Operation: Assembler Syntax: Attributes:

Subtract Address Dest i nation - Sou rce - Desti nation SUBA < ea > ,A n

SU BA

S ize = (Word, Long)

Description: Su btract t he sou rce operand from t he dest i nation address reg i ster and store the res u l t in the address reg i ster. The s ize of the operat ion may be specified to be word or long. Word s ize source operands are sign extended to 32 bit quantities before the operat ion i s done. Condition Codes: I nstruction Format:
15 14 13 12 11 10 Register 9 a 7 OpMode 6 5 4 Mode 3 2 Register o Effective Address

N ot affected.

I nstruction Fields: Reg i ster field - Spec ifies any of t he e i g ht address reg i sters. Th i s is always t he dest i nation. Op-Mode field - Spec ifies the s ize of the operat ion: 01 1 -Word operation. The sou rce operand i s s i g n-extended to a long operand and the operat ion i s performed on the address reg i ster using all 32 bits. 1 1 1 - Long operat ions. Effective Address field - Specifies t he sou rce operand. All addressing modes are al lowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

On An (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000 001 010 011 100 1 01 110 110 1 10 1 10

reg. number:On reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(xxx).w (xxx). L # < data>

111 111 111

000 001 1 00

(d 1 6, PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

111 111 111 111 111

010 011 011 011 01 1

B-1 55

SU BI
Operation: Assembler Syntax: Attributes:

Subtract I mmediate Desti nation - I m med iate Data - Dest ination SUBI # < data > , < ea >

SU B I

Size = (Byte, Word, Long)

Description: Su btract the i m med iate data from the destination operand and store the res u lt i n the dest i nation locat ion. The s ize of the operation may be spec ified to be byte, word, or long. The s ize of the i mmed iate data matches the operat ion s ize. Condition Codes:

1 1 1 1 1
Z V C X

Set Set Set Set Set

if the res u l t is negative. Cleared otherw ise. i f the resu l t is zero. Cleared otherwise. if an overflow is generated. Cleared otherw ise. if a borrow is generated. Cleared otherw i se. the same as the carry bit.

I nstruction Format:

15 0

1 1 1 101 1010
Word Data

14 0

13 0

12 0

11

10 1

7 Size

4
Mode

3
1

2
Register

Eflecllve Address Byte Data

Long Data

Instruction Fields: Size field - Specif ies the s ize of the operat ion. OO- byte operation. 01 - word operat ion. 1 0- long operat ion. Effective Address field - Specifies the desti nation operand. O n ly data alterable addressing modes are allowed as shown:

B-1 56

SU B I
Addr. Mode Mode

Subtract Immediate

SU BI
Mode Register

Register

Addr. Mode

Dn An (An) (An) + - (An) (d 1 6 ,An) (dS,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od)

000
-

reg. number:Dn
-

(xxx).w (xxx).L # < data>

111 111
-

000 001
-

010 01 1 100 101 110 1 10 1 10 1 10

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6 , PC) (dS,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

I mmediate field If s ize = 00, then If s ize = 01 , t hen If s ize = 1 0, t hen

(Data i m med iately fol lowing the i nstruct ion) the data is the low order byte of the i m med iate word. the data is the entire i mmediate word. the data is the next two i m med iate words.

II

8-1 57

SU B Q
Operation: Assembler Syntax: Attributes:

Subtract Quick Dest ination - I m mediate Data Desti nation

SU BQ

-+

S U BQ # < data > , < ea >

Size = (Byte, Word, Lon g)

Description: Subtract the i m med iate data from the dest ination operand. The data range is from 1 8. The s ize of the operation may be specified to be byte, word, or long. Word and long operations are also a l l owed on the address reg isters and t he condition codes are not affected. When subtracting from address reg i sters, the entire dest i na tion address reg i ster is u sed, regard less of the operat ion s ize. Condition Codes:
x

* 1 * 1 * 1 * 1 * 1
Z V C X

Set Set Set Set Set

if the resu l t is negat ive. Cleared otherw i se. if the resu l t is zero. Cleared otherwise. if an overflow is generated. Cleared otherw i se. if a borrow is generated. C leared otherw i se. the same as the carry bit.

Data

Effective Address Mode Register

Instruction Fields: Data field - Three bits of i m med iate data, 0, 1 7 representing a range of 8, 1 to 7 respectively. Size field - Spec ifies the s ize of the operat ion: OO- byte operation. 01 - word operation. 1 0- long operat ion. Effective Address field - Specifies the dest i nation l ocation. Only alterable address i n g modes are allowed a s shown:

B1 58

SU BQ
Addr. Mode Mode

Subtract Quick

SU BQ
Mode Register

Register

Addr. Mode

On An* (An) (An) + - (An) (d 1 6 ,An) (da,An,Xn) (bd,An,Xn) ([bd,An,Xnj,od) ([bd,Anj,Xn,od) * Word and long only.

000 001 010 011 1 00 1 01 1 10 1 10 1 10 1 10

reg. number:On reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(xxx).W (xxx).L # < data>

111 111
-

000 001
-

(d 1 6, PC) (da,PC,Xn) (bd,PC,Xn) ([bd,PC,Xnj,od) ([bd,PC),Xn,od)

81 59

S U BX
Operation: Assembler Syntax: Attributes: SUBX DX, Dy SUBX - (Ax), - (Ay)

Subtract with Extend Dest i nation - Sou rce - X -- Dest i nation

SU BX

Size = (Byte, Word, Long)

Description: Subtract the source operand from the dest i nation operand along with the extend bit and store the res u l t i n the dest i nation locat ion. The operands may be ad. d ressed in two d ifferent ways: 1 . Data reg i ster to data reg ister: The operands are contai ned i n data reg i sters specified i n the i nstruction. 2. M emory to memory. The operands are contai ned in memory and addressed with the predecrement add res s i n g mode u s i n g the add ress reg isters spec ified in the i nstruct ion. The s i ze of the operand may be specified to be byte, word, or long. Condition Codes: x N z

1 1 1 1 1
Z V C X

Set if the res u l t is negat ive. Cleared otherwi se. Cleared if the resu l t is non-zero. U nchanged otherwise. Set if an overflow is generated. Cleared otherwise. Set if a carry is generated. Cleared otherwise. Set the same as the carry bit. N OTE Normally the Z cond ition code bit i s set via progra m m i n g before the start of an operat ion. This a l l ows successfu l tests for zero resu lts u pon completion of m u l t i ple-precision operat ions.

I nstruction Format:
15 14 13 12 11 10 Register Oy/Ay 9 8 7 6 5 4 3 2 Register Ox/Ax 0

Instruction Fields: Reg i ster Dy/Ay field - Specifies the desti nation reg ister: If RIM = 0, specifies a data reg ister. I f RIM = 1 , spec i fies an address reg i ster for the predecrement addressing mode. Size field - Spec ifies the s ize of t he operat ion: OO- byte operat ion. 01 -word operation. 1 0- long operat ion.

B-160

S U BX

Subtract with Extend

S U BX

RIM field - Specif ies the operand addressing mode: 0-The operation is data reg i ster to data reg i ster. 1 -The operation is memory to memory. Reg i ster Ox/Ax field - Spec ifies the sou rce reg ister: If RIM = 0, spec ifies a data reg i ster. if RIM = 1 , spec i f ies an address reg i ster for the predecrement addressing mode .

8-161

SWAP
Operation: Assembler Syntax: Attributes:

Swap Register Halves Reg i ster [31 : 1 6] - Reg i ster [1 5:0]

SWA P

SWAP On

Size = (Word)

Description: Exchange the 1 6bit halves of a data reg ister. Condition Codes:

1 -1 * 1 * 1 0 1 0 1
N Z V C X Set if the most s i g n i f i cant bit of the 32bit resu l t is set. Cleared otherw ise. Set if the 32bit resu l t is zero. Cleared otherw ise. Always cleared. Always cleared. Not affected.

Instruction Format:

I 0I

15

14 1

I 0 I 0 I

13

12

11 1

I 0 I 0 I 0

10

7 o

6 1

5 o

I 0

3 o

2 Register

I nstruction Fields: Reg i ster field - Spec ifies the data reg ister to swap .

81 62

TAS
Operation: Assembler Syntax: Attributes:

Test and Set an Operand Dest i nation Tested TAS < ea > Cond ition Codes; 1 bit 7 of Desti nation

TAS

-+

-+

Size = (Byte)

Description: Test and set the byte operand addressed by the effective address field. The cu rrent value of the operand is tested and N and Z are set accord i n g ly. The h i g h order b i t o f the operand is set. T h e operat ion is indivisible ( u s i n g a read-modify-write memory cyc le) to al low synchron ization of several processors. Condition Codes:

1-1 * 1 * 1 0 1 0 1
N Z V C X Set if the most s i g n ificant bit of the operand was set. Cleared otherw i se. Set if the operand was zero. Cleared otherwise. A lways c leared. A l ways c leared. N ot affected.

Instruction Format:
15 14 13 12 11 10 9 e 7 6 5 4 Mode 3 2 Register o Effective Address

Instruction Fields: Effective Address field - Specifies the locat ion of the tested operand. Only data alterable address i n g modes are al lowed as shown:
Addr. Mode Mode Register Addr. Mode Mode Register

Dn (An) + (An) - (An) (d 1 6 ,An) (de,An,Xn) (bd,An,Xn) ([bd,An,Xn),od) ([bd,An),Xn,od) An

000 010 011 1 00 1 01 1 10 110 1 10 110

reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(xxx).W (xxx).L # < data >

111 111
-

000 001

(d 1 6 ,PC) (de,PC,Xn) (bd,PC,Xn) ([bd,PC,Xn),od) ([bd,PC),Xn,od)

B-1 63

T RAP
Operation:

Trap sSP - 2 -- SSP; Format/Offset -- (SSP); SSP - 4 -- SS P; PC -- (SSP); SSP - 2 -- SS P; SR -- (SSP); Vector Address -- PC TRAP # < vector > U nsized

T RA P

Assembler Syntax: Attributes:

Description: The processor i n i t iates exception proceSS i ng . The vector n u m ber is generated to reference the TRAP i nstruction exception vector speci fied by the low order fou r bits of the i nstruction. Sixteen TRAP i nstruction vectors (0- 1 5) are avai lable. Condition Codes: Instruction Format:
15 14 13 12 11 10 9 8 7 o

N ot affected.

6 1

5 o

4 0

2 Vector

Instruction Fields: Vector field - Spec ifies which t rap vector conta i n s the new program cou nter to be loaded .

8-164

T RA Pcc
If cc then TRAP TRAPcc TRAPcc.W # < data > TRAPcc. L # < data >

Trap o n Condition

T RA Pcc

Operation: Assembler Syntax:

Attributes:

Unsized or Size = (Word, Long)

Description: If t he selected cond ition is t rue, the processor i n i t iates exception process i ng. The vector n u m ber is generated to reference the TRAPcc exception vector. The stacked prog ram counter poi nts to the next i nstruct ion. If the selected condition i s not t rue, no operat ion is performed, a n d execution conti n ues w i t h t h e next i nstruc tion in seq uence. The i m mediate data operand(s) is placed i n the next word(s) fol low i n g the operation word and is (are) avai lable for u ser def i n ition for u se w i t h i n the t rap handler. " cc" may specify the following conditions.
CC CS EQ F GE GT HI LE carry clear carry set equal never true greater o r equal greater than high less or equal 0100 0101 01 1 1 000 1 1 1 00 1 1 10 0010 1111 C C Z 0 N . V + N.Y N . V .Z + N .\i. Z :Z Z + N .Y + N . V LS LT MI NE T VC VS low or same less than minus not equal plus always true overflow clear overflow set 001 1 1 1 01 1011 01 1 0 1010 1 000 1 001 C+Z N .Y + N.V N

PL

0000

Jq 1 Y V

Condition Codes: Instruction Format:

15

N ot affected.

o I

14 1

13 0

12 1

11

10

Condition

7 1

Optional Word or Long Word

6 1

5 1

4 1

3 1

2 Op-Mode

Instruction Fields: Cond ition field - One of s ixteen conditions discussed previous ly. Op-M ode field - Selects the i nstruct ion form. 0 1 O - l nstruction i s fol lowed by one operand word. 01 1 - l nstruction is fol lowed by two operands words. 1 00 - l nstruction has no following operand words.

8-1 65

T RA PV
Operation: Assembler Syntax: Attributes: If V t hen TRAP TRAPV U ns ized

Trap on Overflow

T RA PV

Description: I f the overflow condition is set, the processor i n i t iates except ion processing. The vector n u mber is generated to reference the TRAPV exception vec tor. If the overflow condition is clear, no operat ion is performed and execution con t i n ues with the next i nstruction in sequence. Condition Codes: I nstruction Format:
15 o 14 1 13 o 12 0 11 10 9 8 7 6 5 4 3 2 0

N ot affected.

8-1 66

TST
Operation: Assembler Syntax: Attributes: Desti nation Tested TST < ea >

Test an Operand Condition Codes

TST

-+

S ize = (Byte, Word, Long)

Description: Com pare the operand with zero. No resu lts are saved; however, the condi tion codes are set accord i ng to resu lts of the test. The size of the operat ion may be spec ified to be byte, word , or long. Condition Codes: x N z N Z V C X V c

1-1 * 1 * 1 0

0 1

Set if the operand is negat ive. Cleared otherw i se. Set if the operand is zero. Cleared otherw i se. Always cleared. Always cleared. N ot affected.
o

Instruction Format:
15 14 13 12 11 10 9 s 7 6 5 4 Mode 3 2 Register Effective Address

Instruction Fields: S ize field - Specifies the s ize of the operation: OO- byte operation. 01 -word operat ion. 1 0- long operat ion. Effective Address field - Spec ifies the dest i nation operand. If the operat ion s ize is word or long, a l l addressing modes are a l l owed. If the operat ion s ize is byte, only data address i n g modes are a l l owed as show n :
Addr. Mode Mode Register Addr. Mode Mode Register

Dn An (An) (An) + - (An) (d 1 6 ,An) (ds,An,Xn) (bd,An,Xn) ([bd,An,XnJ,od) ([bd,AnJ,Xn,od)

000 010 011 1 00 1 01 1 10 110 110 1 10

reg. number:Dn
-

(xxx).W (xxx).l # < data >

111 111
-

000 001
-

reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An

(d 1 6,PC) (ds,PC,Xn) (bd,PC,Xn) ([bd,PC,XnJ,od) ([bd,PCJ,Xn,od)

111 111 111 111 111

010 011 011 01 1 011

B-1 67

U N LK
Operation: Assembler Syntax: Attributes:

U nlink An - S P; (SP) - An; SP + 4

U N LK A n

U N LK

--

SP

U nsized

Description: The stack pointer is loaded from the specified address register. The ad d ress reg ister is t hen loaded with the long word p u l led from the top of the stack. Condition Codes: Instruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 1

N ot affected.

3 1

2 Register

I nstruction Fields: Reg i ster field - Spec ifies the address reg ister t h rough which the u n l i nking is to be done.

8-1 68

U NPK
Operation: Assembler Syntax: Attributes:

U npack BCD

U N PK

Sou rce (Packed BCD) + adj u stment -- Destination (Un packed BCD) U N PACK - (Ax), - (Ay),# < adj ustment > U N PK DX, DY,# < adj ustment > U nsized

Description: I n the u npack operat ion, two BCD d i g its w i t h i n the byte source operand are separated i nto two bytes with the BCD d i g i t residing in the lower n i bble and 0 in the u pper n ibble. The adj u stment is then added to this u npacked value without affecting the cond ition codes. When both operands are data reg i sters, the sou rce reg ister contents are u n packed, t he extension word is added, and the result is placed in the desti nation reg i ster. The high word of the dest i nation reg ister is u naffected. Source:
Ox
a

I I

15 u

I I

14 u

I I

13 u

I I

12 u

11 u

I I

10 u

9 u

8 u

I I

I I

6 b

I c I I
5 0

4 d

3 e

I I

I I

I I

0 h

I ntermediate Expansion:
15 0 14 0 13 0 12 0

11

10 b

I c I
9

8 d

7 0

6 0

4 0

3 e

2 f

Add Adj u stment Word:

15 14 13 12 11 10 8 7 6 5 4 3 2 0 1 6Bit Extension

Dest i nation:
Oy

15 v

14 v

13 v

12 v

11

'

10 b'

I c' I

8 d'

7 w

6 w

5 w

4 w

3 e'

2 f'

g'

h'

When the addres s i n g mode spec ified is predecrement, two BCD dig its are extracted from a byte at t he sou rce address. After add i n g the extension word, two bytes are then written to the desti nation address. Sou rce:
a

(Ax)

6 b

I c I

4 d

3 e

0 h

- Conti nued -

B-1 69

UNPK
I ntermedi ate Expansion:

U npack BCD

UNPK
I
5 0 4 0 3 e

Add Adj ustment Word :

15 14 13 12 11

15 0

14 0

13 0

12 0

11

10 b

9 c

8 d

7 0

6 0

2 f

0 h

10

7 9 8 " 1 6Bit Extension

Dest i nation:

(Ay)

Condition Codes: Instruction Format:

15 14 13

N ot affected.

7
v w

: 1 : 1 : 1 : 1 I I : I
6 5 4 3 2 o
"

12

11

10 Register Dy/Ay

2 Register Dx/Ax

Instruction Fields: Reg i ster DylAy field - Specif ies the dest ination reg i ster. If RIM = 0, specifies a data reg ister. I f RIM = 1 , spec ifies an add ress reg i ster for the predecrement addressing mode. RIM field - Specifies the operand addressing mode. 0-The operat ion is data reg i ster to data reg ister. 1 -The operat ion is memory to memory. Reg i ster DxlAx field - Spec i f ies the data reg ister. If RIM = 0, specifies a data reg i ster. If RIM = 1 , specifies an address reg i ster for the predecrement addressi n g mode. Adj ustment field - I m mediate data word which is added to the sou rce operand. Appropriate constants can be u sed to trans late from BCD to ASC I I or EBCDIC .

B-1 70

APPEN DIX C I NSTR U CTION FORMAT SU M MARY

This appendix provides a summary of the primary words in each i nstruct ion of the i n struction set. The com plete i nstruction def i n ition consists of the primary words fol lowed by the addressing mode operands such as i m med iate data fields, d i splacements, and i ndex operands. Table C-1 is an operat ion code (opcode) map which i l l u strates how bits 15 through 12 are used to specify the operat ions. The fi rst sect ion g roups the standard i n struct ions accord i ng to the opcode map. Disti nctions are made as to processor model su pport. Later processors s u pport all earl ier model i nstructions and addressing modes. The next section documents coprocessor i nstruct ion forms. The last shows coprocessor pri m i t ives which themse lves are not i nstructions but are command formats used across the coprocessor i nterface.

Table C1 . Operation Code Map

()()()()

Bits

15 through 12

Operation

0001 0010 001 1 0100 0101 0110 01 1 1 1000 1 001 1010 101 1 1 100 1 101 1 1 10 1111

Bit Manipulation/MOVEP/ lmmediate Move Byte Move Long Move Word Miscellaneous AOOO/ S U BO/ Scc/OBccITRAPcc Bcc/ B S R / B R A MOVEO O R / OIV /SBCO S U B / SUBX (Unassigned, Reserved) C M P/EOR ANO/MULI ABCO/ EXG AOO/AOOX Shift/Rotate/Bit Field Coprocessor Interface

C-1

Table C2. Effective Addressing Mode Categories

Address Modes Mode Register Data Memory
-

Control
-

Alterable

Assembler Syntax

Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Postincrement

000 001 010 01l 100 101 1 10 110 1 10 110 111 111 111 111 111 111 111 111

reg. no. reg. no. reg. no. reg. no. reg. no. reg. no reg. no. reg. no. reg. no. reg. no. 000 001 101 01 1 01 1 01 1 01 1 100

X
-

X X X X X X X X X X X X X X X X

X X X X X X X X X X X X X X X X

X
-

X X X X X X X X X X X X
-

On An IAnl IAnl + - IAnl I d 16 ,Anl Ids,An,Xnl Ibd,An,Xnl ( [bd,AnI,Xn,odl l[bd,An,XnJ ,odl Ixxxl .W Ixxxl . L Id 16 ,PCI Ids,PC,Xnl Ibd,PC,Xnl l [ bd, PCI,Xn,odl l [ bd,PC,XnJ,odl # < data >

Address Register Indirect with Predecrement

Address Register Indirect with Displacement Address Register Indirect with Index IS-Bit Displacement! Address Register Indirect with I ndex I Base Displacementl Memory Indirect Post-Indexed Memory Indirect Pre-Indexed Absolute Short Absolute Long Program Counter Indirect with Displacement Program Counter Indirect with Index IS-Bit Displacement! Program Counter Indirect with Index I Base Displacementl PC Memory Indirect Post-Indexed PC Memory Indirect Pre-Indexed Immediate

X X X X X X X X X X X X
-

Table C3. Conditional Tests

Mnemonic Condition Encoding

Test

T* F* HI LS CCIHSI CSI LOI NE EO VC VS PL MI GE LT GT LE

= =

True False High Low or Same Carry Clear Carry Set Not Equal Equal Overflow Clear Overflow Set Plus Minus Greater or Equal Less Than Greater Than Less or Equal

0000 000 1 0010 0011 0100 0101 0110 01 1 1 1000 1001 1010 1011 1 100 1 101 1 1 10 1111

1 0 CZ C+Z C C Z Z V V N N N . V + N.V N V + NV N .V .Z + N .V.7 Z + N.V + N . V

Boolean AND + Boolean OR N Boolean NOT N

=

* Not available for the Bee and cpBcc instructions

C2

STA N DARD I N STRUCTIONS

OR I mmediate
15 14 13 12 11 1

4 Mode

2 Register

Effective Address

Size field: 00 = byte

01 = word

10 = long

OR Immediate to CCR
15 14 13 12 11 1

OR I mmediate to S R
15 14 13 12 11 1

1 o

Word Data

0 0 I

C M P2 (MC68020)
15 14

0
AID

Register

Size field: 00 = byte

I0 I0
13

13

12

11

0 0

0
Size

7 1

6 1

4 Mode

2 Register

01 = word

0 1 0

0 0

Effective Address

1 0 = long

0 1 0 1 0 11 0 1 0 1 0

C H K2 (MC68020)
15 14

0
AID

Size field:

00 = byte

Register

I0I0
13 12

12

11

0
1

0
Size

7 1

6 1

1 0

0 0

Register Mode 0 10 10 I0 1 0 1 0 1

Effective Address

01 = word

10 = long

Dynamic Bit
15 14 11 10 Data Register Type field: 00 = TST 10 = CLR = CHG 1 1 = SET 9 8 7 6 5 4 Mode 3 2 Register o

Effective Address

01

C-3

MOVEP
15 14 13 12 11 10 Data Register 9 8 7 Op-Mode 6 5 4 3 2 Address Register 0

Op-Mode field: 100 = transfer word from memory to register 101 = transfer long from memory to register 1 1 0 = transfer word from reg ister to memory 1 1 1 = transfer long from register to memory

AND Immediate
15 14 13 12 11 10 9 8 7 6 5 4 Mode Size field: 00 = byte 01 = word 10 = long 3 2 Register 0

Effective Address

A N D Immediate to CCR

I I I I I I I I I
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

15

14

13

12

11

10

7 0

6 0

1 0

0 0

Byte Data

AND Immediate to S R
15 0 14 0 13 0 12 0 11 0 10 0 9 8 0 7 0 6 5 4 3 2 0 0 0

Word Data

SUB I mmediate
15 14 13 12 11 10 9 8 7 6 5 4 Mode Size field: 00 = byte 01 = word 1 0 = long 3 2 Register 0

Effective Address

ADD I mmediate
12 11 10 9 8 7 6 5 4 Mode Size field: 00 = byte 01 = word 1 0 = long 3 2 Register 0

Effective Address

C-4

RTM (MC68020)
15 0 14 0 13 0 12 11 10 9 8 7 6 5 o 4 o

I D/A I

2 Register

CALLM (MC68020)
15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 1 0 9 1 0 8 0 0 7 1

6 1

I
I

4 Mode

o Register

Effective Address Argument Count

CAS (MC68020)
15 0 0 14 0 0 13 0 0 12 0 0 11 1 0 o 10 Size 9 8 0 0

1 1
1 Du

6 1

4 Mode 0

o Register Dc

Effective Address 0

Size field: 01 = byte

10 = word

1 1 = long

CAS2 (MC68020)
15 0 D/A1 D/A2 14 o

13 0

12 0

11 1 0 0

10 Size o o

Register 1 Register 2 01 = byte

I
I

0 0

J 1 .1
Du1 Du2

6 1

5 1 0 0

4 1 0 0

3 1 0 0

2 1

0 Dc1 Dc2

o 0

Size field:

1 0 = word

1 1 = long

Static Bit
15 0 0 14 0 0 13 0 0 12 0 0 11 1 0 10 0 0 9 0 0 8 o

7 Type

4 Mode

o Register

Effective Address Bit Number

Type field: 00 = TST 1 0 = CLR 01 = CHG 11 = SET

EOR I mmediate
15 14 13 12 11 10 9 8 7 6 5 4 Mode Size field: 00 = byte 01 = word 10 = long 3 2 Register o

Effective Address

C-5

EOR I mmediate to CCR

15 0 0 14 0 0

I I I I I I I
0 0 1 0 1 0 0 0 0 0 0 0 13 0 12 0 11 10 0 9 8 0

13

12

11

10

7 0

6 0

5 1

4 1

Byte Data

1 0

0 0

EOR Immediate to SR
15 0 14 0 7 0 6 5 4 1

Word Data

3 1

2 1

1 0

0 0

CMP Immediate
15 14 13 12 11 10 9 8 7 6 5 4 Mode Size field: 00 = byte 01
=

2 Register

Effective Address

word 1 0 = long

MOVES (MC68010)
15 0 AID 14

Register

dr field: 0 = EA to register 1 = register to EA

I I
0 13

13

12 0

11 1 dr

10 1 0

9 1 0

8 0 0

7 Size

4 Mode 0

0 Register

Effective Address 0 0

o1

1 1

MOVE Byte
15 14 12 11 10 Register
Note register and mode locations

7 Mode

4 Mode

2 Register

Destination

Source

M OVEA Long
15 14 13 12 11 10 Register 9 8 7 6 5 4 Mode 3 2 Register 0

Destination

Source

C-6

MOVE Long
15 14 13 12 11 10 Register
Note register and mode locations

7 Mode

4 Mode

2 Register

Destination

Source

MOVEA Word
15 14 13 12 11 10 Register 9 8 7 6 5 4 Mode 3 2 Register 0

Destination

Source

MOVE Word
15 14 13 12 11 10 Register
Note register and mode locations

7 Mode

4 Mode

2 Register

Destination

Source

N EGX
15 14 13 12 11 10 9 8 7 6 5 4 Mode Size field: 00 = byte 01 = wore( 10 = long 3 2 Register 0

Effective Address

MOVE from S R
15 14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

CHK
15 14 13 12 11 10 Data Register Size field: 1 0 = Longword (MC68020) 1 1 = Word 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

C-7

LEA
15 14 13 12 11 10 Address Register 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

CLR
15 14 13 12 11 10 9 8 7 6 5 4 Mode Size field: 00 = byte 01 = word 10 = long 3 2 Register 0

Effective Address

MOVE from CCR (MC6801 0)

15 14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

N EG
15 14 13 12 11 10 9 8 7 6 5 4 Mode Size field: 00 = byte 01 = word 10 = long 3 2 Register 0

Effective Address

MOVE to CCR
15 14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

N OT
15 14 13 12 11 10 9 8 7 6 5 4 Mode Size field: 00 = byte 01 = word 1 0 = long 3 2 Register 0

Effective Address

MOVE to S R
15 14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

ca

N BCD
15 14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

LINK Long (MC68020)

15

1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 1 0 0 0 0 0 0 0 1 High-Order Displacement Low-Order Displacement 14 13 0 12 0 11 10 0 9 8 7 6 5 4 3

14

13

12

11

10

2 Data Register

SWAP

I I I I I I I I I I I I I I
0 0 0 0 0 0 0

15

2 Data Register

BKPT (MC6801 0)
15 0 14 1 13 0 12 0 11 1 10 0 9 0 8 0 7 0

6 1

5 0

4 0

3 1

2 Vector

PEA
5 4 Mode 3 2 Register 0

Effective Address

EXT/EXTB (EXTB-MC68020)

I I I I I I I I
0 0 0 0 0 Type Field: 01 0 = Extend Word 011
=

15

14

13

12

11

10

7 Type 111

Extend Long

Extend Byte Long - (MC68020)

I I I I
0 0 0 5 4 Mode 3

2 Data Register

MOVEM Registers to EA
15 14 13 12 11 10 9 8 7 6 2 Register 0

Effective Address

Sz field: 0 = word transfer

long transfer

C-g

TST
15 14 13 12 11 10 9 8 7 6 5 4 Mode Size field: 00 = byte 01
=

2 Register

Effective Address

word

1 0 = long

TAS
15 14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

I L LEGAL
15 0

14 1

13 0

I-

12 0

11 1

10 0

9 1

8 0

7 1

6 1

5 1

4 1

3 1

2 1

1 0

0 0

M U LS/M U L U Long (MC68020)

15 0 0 14 1

I I
0 DI

13

12 0

11 1

10 1

9 0 0

8 0 0

7 0 ' 0

6 0 0

4 Mode 0

0 Register Dh

Effective Address 0

Type Size

Type Field: 0 = MULU 1 = MULS

Size Field: 0 = Longword Product 1 = Quadword Product

DIVS/DIVU Long (MC68020) DIVU UDIVSL (MC68020)

15 0 0 14 1

I I
0 Dq

13

12 0

11 1

10 1

9 0 0

8 0 0

7 0 0

6 1 0

4 Mode 0

Effective Address

Type Size

Type Field: 0 = DIVU 1 = DIVS

Size Field: 0 = Longword Dividend 1 = Quadword Dividend

o 1

1 1

Register Dr

MOVEM EA to Registers
5 4 Mode Sz field: 0 = word transfer 1 = long transfer 3 2 Register

Effective Address

C-1 0

TRAP
15

14 1

13 0

12 0

11 1

10 1

9 1

7 0

6 1

5 0

4 0

2 Vector

L I N K Word

I I I I 1 I111I I I1I I1I I

15 0 14 1 13 0 12 0 11 1 10 9 8 0 7 6 5 4 3 0 0 0

2 Address Register

U N LK

I I I I I I I I I I I I I I
0 0 0 0 0 0

15

14

13

12

11

10

2 Address Register

MOVE to USP

I I I I 11I I I I 1 I I I
15 0 14 13 0 12 0 11 10 9 1 8 0 7 6 1 5 1 4 0 0

3 0

2 Address Register

M OVE from USP

I I I I I I 1 I I I I I 11I
15 0 14 13 0 12 0 11 10 9 1 8 0 7 6 5 4 3 0 0

2 Address Register

RESET
15 0 14 1

13

12 0

11 1

10 1

9 1

7 0

5 1

4 1

3 0

2 0

1 0

0 0

NOP
15 0 14 1 13 0 12 0 11 1

10 1

9 1

8 0

7 0

5 1

4 1

3 0

2 0

1 0

0 1

C-1 1

STOP
15 0 14 1 13 0 12 0

11 1

10 1

9 1

8 0

7 0

5 1

4 1

3 0

2 0

0 1 0

RTE
15 0

14 1

13 0

12 0

11 1

10 1

9 1

8 0

7 0

5 1

4 1

3 0

2 0

0 1

RTD (MC6801 0)

I
RTS

15 0

14 1

13 0

12 0

11 1

10 1

9 1

8 0

7 0

6 1

5 1

4 1

3 0

2 1

0 0

15 0

14 1

13 0

12 0

11 1

10

8 0

3 0

1 0

TRAPV
15 0

14 1

13 0

12

11

10 1

7 0

6 1

4 1

3 0

0 0

RTR
15 0

14 1

13 0

12 0

11 1

10 1

9 1

8 0

7 0

5 1

4 1

3 0

2 1

0 1

MOVEC (MC6801 0)

dr field: 0 = control register to general register 1 = general reg ister to control register Control Register field: $000 = SFC $001 = DFC $002 = CACR (MC68020) $8oo = USP $801 = VBR $802 = CAAR $803 = MSP $804 = ISP

(MC68020) (MC68020) (MC68020)

C-1 2

JSR
15 14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

JMP
15 14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

ADDQ
15 14 13 12 11 10 Data 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

Data field: Three bits of immediate data, 0, 17 representing a range of 8, 1 to 7 respectively. Size field: 00 = byte 01 = word 1 0 = long

See
15 14 13 12 11 10 9 8 7 5 4 Mode 3 2 Register 0

Condition

Effective Address

OSee

I I I I
0 0

15

14

13

12

11

10

Condition

I I I I I I
0 0 7 6 5 4 3

2 Data Register

TRAPee (MC68020)

15 0

14

13 0

12

11

10

2 Mode

Condition Operand

Mode Field: 010 = Word Operand 0 1 1 = Longword Operand 1 00 = No Operand

C-1 3

SUBQ
11 10 Data 9 5 4 Mode 3 2 Register

Effective Address

Data field: Three bits of Immediate data, 0, 1-7 representing a range of 8, 1 to 7 respectively. Size field: 00 = byte 01 = word 1 0 = long

Bee
15

14

13

12

11

10

Condition

1 6-Blt Displacement If 8-Blt Displacement = $00 32-Bit Displacement if 8-Blt Dlplacement = $FF

8-Blt Displacement

B RA
15

14 1

13 1

12 0

11

1 6-Bit Displacement if 8-Bit Displacement = $00 32-Bit Displacement If 8-Blt Displacement = $FF

10 0

8 0

8-Blt Displacement

BSR
15

14 1

13 1

12 o

11 o

10

1 6-Bit Displacement if 8-Bit Displacement = $00 32-Bit Displacement if 8-Bit Displacement = $FF

8-Bit Displacement

MOVEQ
15 14 13

12

11

10 Data Register

4 Data

Data field: Data is sign extended to a long operand and all 32 bits are transferred to the data register.

OR
11 10 Data Register Op-M ode field : Byte 000 1 00
Word 001 101 Long 010 110

7 Op-Mode

4 Mode

2 Register

Effective Address

Operation ea v Dn - < Dn > D n v ea - < ea >

C-1 4

DIVUlDIVS Word
14 12 11 10 Data Register Type field: 0 = DIVU 1
=

4 Mode

2 Register

Effective Address

DIVS

SBCD
15 14 13 12 11 10 Register * RIM field: 0 = data register to data register 1 = memory to memory * If RIM = 0, specifies a data register If RIM = 1 , specifies an address register for the predecrement addressing mode. 9 8 7 6 5 4 3 2 Source Register* 0

Destination

PACK (MC68020)
15 14 13 12 11 10 Register* 1 6-9it Extension: Adjustment RIM field: 0 = data reg ister to data register 1 = memory to memory * If RIM = 0, specifies a data reg ister If RIM = 1 , specifies an address register for the predecrement addressing mode. 9 8 7 6 5 4 3 2 Source Register* o

Destination

U N PK (MC68020)
15 14 13 12 11 10 Register* RIM field: 0 = data register to data register 1 = memory to memory * If RIM = 0, specifies a data register If RIM = 1 , specifies an address register for the predecrement addressing mode. 9 4 3 2 Source Register*

Destination

SUB
15 14 13 12 11 10 Data Register Op-Mode field: Byte 000 100
Word

7 OpMode

4 Mode

2 Register

Effective Address

Long

Operation

001 1 01

010 1 10

Dn - ea - < Dn > ea - Dn - < ea >

C-1 5

SUBA
15 14 13 12 11 10 Data Register Op-Mode field:
Word 011

7 Op-Mode

4 Mode

2 Register

Effective Address

Long 111

Operation An - ea - < A n >

SUBX
15 14 13 12 11 10 Register* Size field: 00 = byte 01 = word 1 0 = long RIM field: 0 = data register to data register 1 = memory to memory * If RIM = 0, specifies a data register If RIM = 1 , specifies an address register for the predecrement addressing mode_ 9 8 7 6 5 4 3 2 Source Register" 0

Destination

CMP
11 10 Data Register Op-Mode field: Byte 000
Word 001

7 Op-Mode

4 Mode

2 Register

Effective Address

Long 010

Operation Dn - ea

CMPA
11 10 Data Register Op-Mode field:
Word 011

7 Op-Mode

4 Mode

2 Register

Effective Address

Long 111

Operation An - ea

EO R
15 14 13 12 11 10 Data Register Op-Mode field: Byte 1 00
Word 1 01

7 Op-Mode

4 Mode

2 Register

Effective Address

Long 1 10

Operation ea e Dn - < ea >

C-1 6

CMPM
15 14 13 12 11 10 Register Size field: 00 = byte 01 = word 10 = long 9 8 7 6 5 4 3 2 Source Register 0

Destination

AND
11 10 Data Register OpMode field: Byte 000 1 00
Wo rd 001 1 01

7 OpMode

4 Mode

2 Register

Effective Address

Long 010 1 10

Operation ea A D n - < On > D n A ea - < ea >

M U L U Word M U LS Word
15 14 13 12 11 10 Data Register Type field: 0 = MULU 1 = MULS 9 8 7 6 5 4 Mode 3 2 Register 0 Effective Address

ABCD
15 14 13 12 11 10 Register* RIM field: 0 = data register to data register 1 = memory to memory * If RIM = 0, specifies a data register If RIM = 1 , specifies an address register for the predecrement addressing mode. 9 8 7 6 5 4 3 2 Source Register' 0

Destination

EXG Data Registers

15 14 13 12 11 10 Data Register 9 8 7 6 5 4 3 2 Data Register 0

EXG Address Registers

15 14 13 12 11 10 Address Register 9 8 7 6 5 4 3 2 Address Register 0

C1 7

EXG Data Register and Address Register

15 14 13 12 11 10 Data Register 9 7 4 3 2 Address Register 0

ADD
15 14 13 12 11 10 Data Register Op-Mode field: Byte 000 1 00
Word 001 101

7 Op-Mode

4 Mode

2 Register

Effective Address

Long 010 110

Operation ea + D n - < Dn > Dn + ea - < ea >

ADDA
15 14 13 12 11 10 Address Register Op-Mode field:
Word 01 1

7 Op-Mode

4 Mode

2 Register

Effective Address

Long 111

Operation ea + An - < An >

ADDX
15 14 13 12 11 10 9 8 7 6 5 4 3 2 Source Register' o

Destination Register* Size field: 00 = byte 01 = word 1 0 = long RIM field: 0 = data register to data register 1 = memory to memory * If RIM = 0, specifies a data register If RIM = 1 , specifies an address register for the predecrement addressing mode.

S H I FT/ROTATE - Register
15 14 13 12 11 10 Countl Register Count/Register field: If i/r field = 0, specifies shift count If i/r field = 1 , specifies a data register that con tains the shift count dr field: 0 = right 1 = left Size field: 00 = byte 01 = word 1 0 = long i/r field: 0 = immediate shift count 1 = register shift count Type field: 00 = arithmetic shift 1 0 = rotate with extend 01 = logical shift 1 1 = rotate 9 8 7 6 5 4 3 2 Data Register o

C1 8

S H I FT/ROTATE

Memory
14 13 12 11 10 9 8 7 6 5 4 Mode 3 2 Register 11 = rotate

15

Effective Address

Type field: 00 = arithmetic shift dr field: 0 = right 1 = left

01 = logical shift

10 = rotate with extend

Bit Field (MC68020)

15 1 0 14 1

Register

I I
1

13

12 0

11 1 Do

10

9 Type

Offset

I I
1

6 1

4 Mode

o
Register

Effective Addres Ow

Type Field: 000 = BFTST 1 00 = BFCLR 001 = BFEXTU 1 01 = BFFFO 010 = BFCHG 1 1 0 = BFSET 0 1 1 = BFEXTS 1 1 1 = BFINS Register Field Is 000 for BFTST, BFCHG, BFCLR, and BFSET Do field: 0 = Offset Is Immediate 1 = Offset Is Data Register Ow field: O = Wldth is Immediate 1 = Width Is Data Register

Width

C- 1 9

/'

COPROCESSOR I N STRUCTIONS cpG E N (MC68020)

15

14

13

12

11

10
Cp-Id

Coprocessor Dependent Command Word

I I I
o

7 0

6 5 4 3 2 o Effective Address II---:----r---:-::---:-:0 Mode Register I ----:--I

cpScc (MC68020)

15 1 0
cpDBcc (MC68020)

14 1 0

13 1 0

12 1 0

11

10
Cp-Id

0 1 0 1 0

8 0 0

7 0 0

6 1 0

4
Mode

3
1

2
Register

Effective Address Coprocessor Condition

15 14 13 12 1 1 1 0 1 1 1 1 1 1 1 1 Cp-Id 0 I 0 I 0 I 0 I 0 I 0 I
cpTRAPcc (MC68020)

8 7 6 5 4 3 2 0 1 0 1 1 I o I 0 I 1 I Register 1 Coprocessor Condition I 0 I 0 I 0 I

Displacement

15 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2 Cp-Id 1 1 1 1 1 1 1 1 Mode 1 0 1 0 1 1 1 1 I 1 I 1 I Coprocessor Condition 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 10 1 0 1

Mode field:

01 0

Word Operand

01 1

Operand

Longword Operand

1 00

No Displacement

cpBcc (MC68020)

15

14 0

13
=

12

11

10
Cp-Id

9 Displacement
=

Coprocessor Condition

Size field:

Word Displacement

Longword Displacement

C20

cpSAVE (MC68020)
15 14 13 12 11 10 Cp-Id 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

cpR ESTO RE (MC68020)

15 14 13 12 11 10 Cp-Id 9 8 7 6 5 4 Mode 3 2 Register 0

Effective Address

C-2 1

COPROCESSO R PRIM ITIVES (MC68020) BUSY

15 1

I PC I

14

13 1

12 o

11 0

10 1

9 o

8 o

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

T RANSFER M U LTIPLE COPROCESSOR REG ISTERS

15 CA

I PC I

14

13 dr

12 0

11 0

10 o

9 o

8 1

Length

TRANSFER STATUS REGISTER A N D SCAN PC

I CA I PC I
SUPERVISOR CH ECK

15

14

13 dr

12 0

11 0

10 0

9 1

I SP I

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

15 1

I PC I

14

13 o

12 0

11 0

10 1

9 o

8 o

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 o

TAKE ADDRESS A N D TRANSFER DATA

I CA I PC I

15

14

13 dr

12 0

11

10 1

8 1

Length

TRANSFER M U LTIPLE MAI N PROCESSOR REG ISTERS

I CA I

15

14 PC

13 dr

12 0

11 0

10 1

9 1

8 0

7 0

6 0

4 0

3 0

2 0

1 0

0 0

TRANSFER O PERATIO N WORD

I CA I PC I
N U LL

15

14

13 0

12 0

11 0

10 1

9 1

8 1

7 0

5 0

4 0

3 0

2 0

1 0

0 0

I CA I PC I

15

14

13 0

12 0

11 1

10 0

9 0

8 IA

7 0

5 0

4 0

3 0

2 0

I PF I TF I

C-22

EVALUATE AND TRANSFER EFFECTIVE ADDRESS

I CA I PC I

15

14

13 0

12 0

11 1

10 0

9 1

7 0

6 0

5 0

4 0

3 0

2 0

T RANSFER S I N G L E MAIN P ROCESSOR REGISTER

I CA I PC I

15

14

13 dr

12 0

11 1

10 1

9 0

8 0

7 0

6 0

5 0

4 0

l OlA I

2 Register

TRANSFER MAIN P ROCESSO R CONTROL REG ISTER

I CA I PC I

15

14

13 dr

12 0

11 1

10 1

9 0

8 1

7 0

5 0

4 0

3 0

2 0

1 0

0 0

T RANSFER TO/FROM TOP OF STACK

I CA I PC I DR I

15

14

13

12 1

11 1

10 1

9 0

4 Length

TRANSFER FROM I N STRUCTION STREAM

I A I PC I
C

15

14

13 0

12

11 1

10 1

9 1

8 1

Length

EVALUATE EFFECTIVE ADDRESS AND TRANSFER DATA

I CA I

15

14 PC

13 dr

12 1

11 0

10

9 Valid

EA

Length

TAKE P REI NSTRUCTION EXC EPTION

15 0

14 PC

13 0

12 1

11 1

10 1

9 0

o
8

Vector Number

TAKE M I DINSTRUCTION EXCEPTION

15 0

14 PC

13 0

12 1

11 1

10 1

9 0

8 1

Vector Number

II

C23

TAKE POSTI NSTRUCTIO N EXCEPTIO N

15 0

14
PC

13 0

12 1

11 1

10 1

Vector Number

WRITE TO PREVIOUSLY EVALUATED EFFECTIVE ADDRESS

I CA I

15

14
PC

13 1

12 0

11 0

10 0

Length

C-24

APPENDIX D ADVANCED TOPICS

This appendix provides i nformation on the fol lowing advanced topics: Module Su pport Access Levels Extension Words CAS/CAS2 for Systems Programmers
0.1 MODULE SU PPORT

The M C68020 incl udes su pport for modules with the call module (CA LLM) and return from mod u le (RTM) i nstructions. The CALLM i nstruction references a mod u le descri ptor. This descriptor contains control i nformat ion for entry i nto the cal led modu le. The CALLM in struction creates a mod u l e stack frame and stores the cu rrent mod u l e state i n that frame and loads a new mod u l e state from the referenced descri ptor. The RTM i n struct ion recovers the previous mod u le state from the stack f rame and ret u rn s to the ca l l i ng modu le. The module i nterface fac i l itates finer resolution of access control by external hardware. Although the M C68020 does not i nterpret the access control i nformat ion, it does com m u n i cate with external hardware when the access control is to be changed, and rel ies on the external hardware to verify t hat the changes are legal.
0.1 .1 Module Descriptor

Figure D1 i l l u st rates the format of the mod u l e descriptor. The f i rst long word conta i n s control i nformation u sed d u ri n g the execution o f t h e CALLM i nstruction. The rema i n i n g l ocations conta i n data which may b e loaded i n t o processor reg i sters b y t h e CALLM i n struction. The Opt field specifies how arguments are to be passed to the cal led module; the M C68020 recognizes only the options of 000 and 1 00, all others cause a format except ion. The 000 option i n d i cates that the cal led mod u le expects to f i nd arg u ments from the cal l i ng mod u le o n t h e stack j u st below t h e module stack frame. I n cases w here there i s a change of stack pOinter d u r i n g the cal l , the M C68020 w i l l copy the arguments from the old stack to the new stack. The 1 00 option i nd i cates t hat the cal led module w i l l access the arguments f rom the c a l l i n g module t h rough an i nd i rect pointer in the stack of t he cal l i ng modu le. Hence, t he arguments are not copied, but the M C68020 puts the val ue of the stack poi nter from t he cal l i ng module in t he mod u l e stack frame.

D1

31 Base -+ S04 Opt

28

23 Type

15 Access Level

o
( Reserved, Must be Zero)

Module Entry Word Pointer Module Data Area Pointer

+ S08
+ SOC + S10

Additional User-Defined Information

Figure 01 . Module Descriptor Format The Type field specifies the type of the descri ptor; the M C68020 only recog n izes descrip tors of type $00 and $01 , a l l others cause a format except ion. The $00 type descriptor defi nes a mod u le for which there i s no change in access rig hts, and the cal led mod u l e bui lds i t s stack frame o n t o p o f t h e stack used b y the cal l i ng mod u le. The $01 type descriptor defi nes a mod u l e for which t here may be a change In access rig hts, such a cal led mod u l e may have a separate stack area from that of the cal l i ng mod u le. The access level field i s u sed o n ly with the type $01 descriptor, and is passed to external hardware to change the access control. The mod u le entry word pointer specif ies the entry address of the cal led modu le, The f i rst word at the entry address (see F i g u re D-2) specifies the reg ister to be saved in the module stack frame and t hen loaded with the module descriptor data area poi nter; the f i rst i n struction of the module starts with the next word. The module descriptor data area pointer field conta i n s the address of the cal led mod u l e data area. If t he access change req u i res a change of stack poi nter, the old va lue is saved in the mod u le stack frame, and the new value is taken from t he module descriptor stack pointer field, Any further i nformation in the mod u le descriptor is user def i ned.
14 12 13 Register

Figure 02. Module Entry Word A l l module descriptor types $1 0$1 F are reserved for u ser defi n i t ion and cause a format error exception, This provides the u ser with a means of disab l i ng any module by setti n g a s i n g l e bit i n its descriptor, w it hout loss of any descri ptor i nformation. If the cal led mod u l e does not wish the module data area poi nter to be loaded i nto a reg ister, the mod u le entry word can select reg ister A7, and the l oaded value w i l l be over w ritten with the correct stack poi nter value after the mod u l e stack frame is created and f i l led.

D-2

0.1 .2 Module Stack Frame

Figure D-3 i l l ustrates the format of the module stack frame. Th i s frame is constructed by the CALLM i nstruction, and is removed by the RTM i nstruction. The f i rst and second long words conta i n control i nformat ion passed by the CALLM i nstruction to the RTM i nstruc tion. The module descri ptor poi nter conta i n s the address of the descriptor u sed d u r i n g t h e mod u l e call. A l l other locations contai n i nformat ion to b e restored on return t o the cal l i ng mod u le.
S p ..... 15 0 0 + $08 + SOC + $10 + $14 + $1 8 Arguments (Optional) 12 7
o o

o
Saved Access Level Condition Codes Argument Count

I I

Opt
o

I I

0 0

I I

I I

Type
o o

I I

I I

0 0 (Reservedl

Module Descriptor Pointer Saved Program Counter Saved Module Data Area Pointer Saved S tack Pointer

Figure 03. Module Call Stack Frame The program counter is the saved address of the i nstruction follow i n g the CALLM i n struction. The Opt and Type fields spec ify the argument options and type of module stack frame, and are copied to the frame from the module descriptor by the CALLM i n struction; the RTM i nstruction w i l l cause a format error if the Opt and Type fields do not have recog n izable val ues. The access level is the saved access control i nformation, which i s saved from external hardware by the CALLM i nstruction and restored by the RTM i nstruction. The argument count f ield is set by the CALLM i nstruction, and is u sed by the RTM i nstruction to remove arguments from the stack of the cal l i n g modu le. The contents of the CCR are saved by the CALLM i nstruction and restored by the RTM i n struction. The saved stack poi nter f ield conta i n s the value of the stack pOi nter when the CALLM i nstruction started execution, and t hat value is restored by RTM. The saved mod u l e data poi nter field contai n s the saved value of t he mod u l e data area pointer reg i ster from the c a l l i n g module.
0.2 ACCESS LEV E LS

The M C68020 module mechanism su pports a finer level of access control beyond the d i st i nction between u ser and su pervisor modes. The mod u l e mechanism al lows a mod u l e with l i m ited access rights to call a module with g reater access rights. With the help of external hardware, the processor can verify that an i ncrease i n access rig hts i s allowable, or c a n detect attempts b y a mod u l e t o gain access rights to which it i s not entit led. D-3

Type $01 mod u l e descriptors and module stack frames i nd i cate a request to change ac cess levels. W h i l e proces s i n g a type $01 descr i ptor or frame, the CALLM and RTM i n structions com m u n i cate w i t h external access control hardware via accesses i n the CPU space. For these accesses, address bits [ 1 9: 1 6] eq ual 0001 . F i g u re 0-4 shows the address map for t hese CPU space accesses. If the processor receives a bus error on any of these CPU space accesses d u r i n g the execution of a CALLM or RTM i nstruction, the processor w i l l take a format error except ion.
$00 $04 $08 31 CAL STATUS IAL DAL Function Function Function Function Function Function Function Function 23 (Unused, Reserved) (Unused, Reserved) (Unused, Reserved) (Unused, Reserved) Code 0 Descriptor Address Code 1 Descriptor Address ( User Data) Code 2 Descriptor Address (User Program) Code 3 Descriptor Address Code 4 Descriptor Address ( Supervisor Data) Code 5 Descriptor Address ( Supervisor Program) Code 6 Descriptor Address Code 7 Descriptor Address (CPU Space)
o

soc

$40 $44 $48 $4C $50 $54 $58 $5C

Figure 0-4_ Access Level Control Bus Registers The cu rrent access level reg i ster (CAL) conta i n s the access level rights of the cu rrently exec u t i n g modu le. The i ncrease access level reg i ster (IAL) i s t he reg i ster through which the processor requests i ncreased access rig hts. The decrease access level reg i ster (OAL) is the reg i ster t h rough which the processor req uests decreased access rights. The for mats of these t h ree reg i sters are u ndef i ned to the main processor, but the main pro cessor assumes that i nformat ion read f rom t he mod u l e descri ptor stack frame, or the cu rrent access l evel reg i ster can be mea n i ngfu l ly w ritten to the i ncrease access level reg i ster or the decrease access level reg i ster. The access status reg ister a l l ows t he pro cessor to query t he external hardware as to the legal ity of i ntended access level transi tions. Table 0-1 l ists the val id values of the access status reg i ster. Table 0-1 _ Access Status Register Codes
Value Validity Processor Action

00 01 02-03 04-07 Other

Invalid Valid Valid Valid Undefined

Format Error No Change in Access Rights Change Access Rights with no Change of Stack Pointer Change Access Rights and Change Stack Pointer Undefined !Take Format Error Exception)

The processor u ses the descri ptor address reg i sters during the CALLM i nstruction to com m u n i cate the add ress of the type $01 descri ptor. This al lows external hardware to verify t hat the add ress i s a va l i d address for a type $01 descriptor. This prevents a module from creati n g a type $01 descriptor to s u rreptitiously i ncrease its access rights.

0-4

0.2.1 Module Call The CALLM i nstruct ion i s u sed to make the mod u l e cal l . For the type $00 mod u l e descrip tor, the processor s i mply creates and f i l l s the mod u l e stack frame at the top of the act ive system stack. The cond ition codes of the cal l i ng mod u l e are saved in the CCR field of the frame. If Opt is equal to 000 (argu ments passed on the stack) in the mod u l e descri ptor, the M C68020 does not save the stack pointer or l oad a new stack poi nter value. The pro cessor u ses the mod u l e entry word to save and l oad the mod u l e data area pointer reg i ster, and then beg i n s execution of the called mod u le. For the type $01 mod u le descriptor the processor m u st f i rst obtain the cu rrent access level from external hardware. It also verifies that the ca l l i ng mod u l e has the right to read f rom the area poi nted to by the c u rrent va l u e of the stack pointer by read i n g from that ad dress. It then passes the descriptor address and i ncrease access level to external hard ware for val idation, and then reads the access status. If external hardware determi nes that the change in access rights should not be g ranted, the access status i s zero, and the processor takes a format e rror except ion. N o visible processor reg i sters are changed, nor should the cu rrent access level enforced by external hardware be changed. If external hardware determ i nes that a change should be g ranted, the external hardware changes its access level , and the processor proceeds. If the access status register i nd icates that a change i n the stack poi nter is req u i red, the stack poi nter is saved i nternal ly, a new va l u e i s loaded from the mod u l e descri ptor, and arguments are copied from the cal l i ng stack to the new stack. F i na l ly, the mod u le stack frame is created and f i l led on the top of the cu rrent stack. The cond ition codes of the cal l i ng mod u l e are saved i n t he CCR field of the frame. Execution of the cal l ed mod u l e then beg i n s as with a type $00 descri ptor. 0.2_2 Module Return The RTM i nstruct ion is u sed to ret u rn from a mod u le. For the type $00 mod u l e stack f rame, the processor reloads the cond ition codes, the program cou nter, and the mod u l e data area pOinter reg ister from the frame. T h e frame i s removed from t h e t o p o f t h e stack, the arg u ment count is added to the stack pointer, and execution returns to the cal l i ng mod u le. For the type $01 mod u l e stack frame, the processor reads the access level , condition codes, program cou nter, saved mod u l e data area poi nter, and saved stack pointer from the mod u l e stack f rame. The access level is w ritten to the decrease access level reg i ster for val idation by external hardware, the processor t hen reads the access status to check the val idation. If the external hardware determi nes t hat the change in access rig hts should not be g ranted, the access status i s zero, and the processor takes a format error exception. N o visible processor reg i sters are changed, nor should the cu rrent access level which is enforced by external hardware be changed. If the external hardware deter m i nes that the change in access rig hts should be g ranted, the external hardware changes its access leve l , the values read from the mod u le stack frame are loaded i nto the correspo n d i ng processor registers, t he argument count i s added to the new stack pointer val ue, and execution ret u rn s to the cal l i ng modu le. If the cal led mod u l e does not wish the saved mod u l e data pointer to be loaded into a reg i ster, the RTM i nstruction word can select reg i ster A7, and the loaded val u e w i l l be overwritten w i t h the correct stack pointer val u e after the mod u l e stack frame i s dea l l ocated. 0-5

D.3 EXTENSION WO RDS I f it is desi red to w rite programs t hat can be transported from one member of the M68000 processor Fam i ly to another, certai n restrictions may have to be observed. F i rst of a l l , each new member o f t h e Fami ly i s always upward object code compatible with earlier members, with some extensions to the architect u re. Th us, t ransport i n g appl i cations code from an early mach i ne to a new one i s stra i g htforward, s i nce no changes are necessary. Secondly, a l l processors f u l l y decode a l l 65,536 possi ble operat ion words and i n itiate except ion proces s i n g if an opcode i s encou ntered that i s not i m plemented by a g iven processor. Thus, if code written for a new member of the Family is executed on an earlier machi ne, new i nstructions for t he new processor w i l l be 'trapped out' by the earlier processor and can be emu lated with run-time su pport software on the o lder system. H owever, only the f i rst word for an i nstruct ion i s checked for legality; any exten sion words i n d i cated necessary by the f i rst word are assu med to be val id and are not checked. The extension words are of concern when u s i n g certain addressing modes of the M C68020. Spec i f ical ly, the address reg i ster memory i n d i rect with i ndex, and program counter relat ive i n d i rect with i ndex addressing modes are extensions of the correspond ing addressi n g modes of the M C68000, MC68008, MC6801 0, and MC680 1 2. The extension words of these effective addressi n g modes are show n i n F i g u re 0-5. As can be seen from this f i g u re, the M C68020 address reg i ster i n d i rect with i ndex, with a scal i n g m u lt i p l ier of one (Scale = 00) encod i ng, is eq u ivalent to the M C68000, et. aI., encod i n g so that u pward compat i bi l ity is mai ntai ned. H owever, if any other encod i n g for the MC68020 is u sed, downward com pat i b i l ity of the i nstruction is lost and special precautions m ust be taken s i nce these extension words are not checked for val i d ity on the older processors. The following two examples i l l ustrate why these precautions must be observed to i ns u re downward compat i b i l ity. Example 1 . M C68020 Address Register Indirect with I ndex versus M68000 Address Register Indirect with Index
Assembly Language Source Code Object Code
M C68000 Program

MC66020 Program

MOVE.L 2230 08XX

OFFSET(AO , 00. L), 0 1

MOVE.L 2230 OCXX

(OFFSET,AO,OO.L * 4),01

As can be seen from the object code, only one bit (bit 1 0 of the extension word) is d if ferent i n the two i nstructi ons, yet the sou rce effective address values are q u i te d i fferent. I f the M C68020 code were executed on an M C68000, the processor would i nterpret the code as though it were the M C68000 code and the w rong data would be fetched, but no exception wou ld occur. Example 2. MC68020 Address Register Indirect with I ndex/Indirect versus MC68000 Address Register Indirect with Index
Assembly Language Source Code Object Code
M C68000 Program MC68020 Program

MOVE.L 3230 08XX

OFFSET(AO , 00.L), 0 1

MOVE.L 3230 0021 XXXX

([OFFSET,AO,OO. L * 4]), 0 1

06

A comparison of the object code i n t h i s example shows a more volat i l e situation that w i l l occur i f t he M C68020 code i s executed on a n M C68000. I n t h i s case, t he M C68000 w i l l ig nore bits 8-1 0 of the f i rst extension word and i n terpret the i nstruction as " M OVE.L $21 (AO,DO.L), D 1 " , and t hen erroneously u se the second extension word as the f i rst word of the next i nstruction. Th us, the processor w i l l get 'out of sync' with the i ntended i n struction stream and u n pred i ctable res u lts w i l l occu r. Eventual ly, t he processor may en counter an i l legal i nstruction and t rap to the operati n g system, but i ncorrect execu tion may have occu rred, with no i nd icat ion that the M C68020 extended addressing mode was at fau lt. I f it i s des i red to protect against the above s ituations, t he u ser m i g ht precede any pro g ram that u t i l izes the advanced features of the M C68020 with the "TRAPF" i nstruction. This i nstruction performs no operation on the M C68020, but w i l l cause an i l l egal i nstruc tion except ion on the MC68000, M C68008, MC6801 0, or MC680 1 2; thus prevent i ng the pro g ram from executing on the o lder processors.
MC68020, Brief Format

I D/A I
15 D/A

15

14

13 12 Register

I W/L I

11

10 9 Scale

8 0

4 3 Displacement

MC68020, Full Format

14

13 12 Register

I W/ L I

11

10 9 8 7 5 4 6 Scale 1 BS 1 IS 1 BD S IZE Base Displacement 10, 1 , or 2 Wordsl Outer Displacement 10, 1, or 2 Wordsl

10

2 IllS

Figure 05. Indexed/Indirect Addressing Mode Extension Words

The fields used in Figure D-5 are as follows:

Mode Addressing Mode Mode Addressing Mode

Register D/A W/L Scale

BS

Index Register Number Index Register Type: 0 = Dn 1 = An Word/Long Word Index Size: 0= Sign Extended Word 1 = Long Word Scale Factor: 00 = 1 01 = 2 10=4 11 =8 Base Suppress: 0= Base Register Added 1 = Base Register Suppressed

IS BD SIZE

IllS

Index Suppress: 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand Base Displacement Size: 00 = Reserved 01 Null Displacement 1 0 = Word Displacement 1 1 = Long Displacement Index/ lndirect Selection: Indirect and I ndexing Operand Determined in Conjunction with Bit 6, Index Suppress
=

D-7

IS

Index/ Indirect

Operation

0 0 0 0 0 0 0
0

000 001 010 01 1 1 00 101 1 10 000 001 010 01 1 100- 1 1 1

111

1 1 1
1

No Memory Indication Indirect After Indexing with Null Displacement I ndirect After I ndexing with Word Displacement Indirect After Indexing with L ong Displacement Reserved Indirect Before Indexing with Null Displacement Indirect Before Indexing with Word Displacement Indirect Before Indexing with Long Displacement No Memory Indication Memory Indirect with Null Displacement Memory Indirect with Word Displacement Memory Indirect with Long Displacement Reserved

0.4 CAS/CAS2 FO R SYSTEMS P ROG RA M M ERS

The CAS i nstruction al lows sec u re u pdating of system cou nters, history i nformation, and g loba l ly shared poi nters. Secu rity is provided in single processor systems, multitasking environments, and i n m u ltiprocessor environments. In a s i n g le processor system, the non-i nterru ptable u pdate operat ion provides security i n an i nterru pt driven environment; w h i l e i n a m u ltiprocessor environment, the i ndivisible bus cyc le operation provides the sec u rity mechanism. For exam ple, suppose l ocation SYS_CNTR contains a count of the n u m ber of ti mes a particular operat ion has been done, and t hat this operation may be done by any process or any processor in the system. Then the following seq uence guarantees t hat SYS_CNTR is correctly i ncremented.
M OVE.w M OVE.w AOOQ.w CAS.w BNE SYS_C NTR, OO 00, 01 #1,01 00, 0 1 ,SYS_CNTR I N C_LOOP get the old value of the counter make a copy of it and i ncrement it i f counter value is sti l l the same, u pdate it i f not, try again

The CAS and CAS2 i n st ructions together a l l ow safe operat ions i n manipu lation of system q ueues. I f a queue can be managed last-i n-fi rst-out, only a Single l ocat ion H EAD need be contro l led. I f the queue is em pty, H EA D contains the N U LL poi nter (0). The fol lowi n g seq uence i l l u st rates the code for i n sertion and deletion from such a queue. Figures D-6 and D-7 i l l ustrate the i nsertion and deletion, respectively.

D-8

S I N SERT SI LOOP MOVE.L MOVE.L M OVE.L CAS.L BNE H EA D , DO DO,(N EXT, A 1 ) A1,D1 DO, D 1 , H EA D S I LOOP

Before Inserting a n Element:

allocate new entry, addr i n A 1 move head pOinter value to DO establish fwd l i n k in new entry move new entry ptr value to 01 if we sti l l point to top of stack, u pdate the head ptr if not, try again

Entry
+ Next

New

Head

J1 FV
Entry
'_ _ --'----'

'"

Entry

+ Next

Next

After Inserting an Element:

Entry
+ Next

Entry
Next

Entry
+ Next

Figure 06. Linked List Insertion

SDELETE LEA MOVE. L TST.L B EQ LEA MOVE.L CAS2 . L BNE SDEM PTY
Before Deleting a n Element:

S D LOOP

H EA D,AO (AO),DO DO SDEM PTY (N EXT, DO),A1 (A1),D1 00: 0 1 , 0 1 : 0 1 ,(AO):(A 1 ) S D LOOP

load add r of head ptr i nto AO move value of head ptr i nto DO check for n u l l head ptr if em pty, not h i n g to delete load addr of fwd l i n k i nto A1 put fwd l i n k value i n 0 1 i f sti l l p o i n t to entry to b e deleted, then u pdate head and fwd ptrs i f not, try again successful deletion, addr of deleted entry in DO (may be n U l l)

Head

J1
Entry Entry
+ Next
+

Entry
+ Next

Next

'-------'----'

'-------'----'

After Deleting an Element:

Entry
+ Next

Entry
+ Next

Entry

Next

Head

Figure 07. Linked List Deletion

--

0-9

The CAS2 i nstruct ion may be u sed to maintain a f i rst-in-fi rst-out doubly l i nked l i st safely. Such a l i n ked l i st needs two control led l ocations, LIST_PUT and LIST_G ET, which point to the last element i nserted in t he l i st and the next to be removed, respect ively. I f the l i st is empty, both poi nters are N U LL (0). The follow i n g seq uence i l l ustrates the i nsertion and deletion operat ions in such a l i n ked l i st. F i g u res 0-8 and 0-9 i l l ustrate the i nsertion and delet ion from a doubly l i n ked l i st.
DI NSERT LEA LEA MOVE. L MOVE. L TST. L B EQ MOVE. L CLR.L MOVE.L LEA CAS2.L BNE B RA MOVE.L MOVE.L CAS2.L BNE O I OO N E
Before Inserting New Entry:

O I LOOP

LIST_PUT,AO LlST_G ET,A1 A2,02 (AO),OO DO O I E M PTY 00,(N EXT,A2) 01 0 1 ,(LAST,A2) (LAST,00),A1 00: 0 1 , 02: 00,(AO):(A 1 ) OI LOOP DlOONE 00,(N EXT,A2) 00,(LAST,A2) 00:00,02: 02,(AO):(A 1 ) O I LOOP

(al locate new l ist entry, load addr i nto A2) load add r of head ptr i nto AO load addr of tai l ptr i n to A1 load new e ntry ptr i nto 02 load ptr to head entry i nto DO is head ptr n u l l (0 entries i n l ist)? if so, we need only to establ ish ptrs put head ptr i nto fwd ptr of new entry put n u l l ptr value i n 01 put n u l l ptr i n bkwd ptr of new entry load bkwd ptr of old head entry i nto A 1 if we sti l l point to old head entry, u pdate poi nters if not, try again put null ptr i n fwd ptr of new entry put n u l l ptr in bkwd ptr of new entry if we sti l l have no entries, set both poi nters to this entry if not, try agai n successfu l list entry i nsertion

O I E M PTY

Entry

Entry

Entry Last Next

Entry

Figure 0-8_ Doubly Linked List Insertion

0-1 0

O O ELETE LEA LEA MOVE. L B EQ MOVE.L B EQ LEA CLR.L CAS2 . L BNE BRA CAS2. L BNE OOOONE LIST_PUT,AO LlST_G ET,A1 (A1 ), 0 1 OOOO N E (LAST, 0 1 ) , 02 OOEM PTY (N EXT,02),A2 DO 0 1 : 0 1 , 02: 00,(A 1 ):(A2) OOLOOP OOOO N E 0 1 : 0 1 , 02: 02:(A 1 ):(AO) OOLOOP get addr of head ptr i n AO get addr of tai l ptr in A1 move tai l p t r i nto 0 1 i f n o l ist, q u i t put bkwd ptr i n 02 if only one element, u pdate ptrs put addr of fwd ptr in A2 put n u l l ptr val ue in DO if both ptrs sti l l point to this entry, u pdate them if not, try agai n if sti l l f i rst entry, set head and tial ptrs to n u l l if not, try agai n successf u l entry deletion, add r o f deleted entry i n 0 1 (may b e n U l l)

O O LOOP

OOEM PTY

Before Deleting Entry:

Entry

After Deleting Entry:

Entry

Deleted Entry

Figure D9.Doubly Linked List Deletion D.5 A P ROG RAM M E R'S V I EW OF T H E MC68020 ADDRESSING MODES Extensions to the i ndexed addressi n g modes, i nc l u d i n g i nd i rection along with the s u p port of fu l l 32bit d isplacements, provide the M C68020 programmer with addressing capabil ity new to the M68000 Fam i ly. The pu rpose of the following parag raphs i s to i nd icate the new techniq ues available and to sum marize them from a programmer's poi n t of view. These tec h n iq ues w i l l be cal led " generic" addressi n g modes s i nce they may or may not relate d i rect ly to a u n ique effec t ive address mode as defi ned by the M C68020 arch i tecture. D.5.1 New Addressing Capabilities The s u ppression of the base address reg i ster in the M C68020 i ndexed addressing mode al lows the u se of any i ndex reg ister to be used in place of the base reg ister. Since any of

II

01 1

the data reg i sters can be i ndex reg isters, the new forms (On) and (disp,Dn) are obta i ned. These could be cal led Data Regi ster I nd i rect but its probably better to t h i n k in terms of (Rn) and (d isp,Rn) as j u st Reg i ster I nd i rect where any data or address reg ister is al lowed. Remember that w henever an i ndex reg ister appears (X n), its s ize may be spec ified to be a s i g n-extended word or a long word. Si nce d i splacements may be a f u l l 32 bits, they may represent absol ute addresses or the res u l t of express ions which conta i n absol ute addresses. This allows the general Register I n d i rect form above to become (addr, Rn), and with the base not suppressed we get (addr,A n , R n). Thus, an absol ute address may be d i rect ly i ndexed by one or two reg i sters. Scal i n g provides for an optional shift i n g of an i ndex reg ister to the left by zero, one, two, or t h ree bits before bei n g u sed in the effective address calculation. This is eq u i valent to m u l t i plying the reg i ster by one, two, fou r, or eight, which al lows d i rect su bscript i n g i nto an array of components of t hat size by an arithmet i c value residing in any of the 16 i ndex able reg i sters. Sca l i n g , combi ned with the appropriate new modes derived above, al lows new modes. Arrayed structu res may be add ressed absolutely and then subscri pted, Le., (addr, R n * scale). Optional ly, an address reg ister may contain a dynamic disp lacement value s i nce it may be i nc l uded in the address calcu lation (addr,An, R n * scale). Other varia tions can be generated by assu m i n g an add ress reg ister points d i rectly to the arrayed item with (An, R n * scale) or that an address reg ister with disp lacement (Le., a base ad d ress) points to the arrayed item (di sp,A n , R n * scale). Yet another featu re of the i ndex i n g mode on the MC68020 is memory i n d i rect ion. This al l ows a long word pointer i n memory to be fetched and u sed to point to the data operand. Any of the modes mentioned earlier can be used to address t he memory poi nter. I n add ition, when both reg i sters are s u ppressed, the displacement acts as an ab sol ute address. Hence, absolute address i n g can be used to access the memory pointer as wel l . O nce t he memory pointer i s fetched it c a n optiona l ly have yet another constant displace ment added to it before it is u sed to access the f i nal data operand. This second d i splace ment is cal l ed the Outer Displacement. Thus the memory poi nter may itself be t reated as a base address. When memory i nd i rection is bei n g u sed, t he i ndex reg i ster may be u t i l ized in one of three ways. It may be s u ppressed, used to access the memory pointer (before the i n d i rect ion, or pre i n d i rect), or used to access t he final data operand (after the i n d i rect ion, or post i nd i rect). This last case causes the i ndex reg i ster to be added to the fetched poi nter from memory (and optionally the Outer Disp lacement if present). Si nce i ndex reg isters on the M C68020 can be scaled, subscript i n g also may be employed on the data operand that the fetched memory poi nter accesses. H owever, w hen the i ndex reg i ster is used to access the final data operand it is not available to address t he memory poi nter. That is, i ndexi n g i s not al lowed both before a n d after i n d i rection; rather it is o n l y a l l owed before o r after i n d i rect ion. 0.5_2 A General Addressing Mode Summary Some of the generic address i n g modes mentioned in the previous paragraphs do not ac tually ex i st as d i sti nct basic M C68020 effective address modes s i nce t hey either rely on a

0-1 2

spec ific com bi nation of opt ions i n the i ndex i n g mode, or may be derived from two d i f ferent nat ive M C68020 modes. For example, the generic mode cal led Register I nd i rect (Rn) wou l d assemble to the basi c mode Address Reg i ster I nd i rect if the reg ister was an address reg i ster, or to the Reg i ster I n d i rect with I ndex with address reg i ster su ppression if R n was a data reg i ster. A nother case i s (di sp,An) which depends on the s ize of the d i s placement. I f the disp lacement fits w i t h i n 1 6 bits, then the nat ive Address Reg i ster I n d i rect with Displacement (d 1 6 ,An) w i l l be used, otherw i se the Address Reg i ster I nd i rect with I ndex w i l l be u sed s i nce o n ly it can su pport a larger d i splacement. On t he other hand, two or more of the modes mentioned may assemble i nto the very same nat ive effective add ress option. For i nstance, an absolute address with a reg i ster i ndex (addr,Rn) and a base address with a large displacement (d isp, R n) are both two ways of looki n g at the same t h i n g - a reg i ster with a 32-bit d isplacement. They both assem ble i nto the very same object code. An assembler makes the necessary disti nct ions and chooses which basi c address i n g mode t o use; always p i c k i n g the more effi c ient o n e if more t h a n o n e is applicable. Nor mal ly, the prog rammer need not be concerned about t hese dec i sions, so it is usef u l to s u mmarize the addressing modes avai lable to a prog rammer w i t hout regard to t he nat ive M C68020 effective add ressing mode actually i m p lemented on c h i p. The ' generic' address i n g modes d iscussed be low are defi ned i n normal progra m m i n g terms which s h o u l d n o t b e d i rect ly related t o a n y specific bas ic modes a s provided b y the M C68020 arch itecture, even though some w i l l have obvious cou nterparts. F i rst, some terms commonly u sed by program mers are defined here as to their exact mea n i ng. poi nter base i ndex Long word va lue in a reg ister or in memory which represents an add ress. A poi n ter combi ned with a disp lacement to represent an address. A constant or variable value which the programmer uses to add a bias i nto an effective address calcu lation. As a constant, the i ndex ends u p treated as a displacement. A variable i ndex is always represented by a reg i ster con tai n i ng the value. Displacement, a constant i ndex. The use of any of the data or address reg isters as a variable i ndex subscript i nto arrays of items 1 , 2, 4, or 8 bytes i n s ize. An add ress based with the Program Cou nter. This makes the reference code posi t i on i ndependent and the operand accessed is in Program Space. A l l others but psaddr (below) fall i nto Data Space. An absol ute add ress. An absolute address in Program Space. A l l others but relative fal l i nto Data Space.

d i sp subscript re lative

addr psaddr

D-1 3

Secondly, the generic modes are summarized as fol lows: I m mediate Data Reg i ster Di rect Scan n i ng M odes - #data Rn (An) + - (A n) Absolute Address - (addr) (psaddr,ZPC) Reg i ster Pointer (Rn) (d isp,Rn) (An , R n) (d isp,An, Rn) The data i s a constant i n the i nstruct ion stream. The contents of a reg ister i s specified. Address reg ister poi nter automat ically i ncremented after u se. Address reg ister poi nter automat ically decremented before u se. Absol ute address in data space. Absolute address in program space. Register as a pOi nter. Register as a poi nter and constant i n dex (or base address.) Register pointer with variable i ndex. Reg i ster poi nter with constant and variable i ndex (or a base address with a variable i ndex). A bsol ute address with variable i ndex. Absolute address with 2 variable i n dexes. Address reg ister pOinter subscri pt. Address reg i ster pOi nter subscript with constant d i splacement (or base ad dress with su bscript). Absol ute address with subscri pt. A b s o l u t e a d d re s s s u b s c r i pt w i t h variable i ndex. Simple re lative. Relat ive with variable i ndex. Relat ive with subscri pt.

I ndex i n g

(addr,Rn) (addr,A n , R n) Subscripting (An, Rn * scale) (disp,An , R n * sca le)

(addr, R n * scale) (addr,A n , R n * scale) Program Relative - (d isp,PC) (d isp,PC,Rn) (d isp,PC,Rn * scale)

0-1 4

Memory Poi nter

([* modes])

M e m o ry p o i nter d i rectly to data operand. ([* modej,d isp) Memory pointer as base with displace ment to data operand. ([* * modesj, Rn) M emory poi nter with variable i ndex. ([* * modesj,disp, R n) Memory pointer with constant and variable i ndex. ([* * modesj,Rn * scale) Memory poi nter subscri pted. ([* * modesj,disp,Rn * scale)Memory pOinter subscri pted with cons tant i ndex.

* -al lowed modes are any of the above from absolute address through program relative. * * -al l owed modes are as fol l ows: Absol ute address in data space. addr psaddr,ZPC Absol ute address in program space. An Reg i ster poi nter. disp,An Register pOinter with constant displacement (or base add ress). addr,An Absolute address with single variable i ndex. d i s p, PC S i m p l e program relat ive.

-0-1 510 1 6

APPEN DIX E MC68020 EXTENSIONS TO M68000 FAM I LY

This Append i x summarizes the extensions to the M6BOOO Family i mplemented by the M C6B020 microprocessor. N OTE In the following description, the notation " M C6BOOO" i n c l udes the M C6BOOO and the M C6BOOB together, and " MC6B010" incl udes the M C6B0 1 0 and MC6B0 1 2 together, except w here spec i fically mentioned. E laborat ion on M C6BOOO and M C6B0 1 0 d ifferences may be found in the M68000 Program mer's Reference Manual. Data Bus Size (Bits) M C6B020 . . . . . . . . . . . . . . . . . B, 1 6, 32 M C6BOOO/M C6B0 1 0 . . . . . . . . . 1 6 M C6BOOB . . . . . . . . . . . . . . . . . B Address Bus Size (Bits) M C6B020 . . . . . . . . . M C6B01 2 . . . . . . . . . M C6BOOO/M C6B01 0 . M C6BOOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 . 30 (plus A3 1 ) . 24 . 20

I nstruction Cache M C6B020 . . . . . . . . . . . . . . . . . 1 2B Words MC6B0 1 0 . . . . . . . . . . . . . . . . . Provides Loop M ode (3 Words) V i rtual Memory/Machine M C6B020/MC6B0 1 0 . . . . . . . . . Provides Bus E rror Detect ion, RTE Recovery Coprocessor I nterface M C6B020 . . . . . . . . . . . . . . . . . In M i crocode M C6BOOO/M C6B0 1 0 . . . . . . . . . E m u l ated in Software Processor S i g na l s and P i n ASSig n ments Detai led in each specific data sheet. I nstruction Execution Time Detai led i n each spec ific data sheet.

E-1

Word/Long Word Data A l i g n ment M C68020 . . . . . . . . . . . . . . . . . Only I nstruct ions M ust be Word A l i g ned M C68000/M C680 1 0 . . . . . . . . . Word/Long Word Data, I nstructions, and Stack M u st be Word Alig ned Control Reg isters M C68020 . . . . . . . . . . . . . . . . . SFC, DFC, VBR, CACR, CAAR M C680 1 0 . . . . . . . . . . . . . . . . . SFC, D FC, V B R M C68000 . . . . . . . . . . . . . . . . . N one Stack Poi nters M C68020 . . . . . . . . . . . . . . . . . USP, SSP (MSP, ISP) M C68000/M C680 1 0 . . . . . . . . . USP, SSP Status Reg i ster M C68020 . . . . . . . . . . . . . . . . . TOIT1 , S, M, 1 0/ 1 1 /12, X/NIl/V/C M C68000/M C6801 0 . . . . . . . . . T, S, 1011 1 112, X/NIZlV/C Fu nction Code/Address Space M C68020/MC6801 0 . . . . . . . . . FCOFC2 = 7 is CPU Space M C68000 . . . . . . . . . . . . . . . . . FCOFC2 = 7 is I nterru pt Acknowledge, Only I ndivisible B u s Cyc les M C68020 . . . . . . . . . . . . . . . . . Use RMC Signal M C68000/M C680 1 0 . . . . . . . . . U se AS Si gnal (MC6801 2 Also U ses RMC) Exception Vectors Detailed in each specif i c data sheet. Stack Frames M C68020 . . . . . . . . . . . . . . . . . Su pports Formats $0, $1 , $2, $9, $A, $B M C6801 0 . . . . . . . . . . . . . . . . . Su pports Formats $0, $8 M C68000 . . . . . . . . . . . . . . . . . Supports Original Set Addressing M odes M C68020 extensions: memory i n d i rect addressing modes, scaled index, and larger d isplacements. Deta i l s are found in each spec ific data sheet. M C68020 I nstruct ion Set Extensions Bcc . . . . . . . . . . . . . . . . . . . . . . Su pports 32Bit Displacements BFxxxx . . . . . . . . . . . . . . . . . . . Bit Field I nstructions (BFCHG, BFCLR, BF EXTS, B FEXTU, B F EXTS, BF FFO, BFI NS, BFSET, BFTST) BKPT . . . . . . . . . . . . . . . . . . . . New I nstruction Fu nctional ity BRA . . . . . . . . . . . . . . . . . . . . . Supports 32Bit Disp lacements BSR . . . . . . . . . . . . . . . . . . . . . Supports 32Bit Disp lacements CALLM . . . . . . . . . . . . . . . . . . . New I nstruction CAS, CAS2 . . . . . . . . . . . . . . . . New I nstruction CHK . . . . . . . . . . . . . . . . . . . . . Supports 32Bit Operands C H K2 . . . . . . . . . . . . . . . . . . . . New I nstruction E2

II

C M P I . . . . . . . . . . . . . . . . . . . . Supports Program Counter Relative Add ressing M odes C M P2 . . . . . . . . . . . . . . . . . . . . New I nstruction cp . . . . . . . . . . . . . . . . . . . . . . . Coprocessor I nstructions DIVS/DIVU . . . . . . . . . . . . . . . . Su pports 32-Bit and 64-Bit Operands EXTB . . . . . . . . . . . . . . . . . . . . Supports 8-B it Extend to 32 Bits LI N K . . . . . . . . . . . . . . . . . . . . . Supports 32-Bit D i splacement M OVEC . . . . . . . . . . . . . . . . . . Su pports New Control Reg isters M U LS/M U LU . . . . . . . . . . . . . . Supports 32-Bit Operands PACK . . . . . . . . . . . . . . . . . . . . New I nstruction RTM . . . . . . . . . . . . . . . . . . . . . New I nstruction TST . . . . . . . . . . . . . . . . . . . . . . Supports Program Counter Relative Addressi n g M odes TRAPcc . . . . . . . . . . . . . . . . . . New I nstruction U N PK . . . . . . . . . . . . . . . . . . . . New I nstruction

A17717-1

4/85

E-3/E-4

II

NOTES

NOTES

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AO- A31
FCO-FC2

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K K

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50

51

52

53

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55

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+(i
2

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13

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05

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,

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BEAA

I+\.

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HALT All Asynchronous Inputs

NOTE:

.J.

Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts. unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 volt and 2.0 volts.
Figure 1 0-5. Read Cycle Timing Diagram
Foldout 1

. 47a

I+-
+-

.I -@

AO-A31

FCO-FC2

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so

S1

S2

S3

S4

S5

J -+t 0V * -+ I+ )Hf--:--+--+-

l -+----+-f---''f",----

OCS

1+ 1i) -- 14 l------l ""' , -+- .:.AS -

-4 ,..-4 'r,oa) -.I/ --+------4------4--I 1'-

R/W

a +----+--8 l (9)r- --h. 1. "'""'---I'l 10-----+----.1 +- -+ ;";""+OS - - "'::':: , ...".... --I'I )..--j\.. -+ @ 1+t --< 2 }------i- I---{ - t2 I+-
,

OSACKO -----' I OSACK 1

00-031 - - + - + - -t
OBEN

--'

---+----Il---+-- I 1\ r- .. e 1'---....-----I-.j.-""8.t--' Ir--2 , I I 55'-. C\ -@::: f*-----+-+-) -' C--+-

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_

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& f+-

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BERR

HALT
NOTE:

----------
-

4+

I+ ---,

Timing measurements are referenced to and from a low voltage of .8 volt and a high voltage of 2. volts, unless otherwise noted. The voltage swing through this range should start outside and pass0through the range such that the 0rise or fall wil be linear between 0.8 volt and 2. 0 volts.
Figure 1 06. Write Cycle Timing Diagram

Foldout 2

ClK AO-A3l DO-D3l FCO-FC2 SIZO-SIZl ECS

ocs

(2)

AS DS
R/W

'DBEN DSACKO DSACKl

BR

BG BGACK

39

NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall wil be linear between 0.8 volt and 2.0 volts.
Figure 1 0-7_ Bus Arbitration Timing Diagram

Foldout 3