Release Notes For ModelSim Actel 6.

6d Nov 01 2010 Copyright 1991-2010 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. The following are trademarks of of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal Spy. A current list of Mentor Graphics trademarks may be viewed at www.mentor.com/terms_conditions/trademarks.cfm. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. _______________________________________________________________________ Product Installation and Licensing Information For brief instructions about product installation please visit the "install_notes" file in www.model.com. The install_notes file can be viewed at: [1]http://www.model.com/products/release.asp For detailed information about product installation and licensing see the ModelSim Start Here Guide. The manual can be downloaded from: [2]http://www.model.com/support/documentation.asp Release Notes Archives For release notes of previous versions visit the release notes archive at: [3]http://www.model.com/support/default.asp or find them in the installed modeltech tree in <path to modeltech installation>/docs/rlsnotes How to get Support

ModelSim Actel is supported by Actel Inc. * Telephone Support Call 1-800-262-1060 * Email Support [4]tech@actel.com * World-Wide-Web Support [5]http://www.actel.com/support _______________________________________________________________________ Index to Release Notes [6]Key Information [7]User Interface Defects Repaired in 6.6d [8]Verilog Defects Repaired in 6.6d [9]PLI Defects Repaired in 6.6d [10]VHDL Defects Repaired in 6.6d [11]FLI Defects Repaired in 6.6d [12]VITAL Defects Repaired in 6.6d [13]SystemC Defects Repaired in 6.6d [14]Assertion Defects Repaired in 6.6d [15]Mixed Language Defects Repaired in 6.6d [16]Coverage Defects Repaired in 6.6d [17]General Defects Repaired in 6.6d [18]Mentor Graphics DRs Repaired in 6.6d [19]Known Defects in 6.6d [20]Product Changes to 6.6d [21]New Features Added to 6.6d _______________________________________________________________________ Key Information * The following lists the supported platforms: + win32acoem - Windows XP, Vista, Windows 7 + sunos5acoem - Solaris 8, 9, 10 + linuxacoem - RedHat 9 and higher, RedHat Enterprise Linux 3, 4 and 5, SUSE Linux Enterprise Server 9.0, 9.1, 10 and 11. _______________________________________________________________________ User Interface Defects Repaired in 6.6d

* Failure in [virtual function] broke subsequent search of context tree. This is now fixed. * GenerateFormat setting in modelsim.ini caused errors in the GUI during name lookups. This issue is now fixed. * Waveform compare gave inconsistent results in certain command sequences. In some case, the compare output was not reporting that a new compare had started or would mis-count the number of new compare differences that should be reported. * Checkpoint/Restore crashed if transaction recording was used. Checkpoint/Restore remains unsupported when the simulation includes transaction recording, but the checkpoint command has been modified to verify this condition and to issue a clear error if Checkpoint/Restore is blocked by transaction recording. * The find nets command does not work on an array indexed by an enumerated type. This issue is now fixed. * When changing preferences for the Wave window the changes would not be reflected in the embedded wave pane of the Dataflow or Schematic windows. This has been fixed. * Reloading a dataset could sometimes result in a crash. The defect has been corrected. * The modelsim and questasim programs no longer show the appropriate icon and when starting up, a blank console window is displayed. This has been fixed. * Dataflow could crash when accessing nets in Verilog modules that contain specify blocks. * Repeated simulation restarts could leak memory if objects are being logged to the WLF file. * The Help toolbar search results page now properly shows in Firefox 3. * Class subelements that were arrays of class references could generate internal errors when logged directly or indirectly via ui_VVmode full. * Expanding nets to drivers or readers in the Dataflow window could result in the error "Debug data file, vsim.dbg, does not exist" and broken connectivity when the option to show hierarchy was enabled. * Grouping a single item in the Wave window, then ungrouping it, then grouping it again could cause a crash. * It takes a long time to redraw signals in the WLF file. The problem was a signal linked to an MVC transaction stream. The link forced the WLF scan to include the transaction data. In this case, the TX data was not needed since no TX streams were loaded into the Wave window. This is now fixed. Note that when TX streams are added to the Wave window, the scan WILL include TX data and may be slowed. * Fixed an issue with the import library command. Under certain circumstances the resulting vmap command would produce an error, causing the operation to halt. * Undocking the Transcript window and raising the popup menu could cause keyboard focus to return to the Main window. Subsequent commands could be redirected to the wrong window. Focus is now managed properly in this situation. * On Windows only, file type registration now recognizes different simulator versions with file associations. A menu pic has been added that will reset the file associations to the current version. * Expressions containing spaces after the final quote in string values in when breakpoint expressions would cause the value to not be treated as a string. * A new project command has been added. project filenames will return a list of the filenames associated with the project. These file names will be returned in a hard path format. * When a project is open, and a file is opened and edited and then

compiled, the UI would not query the user as to whether the file should be saved first. The UI will now ask the user if they would like to save the file before proceeding with the compile. * Hyphenated font family names no longer cause an error message when selected in preferences. * Using the command line jobspy commands on Windows, in the background, causes other window applications to loose focus. Jobspy also runs slowly on this platform. These issues have been fixed. * The capacity tool crashed while reporting assertions capacity data. This issue has been fixed. _______________________________________________________________________ Verilog Defects Repaired in 6.6d * The vlog tool would crash with malformed timescale directives. * vlog's -Epretty switch will now print out the timescale and timeunit directives correctly. * vopt consumed excessive memory in propagating constants through complex continuous assignments in some cases. * MODEL_TECH specific Verilog preprocessor directives `mti_v2k_int_delays_on and `mti_v2k_int_delays_off provided a mechanism to ensure that SDF annotation to a specific module instance was done in "-v2k_int_delays" mode. Since release 6.4, compiled SDF has been the default SDF annotation flow, which annotates in "-v2k_int_delays" mode. Therefore, the work around provided with the above pre-processor directives, has been disabled. * vopt issued an incorrect "Illegal left-hand side" error for a connection to an inlined module in some cases. * An optimization of a combinatorial always block that assigns to a 2-state variable resulted in an elaboration crash. * The type, byte, was mistakenly identified as a bit[7:0]. * The "power" operator produced incorrect results in some cases if the exponent was greater than 32-bits wide. * Non-net connections to a "port shorting" or "aliasing" module in an optimized design resulted in a vsim elaboration crash. * A very large port hierarchy "port shorted" or "aliased" to a large number of nets resulted in extremely slow elaboration. * Taking a part-select of a packed struct within an array would result in an incorrect value in vopt flow. * The check for SystemVerilog operators is now disabled in protected regions. * A clocking drive to a variable slice of an array when the clockvar is an inout may result in a non-blocking assignment to the input side of the clockvar. * Use of specparam outside a specify block with `delay_mode_unit, `delay_mode_zero in Verilog source or +nospecify, +delay_mode_zero, +delay_mode_unit command line options would cause vopt internal errors. * When -O5 is used on the vlog (or vopt) command-line, in some cases, optimization of bit-select or part-select expressions performed on memories with constant subscripts could cause incorrect values to be computed. * In some constraint scenarios involving the modulo operator with a small modulus, ACT performance has been improved. * Using a specparam in a $write() statement outside a specify block would lead to a crash when ran with +nospecify. * Passing a slice of an array of interfaces to an interface-array port did not work correctly. * Sign coercion (using signed') did not work for logic vectors inside structs.

* The error message reporting an incorrect clocking end label displayed the wrong line numbers. _______________________________________________________________________ PLI Defects Repaired in 6.6d _______________________________________________________________________ VHDL Defects Repaired in 6.6d * vsim would crash when a slice of a signal parameter inside a subprogram was passed to another subprogram. * Long simulator loading times could occur if thousands of packages are present in a design. The loading times are now significantly faster. * If a component configuration is an incremental binding and contains an entity aspect, the port map would incorrectly leave ports bound in the primary configuration open. * This bug has been fixed since 6.6c. The simulator would crash when elaborating a VHDL design that had a PROCESS statement that contained both a protected type VARIABLE declaration and PROCEDURE declaration. * This problem has been fixed since 6.6c. When a protected type method declarative part contained a subprogram that recursively called itself, the compiler was not able to resolve the recursive subprogram call, issuing an error when in fact the call is legal. * Because equality and inequality operations on composites were evaluated by comparing corresponding bytes, incorrect results would occur if composites contained corresponding elements -0.0 and 0.0. When composites contain real-valued elements, equality and inequality operations are now performed by comparing corresponding elements. * When a design was compiled using vcom and the 2008 version of VHDL, the compiler would not accept an overloaded declaration of to_string which had more than one parameter. This has been fixed. _______________________________________________________________________ FLI Defects Repaired in 6.6d _______________________________________________________________________ VITAL Defects Repaired in 6.6d _______________________________________________________________________ SystemC Defects Repaired in 6.6d * Hierarchical reference via SignalSpy in to a Verilog or VHDL design-unit instantiated as black-boxes from SystemC would lead to a crash. * sccom error for overloaded constructor of class templates is fixed. * sccom writing files with group write permissions into the work library is fixed. _______________________________________________________________________ Assertion Defects Repaired in 6.6d _______________________________________________________________________ Mixed Language Defects Repaired in 6.6d * Verilog hierarchical references with part selects to VHDL signals would crash if the hierarchical reference is used in a port map. _______________________________________________________________________ Coverage Defects Repaired in 6.6d * Added the ability to use variable names within a testplan so that

values can be substituted during the xml2ucdb process and therefore changed depending on use. You can use the syntax (%VarName%) in ANY cell in the XML file. For example: Link = covergroup,(%INSTA%):coverpoint To provide a value for the variable use the command option: -G(varname)=<value> # Assigns <value> to variable (varname) For example: "-GVarx=7" (%varname%). Note that this usage is added to the help message of xml2ucdb: You can also provide values for the variables by using a config file, whose name is read by default from the modelsim.ini file. varfile = <fileName> and could be changed using the command option: -varfile <filename> # Name of file containing variable values The varfile contains variable values in this format: varName = varValue You can use ";" in the beginning of any line to comment this line out. For example: ;var1 = 5 # will be ignored. If a variable was assigned values from both the varfile and the -G option, the value provided by the -G option will overwrite the value from the file. You can use any number of variable in the same cell and as many variables as you want in the whole XML file. Each variable should have a corresponding -G option or a line in the varfile to provide the variable a value. If variable did not have a value, an error will be issued and the section and row where this variable was found will not be in the output UCDB file. For example: Error: No value found for Variable "OneDotOne" (Use: -GOneDotOne <var_value>) And if a -G was provided for a variable that does not exist in the XML file, a warning will be issued. For example: Warning: Variable "two" was not found in the XML file. Variable names are case INSENSITIVE. * Added the ability to use variable names within a testplan so that values can be substituted during the xml2ucdb process and therefore changed depending on use. You can use the syntax (%VarName%) in ANY cell in the xml file. i.e. Link = covergroup,(%INSTA%):coverpoint To provide a value for the variable use the command option: This is added to the help msg of xml2ucdb: -G(varname)=<value> Assigns <value> to variable (varname) (i.e "-GVarx=7") <value> will replace (%varname%). You also provide values for the variables by using a config file, whose name is read by default from the ini file. varfile = <filename> and could be changed using the command option: -varfile <varfile> Name of file containing variable values The varfile contains variable values in this format: varName = varValue and you can use ";" in the beginning of any line to comment this line out i.e the line: ;var1 = 5 will be ignored. If a variable was assigned values from both the varfile and the -G option, the value provided by the -G option will overwrite the

value from the file. You can use any no. of variable in the same cell, as many variables as you want in the whole xml file. Each variable should have a corresponding -G option or a line in the varfile to provide the variable a value. If variable didn't have a value, an error will be fired and the section/row where this variable was found will not be in the output ucdb file. e.g. Error: No value found for Variable "OneDotOne" (Use: -GOneDotOne <var_value>) And if a -G was provided for a variable that doesn't exist in the xml file, a warning will be fired. e.g. Warning: Variable "two" was not found in the xml file. Variable names are case INSENSITIVE. * The HTML report utility accepts multiple "-instance <pathname>" options which will make the HTML report include only the instance(s) defined by the option -instance. The report will also has the sub-tree for these instances. The label "(Filtering Active)" will be shown in the tables of the HTML report to indicate that this is not the whole report and some filtering occurred. Note: This label is also shown when any of these options "-instance <pathname>, -cvg, -assert, -directive, or -code bes[t x]fc" are used. * Fixed a bug with VHDL if-statement code generation when branch coverage is on and the first if condition is statically false and there is a non-static elsif clause. This caused the testing of the elsif condition to be skipped, resulting in bad simulation results. * Under some conditions, on Windows platforms, the coverage HTML report generator would not complete while reporting statement coverage. This has been fixed. * A problem causing errors and segmentation fault with 'vcover merge' has been fixed. * vsim was crashing during loading of a UCDB file which does not contain UDP expression coverage but contains FEC expression coverage. * Fixed a problem in which vsim -coverage was used and the design was not compiled with code coverage, and vsim did not output a warning message. * Fixed a problem in which bad simulation results occurred when -novopt mode was used and the size of a Verilog net or reg depended on a parameter, and that net or reg was used in a condition or expression with the respective code coverage turned on. * vcover merge was producing new statements incorrectly due to merging of parameterized module instances in different merging UCDB files. _______________________________________________________________________ General Defects Repaired in 6.6d * dts0100722825 - ui_VVMode full causes internal errors. _______________________________________________________________________ Mentor Graphics DRs Repaired in 6.6d * dts0100631114 - Import Library Wizard errors when importing library WITH library dependencies. * dts0100671791 - RMB on "undocked Transcript window" causes focus to go to Main GUI. * dts0100689873 - Cannot modify Grid and Timeline Properties of dataflow embedded Wave window.

* dts0100710432 - coverage report -excluded command did not report Port Signals. * dts0100711626 - Getting errors and segmentation fault with vcover merge command. * dts0100712987 - Failure in [virtual function] broke subsequent search of context. * dts0100713102 - Problem with load_upf -scope /. * dts0100713462 - Inconsistent waveform compare results. * dts0100714132 - Certain WLF files cause the simulator to crash when performing a dataset reload. * dts0100715425 - Transcript names transcript0, transcript1, transcript2 can not be used in do file operations. * dts0100717247 - Error: bad text index XE.0. * dts0100718014 - Difference in behavior between packed struct and vector of same size and sign. * dts0100719024 - Remove the range requirement for the 'change' command. * dts0100720994 - Memory leak after several restart/run. * dts0100721128 - Can't generate HTML report for a UCDB file in 6.6c on Windows. * dts0100721166 - VPI callback missing for certain data types within a struct. * dts0100721173 - Simulation crash while running with optimization option, -no_autoacc. * dts0100721395 - Wrong result when indexing array of packed struct. * dts0100721836 - Issue from alias optimization. * dts0100721996 - Real value -0.0 in array isn't equal to 0.0 in another array. * dts0100722299 - Loading memory construct even when bounds are out of range in task. * dts0100700138 - "find nets" command does not work on an array indexed by an enumerated type. * dts0100725648 - Long time to redraw signals. * dts0100696479 - Request support for 6x13-ISO8859-1 font. * dts0100718853 - jobspy commands cause applications to loose focus. * dts0100709404 - Crash occurs when simulating optimized design. * dts0100725543 - Parameter override failing in vopt for interface inst. array, works with -novopt. * dts0100685061 - Segfault with non-shared variable of protected type. * dts0100692688 - VHDL recursive subprogram locally in a method of a protected type. * dts0100716613 - VHDL overloaded to_string won't compile with multiple parameters. * dts0100723529 - Expression coverage generating bad code causing incorrect simulation output. * dts0100723480 - Add option to vsim to specify the version of gcc for DPI flows (similar option to -cppinstall for SystemC). _______________________________________________________________________ Known Defects in 6.6d * On the Windows platform, If the Destructor breakpoint on SystemC object is set via command bp -c < function_name >, the Debugger sometimes does not stop at the breakpoint. * On Windows platform, if breakpoint is set on a SystemC object destructor, Debugger sometimes crashes while quitting simulation. This crash can be avoided by setting env variable SC_NO_LIB_UNLOAD, which will prevent unloading of the shared library. * The simulator will hang if it tries to create a WLF file while running on a Linux 64-bit operating system from a working directory

which does not support large files. One common instance of this is executing an add wave command, when the working directory was created under an older 32-bit Linux OS. This is a Linux operating system bug and cannot be fixed by the simulator. A workaround for release 6.3 and above is to execute the simulator with command line option -wlfnolock. * The stack unwinder on the linux_x86_64 OS is unreliable. The unwinder is the fundamental facility provided by the OS for sampling where program execution is at. The unwinder is necessary for gathering performance data. This is a known issue with this specific OS and is why performance data will be incorrect or non-existent on this platform. * Users should be mindful of enabling both performance profiling and memory profiling at the same time. Memory profiling requires much overhead process, and it can skew the results of the performance profiling data. * On certain (RedHat) Linux Operating System versions the "-restore" feature occasionally fails. This is due to the memory allocation security (anti-hacking) feature of Linux. RedHat Enterprise release v.3 update3 was the first version to have this security feature. In these Linux releases two consecutive program invocations do not get the same memory allocation foot-print. For the "-restore" feature the simulator relies on having the same memory allocation foot-print. Users are advised to re-try this feature a few times as on average 3 out of 5 attempts are successful. In recent Linux versions, an override for this anti-hacking feature is provided. Please use it at your own discretion. * The detect_overlap option of Coverpoint does not work with transition bins. It only works with value bins. * Support of debugging C code during a quit command was disabled on Windows. The corresponding C Debug command cdbg stop_on_quit was also disabled on Windows. * Specparams can be learned during the learn flow, but cannot be found on consumption. The workaround is to use full +acc deoptimization. * On Red Hat Enterprise Linux release 5 platform, If SIGSEGV signal occurs during the simulation and if CDEBUG is on, C-debugger traps the signal, and when continued, vsim gets terminated right away, instead of exiting with proper error status. * The vpiPorts iteration on vpiEnumNet, vpiIntegerNet, and vpiStructNet VPI objects has been disabled as it was incomplete and unsafe to use. * The following sequence of operations may cause a 'database locked' error message: $ vsim -debugdb <design> VSIM 1> view schematic VSIM 2> quit -sim ModelSim> vsim -debugdb <design> The workaround is to exit the simulator UI completely rather than using just 'quit -sim'. * The value annotation in the Schematic window has some known limitations. + MUX output values are not shown in all cases. + Net slices are annotated with the full value of the net, not the value of the slice. Gates that have a slice of a net as input do not show a value on the output. + RTL function output values are not shown in all cases. + Concatenation symbols will not show output values.

+ Anytime a net is missing a value, downstream gates will also not display any output value. _______________________________________________________________________ Product Changes to 6.6d * Conversion of time values to reals has changed. The way to convert a time value to a real is normally done with an expression of the form: real( time_expression_1 / time_expression_2) This conversion is now without truncating the division to 32-bits. * If finish_address specified to $readmem is out of bounds, $readmem reads data into the remaining valid memory addresses. * The file list specified by vlog's -f switch now accepts line continuation. * The vcover merge ... -combine option now has two new variant options: Both may be used to merge two or more different runs of a single test, or re-joining stripped versions of a UCDB file (optional). 1. -combinemax: When using this argument, for nodes with conflicting toggle information, the maximum count is saved in the UCDB. 2. -combinemin: When using this argument, for nodes with conflicting toggle information, the minimum count is saved in the UCDB. * The files and directories in the pre-compiled libraries (std, ieee, pa_lib etc) are now write-protected. * Several behavioral enhancements have been made to the Results Analysis front-end commands: + An -append option has been added to the triage dbfile command which will allow additional messages to be posted to the database even if other messages exist under the same testname as the message being inserted. + A -debug option has been added to the triage dbfile and triage transform commands to display every message exported during the course of the command. + The triage query command now returns its results instead of simply echoing them to the transcript (so triage query can now be used in scripts). + When the -wlfattr and/or -logattr options are used on the triage dbfile command, the contents of the indicated UCDB attributes are placed into the "wlfname" and "logname" columns of the test table. + An error is generated if the -wlfattr or -logattr options are used twice in the same command (they may, of course, be used together -- once each). + If a WLF or plain-text LOG file is included directly on the command line or in an "input file" designated by the -inputsfile option, and that same file is referred to by a test data record imported from a UCDB file specified in the same command, the UCDB reference is ignored with a warning (previously resulted in an error). + Any time a transformation overrides the value of the "time" or "wlftimeunit" fields for a message, the value of "normalizetime" is also changed unless the transformation also happens to override "normalizetime". + The text of several error and informational messages has changed to use more consistent terminology. * SystemVerilog only. In some special situations structure literals will be allowed to be written without the tick "'" preceding the opening left curly-brace. This relaxation of the IEEE 1800

specification can be disabled with the flag -pedanticerrors. * The default for VHDL Vital has been changed to VITAL 2000. To get the behavior of previous releases you need to do the follow vmap command vmap IEEE $MODEL_TECH/../vital1995 If a design refers to both IEEE and VITAL2000 for the VITAL libraries, then the logical library VITAL2000 must be remapped to IEEE. vmap VITAL2000 $MODEL_TECH/../ieee * The new UCDB API adds two "levels of attribute indirection": where an attribute can be a handle to: 1. refer to some other set of attributes or 2. refer to an array of attributes. * Deprecated the q flag from the set of vopt +acc specifier characters. vopt +acc=q is a synonym for vopt +acc=v +floatgenerics, and thus is not a proper member of the orthogonal +acc specifiers. * The default behavior for the vsim command when the only argument is a wlf file is to open a Wave window and add all signals in the design to the window. This behavior has been changed. The signals will no longer be added to the wave window. The user can change this default behavior by modifying the PrefWave(OpenLogAutoAddWave) setting. A true (1) value will enable the automatic add operation, a false (0) value disabled this action. * Wildcard matching for the UCDB API routines ucdb_PathCallBack() and ucdb_MatchCallBack() have been enhanced. Wildcarding: * matches any substring within a level of hierar chy ? preceding character is optional [< int >:< int >] matches an integer index within the range (< int * > to < int * >) matches an integer index within the range (< int * > downto < int * >) matches an integer index within the range * The 'vcover' tools have been extended to handle -warning, -error, -note, and -suppress options. Note: Many vcover messages are internal and use "printf" directly. These messages do not use the message system (i.e. they do not have message numbers) and cannot be controlled by these options. * The -pedanticerrors flag will promote warnings in the LRM group of messages to errors. * Executables in the bin directory will default to 32-bit mode on 64-bit Linux machines unless MTI_VCO_MODE is set to 64. vco will behave in a similar fashion. * The acc and tf routines have been deprecated by the IEEE as of the 2005 standards. The tf_nodeinfo support for providing direct pointer access to memories by way of the memoryval_p pointer has now been removed. Although other information provided by tf_nodeinfo will not be impacted, the memoryval_p will now provide a null pointer for any memory. * VHDL "for generate" equivalent blocks now have design pathnames more in line with the LRM requirement. The name at each iteration is constructed in the form [label] '(' [literal] ')', where [label] is the generate statement label and [literal] is the value of the generate parameter at that particular iteration. Prior releases constructed the name using the generate statement label and the position number of the value of the generate parameter at a particular iteration and the [vsim] section GenerateFormat variable (default value "%s__%d"). * Cross selection has been enhanced to include index and subfield

* *

selection. When a signal is selected in one window, for example, the Wave window, the corresponding signal is also selected in the Objects window. If an index or field of a record is selected, the item in the Objects window will be expanded and the appropriate index or field will be selected. vlog will always create a package in the design library when the -mfcu and the -cuname options are specified. The coverage system default behavior in the area of SystemVerilog covergroups has changed. Specifically, it has changed to be compliant with the latest IEEE 1800-2009 clarifications and changes. The vsim switch -cvg63 reverts to the pre-6.6 behavior. The switch -nocvg63 explicitly forces the new behavior. This change has several aspects, each of which can be individually reverted by SystemVerilog source code changes. The list of changes, briefly, is as follows: 1. The default algorithm used to calculate the coverage score for a covergroup type changes to an average-of-instances algorithm, where the tool previously defaulted to the merge-instances algorithm. This can now be controlled directly by the type_option.merge_instances covergroup syntax. A consequence of this change is that, by default, the supporting data for the merge-instances algorithm is no longer collected. Another visible consequence is that coverage numbers may differ from previous versions, because they are calculated using a different algorithm. 2. The reporting of per-instance data is also affected. In this case, the 1800-specified behavior is that per-instance reporting is suppressed if option.per_instance is 0 (the default), and database storage of per-instance data is optional in this case. In fact, the tool will save the per-instance data, irrespective of this option, but the reporting is affected and can be restored by setting option.per_instance to 1. 3. The behavior of the get_inst_coverage() method also changes. This was previously ambiguous where per_instance was set to 0. The ambiguity was that if this option is set to have the effect of not tracking the per-instance data, what response should the tool provide, when this untracked data is queried using get_inst_coverage()? The previous resolution to this ambiguity was to default the get_inst_coverage() method behavior to the get_coverage() method in this case. This behavior is no longer ambiguous as the per-instance data is now always tracked and always available from get_inst_coverage(), even if per_instance is false. If required, however, the original behavior can be restored by setting the option.get_inst_coverage to 1. When using Causality Traceback after simulating with the -novopt switch you will only have access to the Show Driver option in the Source window. The Show Cause and Show Root Cause options will display a warning. The "missing timescale" elaboration warnings (messages 3009 and 3010) are now elaboration errors. Having missing timescales resulted in reduced performance in some cases, and the warnings were easily overlooked. These errors can be reduced to warnings with the vsim option -warning 3009,3010, and the +nowarnTSCALE option continues to suppress the elaboration check. In addition, to eliminate false errors the elaboration check no longer considers modules that do not contain delays. Relaxed the checking of undefined DPI import C functions at elaboration time. A warning is issued instead of a fatal error. If

the undefined DPI import C functions are called on runtime, a runtime fatal error will be issued. * Messages issued for SystemVerilog source code in packages may produce different line numbers than previous versions of the simulator. * The random initial values generated by using +initreg option used to be the same for different instantiations of a design unit. Now, the simulator generates different random initial values for different instances of a design unit when this option is enabled. _______________________________________________________________________ New Features Added to 6.6d * A user can specify a recursion level for the +cover option, similar to the +acc option. * vsim has a new -dpicppinstall <[gcc g++] version> switch to specify the GNU compiler version supported and distributed by the simulator. For example: To use the linux 4.3.3 version of gcc i.e. <install_dir>/gcc-4.3.3-linux/bin/gcc Use the following command: vsim -dpicppinstall 4.3.3