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Optimization of a High Speed

PCB Signal Launch

Authored by:
Suresh Subramaniam (Xilinx)
Martin Vogel (Ansoft)

Ansoft 2003 / Global Seminars: Delivering Performance


Presentation #12
Motivation for Work

“How can Xilinx


help its customers
make their signal
launches more
transparent?”
Agenda
w Description of Device
w Fixed Parameters
w Variable Parameters
w Simulation Set-Up
w Optimized Design
w Sensitivity Analysis
w What-If Analysis
w Conclusions
PCB Launch
Fixed Elements
• Board manufacturing technology Coaxial cable
• Connector geometry
• Board stack-up
• Signal layer on PCB

Signal via
(radius only)
Ground vias
Connect to all
ground planes,
not to power
planes.
Variable Elements
Distance from ground via to signal via
Radius of ground via
Variable Elements
Length of via stub
Variable Elements
Radius of antipad under trace
Variable Elements
Radius of other antipads
Variable Elements
Radius of signal pad
Agenda
w Description of Device
w Simulation Set-Up
w Initial Geometry
w Nominal Performance
w Optimization Goals
w Optimized Design
w Sensitivity Analysis
w What-If Analysis
w Conclusions
Tools Used

w 3D electromagnetic simulation
w Optimization
w S-parameter results
w TDR/TDT results

w Eye diagram results


Variables in HFSS 9:
simply type variable names in the commands
• Nominally 100 according to Xilinx
design guide
• Replaced with variable for
optimization
Overview nominal design
TDR/TDT nominal design
Eye diagram nominal design
Spectral Response of PRBS Signal
0.35 / Trise 0.50 / Trise
11.7GHz 16.7GHz

Normalized Cumulative PSD

100.00%

80.00%
Bit Rate = 10Gb/s
Percent of Total Power

60.00%
Rise Time = 30pS
40.00% 97.2% 99.5%
20.00%

0.00%
0 5 10 15 20 25
Frequency (GHz)
S-Parameters nominal design

S21
S11 (at coax)
S22 (on trace)

S11 goal
Example Optimization
Agenda
w Description of Device
w Simulation Set-Up
w Optimized Design
w Sensitivity Analysis
w What-If Analysis
w Conclusions
Which variables were changed?

Parameter From To
Radius of Antipad under trace 40 mils 36 mils
Radius of Antipad above trace 75 mils 40 mils
Radius of other antipads 75 mils 44 mils
Length of connector below below trace 31.5 mils 15.5 mils
Optimized design

Subtle
changes can
have
significant
impact on
performance
Performance Optimized Design
achieved with more ambitious cost function

Initial S11 goal


Comparison

S11 nominal design

16 dB
S11 optimized design
TDR/TDT Optimized Design
Eye diagram optimized design
Agenda
w Description of Device
w Simulation Set-Up
w Optimized Design
w Sensitivity Analysis
w What-If Analysis
w Conclusions
Sensitivity Analysis

w Investigate sensitivity to changes in


w Signal via radius
w Connector signal pin length
w Antipad radius under trace
w Antipad radius above trace
w Ground via distance
Signal via radius ? 1 mil

16
15

14 mil
Sensitivity to via radius

15GHz

5GHz
Signal pin length ? 4 mil

19.5 mil
15.5
11.5
11.5
15.5
19.5 mil
Radius antipad under trace ? 4 mil

32 mil 40 mil

36 mil
40

36
32
Radius antipad above trace ? 4 mil

36 mil 44 mil

40
44
40
36
Ground via distance ? 10 mil

90 mil

110
100 100 110

90
Agenda
w Description of Device
w Simulation Set-Up
w Optimized Design
w Sensitivity Analysis
w What-If Analysis
w Conclusions
What if…
… we trade return loss at lower frequencies for return loss at
higher frequencies by various techniques?
1. Flatter characteristic
Achieved by reducing stub length to zero
2. Improve at lower freqs
Achieved by reducing two main antipad sizes
What if ...
… the trace is on layer 3 instead of layer 10?

• Design optimized
for layer 10
• Now has a large
stub below layer 3
• Does this matter?
Launch to Layer 3 S-Parameters
The eye is closing
Try back drilling

Signal via

Layer 3
S11 < -20 dB over wide range
Before

After
The eye is open
Summary
w Connector launches onto PCB’s need to be designed
w Subtle changes in geometry can have significant effects
on performance
w Design depends on:
w Connector geometry (fixed)
w Board stack-up (fixed)
w Signal layer (fixed)
w Board manufacturing technology (fixed)
w Footprint
w 3D electromagnetic simulation is central to successful
launch design
Conclusion

“In high-speed PCB design, it is amazing how much extra


performance you can squeeze out of relatively low-cost
components when you optimize them with Ansoft HFSS”

Suresh Subramaniam
Sr. Design Engineer
Xilinx

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