1

Modeling and Analysis of DC-DC Converters Under Pulse Skipping Modulation

Santanu Kapat, Soumitro Banerjee, Senior Member, IEEE, and Amit Patra, Member, IEEE Department of Electrical Engineering, Indian Institute of Technology, Kharagpur - 721302, India

Abstract The technique to model dc-dc converters governed by Pulse Skipping Modulation (PSM), which is based on energy balance principle, is not accurate enough. In this paper, an attempt has been made to model them accurately using the discrete-time modeling approach. PSM scheme is essential to improve the efciency of a dc-dc converter during the light load condition, mainly during standby or sleep mode. Here, a dc-dc boost converter has been considered as an example. There are four different ways by which the inductor current and output voltage can evolve from one clock instant to the next for the PSM operation, i.e., four different regions. The discrete maps have been derived for those regions, which are piecewise smooth. The derived maps have been validated with the actual circuit behavior. For a specic range of the input voltage, it is shown that the entire map turns out to be a one-dimensional discontinuous map. The border collision bifurcation of the map is then analyzed. Stable higher periodic behavior is observed with a nonmonotonic variation in periodicity for a smooth parameter variation, but no chaos. The experimental investigation has been carried out and the results have been presented to validate the theoretical predictions.

I. I NTRODUCTION Improving power conversion efciency of dc-dc converters during light load condition, especially during standby or sleep mode, becomes an essential requirement for the portable battery powered applications such as mobile phone, laptop, PDA, digital camera etc. To extend their battery lives, power consumption needs to be minimized. Conventional pulse width modulation (PWM) scheme results in poor efciency during the light load condition, mainly due to the switching loss. Pulse frequency modulation (PFM) and pulse skipping modulation (PSM) are the alternative schemes to improve the efciency [1] [4]. TPS61200, FAN5308, MAX1771, Si9169 etc. are some of the commercially available power management ICs which adopt PSM/PFM during light load. PFM considers a change in switching frequency by keeping either the ON time or the OFF time of the power MOSFET constant. Hence it is difcult to design an input lter, thus giving rise to the problems of EMI. PSM considers few charged pulses (switching in between) with xed duty ratio followed by few skipped pulses (no switching) depending upon the status of the output voltage. Since the clock frequency of PSM operation remains xed, there is neither the problem due to EMI nor the difculty in input lter design. Over the past few years, several PSM control schemes have been reported [5] [8]. Each of them has its own advantages and disadvantages. Nevertheless, their modeling techniques are completely based on the energy

balance principle. Most importantly, the averaged approximation of the quantities under consideration may not hold true due to the large voltage ripple. Again, the assumption, that the inductor current is maintained within DCM in each clock cycle, may not remain valid over a large range of the input voltage and load resistance. Therefore, the available models fail to accurately capture the actual circuit behavior. Thus, the analysis remains inaccurate. In this paper, the discrete-time map [9] through stroboscopic sampling has been derived by observing the state at the beginning of each clock cycle. A dc-dc boost converter has been considered here. Depending upon the evolution of the inductor current and output voltage, four different regions are obtained, each of which has different functional form. The derived discrete maps are validated with the time domain simulation of the actual circuit. If the input voltage is lower than half of the reference voltage, it has been shown that the resulting discrete map takes the form of a one-dimensional discontinuous map. We analyze the border collision bifurcation [10], [11]. We carry out the experimental investigation and present those results. Beyond the region considered above, it can be shown that the map remains a discontinuous map with 1-D in one side and 2-D on the other side [12], [13]. The proposed approach can be generalized for other converters under PSM. II. M ODELING OF A PSM B OOST C ONVERTER We consider a PSM boost converter as shown in Fig. 1. It consists of a controlled switch S (MOSFET), an uncontrolled switch D (diode), an inductor L, a capacitor C, and a load resistance R. The gate of the MOSFET, S, is solely controlled by the PSM control logic using an externally generated clock of time period T and duty ratio D, which is xed. A. Overview of PSM Control Scheme PSM control scheme decides whether a charge pulse with xed duty ratio or a skipped pulse (no switching) is to be generated depending upon the status of the output voltage. This is achieved by obtaining an error voltage ve = (Vref vo ), as a difference between the output voltage vo and the reference voltage Vref . The error voltage ve is compared with the ground. For the nth clock period, if ve (nT ) 0, S turns on and remains on until t = nT + DT . Then, S turns off till the end of the clock period. If ve (nT ) < 0, S remains off throughout the clock period.

The duty ratio related to the PSM control scheme can be in the form d= D 0 if if vo (nT ) Vref vo (nT ) < Vref
+

L iL S C R +

(1)

vin

vo
_

The inductor current ramps up during the ON time and the system is said to be in Mode 1. During OFF interval, inductor current falls until it reaches zero and the system is said to be in Mode 2. If the inductor reaches zero before the arrival of the next clock, the operation is said to be in discontinuous conduction mode (DCM), else it is in the continuous conduction mode (CCM). When inductor current continues to be at zero, the system is said to be in Mode 3. There are essentially three modes representing three different subsystems described by the following sets of differential equations: The equations during Mode 1 dx = dt

CLR Q _ Q 7 4 7 4 PR D

_ +

Vref

Clock
Fig. 1. A dc-dc boost converter under PSM: iL = inductor current and vo = output voltage.

0 0

1 RC

x+

1 L

vin ;

(2)

B. Operating Region for PSM A PSM scheme is applicable at light load condition which is well within the DCM mode of operation. The border between CCM and DCM, in terms of R, can be formulated as [14] Rt = 2Vo L Vin (1 D)DT (8)

The equations during Mode 2 dx = dt

1 C

1 L 1 RC

x+

1 L

vin ;

(3)

The equations during Mode 3 dx = dt 0 0

1 RC

x+

0 0

vin ;

(4)

iL ; iL and vo are the inductor current and the vo output voltage respectively. The corresponding solutions are as follows: During Mode 1: where x = iL (t) = iL (t ) + vo (t) = vo (t )e

(tt ) RC

where Rt is the threshold value of the load resistance. Hence, for a PSM operation, the load resistance must satisfy R Rt . The external clock considered here, has a duty ratio D = 50% and time period T = 50s. The system parameters considered, are given below L = 60H, C = 470F, R = 80, Vref = 5V, Vin [1.2V, 4V]. The same parameter set has been considered for the theoretical analysis, MATLAB simulation and experimental investigation.

vin (tt ) L

(5)

During Mode 2: iL (t) vo (t) where

in k1 = iL (t ) vR ; k3 = vo (t ) vin ; iL (t ) k4 = C 2vin ; (t in k2 = iL (t ) voL ) + R 2 vR ; RC L in = vR + k1 e(tt ) cos (t t )+ k2 k1 (tt ) e sin (t t ) (tt ) = vin + k3 e cos (t t )+ k4 k3 (tt ) e sin (t t ).

III. S TRUCTURE OF THE D ISCRETE S TATE S PACE We obtain the discrete-time map through stroboscopic sampling by observing the state at the beginning of each clock cycle. Fig. 2 shows that there can be four different ways in which the state can evolve from one clock instant to the next under the PSM operation. As a result, the discretized state space is divided into four regions with four different mappings giving the complete model of the system. Let the inductor current and the voltage at the start of the nth clock pulse be in and vn , and those at the end of the clock period be in+1 and vn+1 respectively. A. Region 1 iL (t) = 0 vo (t) = vo (t )e In this region, all the Mode 1, Mode 2 and Mode 3 occur, as shown in Fig. 2(a), and the system enters into the DCM with vn+1 Vref . The nal value of the state vector of Mode 1 (vn , in ) becomes the initial condition for Mode 2, and the nal value of the state vector at the end of Mode 2 (vn , in ) is equal to the initial state vector of the discontinuous mode (Mode 3).

(6)

1 2RC ;

1 LC

During Mode 3:
(tt ) RC

(7)

where t indicates the initial time when a mode starts operating.

D. Region 4

iL in vn vo

m 1 m 2 i n+1
Vref

iL in vn vo

m1
Vref

m 2 i n+1 vn+1

vn+1

Mode 2 and Mode 3 exist in this region maintaining the sequence Mode 2 Mode 3 shown in Fig. 2(d). The following cycle needs to be skipped here, but the inductor needs to be completely discharged rst by forcing iL to zero within a time duration, T1 and then it continues to be at zero till the end of the clock. The discrete map can be approximated as in+1 = 0; vn+1 = T1 (1 + C
T1 2RC )in

DT
T

DT
T

+ (1

2 T1 2LC )vn

2 T1 2LC Vin .

(a): Case 1

(b): Case 2

(12)

where

iL i n vn vo
Vref

i n+1 vn+1

iL i n vn vo T1
T

i n+1 vn+1
Vref

b T1 = b+ 2a 4ac ; a = (in vn ); R b = 2C(vn Vin ); c = 2LCin .

IV. M ODEL VALIDATION The accuracy of the derived discrete-time maps needs to be validated. To accomplish that, we present the simulation results of the inductor current and the output voltage of the actual circuit along with those obtained from the discrete maps. Since the maps consider the status of the state variables at each clock instant, we assign them using the symbol, o. For a load resistance of 75, Fig. 3 and Fig. 4 show that the maps accurately capture the actual circuit behavior for the input voltages of 1.5V and 3.3V respectively. Also, Fig. 3 indicates the circuit behavior with a combination of Region 1 and Region 2, whereas Fig. 4 shows the combined behavior of Region 2, Region 3 and Region 4. Since those results are obtained by considering two extreme input voltage conditions, we can conclude the accuracy of the maps to be good enough. Hence, we can proceed further for their bifurcation analysis.
Output Voltage (V) Inductor Current (A) Model Validation: Vin = 1.5; R = 75. 0.6 0.4 0.2 0 0

(c): Case 3

(d): Case 4

Fig. 2. Possible evolutions of the inductor current and the output voltage between two clock instants (t = nT and t = (n + 1)T ) where: (a) Case 1 (Region 1): in = 0, vn Vref and in+1 = 0; (b) Case 2 (Region 2): in = 0, vn Vref and in+1 > 0; (c) Case 3 (Region 3): in = 0, vn > Vref and in+1 = 0 and (d): Case 4 (Region 4): in > 0, vn > Vref and in+1 = 0.

Then using (5)(7), we get the complete map in this region. The above map can be approximated by considering upto 2nd order damped sinusoidal terms and simplied as in+1 = 0 vn+1 = vn + where = 1
T RC
2 D 2 vin (vn vin ) .

(9)

T2 2R2 C 2 ;

T2 2LC .

0.5

1.5

B. Region 2 In this region, only Mode 1 and Mode 2 exist as shown in Fig. 2(b). From (5)(6), the discrete map can be derived in a similar way and represented as in+1 vn+1 where, a11 = 1 (1 D)2 ; a22 = (1 D)2 ; 2 a12 = (1D)T + (1D) ; L R 2 2 a21 = (1D)T (1D) 2T . C 2RC C. Region 3 In this region, only Mode 3 exists throughout the clock cycle as shown in Fig. 2(c). The discrete map can be represented as in+1 = in = 0; vn+1 = vn . (11) = a11 a21 a12 a22 in vn + b1 b2 Vin . (10)

2 2.5 Time (s)

3.5 x 10

4
3

4.99 0 0.5 1 1.5 2 2.5 Time (s) 3 3.5 x 10 4

3

Fig. 3. Model validation for an input voltage of 1.5V and load resistance of 75.

V. A NALYSIS OF THE PSM B OOST C ONVERTER For the specied input voltage range, we can show that the entire map turns out to be a one-dimensional discontinuous map comprising Region 1 and Region 3. Since we are interested only in the bifurcations that occur when a xed point crosses the border, the system is studied through the piecewise linear approximation in the neighborhood of the border. Vref

Output Voltage (V) Inductor Current (A)

Model Validation: Vin = 3.3; R = 75. 1 0.5 0 0

the border at = 0 and the xed point x collides with the R border at = l . Therefore, it is expected that two bordercollision events would occur as the parameter is varied smoothly.
3.5 x 10 4
3

0.5

1.5

2 2.5 Time (s)

L x n+1

R x n+1 = x n >0

5.05 5 0 0.5 1 1.5 2 2.5 Time (s) 3 3.5 x 10 4

3

xn _ <0
* xL
Fig. 5. The graph of the map: L and R indicate the side and right side of the border, solid line indicates the graph of the corresponding map and dashed line indicates the unity slope line.

Fig. 4. Model validation for an input voltage of 3.3V and load resistance of 75.

is the only border here and the piecewise linear map can be written as vn+1 = f (v; ) = avn + bvn + + l for for vn Vref vn > Vref (13)

where a, b, and l are obtained by linearizing (9) and (11) and represented as a= and b = ; l =
2 2 D2 vin D2 vin (2Vref vin ) ; = (Vref vin )2 (Vref vin )2 2 D2 vin . (Vref vin )

(14)

For the 1-D discontinuous map considered here, it can be shown that l , which depends on the input voltage, is always negative. a and b , both of which depend on the load resistance, always maintain, 0 < a < 1 and 0 < b < 1 irrespective of the load resistance range. depends on the input voltage which may be negative or positive. The quantity, + l can be expressed as +l =
3 D2 Vin + (1 )Vref . (Vref Vin )2

(15)

(17)

The piecewise map given in (13) clearly shows a 1-D discontinuous map with a discontinuity of length l [10]. The 1-D map, f (v; ), maps the real line 1 to itself and depends smoothly on the parameter . The border in the real line divides it into two regions. The map is piecewise continuous in the sense that it is continuous in (v; ) on each of the regions, but is discontinuous at Vref . It can be shown that the partial derivatives of the map and the length of the discontinuity at the border are independent of the parameter . A co-ordinate transformation can be applied by substituting, xn = vn Vref and xn+1 = vn+1 Vref , to move the break-point, Vref , into the origin. After transformation, the map, f (v; ) can be represented as xn+1 = where a = a; b = b; l = l; = (1 )Vref l. From (16), it is clear that after co-ordinate transformation, the slopes of the map in the either side of the border and the length of the discontinuity remain unchanged whereas the bifurcation parameter, changes. The state space is divided into two halves L (left) and R (right) which is shown in Fig. 5. The xed point in L is located at x = (1a ) and that in R L = The left half of the map intersects is located at with unity slope line for < 0 and the right half intersects for > l . This shows that the xed point x collides with L x R
+l (1b ) .

Equation (17) clearly shows that < l . Therefore, the entire analysis for the region of interest is reduced to two subcases, Subcase 1: < 0 and Subcase 2: l > > 0 which is discussed below. A. For < 0 Here, there is a stable xed point shown in the bifurcation diagram in Fig. 11. The experimental bifurcation diagram is shown in Fig. 12. It is restricted to = 0, which gives us the input voltage range of the actual circuit, Vin 1.45V . The simulated time domain waveform of the converters output voltage is shown in Fig. 6 which also conrms the period-1 operation. The eigenvalue of the Jacobian matrix can be shown to be inside the unit circle. Hence, the period-1 orbit is stable. In this region, the input voltage is not sufcient to provide enough energy to boost the output voltage to the desired value Vref , though the inductor current goes into DCM. Since there is no skipped pulse, it is not a feasible region for PSM operation. Therefore, it is necessary either to increase the duty ratio D to operate the converter under PSM or to handover the controller from PSM to PWM mode. B. For l > > 0 Here, there is no xed point, because x > 0 and x < 0. L R The orbits in the left half move towards the right and those in the right half move towards the left enabling stable high period orbits to exist. Since the map is piecewise linear in

a xn + b xn + + l

for for

xn 0 xn > 0

(16)

5.01

4.99 Clock Pulse

4.98 0.0341 0.0342 0.0343 Time (s) 0.0344 0.0345

Fig. 6.

Time domain simulation result for an input voltage of 1.45V.

either side, high periodic orbits cannot exist with all points in L or all points in R. The period-2 xed point must be of LR + type, with the points in L given by (b (1a b+l ) and the point ) in R given by
(a + +a l ) . (1a b )

events, the circuit undergoes an extra skipped phase (Region 3) followed by an usual pair of events. The incremental change in energy after each pair along with an extra skipped pulse forces output voltage to change accordingly, hence resulting in stable high periodic orbits. Similarly, it can be explained for a decrease in the input voltage. Hence, the variation of periodicity occurs in a nonmonotonic manner for a smooth parameter variation. For Vin = 2.25V , there exists a stable period-3 orbit. Fig. 9 and Fig. 10 show the simulation result and experimental result respectively for period-3 orbit consisting of alternative occurrence of a charge followed by two skipped pulses. Here, the injected energy during the charged phase is released during two consecutive skipped phases without leaving any excess or decit of energy. A small variation of parameter in either direction results in stable high periodic orbits in a similar way mentioned earlier. This period adding cascades are mainly due to the grazing for the above discontinuous map [15].
Output Voltage (V) Clock Pulse

Output Voltage (V)

This orbit will exist so long as (18)

(b + + l ) (a + + a l ) < 0 and > 0. (1 a b ) (1 a b )

5.006 5.004 5.002 5 4.998 4.996 4.994 4.992 0.0226 0.0228 0.023 0.0232 0.0234 0.0236 0.0238 Time (s)

There can be two types of period-3 orbits - LRR type and LLR type and the existence can be veried in a similar manner, but the expressions become cumbersome, and are thus excluded here. A few conclusions can be drawn from the above which are enumerated below. 1) Since a and b are both less than unity, if any highperiodic orbit exists it is stable, and there can be no chaotic orbit since the map is not stretching. 2) There is one range of parameter where period-2 orbit will exist, two range of parameter where period-3 orbit will exist, and similarly the period-n orbit will exist in (n-1) ranges of the parameter. 3) The ranges of occurrence of orbits of consecutive periodicity (e.g., period-2 and period-3) are not continuous here. Therefore, the occurrence of high-periodic orbits is non-monotonic. The bifurcation diagram shown in Fig. 11 indicates that for Vin = 1.92V , period-2 orbit exists. The eigenvalues of the Jacobian are found to be within the unit circle, hence stable. Fig. 7 and Fig. 8 show the simulation result and experimental result respectively for period-2 orbit consisting of alternative occurrence of a charge and a skipped pulse. There is a steady difference of 0.35V between simulation and experimental results, which is half of the diode voltage, not included in the discrete-time map. There is a synchronization between the injected energy during charge phase and the released energy during the skipped phase. After each pair, there will be neither any excess nor decit of energy, hence it continues to occur in that pair throughout. Now if the input voltage is slightly increased, then the above pair of events (Region 1 Region 3) continues to occur but a small amount of excess energy goes on accumulating at the end of each pair. When the accumulated energy becomes sufciently large after a large number of similar pair of

Fig. 7.

Period-2 operation for vin = 1.92V : simulation result.

Fig. 8. Experimental result for period-2 operation for vin = 2.27V where, Ch1 and Ch2 indicate the external clock and output voltage, respectively.

VI. C ONCLUSION In this paper, we accurately derived the discrete-time model of a PSM boost converter, which is piecewise smooth, divided into four regions, each with a different functional form. We

Output Voltage (V)

5.02

5.01 5.005

Output Voltage (V)

5.015

5.01 5.005 5 4.995

Clock Pulse

5 4.995 0.0298 0.03 0.0302 0.0304 0.0306 0.0308 0.031 0.0312 0.0314 Time (s)

1.5

1.6

1.7

1.8 1.9 2 2.1 Input Voltage (V)

2.2

2.3

Fig. 9.

Period-3 operation for vin = 2.23V : simulation result.

Fig. 11. Bifurcation diagram for the dc-dc boost converter considering the input voltage as a bifurcation parameter.

Fig. 10. Experimental result for period-3 operation for vin = 2.58V where, Ch1 and Ch2 indicate the inductor current and output voltage, respectively.

Fig. 12. Bifurcation diagram obtained experimentally for R = 80 and the input voltage as the bifurcation parameter where X axis represents the input voltage (V) and Y axis represents the sampled output voltage (V).

also found that the derived model accurately reects the actual circuit behavior with an error lower than 0.2%. Within a specic region, it is shown that it takes a 1-D discontinuous form, otherwise, a combination of 1-D and 2-D forms. We then analyzed the bifurcation behavior of the map along with the experimental conrmation. From the map considering a conventional PSM, we investigated a stable higher periodic behavior, where the variation in periodicity occurred nonmonotonically for a smooth parameter variation, but there was no chaos. The stability analysis considering other regions, has been left out due to the space limitation. Modeling and analysis of other types of converters can be done in the same manner. R EFERENCES
[1] G. Patounakis, Y. W. Li, and K. L. Shepard, A Fully Integrated OnChip DC-DC Conversion and Power Management System, IEEE J. Solid-State Circuits, vol. 39, no.3, pp.443-451, March 2004. [2] J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, A 4-uA Quiescent-Current Dual-Mode Digitally Controlled Buck Converter IC for Cellular Phone Applications, IEEE J. Solid-State Circuits, vol.39, no.12, pp.2342-2348, Dec. 2004. [3] H. W. Huang, H. H. Ho, C. C. Chien, K. H. Chen, G. K. Ma and S. Y. Kuo, Ditherng Skip Modulator with a Width Controller for Ultra-wide-load High-Efciency DC-DC Converters, IEEE Custom Integrated Circuits Conference, September 2006. [4] H. W. Huang, C. C. Chien, K. H. Chen and S. Y. Kuo, Highly Efcient Tri-Mode Control of Buck Converters with Load Sensing Technique, IEEE PESC06, June 2006.

[5] P. Luo, L. Luo, Z. Li, J. Yang and G. Chen , Skip cycle modulation in switching DC-DC converter, IEEE International Conference on Communications, Circuits and Systems, July 2002. [6] M. Telefus, A. Shteynberg, M. Ferdowsi and A. Emadi, Pulse Train control technique for yback converter, IEEE Transactions on Power Electronics, vol. 19, No.3, pp.757-764, May 2004. [7] P. Luo, Z. Li and B. Zhang, Analysis of PSM mode in switching converter and its improved mode, IEEE International Conference on Communications, Circuits and Systems, May 2005. [8] P. Luo, Z. Li and B. Zhang, A novel improved PSM mode in DC-DC converter based on energy balance, IEEE PESC06, June 2006. [9] S. Banerjee and G. C. Verghese, Eds., Nonlinear Phenomena in Power Electronics: Attractors, Bifurcations, Chaos, and Nonlinear Control, New York: IEEE Press, 2001. [10] P. Jain, S. Banerjee, Border collision bifurcations in onedimensional discontinuous maps, Int. J. Bifurc. Chaos 13(11), pp.3341-3352, 2003. [11] S. J. Hogan, L. Higham and T. C. L. Grifn, Dynamics of a piecewise linear map with a gap, Proceedings of the Royal Society A, Vol. 463, pp. 49-65, July 2006. [12] S. Parui and S. Banerjee, Border collision bifurcations at the change of state-space dimension, CHAOS, Vol. 12, No. 4, Dec. 2002. [13] P. S. Dutta, B. Routroy, S. Banerjee and S. S. Alam, On the existence of low-period orbits in n-dimensional piecewise linear discontinuous maps, Int. J. of Nonliear Dynamics, Springer, 2007. [14] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Dordrecht, The Netherlands: Kluwer, 2001. [15] M. D. Bernardo, C. J. Budd, and A. R. Champneys, Grazing and Border-Collision in Piecewise-Smooth Systems: A Unied Analytical Framework, Physical Review Letters, Vol.86, No.12, March 2001.