Electronics based on lowdimensional systems: nanowires and memristors

Wei Lu
University of Michigan Electrical Engineering and Computer Science

Memristor and Memristive Effects

Memristor: memory + resistor
Two-terminal resistive device with inherent memory. Device resistance not determined by the present voltage or current value, but by the history of the applied signals. Some argue it is the fourth basic circuit element along with resistor, capacitor and inductor.
Generalized memristor Eqs.

i = G ( w, v)v w = f ( w, v)

Can be used as memory or switch.

L. Chua, Memristor-The Missing Circuit Element IEEE Trans Circuit Theory, 8, 507, 1971 Strukov et al, The Missing Memristor Found, Nature 453, 80 (2008), HP High-Density Crossbar Arrays Based on a Si Memristive System, S. H. Jo, K.-H. Kim and W. Lu, Nano Lett. 9, 870-874 (2009). Ag/a-Si:H/c-Si Resistive Switching Nonvolatile Memory Devices, S. Jo, and W. Lu, IEEE NMDC 2006 Lu group EECS, UM

I-V, w - state variable. The rate of the state variable w is controlled by input signals

Digital Memristive Devices

Crossbar Structure
Top Electrode

Bottom Electrode

Switching Medium

Ag electrode
300

Measured Current (nA)

200

100

Sweep1 Sweep2 Sweep3 Sweep4 Sweep5 Sweep6 Sweep7 Sweep8 Sweep9 Sweep10

on
filament p-Si electrode Ag electrode

on

0 -2 -1 0

off off
1 2 3

Applied Bias (V)

p-Si electrode

Lu group EECS, UM

Endurance and Speed

50

Measured Current (nA)

0.5 0.4
10-8
Current (A)
Virgin 106 107 108

Endurance Cycles

40 30 20 10 0

on off on off

104, 106,

105 107

Output (V)
0 1 2 3
Bias (V)

0.3 0.2 0.1

10-10 10
-12

10-14 -2 -1

0.0 0 100 200 300 400

100 101 102 103 104 105 106 107 108

Endurance Cycle
> 10E8 W/E endurance Data retention > 7 years.

Time (uS)
Write/Read/Erase/Read pulse : 50nsec ,5V /50usec, 0.7V /100nsec, -3.5V /50usec, 0.7V
Lu group EECS, UM

Yield Map of 1kb Array

Jo et al. Nano Lett. 9, 870-874 (2009).

Lu group EECS, UM

Memristor Array Integration with CMOS

10x10 and 40x40 crossbar memory arrays fabricated on top of CMOS CMOS provides address mux/demux Crossbar array: 100nm pitch, 50nm linewidth with density of 10Gbits/cm2 Memristor crossbar

CMOS

Fabricated 10x10 crossbar array

Schematic of integrated device

Lu group EECS, UM

Analog Memristors
Abrupt Resistance Switching

Incremental Resistance Switching

Current (1uA)

1.0 0.8 0.6 0.4 0.2 Successive erase 0.0 -0.2 -0.4 -2 -1 0 1 2 3

Successive writings

: :
On 3 On 2 On 1

processes

Voltage (V)

Conductance can be changed incrementallyUM EECS,

Lu group

Analog Memristor in Neuromorphic Circuits

Memristor synapses form at each cross-point connecting CMOS-based preand post- synaptic neurons for neuromorphic circuits Crossbar network offers connectivity and function density comparable to bio logical systems

post-neuron

Snider, G. S. 2008 IEEE/ACM International Symposium on Nanoscale Architectures, pp 85-92.

pre-neuron

S.H. Jo, T. Chang, I. Ebong, B.B. Bhadviya, P. Mazumder, & W. Lu, Nano Lett. 10, 12971301 (2010). Lu group EECS, UM

Pulse Response
Potentiation synaptic weight enhanced Depression synaptic weight reduced

P: 3.2V, 300s D: -2.8V, 300s R: 1V, 2ms

Memristor synapse weight depends on the history of the P/D pulses. Conductance change depends on both the polarity and width Lu group of the applied pulses. EECS, UM

Achieving STDP with Memristor Synapse

Cells that fire together, wire together

Bio-system

CMOS neuron/memristor synapse

300nm

50 m

t = tpre - tpost
From G. Q. Bi, M. M. Poo, J. Neurosci. 1998. Inset: neuron image with permission from Kaech, S.; Banker, G. Nature Protocols 2006. S.H. Jo, T. Chang, I. Ebong, B.B. Bhadviya, P. Mazumder, & W. Lu, Nano Lett. 10, 12971301 (2010). Lu group EECS, UM

Enhancement of Memory through Rehearsal

Incoming Information

0.8

Rehearsal
0.6

I (uA)

STM
Transfer

LTM

0.4 0.2 0.0 -1.0 -0.5 0.0 0.5 1.0

Decay
60 0.15

Time (sec)
0.8

40

0.10

(sec)

0.6
I (uA)

(sec-1)

20

0.05

0.4

0.2
0 0 5 10 15 20 25 30 35 40 0.00

# Training

0.0 0.0 0.1 0.2 0.3

Retention improved by 50 times

Time (sec)

Lu group EECS, UM

Semiconductor Nanowires
Vapor-Liquid-Solid (VLS) growth process
SiH4 Au Si+2H2 Si Si

cluster formation

nucleation and growth

nanowire

Semiconductor Nanowires, W. Lu and C. M. Lieber, J. Phys. D.: Appl. Phys. 39 R387-R406 (2006). W. Lu, and C. M. Lieber, Nature Mater., 6, 841-850 (2007). W. Lu, P. Xie and C. M. Lieber, IEEE Trans. Elec. Dev., 55 (11), 2859-2876 (2008).

Lu group EECS, UM

Nanowire-Based TFT: Fabrication

Fabrication Steps: (a) SEM image

Aligned Nanowire Film is contact printed onto a glass substrate Transparent & flexible circuits on glass/plastic substrates

10 m

Lu group EECS, UM

Transparent Nanowire TFT: Performance

Ion = 280 uA (6 mA/mm)
fT = 35 MHz fmax= 110 MHz

High On/Off ratio

Ids Igs
On / Off > 107 S = 330 mv / dec
Lu group EECS, UM

Nanowire Heterostructures & Superlattices

d=10nm
L = 1 um

axial growth

radial growth core/shell nanowire

Vd = -100 mV = 470 cm^2/Vs

Lu, Xiang, Timko, Wu & Lieber, PNAS 102, 10046 (2005) Xiang, Lu, Hu, Wu, Yan, & Lieber, Nature. 441, 489-493 (2006).

600 nm

Nanoelectronics from the Bottom-Up, W. Lu, and C. M. Lieber, Nature Mater., 6, 841-850 (2007). Nanowire Transistor Performance Limits and Applications, W. Lu, P. Xie and C. M. Lieber, IEEE Trans. Elec. Dev., 55 (11), 2859-2876 (2008).

Lu group EECS, UM

Vertical growth of Ge NWs on Si (111)

~ 84 % vertical yield

10 m ~ 98 % vertical yield Ge NW

1 m After Au catalyst removal

Si substrate

1 um

250 nm

Lu group EECS, UM

Vertical NW FET with GAA Structure

Ni top contact

Spin-on glass top spacer Gate p+ Si (111) VG = 2 to -2V, 0.5 V step Al2O3 Gate dielectric

Cr removed from upper part of NW Conformal Cr gate

Ready 500 nm for top contact

Lu group EECS, UM

Tunneling FET Utilizing the Sharp Ge/Si Interface

OFF State CB p-type Ge NW n+ Si VB

n+ Si (111)

p-type Ge intrinsic Ge

ON State

e-

Si-Ge heterojunction
Smaller band gap of Ge higher ON current Abrupt doping profile Band line-up of Si and Ge suitable for tunneling PFET Ge/Si p/n+ diode
Lu group EECS, UM

Acknowledgements
Grad students:
*Sung-Hyun Jo Kuk-Hwan Kim Sid Gaba Ting Chang Shin-Hyun Choi Patrick Sheridan *Eric Dattoli Wayne Fung Seok-Youl Choi Lin Chen *Woo Hyung Lee

National Science Foundation (ECS-0601478, CCF-0621823, ECCS-0804863, CNS-0949667, ECCS-0954621). U-M Rackham Junior Faculty Research Grant Engineering Translational Research (ETR) Grant DARPA SyNAPSE program Industry partners

PostDocs:
*Dr. Zhongqing Ji * Dr. Qing Wan Dr. Yuchao Yang

* alumni

Lu group EECS, UM