Outlook on CMOS Device Scaling

Meikei Ieong IBM SRDC & Research

Acknowledgments
R. Amos, K. Chan, G. Cohen, R. Dennard, M.Fischetti, D. Frank, K. Guarini, E. Gusev, P. Oldiges, L. Huang, E. Jones, S. Koester, S. Laux, T. Ning, K. Rim, P. Solomon, Y. Taur, C. Wann, J. Welser Device Fabrication: Advanced Silicon Technology Laboratory DARPA AME Microelectronics at its Limits (N66001- 97- 1- 8908)
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Outline
CMOS Device Performance Trend/Challenges Overcoming the limits by:
Innovation in Materials Novel Device Structures

Double-gate FET Performance Analysis Conclusions

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Silicon Technology
Moores 1975 Prediction
[After Gordon Moore, IEDM 75]

Enabled by 1) Lithography 2) Device Fab. Tech.

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Evolution of Silicon Logic Devices

CMOS has been the preferred digital logic technology platform because of power and scaling properties. Primary direction in the new millennium:
further scaling of CMOS.
After T. Ning, IRPS2000

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CMOS Performance Metrics

Delay Gate & Interconnect Switched Energy Cload Vdd/Idsat Cload Vdd2

Energy Delay product Cload2Vdd3/Idsat Cload = Cgate + Cj + Cwire

Idsat ~ mu * Cgate * (Vdd-Vt) * Vdd / L
Where mu is the mobility, Cgate=eps LW/tinv is the gate cap, and Vt is the threshold voltage.

To meet the overall performance target requires design trade off:

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Device Scaling Basic (I)

Scaled Device
Voltage, V /
WIRING
R. Dennard IEEE JSSC, 1974

SCALING:
Voltage: Oxide: Wire width: Gate width: Diffusion: Substrate: V/ tox / W/ L/ xd / * NA

tox/
GATE
n+ source

W/
n+ drain

L/

xd/

p substrate, doping *NA

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Device Scaling Basic (II)

Scaled Device
Voltage, V /
WIRING
R. Dennard IEEE JSSC, 1974

SCALING:
Voltage: Oxide: Wire width: Gate width: Diffusion: Substrate: V/ tox / W/ L/ xd / * NA

tox/
GATE
n+ source

W/
n+ drain

L/

xd/

RESULTS:
Higher Density: *2 Higher Speed: * Lower Power: 1/2 / per circuit Power Density: Constan
8

p substrate, doping *NA

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Power Supply Voltage Projections for CMOS

Vdd non-scaling
Device/circuit speed Compatibility

Vdd scaling
chip power Reliability Allow further scaling of device size for speed and density
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After T. Ning, IRPS2000

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Equivalent Gate Oxide Thickness Trends

Thin gate oxide has significant performance advantage Limit by direct tunneling and reliability concerns High-k dielectric and new gate electrodes are needed
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CMOS Scaling Trend

Technology node (nm) Vdd (V) Tinv (Electrical) (A) Tox (Physical) (A) Nominal Lg* (nm) 180 1.5 30 20 100 130 1.2 25 16 70 100 1.0 20 12 50 70 0.8 16 8-11 35

(*) Minimum Lg is shorter (function of tolerance), ~ 25 nm.

80 % reduction in power supply voltage and gate oxide. 70 % reduction in lithography and channel length.
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Bulk CMOS at the Limits

Lgate=35nm Lchannel=25nm

Y Taur, IEDM Taur,

Ideas: Non-uniform super abrupt halo. Channel-length dependent channel doping.

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Challenges in junction technology Extremely difficult to achieve super-abrupt and localized halo profile. Parasitic capacitance, mobility, and junction leakages.
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Challenges

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Limits in CMOS Technology

CMOS technology is approaching its limit. Innovative research on new materials, processes, and device architectures are needed. It is difficult to achieve transistor performance gain for CMOS gate-length scaled to 25 nm.
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Innovation in Gate Stack

High dielectric constant materials for gate dielectric to alleviate gate leakage problem. Metal-gate to address gate activation issues in poly-silicon gate.

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High-k Dielectric Leverages

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Gate Dielectric Trend

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From Sio2 to High-k Dielectric

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Advanced Gate Electrode

Motivation Requirements Chemical Stability Integration
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- Poly-silicon depletion effect due to limited doping activation degrades intrinsic device performance and gate resistance. - Dual work function metals are needed to achieve low threshold voltages. - Many elemental metals form silicides if the dielectric has SiO2. - Metal diffusion - Limits processing temperature - New integration scheme, such as replacement-gate process may be needed.
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Device Innovation

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Materials/Devices Innovation
Materials:
Strained Silicon CMOS (SS-CMOS)

Device Structures:
Silicon-on-insulator (SOI) Double-gate

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Strained Silicon CMOS

Si layer pseudomorphically grown on relaxed SiGe is under biaxial tensile strain. Tensile strain causes changes in silicon band structure. ! band splitting and deformation. Electron and hole channels for MOSFETs are formed in the top strained Si layer. Underlying SiGe layer supplies strain to the Si layer.

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SSCMOS Mobility Enhancement

Both electron and hole mobilities are enhanced in in-plane directions due to suppressed intervalley/interband scattering and reduced effective transport mass. n-FET and p-FET mobility enhancements have been demonstrated experimentally. (enhancement by up to ~80%).

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SS-CMOS Device Design Issues

Source: K. Rim, IBM

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Process Integration Issues

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Source: K. Rim, IBM

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Silicon-on-insulator (SOI)

G BOX

SOI
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Double-gate Performance Analysis

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Modeling Approach
Self-consistent solution of Schrodinger, Poisson, Continuity, and external circuit equations (including mixed-mode capability): The quantized carrier is obtained by solving many 1D Schrodinger equations along the 2D MOSFET channel.
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Source: Philip Wong

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Conclusions
There is plenty of performance to be milked from nanoscale MOSFET. It is both challenges and excited to implement such performance options into future electronic systems.

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