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Microelectronic Engineering 85 (2008) 10391042 www.elsevier.com/locate/mee

RF MEMS capacitive switch on semi-suspended CPW using low-loss high-resistivity silicon substrate
M. Fernandez-Bolanos a,*, J. Perruisseau-Carrier b, P. Dainesi a, A.M. Ionescu a
b a Electronics Laboratory, Ecole Polytechnique Federale de Lausanne (EPFL), 1015 Lausanne, Switzerland Laboratory of Electromagnetics and Acoustics, Ecole Polytechnique Federale de Lausanne (EPFL), 1015 Lausanne, Switzerland

Received 12 October 2007; received in revised form 14 January 2008; accepted 17 January 2008 Available online 8 February 2008

Abstract A high capacitive ratio RF MEMS switch, with low-actuation voltage is designed, fabricated and experimentally validated on highresistivity silicon (HRS) substrate. Thanks to very good fabrication control of all steps and to the high dielectric constant of TiO2, a down/up capacitive ratio close to 200 is achieved with 8 V pull-in. It is also demonstrated that, using a passivated-surface HRS and semi-suspended conductors on air, the microwave losses in the CPW line are as low as 0.1 dB/mm at 20 GHz. The reported RF MEMS shunt capacitor is expected to serve as core device for phase shifting applications in the 1020 GHz range, both for switching operations and as a variable capacitor in distributed MEMS transmission lines (DMTLs). 2008 Elsevier B.V. All rights reserved.
Keywords: RF MEMS switch; Semi-suspended CPW; High-resistivity silicon (HRS); Microwave losses; Surface-passivation HRS; Titanium oxide (TiO2)

1. Introduction RF MEMS capacitors have been investigated for application in distributed MEMS transmission lines (DTMLs) phase shifters, both analog [1] and digital ones [2]. The idea is to periodically load a coplanar waveguide (CPW) with voltage-controlled varactors (two-state digital capacitors for digital DMTLs [2]), in order to tune the distributed capacitance, the phase velocity and the propagation delay in the line. The rst optimized loaded-line phase shifter was implemented using diodes [3]. However, diodes present low performances at high frequencies (RF), especially in terms of losses, tuning linearity and intermodulation distortion. RF MEMS capacitors overcome these problems, although, they might have limited tuning range and slower switching; however, these are not limiting factor for most phase shifter applications.
Corresponding author. Tel.: +41 21 693 4607; fax: +41 21 693 3640. E-mail addresses: montserrat.fernandez-bolanos@ep.ch, mon tsefb81@hotmail.com (M. Fernandez-Bolanos). 0167-9317/$ - see front matter 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.01.093
*

This paper addresses an electrostatically actuated RF MEMS capacitive shunt switch concept [4] (Fig. 1), which solves the limitations of functionality of digital capacitors [2] and adds two novel improvements: (i) under-etching of the substrate to reduce microwave losses and (ii) the use of titanium oxide (TiO2), as dielectric (er = 20), to achieve a high capacitive ratio at a low-actuation voltage. This device enables the combination of high-performance RF MEMS switching capabilities (for signal routing in recongurable RF front-end systems [5] or switched-line phase shifters [6]) with the DMTLs tuning capacitors requirements. 2. Low loss substrate study: Under-etching process of surface-passivated high-resistivity silicon substrate (HRS) There is a special need for careful selection of the substrate in RF operation, due to its determining inuence on the losses. Quartz is commonly known as the ideal substrate at microwave frequency thanks to the fact that it is an insulating, and very low loss, material. The main disadvantage is its CMOS non-compatibility.

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Aluminum Ground planes
50 45 40

Aluminum movable top electrode Platinum fixed bottom electrode

Capacitance [pF]

Standard HRS

35 30 25 20 15 10

TiO2

Passivated HRS Quartz

-40 -20 0 20 40

RF Signal Partially suspended conductors HR Si substrate

5 0

Voltage [V]

Fig. 1. Schematic view of the RF MEMS capacitive shunt switch.

0.14 0.12

Standard HRS & under-etching

Standard HRS

Concerning standard HRS substrates, a limitation is the non-negligible DC leakage current sensitive to DC bias, since HRS is not an insulating material [7]. Indeed, a silicon oxide (SiO2) layer is placed between the substrate and the metallization. However, this results in the formation of an inversion layer of electrons in the SiSiO2 interface. This induced charge layer is voltage-dependent and increases microwave losses. To alleviate this problem, a highly defective Si as amorphous silicon (a-Si) can be grown on the Si surface, preventing the accumulation of electrons [8]. Fig. 2a shows that a DC bias aects the MOS capacitance on standard HRS, in contrast with quartz and passivated HRS, where no such eect is observed. This conrms the presence of charges at the interface of the standard HRS and shows the eectiveness of passivated HRS. Fig. 2b shows simulated and measured microwave CPW losses on quartz, standard HRS and passivated HRS. Quartz substrate losses are negligible and measured losses can thus be attributed to the metal alone. This allows to extract the conductivity of the Aluminum (Al) CPW by comparison with Ansoft HFSS simulations (table in Fig. 2b). As the Al deposition method is identical for all substrates, its conductivity can be assumed to be the same. Measured losses of standard HRS are much larger than simulated ones with the announced Si resistivity (10 kX cm). This phenomenon is linked with the formation of conductive surface channels at the SiSiO2 interface. In fact, measurements correspond to simulations with a Si resistivity of 0.7 kX cm, namely, 13 times lower. The passivated HRS signicantly reduces the losses (Fig. 2b). Measurements now t the simulations with the specied Si conductivity (10 kX cm), and hence demonstrates the validity of the passivation method. Finally, to further reduce the microwave losses in the HRS substrates, an under-etching process was developed to realize semi-suspended conductors in air. In a CPW, most of the dielectric losses occur in the region close to the edges of the CPW, as a result of the large electric eld density. Therefore, by etching the Si under the conductor, the substrate is replaced by an ideal dielectric, namely, air. First measure-

[dB/mm]

0.1 0.08 0.06

0.1dB/mm
Passivated HRS
HFSS Measurement 13 14 15

Passivated HRS & @ 20GHz under-etching Quartz

16 17 18 19 20

0.04 12

Frequency [GHz]

Parameters 1. Quartz Quartz Aluminum 2. Si-Standard HR Si Resisitivity 3. Si-Passivated HR Si Resisitivity

Ideal 0 S/m 3.7 107 S/m 0.01 S/m >10k.cm 0.01 S/m >10k.cm

HFSS simulation 0 S/m 3.2 10 7 S/m 0.14 S/m 0.7k.cm 0.01 S/m 10k.cm

Fig. 2. (a) CV curve measured at 1 MHz of the substrate MOS capacitors for Quartz, standard HRS and passivated HRS. (b) Losses measurements and Ansoft HFSS simulations of a CPW in: Quartz, standard HRS and passivated HRS before and after Si under-etching. The Table shows the ideal and simulated parameters in order to t with the measurements.

ments results show the improvement obtained with a 4 lmlateral air cavity (dashed lines in Fig. 2b). Moreover, simulations indicate that further enlarging the air cavities would reduce the losses, eventually reaching those of quartz. Thus, under-etching of surface-passivated HRS substrate could become a close-to-ideal substrate for RF with minimum losses and all the well-known advantages of Si, especially when CMOS compatibility is required. 3. Fabrication process ow The six-mask process described in Fig. 3 is used to fabricate the RF MEMS capacitive shunt switch using 10 kX cm P-type Si substrate. The process starts with 300 nm LPCVD a-Si passivation layer and 500 nm of sputtered SiO2 as insulator.

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X profile
Y profile
1. LPCVD -si (300nm), SiO2 sputtering (500nm) and Platinum evaporation (100nm), patterning and dry etching.

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500nm

5. PI2611 polyimide sacrificial layer deposition (15m)

Y profile
X profile
2. Titanium oxide evaporation (200nm) patterning and dry etching in plasma CF4 6. Polyimide chemical mechanical polishing (CMP) and anchor patterning

600nm

50 m

3. Pure Aluminum sputtering (3m), pattern and dry etching in fluorine chemistry.

7. Ion surface cleaning RF-etch. Pure aluminum sputtering (3m) and dry etching.

10 8

1 2 3

Voltage [V]

6 4 2

10um

Device 1 2 3 4

Cr = Cdown /Cup 144 196 178 105

15 20

Pull-in V 10 8 7 6.5
25 30

4. SiO2 anisotropy dry etching and silicon substrate isotropic dry etching.

8. Isotropic dry releasing in plasma O2 polyimide stripper.

Fig. 3. RF MEMS capacitive shunt switch process ow.

0 0 5 10

Next, 100 nm of evaporated platinum (Pt) is deposited in vacuum to minimize contamination. A smooth 200 nm of TiO2 is sputtered at low temperature and patterned with high selectivity in CF4 plasma. The Pt (bottom electrode) and TiO2 dielectric surface roughness are critical not only for achieving a high capacitive ratio, but also for the RF performance and lifetime of the switch. CPWs are made of sputtered Al with a measured conductivity of 3.2 107 S/m (extracted from measurements, see Section 2). The thickness of the Al (3 lm) is chosen to be at least three times larger than the skin depth at 10 GHz ($0.85 lm). Al also acts as structural material to suspend the top electrode. Then, SiO2 is selectively etched out of the CPW lines. It follows by the conductor under-etching step. To achieve air cavities of 4 lm lateral/8 lm depth, a Si isotropic dry etching is performed (Fig. 4). Sacricial thick polyimide PI2611 (15 lm) is span onto the wafer. In order to atten the

Time [s]

0 -5

Sparameters [dB]

Isolation [dB]

-10 -15 -20 -25 -30 10 12 14 16 18

-0.5

-1

-1.5

Frequency [GHz]

Fig. 5. (a) SEM picture of the released switch and optical prolometer measurement of the Al suspended beam. (b) Measurements of voltage-vs.time with a constant current for dierent spring constant (k) devices. (c) Sparameters measurements, S21 for the up/down states.

Fig. 4. Scanning electron microscope (SEM) images. Left: zoom on the semi-suspended conductor on air. Centre: a general view of the RF MEMS switch. Right: the FIB cross section of the released structure.

Insertion Loss [dB]

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device, the sacricial layer needs to compensate for the $12 lm device topography and chemical and mechanical polishing (CMP) is done using neutral ph silica slurry. The topography is successfully planarized to less than 200 nm. An additional mask is used to etch the rest of the PI on top of the CPW ground planes to ensure a good anchoring contact. An ionic surface cleaning RF-etch is done before sputtering the 3 lm pure Al. The top movable electrode is patterned and etched in uorine plasma. Finally, the structure is released as depicted in Fig. 4, using isotropic O2 plasma. An optical prolometer measurement after releasing of the switch shows (Fig. 5a) an excellent atness and, practically, a quasi zero-stress metal membrane (<200 MPa). 4. Electrical characterization

the pull-in voltage (which corresponds to abrupt change in the slopes), and the capacitive ratio (relation between slopes) can be extracted. S-parameter measurements (Fig. 5c) of the RF switch indicate insertion loss of <0 5 dB and an isolation of >20 dB at 20 GHz. 5. Conclusions The fabrication process and rst characterization results of a RF MEMS TiO2 capacitive switch loaded on a semisuspended CPW on air using passivated-surface HRS were reported. DC electrical characterization of the capacitive switch demonstrates an excellent Cdown/Cup ratio. RF characterization shows at 20 GHz an attenuation of 0.1 dB/mm in the line, an insertion loss of <0.5 dB and an isolation >20 dB of the switch. References

The fabricated RF MEMS switches are characterized by the current drive actuation, which consists of the control of the charge delivered to the switch instead of applying a voltage. First measurements validate the current drive electrostatic switching behavior: with a Cup of 60 fF and Cdown close to 10 pF, a capacitive ratio of 196 is achieved in 8 V pull-in, thereby demonstrating the usefulness of the TiO2 layer. According to the authors [9], this mode of current actuation presents advantages in terms of power consumption, in addition to extending the tuning range above the 1/ 3 barrier. Fig. 5b depicts the voltagetime curve of dierent measured capacitive switches. From these measurements both

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