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Intel 8086 Microprocessor Architecture

Program, data and stack memories occupy the same memory space. The total addressable memory size is 1MB. As the most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory. To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory (see the "Registers" section below). 16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte 32-bit addresses are stored in "segment:offset" format as: address: low-order byte of segment address+1: high-order byte of segment address+2: low-order byte of offset address+3: high-order byte of offset Physical memory address pointed by segment:offset pair is calculated as: address = (<segment> * 16) + <offset> Architecture 8086 has two blocks BIU and EU. The BIU handles all transactions of data and addresses on the buses for EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. EXECUTION UNIT Decodes instructions fetched by the BIU Generate control signals, Executes instructions. The main parts are: Control Circuitry Instruction decoder ALU Features It is a 16-bit up. 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB). It can support up to 64K I/O ports. It provides 14, 16 -bit registers. Word size is 16 bits and double word size is 4 bytes. It has multiplexed address and data bus AD0- AD15 and A16 A19. It requires single phase clock with 33% duty cycle to provide internal timing. 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetches up to 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package. Address ranges from 00000H to FFFFFH Memory is byte addressable - Every byte has a separate address. Program memory - program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction.

Data memory - the 8086 processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment). o Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access. Stack memory can be placed anywhere in memory. The stack can be located at odd memory addresses, but it is not recommended for performance reasons (see "Data Memory" above).

Reserved locations: o o 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment:offset. FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address.

Intel Pentium 4 Family

Intel Pentium 4 is a family of high-performance microprocessors that succeeded Pentium III family. Pentium 4 CPUs are based on new NetBurst micro-architecture, which differed significantly from P6 micro-architecture used in Pentium II/Pentium III microprocessors. As an overall CPU performance is proportional to its frequency and its efficiency, to achieve better performance levels many micro-architectures, including P6, strike a delicate balance between faster CPU frequencies and improved efficiency. The NetBurst microarchitecture used different approach - it attempted to improve performance primarily by increasing CPU frequency, often at at the expense of efficiency. One of key elements in this approach was "Hyper-Pipelined Technology" - 20-stage pipeline (not counting decoder stages), that was significantly longer than in previous generation of Pentium processors. While longer pipelines are less efficient than shorter ones, they allow CPU core to reach higher frequencies, and thus increase CPU performance. To improve efficiency of very deep pipeline the Pentium 4 processors included new features: Trace Execution Cache, Enhanced Branch prediction, and Quad Data Rate bus. Intel Pentium 4 CPUs also included 144 new SIMD instructions called SSE2. Because the first generation of Pentium 4 processors, based on Willamette core, proved to be performing not significantly faster, and sometimes slower than the fastest Pentium III microprocessors, Intel added more efficiency improvements to subsequent Pentium 4 core generations - larger size of level 2 cache, faster FSB frequency, SSE3 instruction set, and Hyper-Threading technology. Other features that were eventually added to the family are 64-bit instruction set, and Virtualization technology. First Pentium 4 microprocessors, based on Willamette and Northwood cores, as well as some Prescott processors, were referenced by their speed. To differentiate between Pentium 4 CPUs running at the same frequency, but having different features, Intel used one letter suffix, appended to CPU frequency: * A - Northwood microprocessors with 512 KB L2 cache (for frequencies 2 GHz and lower), or Prescott CPUs with 1 MB L2 cache (for frequencies higher than 2 GHz). * B - processors with 533 MHz FSB frequency. * C - processors featuring Hyper-Threading technology and 800 MHz FSB. * E - Prescott CPUs with 1 MB L2 cache. Later generations of Pentium 4 CPUs, starting from Prescott core, were assigned processor numbers that uniquely identified processor frequency and features. Please see Intel desktop processor numbers page for more information. "Pentium 4" brand was used only for high-performance single-core desktop and mobile microprocessors. Server-class CPUs that were built on NetBurst microarchitecture were branded Xeon and Xeon MP. Low-cost NeBurst microprocessors were manufactured under "Celeron" brand. Dual-core NetBurst-based microprocessors were branded Pentium D. All Pentium 4s were manufactured in three types of packages - 423-pin PGA package for socket 423 motherboards, 478pin micro-PGA package that worked in socket 478 motherboards, and pin-less 775-land LGA package that required socket775 motherboards. Socket 478 package was used by both desktop and mobile microprocessors, while two other packages were designed for desktop systems only.

Desktop Pentium 4 Willamette

This processor was manufactured in second half of May of 2000 - one month before Intel announced Pentium 4 brand name and six months before the Pentium 4 family was officially launched. The processor is not marked with specific speed; the part number specifies speed as 1.X GHz.

Desktop Pentium 4 Northwood

Next Pentium 4 core - Northwood - was a die shrink of Willamette core. Based on 0.13 micron technology, Northwood microprocessors had lower voltage, and, as a result, lower power consumption than Willamette CPUs. The size of level 2 (L2) cache in this core was increased to 512 KB, besides that there were no major changes in microprocessor microarchitecture. Bigger L2 cache gave Northwood processors 5% - 20% speed boost over Willamette processors. Front-side bus frequency in first Northwood microprocessors didn't change. Over time the bus frequency was increased to 533 MHz, and finally to 800 MHz.

Desktop Pentium 4 Prescott

More than just a die shrink of the previous Northwood core, Prescott core was revamped with the goal of reaching higher frequencies and further increasing processor performance. To achieve higher frequencies the processor pipeline was increased to 31 stages. To improve processors performance the sizes of level 1 data cache and level 2 cache were increased, and different parts of the core were optimized - branch prediction enhanced, execution time of a few instructions reduced, data pre-fetching improved, etc. Support for new SSE instructions was added to all Prescott-based Pentium 4 CPUs. More recent Prescott processors also supported EM64T (64-bit technology), Execute disable bit and Virtualization features.

Desktop Pentium 4 Cedar Mill

Cedar Mill, the last single-core Pentium 4 core, was built on 0.065 micron technology. Micro-architecture of this core didn't change from previous Prescott core, therefore performance-wise they are as fast as Prescott CPUs. The only advantage of Cedar Mill processors over Prescott processors is their lower power consumption. For instance, Pentium 4 Cedar Mill 3.6 GHz has 30 Watt lower Thermal Design Power (TDP) than Pentium 4 Prescott 3.6 GHz.

Desktop Pentium 4 Extreme Edition

Started as a direct competitor to Athlon 64 FX family, Pentium 4 Extreme Edition family comprises of the best performing Pentium 4 microprocessors. Being socket-compatible with microprocessors from other Pentium 4 families, Extreme Edition CPUs incorporated such features as very large level 3 cache or increased Front-Side Bus frequency to achieve somewhat better performance than comparably clocked Pentium 4 processors. Small increase in CPU performance came at a hefty price - official price of all newly introduced Extreme Edition processors was $999 per piece. Pentium 4 EE family was ultimately replaced by a family of dual-core processors branded as "Pentium Extreme Edition"

Mobile Pentium 4-M

The first Pentium 4 family of mobile microprocessors was Pentium 4-M. All processors in this family had 0.13 micron Northwood core, 400 Mhz effective Front Side Bus (100 MHz quad-pumped bus) and 512 KB level 2 cache. Intel Pentium 4-M microprocessors had lower core voltage and lower thermal design power than desktop Northwood CPUs. Mobile Pentium 4-Ms also included speed-step technology and Deeper Sleep mode. The microprocessors were manufactured in 478-pin micro-PGA package without integrated heatsink. Mobile Pentium 4-M processor family was replaced by mobile Pentium 4 family.

Mobile Pentium 4
Mobile Pentium 4 was the last generation of mobile microprocessors with NetBurstmicroarchitecure. The mobile microprocessors were based on two Intel Pentium 4 cores - Northwood and Prescott. The processors had either 512 KB (Northwood core) or 1 MB (Prescott core) level 2 cache, and 533 MHz Front side Bus. Some Northwood mobile CPUs and all Prescott processors included Hyper-Threading technology. Although these processors had the same power-saving features of Pentium 4-M microprocessors, power consumption of these CPUs was significantly higher than the one of Mobile Pentium 4-M processors. In fact, the power consumption of Prescott-based mobile Pentium 4 was so high, that it hardly could be considered a "mobile" processor.

Functions of a Microprocessor

Microprocessors are small chips that carry out all the roles of CPU. It is a device that allows a computer to work. It performs in same distinct way whether incorporated on laptops or servers. The first ever microprocessor was introduced by Intel in the year 1971. The processor was called Intel4004 and carried out most simple operations related to mathematics. It is the size of a chip which contains billions of various transistors. The year after 1970s saw 4 bit and 8 bit microprocessors. They have the power to calculate mathematical operations using algorithms. Due to floating point processors, the microprocessors can conduct any operation or computation accurately at the earliest. The microprocessor does enable to transfer data from one location to another. The information that you require is shifted to the hard drive in split seconds. The microprocessors are considered as devices that make instant decisions and carry out multiple commands with the help of the decisions. The register and coder do help the microprocessor to carry out the required duties and instructions. The two memories are responsible for any microprocessor to function properly. Firstly, the read only memory and secondly, random access memory, which together constitute the microprocessor. ROM as a program includes a finite set of instructions that is combined with a constant set of bytes. RAM includes a pre-defined set of bytes that can store a limited amount of information. The other function of microprocessor is to conduct and carry out executions in all kinds of formats be it data, video or audio. However, we have already entered the digital age whereby microprocessors sometimes do not exist. The recent developments in the field of technology, medicine, communications in the twenty first century has lead to various innovations in microprocessors. Microprocessors have improved our lifestyle due to new enabled, lighter and improved hand held machinery.

Basic operation of microprocessor

A microprocessor manipulates data in a computer system. The central processing unit acts as the brain of a computer and consists of one or more microprocessors made up of several thousand transistors on a single integrated circuit. The microprocessor works in conjunction with other parts of the computer to compute arithmetic and logic functions to handle tasks using an instruction set to perform all. Input and Output The microprocessor accepts input from devices, such as a mouse, keyboard or scanner, and performs a function on that data. It makes a decision based on the data, the microprocessor computes the information and then it sends the results to the output devices, such as a monitor or printer, as readable information for the user. For example, if a user using a word processor presses "m" on the keyboard, the microprocessor will accept that and send the letter "m" to the monitor. Arithmetic Logic Unit The arithmetic logic unit gathers information as input from the CPU registers and operands and then does the arithmetic operations (addition, subtraction, multiplication and division) and logic operations (AND, OR and XOR). During data processing, the ALU tests conditions and prepares to take different actions based on results. The ALU also gathers data from additional sources, including number systems, instructions, timing and data routing circuits, such as adders and subtracters. Memory The microprocessor accesses and stores binary instructions into memory, or circuits that store bits. Random access memory is a control memory that uses registers to temporarily store data. The microprocessor stores volatile data used by programs in RAM. Read-only memory stores data permanently on chips with instructions built in. It takes longer to access the information in ROM, but it does not lose information when a computer shuts down as does RAM. Control Unit The control unit directs the flow of operations and data by selecting one program statement at a time, interpreting it and sending messages to the ALU or registers to carry out the instruction. It also decides where to keep information in memory and which devices to communicate with by interfacing with the ALU, memory and input/output devices. The control unit can also shut down a computer if it or another device, such as the power source, detects abnormal conditions.

Information Exchange The system bus connects the microprocessor to the peripherals, such as a keyboard, mouse, printer, scanner, speaker or digital camera. The microprocessor sends and receives data through the system bus to communicate with the peripherals. It only communicates with one peripheral at a time so as to not mix up any information and send it to the wrong place. The control unit controls the timing of the information exchange. Features A microprocessor performs mathematical functions using its arithmetic logic unit, (ALU). Modern processors have the ability to perform large arithmetic computations using floating point processors. Floating point processors allow microprocessors to perform sophisticated computations quickly and accurately. Significance A microprocessor helps to move data from one memory location to another. Microprocessors allow you to transfer information from a USB flash drive to your computer's hard drive in a matter of seconds, depending on the size of the file being moved. Benefits Microprocessors make quick decisions and handle multiple instructions based on those quick decisions. The instruction register and instruction decoder, using the binary system of encoding and decoding data, allowing the microprocessor to quickly perform user requested tasks.

80286 microprocessor
The Intel 80286 was introduced on February 1, 1982 (also called Intel 286 or iAPX 286) belongs to the family of 8086, is a high performance 16 bit microprocessor. As explained earlier it is an advanced version of 8086 but with a different architectural philosophy. It was widely used in IBM PC compatible computers during the mid-1980s to early 1990s. Its initial releases were of 6 and 8 MHZ but they were subsequently scaled up to 12.5 MHZ (AMD and Harris later pushed the architecture to speeds as high as 20 and 25 MHz, respectively.) On average, the 80286 had a speed of about 0.21 Million instructions per clock. The 6 MHZ model operates at 0.9 MIPS, the 10MHZ model at 1.5 MIPS, and the 12 MHZ model at 1.8 MIPS. The 80286 s performance was more than twice of its predecessors (the intel 8086 and 8088) per clock cycle. Here the complex mathematical operations took fewer clock cycles compared to the 8086.

There are two operating modes for 80286. The real address mode and the protected virtual address mode. As explained in the real address mode the processor can address up to 1MB of the physical memory. The virtual address mode is for multiuser and multitasking system. In this mode of operation the memory management unit can manage upto 1 GB of the virtual memory though the real memory may be much less, only 16 MB. Basically in this mode one user do not interfere with the other. Also users cannot interfere with the operating system. These features are called protection. THE 80286 contains four processing units: 1. Bus unit 2. Instruction unit 3. Execution unit 4. Address unit All memory and I/O read /write operations are performed by BU. While the current instruction is being executed, the BU prefetches instructions and keeps them in a queue of six bytes. The function of IU is to decode the perfected instructions and to maintain a queue of 3 decoded instructions for execution. The EU executes instruction. The address unit computes address of memory or I/O devices, which is to be sent by BU for read and write operation. All the four units work in parallel within the CPU. This type of parallel operation is called pipelining. Allmodern 16 bit CPU use pipelining. In pipelining several execution units in a processor work simultaneously in parallel.

80386 Microprocessor
The Intel 80386 (also called Intel386) is a microprocessor which has been used as the CPU of many personal computers since 1986. During its design phase the processor was code-named simply p3 , the third generation processor in the x 86 lines but it is normally referred to as eitheri386 or just 386. The 80386operated at 5 million instructions per second to 11.4MIPS for the 33MHz model. It was the first x86 processor to have 32 bit architecture, with a basic programming

model that has remained virtually unchanged for over 20 years. Successively newer implementations of this same architecture have become literally several hundred times faster than the original i386 chip during these years. As this is a 32 bit microprocessor ithas a circuitry of 275000 transistors. It was basically introduced in the year 1985. It is compatible with 8086,8088, 80186, 80286 microprocessors. It also contains amour-level protection mechanism on the chip itself. It has a total of 129 instructions. The 80386 is a 32 bit microprocessor with a no multiplexed 32 bit address bus housed in a 132 pin grid array package. Basically this microprocessor has three versions: 80386SX,SL and DX. The DX version has a 32 bit internal architecture and a 32 bit data bus whereas the SX and the SL version have a 32 bit internal architecture but a 16 bit wide data bus. The SL version consumes less power and is basically used in laptops and notebooks. These versions operate from 20MHz to 33MHz. It is capable of addressing 4G bytes of physical memory and through its memory management unit it can address 64 terabytes of the virtual memory. The processor can operate in two modes: Real and protected. In the real mode physical address space is 1Mbytes (20 address lines), which is extended to 4G bytes in the protected mode (32 address lines). The primary difference between these modes is the availability of the memory space and the addressing scheme. The 80386 has 32 bit registers and is upward software compatible with the 8086. The execution of the instructions is highly pipelined and the processor is designed to operate in a multiuser and multitasking environment. It has the protection mechanism for this type of environment. It has basically six functional units: bus interface unit, code prefetch unit, instruction decode unit, execution unit, segmentation unit and the paging unit. It has the provision for both memory segmentation and paging. A page is of fixed size 4KB each. Segment vary in size, 4GB is the maximum size of a segment. The 80386 has 11 addressing modes: register, immediate, direct, register indirect, based, indexed, scale indexed, base indexed, base scale indexed, base indexed with displacement and base scale indexed with displacement addressing. In the scale indexed addressing the contents of an indexed register are multiplied with a scaling factor and the result is added to the displacement to obtain the operand s offset. As explained earlier it has 32 bit register and has eight general purpose registers, six 16 bit segment registers, also has a 32 bit instruction pointer, six debug registers and a 32 bit status register. The 80386 has a segment descriptor register associated with each segment register. The 80386 was widely used in powerful PCs before the 80486 was developed.

80486 Microprocessor
Basically this is an upgraded advanced version of 80386 and it was released in the year 1989. It contains a 32 bit CPU, a floating-point math coprocessor, unified instruction and data cache memory and memory management unit in a single IC. It contains an electronic circuitry of 1.2 million transistors. Its operating frequency for its different versions is 25, 33, 66 and 100MHz. It is 3 to 5 times faster than 80386. Basically this is available in two versions: DX and SX. The DX type version is a 32 bit processor housed in a 168 pin grid array package and can operate with the clock frequencies from 25 to 66 MHz as explained earlier. The important additional features of the 486 processor in comparison with the 386 processor are as follows. The 486 processor includes: Built in math coprocessor. In the 386 system, a math coprocessor is an external device. Therefore, the math instructions in 486 systems are executed three times faster than in 386 systems. 8K byte of code and data cache memory on the chip. Highly pipelined execution unit. Therefore the execution time for many instructions is one clock period. Basically we do not use 80486 but instead of that we usei486 because of a court ruling that prohibited trademarking numbers. Intel dropped number-based naming altogether with the successor to the i486-the Pentium processor. The 486 contains the following functional units: Segmentation unit Execution unit Control unit Paging unit Bus interface unit Cache unit Code prefetch unit Floating point unit. Instruction decode unit

The code prefetch unit contains a 32 byte queue to store fetched instruction codes. The control unit also contains a control ROM to store microcodes. The segmentation unit calculates linear address (the starting address of the segment plus the offset) from the logical address. The address given in the program is called the logical address. It also provides 4-level of protection for isolating and protecting tasks and the operating system from each other. The paging unit provides the paging facility within a segment. It translates the linear address into the ROM existing in a computer is known as physical memory. The segmentation and the paging unit constitute memory management unit. In summary, the 486 is a high speed, high performance 32-bit microprocessor. It executes many of its instructions inone clock cycle by using highly pipelined execution units. It is designed to facilitate the execution of high level languages and suited for multiprocessing and multitasking systems. In the early 1990s, 486 was generally used in high end microcomputers and network environments.

Pin Configuration of 8086

The following signal descriptions are common for both modes.

AD15-AD0: These are the time multiplexed memory I/O address and data lines. *Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines. * During T1 these are the most significant address lines for memory operations. * During I/O operations, these lines are low. * During memory or I/O operations, status information is available on those lines for T2,T3,Tw and T4. * The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. * The S4 and S3 combinely indicate which segment register is presently being used for memory accesses as in below fig. * These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is always low. * The address bit is separated from the status bit using latches controlled by the ALE signal. BHE/S7: The bus high enable is used to indicate the transfer of data over the higher order (D15-D8) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during T1 for the first pulses of the interrupt acknowledge cycle. RD Read: This signal on low indicates the peripheral that the processor is performing memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge. READY: This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. The signal is active high.

INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized. TEST: This input is examined by a WAIT instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock. CLK- Clock Input: The clock input provides the basic timing for processor operation and bus control activity. It s an asymmetric square wave with 33% duty cycle. M/IO Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus hold acknowledge . INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt. ALE Address Latch Enable: This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated. DT/R Data Transmit/Receive: This output is used to decide the direction of data flow through the transceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low. DEN Data Enable: This signal indicates the availability of valid data over the address/data lines. It is used to enable the transceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during hold acknowledge cycle. HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle. At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be externally synchronized. If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4 provided: 1. The request occurs on or before T2 state of the current cycle. 2. The current cycle is not operating over the lower byte of a word. 3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence. 4. A Lock instruction is not being executed. S2, S1, S0 Status Lines: These are the status lines which reflect the type of operation, being carried out by the processor. These become activity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles. LOCK: This output pin indicates that other system bus master will be prevented fromgaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction. When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus. RQ/GT0, RQ/GT1 Request/Grant: These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle.

Pin Configuration of 8088

Pin Configuration of 8088

AD7AD0 - ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data (T2, T3, Tw, T4) bus. These lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ``hold acknowledge''. A15A8 - ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1T4). These lines do not have to be latched by ALE to remain valid. A15A8 are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ``hold acknowledge''. A19/S6, A18/S5, A17/S4, A16/S3 - ADDRESS/STATUS: During T1, these are the four most significant address lines for memory operations. During I/O operations, these lines are LOW. During memory and I/O operations, status information is available on these lines during T2, T3, Tw, and T4. S6 is always low. The status of the interrupt enable flag bit (S5) is updated at the beginning of each clock cycle. S4 and S3 are encoded as shown. This information indicates which segment register is presently being used for data accessing. These lines float to 3-state OFF during local bus ``hold acknowledge''. RD - READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending on the state of the IO/M pin or S2. This signal is used to read devices which reside on the 8088 local bus. RD is active LOW during T2, T3 and Tw of any read cycle, and is guaranteed to remain HIGH in T2 until the 8088 local bus has floated. This signal floats to 3-state OFF in ``hold acknowledge''. READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The RDY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. This signal is active HIGH. The 8088 READY input is not synchronized. Correct operation is not guaranteed if the set up and hold times are not met. INTR - INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH. TEST: input is examined by the ``wait for test'' instruction. If the TEST input is LOW, execution continues, otherwise the processor waits in an ``idle'' state. This input is synchronized internally during each clock cycle on the leading edge of CLK.

NMI - NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not mask able internally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized. RESET: causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is internally synchronized. CLK - CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing. VCC: is the a5V g10% power supply pin. GND: are the ground pins. MN/MX - MINIMUM/MAXIMUM: indicates what mode the processor is to operate in. The two modes are discussed in the following sections. IO/M - STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from an I/O access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (I/O e HIGH, Me LOW). IO/M floats to 3-state OFF in local bus ``hold acknowledge''. WR - WRITE: strobe indicates that the processor is performing a write memory or write I/O cycle, depending on the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active LOW, and floats to 3-state OFF in local bus ``hold acknowledge''. INTA - INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3, and Tw of each interrupt acknowledge cycle. ALE - ADDRESS LATCH ENABLE: is provided by the processor to latch the address into an address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note that ALE is never floated. DT/R - DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R is equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T e HIGH, R e LOW). This signal floats to 3-state OFF in local ``hold acknowledge''. DEN - DATA ENABLE: is provided as an output enable for the data bus transceiver in a minimum system which uses the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles. For a read or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write cycle, it is active from the beginning of T2 until the middle of T4. DEN floats to 3-state OFF during local bus ``hold acknowledge''. HOLD, HLDA - HOLD: indicates that another master is requesting a local bus ``hold''. To be acknowledged, HOLD must be active HIGH. The processor receiving the ``hold'' request will issue HLDA (HIGH) as an acknowledgement, in the middle of a T4 or Ti clock cycle. Simultaneous with the issuance of HLDA the processor will floatthe local bus and control lines. After HOLD is detected as being LOW, the processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. HOLD and HLDA have internal pull-up resistors. Hold is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the set up time. SSO - STATUS LINE: is logically equivalent to SO in the maximum mode. The combination of SSO, IO/M and DT/R allows the system to completely decode the current bus cycle status. HOLD, HLDA - HOLD: indicates that another master is requesting a local bus ``hold''. To be acknowledged, HOLD must be active HIGH. The processor receiving the ``hold'' request will issue HLDA (HIGH) as an acknowledgement, in the middle of a T4 or Ti clock cycle. Simultaneous with the issuance of HLDA the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. HOLD and HLDA have internal pull-up resistors. Hold is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the set up time. SSO - STATUS LINE: is logically equivalent to SO in the maximum mode. The combination of SSO, IO/M and DT/R allows the system to completely decode the current bus cycle status. RQ/GT0, RQ/GT1 - I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local bus at the end of the processor's current bus cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ/ GT1. RQ/GT has an internal pull-up resistor, so may be left unconnected.

LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is active (LOW). The LOCK signal is activated by the ``LOCK'' prefix instruction and remains active until the completion of the next instruction. This signal is active LOW, and floats to 3-state off in ``hold acknowledge''. QS1, QS0 24, 25 - QUEUE STATUS: provide status to allow external tracking of the internal 8088 instruction queue. The queue status is valid during the CLK cycle after which the queue operation is performed.

Basic Function of ROM

ROM - read only memory, is used to store the information that will never be changed/ cannot be changed by the user, such as instructions to make the computer properly boot (startup). This does not get erased when the computer's power is lost. Types of ROM

Mask-Programmed ROM (MROM) Programmable ROM (PROM)

programmed at the factory.

can be custom-programmed by the user (once) using special circuitry.

Erasable-Programmable ROM (EPROM) can also be programmed and erased by the user using ultraviolet light and special circuitry external to the computer. Electrically Erasable PROM (EEPROM) can be erased and reprogrammed by special circuitry within the computer.

Flash ROM Advancements in EEPROM technology have produced Flash ROM devices that enable new BIOS information to be written (downloaded) into the ROM to update it. The download can come from an update disk or another computer.

Basic Function of RAM

RAM - is random access memory, which contains the information that the computer is using at that moment. This will get erased if the computer's power goes off. For example, the text you type in a word document will be stored in RAM, until you close the file. Then it will be stored in the hard drive. SRAM Static RAM (SRAM) stores binary bits in such a manner that the bits remain in RAM as long as power to the chip is not interrupted DRAM Dynamic RAM (DRAM), on the other hand, requires that stored data be refreshed, or rewritten, periodically to keep it from fading away. As a matter of fact, each bit in the DRAM must be refreshed at least once every 2 milliseconds or the data dissipates SDRAM (Synchronous DRAM) Almost all systems used to ship with 3.3 volt, 168-pin SDRAM DIMMs. SDRAM is not an extension of older EDO DRAM but a new type of DRAM altogether. SDRAM started out running at 66 MHz, while older fast page mode DRAM and EDO max out at 50 MHz. SDRAM is able to scale to 133 MHz (PC133) officially, and unofficially up to 180MHz or higher. As processors get faster, new generations of memory such as DDR and RDRAM are required to get proper performance. DDR (Double Data Rate SDRAM) DDR basically doubles the rate of data transfer of standard SDRAM by transferring data on the up and down tick of a clock cycle. DDR memory operating at 333MHz actually operates at 166MHz * 2 (aka PC333 / PC2700) or 133MHz*2 (PC266 / PC2100). DDR is a 2.5 volt technology that uses 184 pins in its DIMMs. It is incompatible with SDRAM physically, but uses a similar parallel bus, making it easier to implement than RDRAM, which is a different technology. Rambus DRAM (RDRAM) Despite its higher price, Intel has given RDRAM its blessing for the consumer market, and it will be the sole choice of memory for Intel's Pentium 4. RDRAM is a serial memory technology that arrived in three flavors, PC600, PC700, and PC800. PC800 RDRAM has doubled the maximum throughput of old PC100 SDRAM, but a higher latency. RDRAM designs

with multiple channels, such as those in Pentium 4 motherboards, are currently at the top of the heap in memory throughput, especially when paired with PC1066 RDRAM memory. DIMMs (dual in-line memory modules) are 64-bit components, but if used in a motherboard with a dual-channel configuration (like with an NvidianForce chipset) you must pair them to get maximum performance. So far there aren't many DDR chipset that use dual-channels. Typically, if you want to add 512 MB of DIMM memory to your machine, you just pop in a 512 MB DIMM if you've got an available slot. DIMMs for SDRAM and DDR are different, and not physically compatible. SDRAM DIMMs have 168-pins and run at 3.3 volts, while DDR DIMMs have 184-pins and run at 2.5 volts. RIMMs use only a 16-bit interface but run at higher speeds than DDR. To get maximum performance, Intel RDRAM chipsets require the use of RIMMs in pairs over a dual-channel 32-bit interface. You have to plan more when upgrading and purchasing RDRAM. SIMMs (single in-line memory modules) - is available in 30- and 72-pin versions. units mount vertically on the system board. However, rather than using a pin and socket arrangement, both use special snap-in sockets that support the module firmly.